US3088409A

US3088409A - Electronic timer

Info

Publication number: US3088409A
Application number: US72257A
Authority: US
Inventors: Irvin S Yavelberg
Original assignee: Individual
Current assignee: Individual
Priority date: 1960-11-28
Filing date: 1960-11-28
Publication date: 1963-05-07
Anticipated expiration: 1980-05-07

Description

y 1963 l. s. YAVELBERG 3,088,409

ELECTRONIC TIMER Filed Nov. 28, 1960 ARMING MECHANISM We IZQ:

l l l l sauna E B2 7 20 :1? I] l6 m i B FIG. 2.

JNVEMTOR, mvm s. Y'AVELBERG v ATTO KIM 3,088,409 ELECTRONIC TIMER Irvin S. Yavelberg, Tucson, Ariz., assignor to the United the Secretary of The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes Without the payment of any royalties thereon or therefor;

The present invention relates to timing means, and particularly to a squib-firing electronic timing apparatus.

While adaptable for use in many different types of equipment, the invention is of special utility in missile destructor fuze apparatus and will be described principally with reference to such apparatus.

It is often of importance that air-to-air or ground-toair missiles be prevented from endangering objects beyond the target, or property and personnel on the ground below, and for this reason such missiles must include means operative to accomplish self-destruction of the missile while still aloft and at a predetermined distance beyond the launching point or, more conveniently, at a predetermined time after the launching instant, in the event the missile has passed its intended target. The self-destruction means requires an explosive charge (conveniently, that already carried in the warhead), and a missile destructor fuze apparatus preferably including a destructor squib and timing means to effect electrical detonation or flashing of the destructor squib. Simplicity, sturdiness, compactness and low Weight being at a premium in missile design, it is particularly advantageous to employ a timing device of unijunction transistor type which makes it possible to achieve such characteristics, provided that such a timing device can also be made to yield substantially constant timing (for any selected setting) over the wide temperature range called for by military specifications.

Unijunction transistor type of timing devices make use of an integrating circuit wherein the voltage developed across a capacitor as a function of charging time reaches a transistor firing value upon expiration of a predetermined charging interval, hereinafter termed the squibflashing delay-time. For use in missile self-destruction apparatus as indicated, the squib-flashing delay-time, as measured from substantially the missile launch instant, must be comparatively long, say 60 seconds by way of example. The integrating circuit, further, must be so designed that sufficient energy will have accumulated in the charging capacitor, at the intended self-destruction instant, to effect flashing of the destructor squib. It therefore becomes impractical to employ a charging capacitor of any type other than an electrolytic capacitor of comparatively large microfarad value, preferably a tantalum capacitor because of its extreme compactness. It has been found, however, that over the typical military specification range of temperatures, say -50 to +150 on the Fahrenheit scale, the change in leakage resistance (and correspondingly of leakage current), of a tantalum capacitor as heretofore employed in timing devices broadly of the type hereunder consideration, may be so large as to result in delay-time variations of the order of 100 percent, far too great to be tolerated in missile destructor fuze apparatus.

It is therefore the principal object of the present invention to provide a missile destructor fuze apparatus having improved reliability.

It is another object of the invention to provide a unijunction transistor timing device providing a high degree assess Patented May 7, 1963 of timing stability over a relatively wide range of operating temperatures.

Other objects and many of the attendant advantages of this invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein:

FIG. 1 is a schematic diagram of a unijuncion transistor timing circuit in accordance with principles of the invention; and

FIG. 2 is a schematic diagram of a modified unijunction transistor timing circuit employing a single DC. power source.

Referring now to FIG. 1, the unijunction transistor 10 may be of conventional type consisting of a small bar of uniformly doped N-type silicon having ohmic contacts identified as B1 (base-one) and B2 (base-two) at its two ends, and a single rectifying PN junction identified as emitter E. Unijunction transistor 10 presents a conduction control feature somewhat similar to that of a gas thyratron. In particular, until a control voltage of positive polarity applied to emitter E assumes a critical threshold value of the order of six-tenths of the inter-base voltage, emitter E is in eifect reverse-biased, and the unijunction transistor is said to be cut off, essentially so except for a so-called reverse or back current of comparatively small magnitude in the emitter circuit. When the critical threshold value of control voltage is reached, however, the emitter E becomes forward-biased, and the resistance between emitter electrode E and base electrode B1 of the transistor drops sharply to a comparatively low value, enabling destructor squib 11 to be flashed, as will appear.

Separate DC.

power sources

12 and 13 are provided, in the FIG. 1 embodiment, for supplying the unijunction transistor base-to-base voltage, and for supplying capacitor charging current to the integrating circuit comprising adjustable resistor 14, and

capacitors

15 and 16 having substantially the same capacitance and leakage current characteristics. These

power sources

12 and 13 are most practically and conveniently provided in the form of batteries, as indicated, and the power circuits are arranged to remain open until actuation of

switches

17 and 18.

Switches

17 and 18, forming part of an acceleration-responsive mechanism 19 which may be of any conventional type (therefore not shown in detail) such as employed for missile arming, are to be understood as being thrown into closed condition by mechanism 19, to start the timing function of the unijunction transistor circuit, provided the missile functions successfully to execute rapid acceleration. Relative to the instant at which the

switches

17 and 18 are closed, the control voltage developed across capacitor 16 reaches the firing threshold value after a so-called delay-time dictated by the ohmic value of resistance provided by adjustable resistor 14, the microfarad values of

capacitors

15 and 16, and the magnitudes of the voltages delivered by

sources

12 and 13. It has been found that with compensating capacitor 15 and firing capacitor 16 of exactly the same type and selected to exhibit the same values of capacitance and leakage resistance at normal temperature and, correspondingly, like characteristics of capacitance and leakage resistance variations with temperature change, the timing function for any given setting of resistor 14 remains reasonably constant over the rather wide military specification temperature range indicated above. For example, a test version of the FIG. 1 circuit, employing a unijunction transistor of commercially available 2N489 type,

sources

12 and 13 respectively delivering 15 and 30 volts, tantalum capacitors each of microfarad value and rated at say 30 volts, and a series charging resistance of 1.4 megohms, has exhibited a squib-flashing delay-time of approximately 60 seconds with variations of only about 3 5 percent over the temperature range of 50 F. to +170 F.

FIG. 2 concerns a modification providing like timing stability, but presenting further improvement as to compactness and low weight by use of a single tapped

battery comprising sections

20 and 21, and a compensating resistor 22, as illustrated. Battery section 20 serves as the source of interbase voltage for unijunction transistor 10, and

battery sections

20 and 21 are additive as to the charging voltage applied to the series circuit of resistor 14 and

capacitors

15 and 16. Near-optimum battery compactness is provided by selection of battery section to a yield voltage of about four-tenths of the additive voltage. Resistor 22 is of suitable ohmic value to impose a current drain of about the same magnitude on battery section 21 as is imposed upon battery section 20 by unijunction transistor 10, in this manner serving to maintain substantially the same ratio of terminal voltages supplied by the battery sections under varying conditions, as necessary to maintain the same timing function for a given setting of resistor 14.

Firing or flashing of squib 11 in the FIG. 1 and FIG. 2 circuits is effected by discharge of capacitor 16 through squib 11, enabled at the instant when the control voltage developed in the capacitor has reached the critical value, sometimes termed the firing or peak point emitter voltage, which establishes a forward-bias condition for emitter E. In a typical instance squib 11 may present a resistance of approximately 5 ohms and may require about 5000 ergs of electrical energy to flash it. Assuming that the peak point emitter voltage required to fire the unijunction transistor 11 is of the order of say 10 volts, the energy accumulated in capacitor 16 at that time would be 50,000 ergs, well above the squib-flashing energy requirements in order to insure strong flashing and explosive ignition action.

While the FIG. 1 and FIG. 2 circuits provide stability of squib-flashing delay-time by means of a pair of seriesconnected like capacitors having compensating leakage current characteristics, for use in a non-adjustable or narrowly adjustable timer intended to provide substantially fixed rather than widely variable delay-time, it is also feasible to employ a single capacitor, in place of the pair of series-connected capacitors, presenting capacitance and leakage resistance characteristics which vary oppositely with temperature and combine to yield the necessary transistor-firing control voltage at substantially constant delay-time over the specified operating temperature range.

Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.

What is claimed is:

1. A missile destructor fuze apparatus comprising, in

combination: a destructor squib; a unijunction transistor having an emitter electrode and a pair of base electrodes; means for providing a predetermined potential gradient in said unijunction transistor between said base electrodes and correspondingly establishing a predetermined value of peak point emitter voltage for firing said unijunction transistor; a series-charging network comprising a source of voltage, a switch, a resistor, a compensating tantalum capacitor, and a firing tantalum capacitor, to effect charging of said firing capacitor to said predetermined value of peak point emitter voltage upon expiration of a predetermined time delay initiated upon closing of said switch; said firing capacitor, squib, and unijunction transistor being connected in circuit to effect flashing of said squib by conduction of discharge current from said firing capacitor through said squib and said emitter electrode when the firing capacitor voltage reaches said predetermined value of peak point emitter voltage; and said capacitors having balancing temperature-dependent characteristics which render said predetermined delay time substantially independent of ambient temperature changes.

2. A missile destructor fuze apparatus comprising, in combination: a destructor squib; a unijunction transistor having an emitter electrode and a pair of base electrodes; a battery having a section thereof connected across the base electrodes of said unijunction transistor to provide a predetermined potential gradient therebetween and correspondingly establishing a predetermined value of peak point emitter voltage for firing said unijunction transistor; a compensating current-drain resistor connected across the remaining section of said battery; a series-charging network comprising said battery, a switch, a resistor, a compensating tantalum capacitor, and a firing tantalum capacitor, to effect charging of the firing capacitor to said predetermined value of peak point emitter voltage upon expiration of a predetermined time delay initiated upon closing of said switch; said firing capacitor, squib and unijunction transistor being connected in circuit to effect flashing of said squib by conduction of discharge current from said firing capacitor through said squib and said emitter electrode when the firing capacitor voltage reaches said predetermined value of peak point emitter voltage; and said capacitors having balancing temperature-dependent characteristics which render said predetermined delay time substantially independent of ambient temperature changes.

References Cited in the file of this patent UNITED STATES PATENTS 2,906,206 Morison et al. Sept. 29, 1959 FOREIGN PATENTS 1,136,465 France Dec. 29, 1956 1,218,809 France Dec. 21, 1959

Claims

1. A MISSILE DESTRUCTOR FUZE APPARATUS COMPRISING, IN COMBINATION: A DESTRUCTOR SQUIB; A UNIJUNCTION TRANSISTOR HAVING AN EMITTER ELECTRODE AND A PAIR OF BASE ELECTRODES; MEANS FOR PROVIDING A PREDETERMINED POTENTIAL GRADIENT IN SAID UNIJUNCTION TRANSISTOR BETWEEN SAID BASE ELECTRODES AND CORRESPONDINGLY ESTABLISHING A PREDETERMINED VALVE OF PEAK POINT EMITTER VOLTAGE FOR FIRING SAID UNIJUNCTION TRANSISTOR; A SERIES-CHARGING NETWORK COMPRISING A SOURCE OF VOLTAGE, A SWITCH, A RESISTOR, A COMPENSATING TANTALUM CAPACITOR, AND A FIRING TANTALUM CAPACITOR, TO EFFECT CHARGING OF SAID FIRING CAPACITOR TO SAID PREDETERMINED VALUE OF PEAK POINT EMITTER VOLTAGE UPON EXPIRATION OF A PREDETERMINED TIME DELAY INITIATED UPON CLOSING OF SAID SWITCH; SAID FIRING CAPACITOR, SQUIB, AND UNIJUNCTION TRANSISTOR BEING CONNECTED IN CIRCUIT TO EFFECT FLASHING SAID SQUIB BY CONDUCTION OF DISCHARGE CURRENT FROM SAID FIRING CAPACITY THROUGH SAID SQUIB AND SAID EMITTER ELECTRODE WHEN THE FIRING CAPACITOR VOLTAGE REACHES SAID PREDETERMINED VALVE OF PEAK POINT EMITTER VOLTAGE; AND SAID CAPACITORS HAVING BALANCING TEMPERATURE-DEPENDENT CHARACTERISTICS WHICH RENDER SAID PREDETERMINED DELAY TIME SUBSTANTIALLY INDEPENDENT OF AMBIENT TEMPERATURE CHANGES.