US3001089A - Transistor memory system - Google Patents

Transistor memory system Download PDF

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Publication number
US3001089A
US3001089A US693884A US69388457A US3001089A US 3001089 A US3001089 A US 3001089A US 693884 A US693884 A US 693884A US 69388457 A US69388457 A US 69388457A US 3001089 A US3001089 A US 3001089A
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US
United States
Prior art keywords
transistor
base
collector
free charge
interrogating
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Expired - Lifetime
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US693884A
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English (en)
Inventor
Tulp Theodorus Joannes
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US Philips Corp
North American Philips Co Inc
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US Philips Corp
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Publication date
Application filed by US Philips Corp filed Critical US Philips Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • This invention relates to a circuit arrangement comprising a chain of transistors in which each transistor, in the presence of free charge storage in its base zone, determines the free charge storage in the base zone of a succeeding transistor of the chain by means of interrogating pulses which act as a collector supply voltage.
  • a circuit arrangement is described in co-pending patent specification Serial No. 625,726, liled December 3, 1956.
  • the arrangement may be used yfor shifting infomation given in binary code, for example in calculating machines or in automatic telephony.
  • the arrangements described in said co-pending patent specification invariably require the use of a base separating rectifier in order to maintain the base at a floating potential during the occurrence of the said interrogating pulses.
  • the present invention provides a circuit arrangement in which these separating rectiiiers can be dispensed with. It is characterized in that the collector of a preceding transistor of the chain is connected, through a resistor conducting in both directions, to the base of a succeeding transistor, said resistor together with a resistor included in the collector circuit of the preceding transistor being sufficiently large to prevent any free charge storage lof the second transistor from flowing away in the interval between two interrogating pulses supplied to said second transistor.
  • the invention is based on the recognition that, if a succeeding transistor is controlled from the collector of a preceding transistor, the values of the resistors used can be made so high that even if the said separating rectiiier is omitted (the collector of the preceding transistor thus being connected to the base of the succeeding transistor through a resistor conducting in both directions) the base potential can be assumed to remain floating.
  • FIG. l shows a circuit arrangement in accordance with the ⁇ invention and FIG. 2 shows voltage-time diagrams and current-time diagrams illustrating the arrangement shown in FIG. l.
  • reference numerals 1, 2, 3, 4, 5, 6 designate a number of transistors which, in the presence of free charge storage in their base zones, by means of interrogatin-g pulses A, B acting as collector supply voltage pass current through corresponding collector resistors 7, 8, 9, 10, l1, 12. Erasing pulses supplied from sources A' and B' respectively carry off any 'free charge remaining in the base zones through separating rectifiers 13, 14, ⁇ 15, 16, 17 and 18.
  • the collector of each transistor is connected to the base of the succeeding transistor by resistors 19, 20, 21, 22 and 23 conducting in both directions.
  • the circuit arrangement operates as follows:
  • the collector current of the transistor Z is shown as a function of time by I2 in FIG. 2. Since this transistor was non-conductive during the yfirst interrogating pulse B, at this instant base current is supplied to the transistor 3 through the resistor 20, so that this transistor passes the current I3 at the next subsequent interrogating pulse A, and so on.
  • the transistors 1, 3, 5 become conductive in sequence, that is to say, the ffree charge storage injected into the transistor 1 as information to the next odd-numbered transistor at each succeeding interrogating pulse A.
  • the absence of yfree charge storage of the even-numbered transistors is shifted to the next even-numbered transistor at each interrogating pulse B.
  • the resistors used particularly the sum of the collector and 4the base resistors must be suiciently large. In practice, good results were obtained with resistors of 6009 at a repetition frequency of the interrogating pulses of kc./s. However, such large resistors can be used Without diiculty, ras has been described hereinbefore.
  • a transistor memory system comprising at least two stages connected in cascade arrangement, each stage including a transistor having an emitter, la collector and a base, said base having the property of storing a free charge in response to current passed therein, means connected to apply current to the base of a rst one of said transistors to cause a free charge to be stored therein, means for applying interrogating pulses to the respective emitter-collector circuits of said transistors,y said interro- -gating pulses being the sole means of potential supply for said emitter-collector circuits, load resistors connected respectively in the collector circuit of each transistor, and bi-directionally conducting coupling resistors each connected respectively between the base of each transistor and the collector of the transistor of the preceding stage, the value of each coupling resistor and its associated load resistor being sufficiently large to prevent a free charge stored in the base to which the coupling resistor is connected from leaking away during the time interval between two successive interrogating pulses applied to the transistor containing said base, each coupling resistor operating to

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  • Radar Systems Or Details Thereof (AREA)
  • Meter Arrangements (AREA)
  • Static Random-Access Memory (AREA)
US693884A 1956-11-27 1957-11-01 Transistor memory system Expired - Lifetime US3001089A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL357432X 1956-11-27

Publications (1)

Publication Number Publication Date
US3001089A true US3001089A (en) 1961-09-19

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ID=19785272

Family Applications (1)

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US693884A Expired - Lifetime US3001089A (en) 1956-11-27 1957-11-01 Transistor memory system

Country Status (7)

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US (1) US3001089A (enrdf_load_stackoverflow)
BE (1) BE562668A (enrdf_load_stackoverflow)
CH (1) CH357432A (enrdf_load_stackoverflow)
DE (1) DE1043394B (enrdf_load_stackoverflow)
FR (1) FR1200763A (enrdf_load_stackoverflow)
GB (1) GB838247A (enrdf_load_stackoverflow)
NL (2) NL106421C (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3248564A (en) * 1961-12-07 1966-04-26 Int Standard Electric Corp Logical circuitry for digital systems
US3348066A (en) * 1965-03-17 1967-10-17 Automatic Elect Lab Arrangements of one-transistor bistable circuits
US3699540A (en) * 1970-12-31 1972-10-17 Bell Telephone Labor Inc Two-terminal transistor memory utilizing collector-base avalanche breakdown
US3699541A (en) * 1970-12-31 1972-10-17 Bell Telephone Labor Inc Two-terminal transistor memory utilizing emitter-base avalanche breakdown

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL248378A (enrdf_load_stackoverflow) * 1959-03-30
DE1276143B (de) * 1964-10-14 1968-08-29 Siemens Ag Schaltungsanordnung zur Durchschaltung von Radarechoimpulsen

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2594336A (en) * 1950-10-17 1952-04-29 Bell Telephone Labor Inc Electrical counter circuit
US2644892A (en) * 1952-06-02 1953-07-07 Rca Corp Transistor pulse memory circuits
GB733638A (en) * 1952-10-09 1955-07-13 Standard Telephones Cables Ltd Improvements in or relating to electrical counting circuits
US2848658A (en) * 1955-04-29 1958-08-19 Tung Sol Electric Inc Light responsive circuit
US2877357A (en) * 1955-04-20 1959-03-10 Bell Telephone Labor Inc Transistor circuits
US2910596A (en) * 1955-08-03 1959-10-27 Carlson Arthur William Non-saturating transistor ring counter

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2594336A (en) * 1950-10-17 1952-04-29 Bell Telephone Labor Inc Electrical counter circuit
US2644892A (en) * 1952-06-02 1953-07-07 Rca Corp Transistor pulse memory circuits
GB733638A (en) * 1952-10-09 1955-07-13 Standard Telephones Cables Ltd Improvements in or relating to electrical counting circuits
US2877357A (en) * 1955-04-20 1959-03-10 Bell Telephone Labor Inc Transistor circuits
US2848658A (en) * 1955-04-29 1958-08-19 Tung Sol Electric Inc Light responsive circuit
US2910596A (en) * 1955-08-03 1959-10-27 Carlson Arthur William Non-saturating transistor ring counter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3248564A (en) * 1961-12-07 1966-04-26 Int Standard Electric Corp Logical circuitry for digital systems
US3348066A (en) * 1965-03-17 1967-10-17 Automatic Elect Lab Arrangements of one-transistor bistable circuits
US3699540A (en) * 1970-12-31 1972-10-17 Bell Telephone Labor Inc Two-terminal transistor memory utilizing collector-base avalanche breakdown
US3699541A (en) * 1970-12-31 1972-10-17 Bell Telephone Labor Inc Two-terminal transistor memory utilizing emitter-base avalanche breakdown

Also Published As

Publication number Publication date
GB838247A (en) 1960-06-22
BE562668A (enrdf_load_stackoverflow)
NL106421C (enrdf_load_stackoverflow)
NL212520A (enrdf_load_stackoverflow)
DE1043394B (de) 1958-11-13
FR1200763A (fr) 1959-12-24
CH357432A (de) 1961-10-15

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