US2984826A

US2984826A - Electrical gating circuit

Info

Publication number: US2984826A
Application number: US768236A
Authority: US
Inventors: Robert C Reed
Original assignee: Thompson Ramo Wooldridge Inc
Current assignee: Northrop Grumman Space and Mission Systems Corp
Priority date: 1956-11-30
Filing date: 1958-10-20
Publication date: 1961-05-16
Anticipated expiration: 1978-05-16

Description

y 1961 R. c. REED 2,984,826

ELECTRICAL GATING CIRCUIT Original Filed Nov. v30, 1956 \Ga. I P2062.

FuP- FLOP INVENTOR.

A 77'0/2 NE ys United States Patent ELECTRICAL GATING CIRCUIT Continuation of application Ser. No. 625,532, Nov.

This application Oct. 20, 1958, Ser. No. 768,236

4 Claims. (Cl. 340174.1)

The present invention relates to electrical gating circuits and, more particularly, to an electrical gating circuit which is responsive to an applied bias potential to selectively control the passage of an electrical signal. It is a continuation of copending patent application Serial Number 625,532 now abandoned, filed November 30, 1956.

In many conventional electrical gating circuits, bias potentials are utilized for biasing unilaterally conductive devices either to a conductive state or to a non-conductive state, thereby controlling the passage of signals through the gating circuit. The signals may in general be of the alternating type, the pulse type, or the voltagelevel type. Electrical gating circuits having such abilities are described in an article entitled Practical Circuits for Gating in Digital Computers, by N. R. Scott, published in Control Engineering, February 1956, at page 93. While gating circuits of the prior art, including those described in the Scott article, are satisfactory for some purposes, there is one particular application the requirements of which they are incapable of satisfying. That particular application is a high speed electrical gating matrix arranged in the form of a disjunctive tree.

A disjunctive tree gating matrix is useful in selecting one from a plurality of input signals to be supplied to a common output circuit. This type of matrix is also useful for passing an input signal supplied by an input circuit to a selected one of a plurality of output circuits.

The logical arrangement of a switching circuit in a disjunctive tree configuration has been described in an article entitled The Synthesis of Two-Dimensional Switching Circuits, by Claude E. Shannon, published in the Bell System Technical Journal, January 1949, at page 59. The tree configuration consists of a trunk which is connected to a pair of first-order branches, each first-order branch being connected to a pair of secondorder branches, each second-order branch being connected to a pair of third-order branches, with an extension of this arrangement to a plurality of n-order branches. The disjunctive operation resides in the fact that each of the various branches is switchable to either a conducting or a non-conducting state, a logical switching scheme being provided such that there is a continuous path between the trunk and only a selected one of the n-order branches. Various specific forms of the disjunctive tree are illustrated in Figures 7, 9, 14, and 19 of the Shannon article.

One application of a disjunctive tree switching circuit is to select a signal from one of a plurality of sources, i.e., signal generators, connected to the n-order branches and to pass the selected signal to the trunk of the tree, i.e., the output circuit. In another application the trunk of the tree is utilized as an input circuit for receiving an electrical signal which may then be commutated or distributed to any selected one of a plurality of output circuits associated with the n-order branches of the tree.

While the logical arrangement of a disjunctive tree matrix is fully described in the Shannon article, the

mechanization described therein for switching the various branches to either a conducting or a non-conducting state is the conventional electromechanical relay which is inherently a very slow speed device. For many purposes, a disjunctive tree matrix controlled by relays would have no utility. On the other hand, previously known electrical gating circuits, while having high operating speeds, have not provided satisfactory operation in a disunctive tree matrix.

Many diificulties arise in attempting to provide high speed electrical control of a disjunctive tree matrix. One difficulty is that the selected signal must pass through a relatively large number of serially connected gating elements, such as unilaterally conductive devices, resulting in substantial attenuation. Another difficulty is that bias control currents must be permitted to flow in the signal path along with the selected signal current, thus presenting to the selected signal current a relatively large number of parallel paths through the various bias sources. Even though the impedance levels of the various bias sources are relatively high in comparison to the impedance level of the principal signal path, excessive signal attenuation nevertheless occurs.

According to the present invention there is provided a novel gate which completely attenuates a signal presented to it if the gate is turned off and which passes the signal at a very high impedance level with very low attenuation if the gate is turned on. The novel gate of the present invention may be utilized as a building block to provide a gating matrix of large proportions in which the attenuation of a selected signal is restricted to a nominal value far less than the attenuation characterizing presently known gating techniques.

In its general structural form, the novel gate of the present invention includes a signal path .having a pair of impedance elements therein whose sum value is variable in a discrete fashion between a very low and a very high value, and a bias path arranged in shunt with the signal path and containing a similarly variable impedance element. The operation of the gate is controlled through biasing circuits in such a way that when the passage of a signal along the signal path is to be inhibited, the series impedance is at a maximum and the shunt impedance is at a minimum, while when a signal is to be passed, the converse relationship exists.

In a preferred embodiment, the impedance elements are unilaterally conductive devices such as diodes, having the same polarity with respect to the signal source. An additional impedance element is connected in parallel with a similar unilaterally conductive device contained in the bias path.

It is, therefore, an object of the present invention to provide an improved electrical gating circuit which is responsive to an applied bias potential for selectively controlling the passage of an electrical signal therethrough.

Another object of the invention is to provide an electrical gating circuit having a signal path and a bias control path in shunt therewith, the impedance of the signal path being at a minimum and the impedance of the bias control path being at a maximum when the gate is on, and the impedance of the signal path being at a maximum and the impedance of the bias control path being at a minimum when the gate is 01f.

Yet another object of the present invention is to provide a novel electrical gating circuit for use as a building block in constructing a high speed disjunctive tree switching circuit.

The features of this invention which are believed to be novel and patentable are pointed out in the claims which form a part of this application. For a better understanding of the invention, reference is now made to the accompanying drawing which illustrates, partly in schematic and partially in block form, a signal selection matrix in accordance with the present invention, for selecting a signal from one of eight magnetic reading heads and supplying the selected signal to a reading amplifier. This is a signal. selection matrix in the form of a disjunctive tree wherein a reading amplifier 50 provides the trunk, a pair of electrical gates 40a, 40b provide the first-order branches, electrical gates 30a, 3%, 30c, 30d provide the second-order branches, and electrical gates 20a 2011 provide the third-order branches. Magnetic reading heads a 1011 are coupled to gates a 20h, respectively, the operation of the matrix being such that a continuous path to the reading amplifier is provided from only a selected one of the magnetic reading heads. Gates 20a 2011 are conventional while gates a 30d and a, 401) are novel gates provided by the present invention.

The signal selection matrix of the figure is controlled by flip-

flops

61, 62 and 63 each of which generates a complementary pair of voltage level control signals on corresponding control leads designated as A, A, B, B and C, C. When control lead A is at a high voltage level control lead A is at a low voltage level; for this condition gates Zita, Zilc, lite, and 20g are turned on, while gates Ztlb, 29d, 20f and 20h are turned off. Thus, flip-flop 61 controls the operation of gates 20a 20h permitting only alternate ones to be turned on at the same time. In a similar manner flip-flop 62 controls gates 39a 30d. Control lead B is connected to

gates

30a and 30c which are turned on in response to a high voltage level and turned off in response to a low voltage level, while control lead B controls gates 30b and 39d. Flip-flop 63 controls gates dtla and 40b, control lead C being connected to gate 40a While control lead C is connected to gate 46b.

It is convenient to describe the logical operation of the signal selection matrix of the figure by means of a Boolean algebraic equation as follows:

Selected signal to reading amplifier 59 In the above equation each dot represents the wellknown logical and function, while each plus represents the well-known logical or function. Each symbol, such as A and A, represents the bias potential on the corresponding control lead. Each symbol such as 10a, 1% indicates the signal produced by the corresponding magnetic reading head. The high voltage level of each of the selection signals, such as A and A, is considered as having a binary 1 value, while the low voltage level is considered as binary 0.

Let it be assumed, for example, that all of the control signals A, B and C are at the high voltage level and the complementary control signals A, B and C are at the low voltage level. In the above equation, then, the selected signal is 16a since the selection criteria A.B.C has a binary 1 value while all of the other seven selection criteria have a binary 0 value. Using this assumption as to the states of the control flip-

flops

61, 62, 63, the operation of the gating circuits Within the signal selection matrix of the figure will now be traced in some detail.

The signal path by which the signal from magnetic head 19a is passed to reading amplifier 50 will first be traced and its operation described. The state of flipflop 61 is such that this bias control lead A applies a relatively high voltage level for maintaining gate 20a in the on condition. Gate 20a includes a first signal line 21a, a second signal line 24a, first and second unilateral- 1y

conductive devices

22a and 23a having their cathodes connected to signal lines 21a and 24a, respectively, and

a resistor 25a connected between the anodes of

devices

22a, 23a, and a bias control line 26a which receives bias potential A. The high voltage level of bias potential A is sufiicient to cause both of

devices

22a, 23a to be conductive in the forward direction.

Devices

22a, 23a may, for example, be semi-conductor diodes. Current flowing through device 22a to signal line 21a completes its return path through a winding 11a which is the output circuit of magnetic reading head 10a, anda load resistor 15 and a load capacitor 16 which are connected together in parallel. A grounded lead 65 is illustrated as establishing the reference potential for the system and is connected to one side of load resistor 15, load capacitor 16, reading amplifier 50, and a ground terminal of each of the flip-

flops

61, 62, 63. Load resistor 15 is used in order to permit the potential of signal line 21a to float above the system ground or reference level when gate 20a is turned on. Load capacitor 16 is used in order to prevent alternating signals which are developed by magnetic reading head 10a from being dissipated in load resistor 15.

Each of gates 20b 20h is identical to gate 201:, the corresponding structural elements thereof being indicated with the same small letter suifix as the gate. When gate 20a receives a relatively high bias potential from bias control lead A, gate 20b is receiving a relatively low bias potential from bias control lead A. The bias current which flows through device 23a in gate 20a might conceivably find a return path either through gate 20b or through gate 30a, since line 24a is connected to line 24b of gate 20b and to line 31a of gate 30a. However, the low bias potential level from lead A is negative with respect to the positive potential developed across load resistor 15; hence, unilaterally conductive device 22b is back-biased and does not conduct. Furthermore, device 2315 is back-biased because its anode is at the A potential which is relatively negative compared to the bias voltage A which is applied to gate 20a and causes a current to flow on signal line 24a. Therefore, the bias current flowing through device 23a to signal line 24a can only flow to signal line 31a in gate 30a, rather than to signal line 24b and gate 2%.

Gate 30a is on" because bias potential B is at a high level. Gate 30a includes a first signal line 31a, a second signal line 34a, a first unilaterally conductive device 33a having its anode connected to signal line 31a and its cathode connected to signal line 34a, a second unilaterally conductive device 32a having its anode connected to signal line 31a and its cathode connected to a bias control line 36a, a resistor 35a connected in parallel with device 32a and unilaterally conductive devices 23a and 23b which, as shown, are also active in gates 20a and Ztlb, respectively. The relatively high bias level applied to bias control line 36a is positive with respect to the potential of signal line 31a, hence device 32a is backbiased. Bias current supplied by gate 20a through device 23a therefore flows through device 33a to line 34a. Furthermore, an additional bias current flows through resistor 35a and device 33a to line 34a.

Gates

30b, 30c, 30d, 40a and 4% are identical to gate 30a, the corresponding structural elements thereof being designated by the same reference numerals with appropriate small letter suffix. It is seen, for instance, that unilaterally conductive devices 33a and 33b form part of gate 40a. Signal line 34a, representing the output of gate 30a, and signal line 34b, representing the output of gate 3012, are connected to signal line 41a of gate 40a. Gate 30b receives a low level bias potential B and is therefore in the 06" condition so that unilaterally conductive device 3312 therein is back-biased. Bias current flowing out of gate 3022 on line 34a therefore passes through gate 40a via line 41a.

Gate 40a is on because bias voltage C is at a high level, and its operation is the same as previously described for gate 30a. The total bias current flowing to line 440 includes the bias current on line 34a plus an additional increment received from flip-flop 63 via bias resistor 45a.

Reading amplifier 50 receives the bias current flowing on line 44a and returns it to reference lead 65. Gate 40b is o because bias voltage C is at a low level, hence unilaterally conductive device 43b is backbiased and does not draw any of the current from line 44a.

Reading amplifier 50 includes a coupling resistor 51 connected between signal line 44a and reference lead 65, and a coupling capacitor 52 having one terminal connected to signal line 44a. The other terminal of capacitor 52 is connected to the base of an N-P-N trans1stor 53 which has a source of positive potential applied to its collector. The emitter of transistor 53 is connected through primary winding 54a of an output transformer 54 to a load resistor 56 and a shunt capacitor 57 which are in turn connected to reference lead 65.

The signal selection matrix of the figure may be analyzed with reference to its equivalent direct current circuit and also with reference to its equivalent alternating current circuit. These two analyses will be presented separately.

In the direct current circuit, the bias current supplied through bias resistor a of gate 20a divides between two paths, one through load resistor 15 and the other through resistor 51 of reading amplifier 50. The bias current flowing through bias resistor 35a in gate a, and the bias current flowing through resistor 45a in gate 40a also pass through resistor 51 which acts as a load. It is necessary that reading amplifier 50 have a direct current input resistance of at least a predetermined value in order to obtain the correct biasing action in the gating circuits, this need being filled by resistor 51.

In the alternating current operation of the circuit of Figure l capacitor 16 effectively bypasses load resistor 15. Signal current flowing in response to a signal voltage generated by magnetic reading head 10a flows through unilaterally

conductive devices

22a and 23a, device 33a, device 43a, and thence to reading amplifier 50. Signal current which is intended for reading amplifier 50 finds possible shunt paths via bias resistors 25a, a and 45a. It therefore is significant that the resistance value of each of these resistors is quite large compared to the alternating current input impedance of reading amplifier 50.

Having thus described the path by which signal current flows from magnetic reading head 10a to reading amplifier 50, it will now be convenient to briefly described some other parts of the selection matrix and to explain why no signal is passed through them. Gate 200 is on like gate 20a, and gate 20d is off like gate 20b. No signal passes from magnetic reading head 10c to gate a, however, because gate 30b is off. Bias potential B applied to bias control line 36b of gate 30b is negative with respect to the potential level which would otherwise tend to exist at the anodes of unilaterally conductive devices 220, 23c. Bias current therefore flows through device 23c and device 3212 to bias control line 36b and hence to flip-flop 62. As previously explained, unilaterally conductive device 33b is back-biased.

Gate 300 is on and gate 30d is oflf. Unilaterally conductive device 33d is therefore back-biased, while bias current flows through device 3-30 for maintaining gate 300 on. However, garte 40b is off because of the low potential of bias signal C. Bias current therefore flows through resistor 35c, unilaterally conductive device 33c, unilaterally conductive device 4215 (and to some extent through its parallel resistor b), through flip-flop 63 and reference lead 65 to flip-flop 62. Unilaterally conductive device 43b is back-biased as previously stated.

Having thus described the circuit of the figure and analyzed certain phases of its operation, it is now convenient to list preferred values for the circuit elements.

Bias resistor 25a is preferably 50,000 ohms; load resistor 15, 100,000 ohms; bias resistors 35a and 45a are 100,000 ohms, and coupling resistor 51 is 20,000 ohms. All unilaterally conductive devices are preferably semiconductor diodes having a high forward conductance.

It will be noted that the alternating current input impedance of reading amplifier 50 is of a very low order of magnitude because of the use of a transistor as the amplifying element. Therefore, the shunting effect of

resistors

25a, 35a, 45a and 51 upon the signal current flowing from read head 10a to the transistor amplifier is relatively small. Conversely, the gating efliciency is relatively high and in actual usage with circuit values as listed approximately eighty percent of the signal developed by the reading head is received by the amplifier as a useful driving signal.

It should be understood that, where it is desired that the novel gates of the figure be arranged so that they will be turned on in response to a low bias potential and off in response to a high bias potential, all unilateral conductive devices would simultaneously be connected in reverse polarity to that shown.

Although the gating matrices of the figure have been illustrated as providing a selection function in which a signal from a selected one of a plurality of input circuits is passed to a single output circuit, it will nevertheless be understood that the same logical matrices may be utilized to perform the function of commutation or distribution in which the signal provided by a single input circuit is passed to a selected one of a plurality of output circuits. The only structural changes which would be necessary would be appropriate changes in the input and output circuits themselves. Thus, there are two alternative structural forms of a disjunctive tree gating matrix in accordance with the present invention, each of which may be utilized either for signal selection or for signal distribution.

The novel electrical gating circuit provided by the present invention produces very little attenuation of a selected signal passing through it, and a very high attenuation of a signal which is to be rejected. A plurality of the novel electrical gating circuits of the present invention may be combined to provide a disjunctive tree gating matrix, the size of the matrix being limited only by the permissible signal attenuation.

It is to be expressly understood that the usefulness of the disjunctive tree matrices provided by the present invention is not limited to the particular application which has been illustrated. Rather, the disjunctive tree matrices of the invention may be utilized for controlling any type of signal selection or signal distribution function. Furthermore, the novel electrical gating circuit provided by the present invention is not limited to use in a disjunctive tree matrix, but has general application wherever it may be desired to selectively control the passage of an electrical signal in accordance with the value of an applied bias potential.

Although the semiconductor diodes have been described as being suitable unilaterally conductive devices for mechanizing the circuits of the present invention, it is to be distinctly understood that the invention is not limited to their use, but extends to any type of unilaterally conductive device. Flip-flops have been illustrated as a preferred manner of providing bias control potentials, however, any other suitable method may be employed without departing from the scope of the invention.

What is claimed is:

1. A gating circuit, comprising: a first signal line from which current may be drawn; a second signal line capable of receiving current; a bias control line; a pair of unilaterally conductive devices connected serially between said first signal line and said second signal line in a particular polarity sense with respect to said first signal line; a unilaterally conductive device connected between the junction of said pair of unilateral conductive devices and said bias control line in said particular polarity sense with respect to said first signal line; a resistor connected in parallel with said second unilaterally conductive device; and means for selectively producing either a first bias condition in which said bias control line and said second signal line have a prescribed and opposite polarity with reference to said first signal line, or a second bias condition in which said bias control line and said second signal line each have, with reference to said first signal line, a polarity opposite to that of the first bias condition, whereby current will pass from said first signal line to said second signal line during only one of said bias conditions.

2. A gating circuit, comprising: a first signal line; a second signal line; a bias control line; a first diode having an anode connected to said first signal line; a second diode having an anode connected to the cathode of said first diode and a cathode connected to said second signal line; a third diode having an anode connected to the cathode of said first diode and a cathode connected to said bias control line; a resistor connected in parallel with said third diode; and means for selectively producing either a first bias condition in which said 'bias control line and said second signal line are respectively positive and negative with reference to said first signal line, or a second bias condition in which said bias control line and said second signal line are respectively negative and positive with reference to said first signal line, the gating circuit being operable to pass current from said first signal line to said second signal line only during the first bias condition.

3. In a computer matrix for selecting among output signals generated by a plurality of magnetic heads for energizing a read amplifier, a gating circuit, comprising: an input circuit corresponding to each head and capable of providing a current when its head is energized; an output circuit capable of receiving current; a bistable state circuit having a pair of complementary outputs; a first diode having an anode and a cathode, the anode being connected to said input circuit; a second diode having an anode and a cathode, the anode being connected to the cathode of said first diode and the cathode being connected to said output circuit; a resistor connected between a selected output of said bistable state circuit and the junction of the cathode of said first diode and the anode of said second diode; and a third diode having an anode and a cathode, the anode being connected to the junction of the cathode of said first diode and the anode of said second diode and the cathode being connected to the selected output of said bistable state circuit.

4. In a computer matrix for selecting among output signals generated by a plurality of magnetic heads for energizing a read amplifier, a gating circuit for each of the magnetic heads, comprising: an input circuit providing a current when energized by a magnetic head connected thereto; an output circuit capable of receiving current; a first bistable state circuit having a pair of complementary outputs; a first diode having an anode and a cathode, the anode being connected to said input circuit; a second diode having an anode and a cathode, the anode being connected to the cathode of said first diode to form a junction therebetween and the cathode being connected to said output circuit; a resistor connected to one of the pair of complementary outputs of said first bistable state circuit and the junction; at second bistable state circuit having a pair of complementary outputs, one of which is connected to the anode of said first diode; and a third diode having an anode and a cathode, the anode being connected to the junction and the cathode being connected to said one of the pair of complementary outputs of said first bistable state circuit.

References Cited in the file of this patent UNITED STATES PATENTS 2,535,303 Lewis Dec. 26, 1950 2,563,589 Den Hertog Aug. 7, 1951 2,570,716 Rochester Oct. 9, 1951 2,576,026 Meacham Nov. 20, 1951 2,611,025 J-ankowski Sept. 16, 1952 2,651,718 Levy Sept. 8, 1953 2,657,318 Rack Oct. 27, 1953 2,752,530 Aigrain June 26, 1956 2,802,954 Graham et a1. Aug. 13, 1957 2,840,726 Hamilton June 24, 1958 2,854,655 Beaufoy et a1 Sept. 30, 1958 2,877,451 Williams Mar. 10, 1959 2,892,184 Joel et al June 23, 1959 OTHER REFERENCES Rectifier Networks for Multiposition Switching (Brown), Proceedings of the I.R.E., February 1949, pp. 139-147.

The Development of an Electronic commutator" (Martel), M.I.T. Thesis submitted May 19, 1950, placed in Vail Library, M.I.T., March 5, 1951.

The Development of a High-Speed Triode-Tree Electronic Commutator (Cooper), M.I.T. Thesis submitted August 31, 1951 placed in Vail Library, M.I.T., October 4, 1951.