US2964736A

US2964736A - Digital computing

Info

Publication number: US2964736A
Application number: US476181A
Authority: US
Inventors: Ruhman Smil
Original assignee: Raytheon Co
Current assignee: Raytheon Co
Priority date: 1954-12-20
Filing date: 1954-12-20
Publication date: 1960-12-13
Anticipated expiration: 1977-12-13

Description

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nited States Patent DIGITAL COMPUTING Smil Ruhman, Waltham, Mass, assignor to Raytheon Company, a corporation of Delaware Filed Dec. 20, 1954, Ser. No. 476,181

12 Claims. (Cl. 340-174) This invention relates to computing, and, more particularly, to the use of magnetic field-sustaining elements in the handling of computations or analogous information in code pattern as, for example, a binary code utilizing two contrasting digits adapted for representation in the form of two contrasting magnetic field conditions brought about alternately in each of said elements by application of code-controlled pulse energy thereto.

The invention is characterized by the application, to a sequential array of field-sustaining elements of the char acter indicated, of circuitry operable to cause any one of such elements to deliver signal energy to a selected one of two adjacent elements, that is, to the element immediately preceding in the chain of progression, or to the element immediately following, according to the selection indicated and applied. The invention is herein illustrated as applied to a shift register, as such devices are termed, consisting of a series of such magnetic field-sustaining elements inter-linked by shift windings through which flux-shifting pulse energy may be applied to produce progressive transfer of coded information from element to element of the register, but whereas prior registers of this kind permitted only forward transfer of the coded information, from an initial stage to a final stage, step by step in a continuing forward trend, the register of the present invention permits two-directional stepping of the coded data, with one or more steps forward being followed by one or more steps backward, as governed by control signals, and as dictated by the logical requirements of the problem being handled. This two-directional stepping is made possible by selective application of one or the other of two oppositelypoled shift pulses adapted to produce flux saturation of opposite polarities in the respective magnetic elements and thereby cause forward or backward transfer of the coded information, in accordance with whether the forwardly-acting or the rearwardly-acting shift circuit has been activated.

In the drawing:

Fig. l is adiagram of components and electrical connections embodying the invention; and

Fig. 2 is a logical diagram of the relationship between the components of the Fig. lembodiment.

The illustrated register consists of a series of toroidal magnetic cores A, 'B, C and D of high magnetic retentivity, with each core having a signal input winding, 1', a signaloutput winding, f0, and two shif windings SR and SL, one controlling forward transfer of the coded information, the other controlling backward transfer. The output winding of each core is connected'to the input'winding's i of the adjacent cores through circuitry including oppositely poled unidirectional conductors (diodes) D andv D and the shift ,coils of allthecores are connected in two series circuits 8 and 9 leading to a 3+ source of actuation pulses, whosepropagation is controlled by suitable current drivers 10 and 11, respectively, which may be vacuum-tube pentode amplifiers, one of the series circuits including all of the forwardly Patented Dec. 13, 1960 ice shifting windings and the other series circuit including all of tne rearwardly shifting windings. The circuit connections between the output windings o and input windings "z" of the different cores also contain time delay networks, NR and NL, to delay delivery of the signal energy to the ad acent core pending completion of fluxreversmg action initiated by each shift pulse. As illustrated, each delay network includes at least one condenser c spanning the two sides of the connecting intercore circuitry, and at least one resistor r in the diodeconnected side of the inter-core path. The value of the resistor r is chosen to be large enough to prevent any substantial discharge of the associated condenser c pending completion of the shift pulse, but small enough to allow sufiicient subsequent current flow to the succeeding input winding to accomplish effective signal input thereto.

In operation, if it is desired to impart to the register a single forward step, the driver 10 is triggered to transmit a shift pulse to all of the SR" windings simultaneously. If core B, for example, is at that instant fluxsaturated in the polarity representative of a 1 digital value, the output winding 0 of core B will receive of a polarity to cause current flow through diode BD to delay network BNR, thence (after the predetermined delay) into input winding i of core C. The latter core will thereupon undergo a shift in its saturation polarity, indicative of the reading-in of a I value into said core. A similar forward transfer of a "1 value will occur simultaneously at any other point in the register where there is a core holding a I value at the time of dispatch of the assumed forwardly-acting shift pulse by operation of driver 10.

If, on the other hand, a rearward stepping of the register had been desired, the rearwardly-controlling driver 11 would have been triggered, to cause a similar signal transfer from core B, for example, to core A by way of diode BD and delay network BNL; in this circumstance the shift windings SL, rather than windings SR, would be energized.

In lieu of the two distinct sets of shift windings, SR and SL, there could be substituted single windings connected to be energized in opposite polarities, as occasion dictates. This, of course, would require a suitable source of bipolar current pulses to take the place of the unipolar source shown in Fig. 1.

For best results, and particularly to prevent interference deriving from the non-relevant diode link in each signal transfer step, it is desirable to choose diodes possessing high forward resistance to voltages of low amplitude, and to choose an overall design of delay network and core winding components that will afford a relatively large ratio of read-in to read-out time, thereby effecting a large read-out to read-in voltage ratio on the output winding of each core. In operation, then, it can be seen that signal pulses passing, for example, from output winding 0 of core B to input winding i of core C will be prevented also from continuing on to affect core D by presenting a voltage of low amplitude to the diode D through the relatively large value selected for resistor r of the intercore delay network NL, as opposed to the lower resistance of the winding i of core C. In this manner, it is apparent that diode BD presents a lower forward resistance to the voltage developed in the directly connected output winding 0. of core B than the relatively high forward resistance which diode D presents to the lower voltage output of the network NL.

1. .Thus, the energy which is stored in the delay network whose diode passes the read-in signal has little effect of construction, materials and processes described, as many equivalents will suggest themselves to those skilled in the art.

What is claimed is: g

1. A system comprising a sequence of field-sustaining elements, first and second electrical windings on each of said elements, and a delay network including capacitive storage means for storing signals connected in circuit with the second winding on one of said elements and the first windings on the two elements respectively preceding and succeeding said element in said sequence of elements and forward and rearward field-reversing means on each of said elements controlling whether a given signal is fed to the delay network connected to the first winding of the preceding or succeeding element in said sequence of elements.

2. A system comprising a sequence of field-sustaining elements, input and output electrical windings 'on each of said elements, a delay network for storing signals connected in circuit with the output winding of any one of said elements and the input windings of the two elements respectively preceding and succeeding said element in said sequence of elements, and series connected forward and series connected rearward field-reversing windings on each of said elements adapted to apply, respectively, one or the other of two oppositely poled shift pulses to each of said elements for controlling whether a given signal is fed to the delay network connected to the input winding of the preceding or the succeeding element in said sequence of elements.

3. A system as defined in claim 1, including unidirectional impedance means of opposite polarities in circuit with each delay network.

4. A system comprising a sequence of field-sustaining elements, input and output windings on each of said elements, a delay network for storing signals connected in circuit with the output winding of any one of said elements and the input winding of said two elements respectively preceding and succeeding said element in said sequence of elements, and series connected forward and series connected rearward field-reversing windings on each of said elements adapted to apply, respectively, one or the other of two oppositely poled shift pulses to each of said elements controlling whether a given signal is fed from said output winding to the delay network of the preceding or the succeeding element in said sequence of elements.

5. A system comprising a sequence of field-sustaining elements; input, output and a pair of shift windings on eaeh of said elements; a delay network including capacitive storage means for storing signals connected in circuit with the output winding of any one of said elements and the input winding of the preceding and following element in said sequence of elements, and means including said 'shift'windings for controlling whether a given signal is 'fed to the delay network connected to the input winding of the preceding or succeeding elements in said sequence of elements.

6. A system as defined in claim 4 including unidirectional impedance means of opposite polarities in the input sections of said delay networks.

7. A system as defined in claim 5 including unidirectional impedance means of opposite polarities in the input sections of said delay network means.

8. A bidirectional shift register comprising a sequence of magnetic elements having input and output windings thereon, delay network means including capacitive storage means in circuit with said windings, forward and rearward field-reversing windings for shifting information from any one of said output windings either forward or rearward along said sequence of elements, said field-reversing winding controlling the direction of activation of said delay means.

9. A system comprising a series of field sustaining elements, input and output windings on each of said elements, a delay network for storing signals connected in circuit with the output windings of any one of said elements and the input windings of the two elements, respectively, preceding and succeeding said element in said series of elements, and series connected forward and series connected rearward shift windings on each of said elements adapted to apply one or the other of two oppositely poled shift pulses to each of said elements for controlling whether a given signal is fed to the delay network connected to the input winding of the preceding or succeeding element in said sequence of elements.

10. A system comprising a sequence of magnetic elements, input, output and shift windings on each of said elements, a 'delay network including a capacitive storage element for transferring "signals connected in circuit with the output winding of any one of said elements and the input winding of the preceding and following element in said sequence of elements, 'said shift windings comprising forward shift windings and rearward shift windings each, 'r'espec't'ively, connected in series on each of said element's cooperating with said delay network to control the transfer of said signals to the delay network connected to the input winding of the preceding or succeeding element in said sequence of elements.

11. A single core per bit shift register having input and output windings adapted to connect a plurality of magnetic elements in sequence, a delay network for storin'g signals connected in circuit with the output winding of any one of said elements and the input windings of the two elements, respectively, preceding and succeeding said element in said sequence of elements, shift winding means comprising forward shift windings and rearward shift windings each respectively connected in series on each of said elements for controlling whether a given signal is fed to the delay network connected to the input winding of the preceding or succeeding element in said sequence of elements and means in circuit with said input and output windings to prevent propagation of signals beyond the preceding or following element in said sequence.

12. A system comprising a sequence of magnetic elements, input and output windings on said elements, delay network means including capacitive storage means for storing signals connected in circuit with the output winding of any one of said elements and the input windings of the two elements, respectively, preceding and succeeding said element in said sequence of elements, and series connected forward and series connected rearward shift winding means on each of said elements adapted to apply one or the other of two oppositely poled shift pulses to each of said elements for controlling whether a given signal is fed to the delay network means connected to the input winding of the preceding or the succeeding element in said sequence of elements.

References Cited in the file of this patent UNITED STATES PATENTS 2,652,501 Wilson Sept. 15, 1953 2,708,722 An Wang May 17, 1955 2,781,503 Saunders Feb. 12, 1957 2,825,890 Ridler et al. Mar. 4, 1958 2,911,621 Crooks Nov. 3, 1959 OTHER REFERENCES Thesis by M. K. Haynes, December 28, 1950, pp. 46-50, 57-58.