US2886240A - Check symbol apparatus - Google Patents
Check symbol apparatus Download PDFInfo
- Publication number
- US2886240A US2886240A US484715A US48471555A US2886240A US 2886240 A US2886240 A US 2886240A US 484715 A US484715 A US 484715A US 48471555 A US48471555 A US 48471555A US 2886240 A US2886240 A US 2886240A
- Authority
- US
- United States
- Prior art keywords
- condition
- counter
- digit
- proof
- digits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
Definitions
- a is a set of associated numerical symbols such as those forming a decimal number
- b is one of a group of predetermined fixed :integer coelficients and each characteristic of the position of a symbol in the group
- n is the number of symbols
- p is a predetermined fixed integer used as :a modulus so as to limit the number of different possible values of the function to p.
- the proof :symbol for 278498 will be given by In other words, 6 is the remainder after dividing 149 by 11.
- the number with its proof symbol can, for example, be written as 278498-6 by putting the proof symbol on the right. Then whenever the number is transcribed and there are possibilities of errors, the
- function (1) can be computed from the transcribed digits and checked against the transcribed proof digit.
- transpositions between any two 'digits of a number there remains the possibility of a transposition between a normal digit and the proof symbol. This may be just as likely to happen as an ordinary transposition, especially if the ordinary digits are also used for the proof symbols and, moreover, if it is possible to use the same keys for typing the proof digit as those used for typing the other digits.
- Some considerations on a possible transposition between the proof symbol and one of the ordinary symbols are given in the Belgian patent mentioned above, but the proof symbol is treated as a special case distinct from the other symbols.
- any decimal number to be keyed should have a proof symbol permanently associated with it at all times when such errors can occur. As each digit a, of such a number would be keyed into a machine, this machine would compute the partial function:
- the rank selector will have to make a total number of steps which varies as the number of the digits varies. In one case the rank selector would be left in one position after the keying of a number, while in another case it would be in another position after the keyingof another number having another number of digits, which means that the rank selector would have to be restored to normal after the keying of every number and would require as many positions as the maximum number of digits forming a number.
- the coefficients b can be chosen in such a way that they satisfy the relation where r is also a fixed predetermined integer.
- the coefiicients form a geometric progression of common ratio r such as 68,69 where r is equal to 6, or
- An object of the invention is to calculate a function F (the proof symbol) of the form given by (6) and where the coefficients b (0 i n) are of the form given by (8), by using a recorder with p stable conditions in a novel and advantageous manner.
- a first and a second electrical ring counters both with p stable conditions, a first pulse source and a second pulse source having r times the frequency of the first one are provided, and upon the second ring counter being set in a condition a, corresponding to the numerical symbol a, while the first ring counter is in a condition F,- the first and the second counter are both driven by the first pulse source until they respectively pass through the conditions 0 and (F,- +a,) (mod.p) which O-condition of the first counter causes a two-condition device to be displaced from its first to its second condition, thereby causing the second pulse source to drive the first counter while the second counter remains driven by the first pulse source until the first and second counters respectively reach their r(F,- +a,-) (mod.p) and O-conditions which last condition, in conjunction with the two-condition device in its second condition, causes the disconnection of said pulse sources from said counters which remain in the conditions attained.
- the ring counter CT which is represented as a rectangle divided into into eleven squares each indicating a possible stable condition or stage of the counter.
- the stages are successively numbered from 1 to 9, 10, 0 which last stage is coupled back to the first stage 1 as shown.
- This counter will permit-the finding of residues with respect to 11 used as a modulus of functions fed to it by way of pulses, the number of pulses characterizing the function.
- a lead is shown to be con nected to all the stages of the counter and it is on this lead that the pulses will be applied, each pulse causing the counter to step from one condition to the next, eg. from condition 5 to condition 6.
- counters which permit the achievement of this shift reference is made to the United States Patent No. 2,649,502, issued August 18, 1953, where a suitable counter using a cold cathode tube for each stage is described.
- a second counter GT which can be of the same type indicating that no keying error has been made and that one can proceed with keying the next number, while -1 is used to indicate the corresponding condition of a counter or of a bistable device, an unblocked gate or 8.
- 0 is used to indicate the corresponding condition of a counter or of a bistable device, a blocked gate or an as the first, also has eleven stable conditions or stages :5 closed make contact, or an OK. signal. If digits of a successively numbered from to 2, 1, 0, which last number have already been keyed, the original condition stage is coupled back to the first stage 10 through a gate F, for counter CT represents a sum (mod. 11) of G which is shown as a circle with the input and output partial functions of the type given by (7) e.g. if the first leads in line and pointing towards the center of the circle.
- Counter CT is in the O-con- CT will in efiect be a ring counter, as is CT The closed dition due to previous keying.
- the additional horizontal arrow at the control leads of gates G and G indicate lines in the O-squares of the counters CT and CI, indithat these gates are normally unblocked and are blocked cate preferred conditions.
- the start cir- A lead is also connected to all the stages of CT and cuit should put these stages on, e.g. the corresponding each pulse appearing at terminal P connected to this lead cold cathode tubes should be ionized. will drive the counter CT from one condition to the The bistable devices BS and BS which are of the twonext.
- This terminal P is connected to the output of 21 input (shown on the long sides of the rectangle) type are bistable electronic device BS e.g. a bistable multiviin the O-condition.
- the gates G and G are unblocked brator, represented by a rectangle divided into two squares 25 and a signal is applied tothe gate G Bistable device 1 and 0 representing the two stable conditions.
- the de- BS should initially be in the l-condition, except when an vice BS, is driven by the pulses appearing at the output incorrect number has just been keyed.
- the notation 0/1 of gate 6, which is of the same functional type as G is therefore used.
- the gates G G G and G are and whose input is connected to terminal P at which blocked, while the gates G and G are blocked or unpulses of a suitable repetition frequency are constantly blocked depending on the conditions of BS and CT; delivered.
- G is normally blocked, but respectively.
- No O.K. signal is delivered, since this when it is unblocked, as will be explained later, B8,, is is controlled by a shift key (not shown) which should continuously driven from one condition to the other and be operated only after a full number has been keyed. pulses appear at terminal P at half the frequency of Contacts s and s of this shift key appear on the figure.
- Gates G and G the moment that one of the ten digit keys (not shown) are also unblocked.
- the potential at terminals P, is also constituting a digit selector is depressed actuating a corapplied to stage 0 of GT and will be assumed to cause responding contact such as k this stage to return to the o condition.
- stage 8 will be ionized as B8,; is always left in the 1- condition after the keying of-a digit, for which condition "the potential at terminal P is sufficientl low to permit the ionization.
- the frequency of the pulses will be chosen so that it is compatible with the keying speed. A frequency of 10 kc./s. for the pulses at terminal P appears amply suflicient.
- p (p 4) When p (p 4) is prime, p1 can be decomposed into prime factors. If P is any one of these factors, one
- the normal number 1 will require 9 as a proof digit and therefore, 19 will nevertheless be used, but as 1 followed by the proof digit 9.
- Such a scheme evidently cannot be applied when all numbers have to be used, e.g. numbers on which calculations are to be performed. But for numbers which represent a designation such as bank account numbers for example, a selection of the numbers to be used is permissible.
- the scheme has the great advantage that no extra symbol need be introduced and the proof digit is treated exactly as the others, no separation from the normal digits or special sign being necessary.
- the first 45 decimal numbers which satisfy For all the numbers above, the last digit is always nonsignificant in so far as the designation conveyed by the number is concerned, but permits the checking of errors in transcription.
- the circuit shown could still be used, keycontacts for the eleventh symbol, e.g. the decimal point, being used to break the connection between P3 and'BS and that between stage 0 of counter GT and the ten decoupling means such as R and to drive BS BS andBS to the l-condition when the eleventh symbol is keyed.
- the number such as 267.4 would become 267.47 with the proof digit 7 on the extreme right and a wrong position of the decimal point would always be checked.
- any error. in transcription has 10 chances out of 11 to be detected. Any single wrong digit or any single transposition will always be detected if the number of digits forming a number is limited to 10. A skipped last digit will also be detected in all cases. Several consecutive digits which all suffer the same increase or decrease as a result of a transcription error, e.g. 234 becoming 345, will also be detected in all cases.
- the circuit can be used for an automatic determination of the proof digit. It is merely necessary for the operator to key the significant part of the number and by applying a suitable potential at terminal P one of the lamps L will be lit, indicating the value of the proof digit, e.g. if counter 0T has been left with the stage 7 on, lamp L, which is connected between terminal P and a suitable point of stage 7 will glow. The operator can then further key the proof digit, e.g.
- the embodiment shown carries the computation by means of counters on a dynamic basis as formula 16 is particularly well adapted to such a computation.
- counters using cold cathode tubes, and to a particular type of these, this is merely an example and other types of counters including electro-mechanical counters could also be used.
- Electro-mechanical counters should however be fast enough for the purpose and the use of step-by-step switches for instance, would be dependent on the keying speed desired and on the value of p.
- the bi-sta'ble circuits for example can be realized electronically as Eccles-Jordan circuits using vacuum or gas tubes, with electro-magnetic relays, or in any desired and suitable manner.
- Such details as the polarity of the pulses, the eventual need for pulse inverters, capacitive or DC. couplings, and shaping circuits have not been particularly mentioned, since they depend on the various elements which the designer will wish to combine in accordance with his requirements and facilities and in the manner in which these will be best used, e.g. anode or cathode outputs for vacuum tube circuits.
- the two-condition device BS permits the avoidance of the undesirable effects which contact vibrations, e.g. k would have on the state of the gates such as G If contact arrangements can be designed in such a way that no vibrations occur, then a trigger device such as BS becomes redundant.
- Iclaim 1. Calculating mcansto'calculate-a function "'wherea w i n) is onev of a set of associated numerical symbols, n+1, the number of symbols, p, a predetermined source having r times the frequency of said first source,
- Calculating means comprising a first ring counter and a second ring counter each having a predetermined plurality of stable'conditions, selective means for setting said second counter in a desired condition corresponding to a numerical symbol, means responsive to the release of said setting means for causing both said counters to step successivelyfrom one stable condition to the next stable condition until said first counter reaches a predetermined particular stable condition, means responsive to said first counter reaching said particular stable condition for thereafter altering said stepping means to cause said first counter to step successively from one stable condition to the next at a rate which is a predetermined multiple of the rate at which said second counter is stepped, means responsive to said altering means for thereafter stopping both said counters when said second counter reaches a predetermined particular stable condition, and means for indicating whether or not said first counter has stopped on said particular stable condition.
- Calculating means as claimed in claim 2, further comprising means for indicating at which stable condition the first counter has stopped.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
- Character Spaces And Line Spaces In Printers (AREA)
- Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
- Input From Keyboards Or The Like (AREA)
Description
May 12, 1959 M. LINSMAN CHECK SYMBOL APPARATUS Filed Jan. 28, 1955 Inventor M. Ll N SMAN United States Patent CHECK SYNIBOL APPARATUS Marcel Linsman, Liege, Belgium, assignor to International Standard Electric Corporation, New York, N .Y., a corporation of Delaware Application January 28, 1955, Serial No. 484,715 Claims priority, application Netherlands April 2, 1954 3 Claims. (Cl. 235-153) to be permanently associated with each group and such that it is a linear function of the normal symbols forming the group. To avoid a large number of different proof symbols the following type of function is used:
gb a p) where a; (lin) is a set of associated numerical symbols such as those forming a decimal number, b, (lin) is one of a group of predetermined fixed :integer coelficients and each characteristic of the position of a symbol in the group, n is the number of symbols and p is a predetermined fixed integer used as :a modulus so as to limit the number of different possible values of the function to p. For example, if the coefficients b (1 i 6) are respectively equal to 1, '2, 3, 4, 5, 6 for the digits of six-digit decimal numbers, starting from left to right, and if p=l1, the proof :symbol for 278498 will be given by In other words, 6 is the remainder after dividing 149 by 11. Thus, the number with its proof symbol can, for example, be written as 278498-6 by putting the proof symbol on the right. Then whenever the number is transcribed and there are possibilities of errors, the
function (1) can be computed from the transcribed digits and checked against the transcribed proof digit.
For the function given by (1) a transposition of two symbols of different values a, and a will produce an error which should be different from 0 (mod. p) in order to be detected, i.e.
. i i) r nm p) This means that for ranks between which a single transposition of two symbols should be detected, the respective coefficients b and bj for these ranks should be such that (3) will be satisfied, irrespective of the values of a, and a,-.
As mentioned above, the other most frequent error is a single wrong digit, and in such a case the corresponding change of the function given by (1) should also be different from 0 (mod.p), i.e.
2,886,240 Patented May 12, 1959 2 The succession of coeflicien'ts b; may take various forms other than that given in the above example, as will be explained later. Also various values of p are possible, some giving better results than others.
It is readily recognized that for decimal numbers a value of 11 for p is most suitable since and in such a case the coefficients b, (mod.p) should be chosen so that they all differ from one another if any single transposition of two digits has to be detected, and further, none of these coeflicients should be equal to 0 (mod.p) if (4) is to be satisfied, i.e. if any single digital error should also be detected. A value of 10 for p would also satisfy (5), but since 10=2 5, (3) and (4) could only be satisfied in certain cases, whatever coefficients b, are chosen. On the other hand, it is desirable to take the lowest possible value for p in order to limit the number of the different proof symbols, and also, since the function given by (l) is such that in order to calculate it, it will'at least be necessary to record p different symbols and the necessary recording equipment will increase as p increases.
Apart from transpositions between any two 'digits of a number, there remains the possibility of a transposition between a normal digit and the proof symbol. This may be just as likely to happen as an ordinary transposition, especially if the ordinary digits are also used for the proof symbols and, moreover, if it is possible to use the same keys for typing the proof digit as those used for typing the other digits. Some considerations on a possible transposition between the proof symbol and one of the ordinary symbols are given in the Belgian patent mentioned above, but the proof symbol is treated as a special case distinct from the other symbols.
This is not necessary, and if the proof symbol is treated exactly in the same way as the other symbols, it becomes implicity determined from FEE :12p,- (mod. p) (6) where F (the proof symbol) is a predetermined fixed integer, e.g. 0, p is equal to n+1, and since the n+1 coefficients b form a set of predetermined integer coefficients which include a coefficient for the proof symbol also. All these coefficients can be predetermined at will, bearing in mind the restrictions given above in relation to (3) and (4). Thus it is clear that in the case of p=11, it is possible to choose a group of ten different coefficients, numbered 1, 2, 9, 10, such that any single transposition of two digits (whether it includes the proof symbol or not) as well as any single wrong digit for a ten-digit number (including the proof symbol) can be detected, one of the ten coefficients being assigned to the proof symbol associated with the number.
In order to be able to detect such errors as mentioned above, any decimal number to be keyed should have a proof symbol permanently associated with it at all times when such errors can occur. As each digit a, of such a number would be keyed into a machine, this machine would compute the partial function:
Ina, (mod.p)
and when all digits including the proof symbol would have been keyed, the sum of these partial functions would be obtained so as to derive the check symbol F by taking the remainder of the division of the sum by p. If F is not obtained, a keying error has been made, such as those mentioned above. This means thatforeach of the digits to be keyed, different coefiicients b, must be chosen in accordance with the rank, and a device which can be termed a rank selector can be used, as in the said Belgian patent, to obtain the correct function (7) in accordance with the value of the digit and its rank. If the keying of numbers having a different number of digits is to be considered, the rank selector will have to make a total number of steps which varies as the number of the digits varies. In one case the rank selector would be left in one position after the keying of a number, while in another case it would be in another position after the keyingof another number having another number of digits, which means that the rank selector would have to be restored to normal after the keying of every number and would require as many positions as the maximum number of digits forming a number.
In the Belgian patent mentioned above, it has been mentioned that the coefficients b, can be chosen in such a way that they satisfy the relation where r is also a fixed predetermined integer. In other words, the coefiicients form a geometric progression of common ratio r such as 68,69 where r is equal to 6, or
when the residues with respect to 11 used as a modulus are taken. By this means it becomes possible to use a rank selector which has a certain number of difierent positions but which is closed on itself, so that after the keying of a number having an arbitrary number of digits, the rank selector will be left in some arbitrary position from which it can again be moved cyclically when the number is keyed. If F, in (6) which defines the proof symbol, is made equal to zero by a proper selection of coefficients b;, then it is immaterial in which position the rank selector stands when a number is keyed, e.g. with p=1l and r=6 and with a set of coefiicients b, to be explained later, if the number 278498-8 is keyed when the rank selector stands in the position corresponding to b,=1, then the calculated function F, using the coeflicients b, of (10), will be given by In the Belgian Patent No. 501,548, a rank selector is avoided altogether. An electro-mechanical relay recording device capable of occupying p distinct stable conditio'nsis used andas each digit a, is keyed, the recorder moves from its previous condition F,- to a new condition F, in accordance with the predetermined relation If the recorder is originally in a predetermined condition, i.e. the zero condition, as the digits a a a,, a of a number are keyed, it will be moved to the conditions which last condition is of the form given by (6). The
' computations, i.e. the changes of conditions for the recorder, are carried out in a static manner, in the sense that the recorder is not a cyclic counter, and by means of a; matrix of I suitably interconnected contacts.
4 In the Belgian Patent No. 503,715 a similar arrangement is used for the special case where p=ll and r=l0. If one generalizes this example to the particular case of r being equal to p1, the Relation 13 then becomes i i i1) For the sake of comparison it can be remarked that in case of the Belgian Patent No. 501,525 the relation corresponding to 13 and 14 is but a rank selector is necessary to choose the correct coeflicient b and in this patent the recorder is a cyclic counter.
An object of the invention is to calculate a function F (the proof symbol) of the form given by (6) and where the coefficients b (0 i n) are of the form given by (8), by using a recorder with p stable conditions in a novel and advantageous manner.
In accordance with a characteristic of the invention, as each numerical symbol, such as a,, is keyed, the recorder moves from its previous condition F, to a new condition F in accordance with the predetermined relation i i-1+ i) -P) In this manner, as the digits a a a,, a of a number are keyed, the recorder will be successively moved to the condition ra r(ra +a (mod. p) 2 r"-='a,-(rnod. p), EM -m-(mod. p)
which last condition is of the form given by (6).
In accordance with a further characteristic of the invention, a first and a second electrical ring counters both with p stable conditions, a first pulse source and a second pulse source having r times the frequency of the first one are provided, and upon the second ring counter being set in a condition a, corresponding to the numerical symbol a, while the first ring counter is in a condition F,- the first and the second counter are both driven by the first pulse source until they respectively pass through the conditions 0 and (F,- +a,) (mod.p) which O-condition of the first counter causes a two-condition device to be displaced from its first to its second condition, thereby causing the second pulse source to drive the first counter while the second counter remains driven by the first pulse source until the first and second counters respectively reach their r(F,- +a,-) (mod.p) and O-conditions which last condition, in conjunction with the two-condition device in its second condition, causes the disconnection of said pulse sources from said counters which remain in the conditions attained.
The above mentioned and other objects and characteristics of the invention will be better understood from the following description of an embodiment to be read in connection with the attached figure, which represents an electronic circuit permitting the checking of decimal numbers to determine if they have been correctly keyed, and which can also be used to determine which additional digit should be associated with the normal number in order to permit such a check.
Shown in the figure is the ring counter CT which is represented as a rectangle divided into into eleven squares each indicating a possible stable condition or stage of the counter. The stages are successively numbered from 1 to 9, 10, 0 which last stage is coupled back to the first stage 1 as shown. This counter will permit-the finding of residues with respect to 11 used as a modulus of functions fed to it by way of pulses, the number of pulses characterizing the function. A lead is shown to be con nected to all the stages of the counter and it is on this lead that the pulses will be applied, each pulse causing the counter to step from one condition to the next, eg. from condition 5 to condition 6. As to counters which permit the achievement of this shift, reference is made to the United States Patent No. 2,649,502, issued August 18, 1953, where a suitable counter using a cold cathode tube for each stage is described.
A second counter GT which can be of the same type indicating that no keying error has been made and that one can proceed with keying the next number, while -1 is used to indicate the corresponding condition of a counter or of a bistable device, an unblocked gate or 8.
contacts k k k corresponding to the decimal digits 0, 9 1 are all in the break condition as shown. In the table, 0 is used to indicate the corresponding condition of a counter or of a bistable device, a blocked gate or an as the first, also has eleven stable conditions or stages :5 closed make contact, or an OK. signal. If digits of a successively numbered from to 2, 1, 0, which last number have already been keyed, the original condition stage is coupled back to the first stage 10 through a gate F, for counter CT represents a sum (mod. 11) of G which is shown as a circle with the input and output partial functions of the type given by (7) e.g. if the first leads in line and pointing towards the center of the circle. six digits of the number 278498-8 have already been A control lead also pointing towards the center is used 10 keyed, the counter CT is now in the to appl potentials which will either block or unblock the gate? The open arrow at the end of the control lead 2(8)+4(9)+8(4)+5(8)+10(7)+9(2) 212=3 is used to indicate that the gate G is normally blocked. (mod. 11)th condition, as will be understood from the The reason for using the gate will appear later, but duroperations which occur as a result of the depression ing most of the operations it will be unblocked, so that 15 and release of a digit key. Counter CT is in the O-con- CT will in efiect be a ring counter, as is CT The closed dition due to previous keying. The additional horizontal arrow at the control leads of gates G and G indicate lines in the O-squares of the counters CT and CI, indithat these gates are normally unblocked and are blocked cate preferred conditions. In other words, when the by a potential on the control lead. circuit is placed in the operative condition, the start cir- A lead is also connected to all the stages of CT and cuit should put these stages on, e.g. the corresponding each pulse appearing at terminal P connected to this lead cold cathode tubes should be ionized. will drive the counter CT from one condition to the The bistable devices BS and BS which are of the twonext. This terminal P is connected to the output of 21 input (shown on the long sides of the rectangle) type are bistable electronic device BS e.g. a bistable multiviin the O-condition. The gates G and G are unblocked brator, represented by a rectangle divided into two squares 25 and a signal is applied tothe gate G Bistable device 1 and 0 representing the two stable conditions. The de- BS should initially be in the l-condition, except when an vice BS, is driven by the pulses appearing at the output incorrect number has just been keyed. The notation 0/1 of gate 6,, which is of the same functional type as G is therefore used. The gates G G G and G are and whose input is connected to terminal P at which blocked, while the gates G and G are blocked or unpulses of a suitable repetition frequency are constantly blocked depending on the conditions of BS and CT; delivered. As represented, G is normally blocked, but respectively. No O.K. signal is delivered, since this when it is unblocked, as will be explained later, B8,, is is controlled by a shift key (not shown) which should continuously driven from one condition to the other and be operated only after a full number has been keyed. pulses appear at terminal P at half the frequency of Contacts s and s of this shift key appear on the figure. those fed at terminal P to drive GT When gate G Upon the operation of a digit key, such as K which which is similar to gate G is unblocked, these pulses is the check symbol for the number assumed, the various appearing at terminal P are also applied to GT On conditions of the elements will be as shown in the second the other hand, when gate G which is similar to gate row (k=1). Through the make contact, such as k; G is unblocked, the pulses appearing at the output of and the break contacts k and k a suitable negative po- G; will be applied to CT tential present at terminal P will be applied to the cor- Before continuing the description of the circuit, it will responding stage, such as 8, of the counter GT and be assumed that the counter CT, is originally set in the through the corresponding decoupling means R to the arbitrary condition F,- (0 F 10) and that the 1 inputs of the devices BS BS and BS which all move counter CH is set in its O-condition. Immediately below, to their 1 conditions. Gate G will now be unblocked, a table gives the sequential operations which occur from while gates G and G are blocked. Gates G and G the moment that one of the ten digit keys (not shown) are also unblocked. The potential at terminals P, is also constituting a digit selector is depressed actuating a corapplied to stage 0 of GT and will be assumed to cause responding contact such as k this stage to return to the o condition. If the counter CT; GT9 BS1 BS: BS3 Gila a G415 Ga G7 G8 OK i=8 8 8 8 8 8 8 8 8 8 88 8 k= H a; 1 0 1 1 1 0 1 1 0 1 0 Fd-l'iaiy ll 0 3- }0 o 1 1 o 1 1 1 0 o zgggf'f 0 0 0 1 o 0 1 0 1 1 0 3=1 zhfigfl f o 0 o 0 o 0 1 0 0 1 0 F:-1+a1=11 8 8 8 8 8' 8 8 l 8 8 8 8 s=1 o 0 o o 1 0 0 1 0 1 o 1 In this table, the first two columns refer to the states GT is realized by means of cold cathode tubes, one for of the counters CT and GT respectively, the next three each stage, as detailed inthe United States Patent No. to the states of the bistable devices BS BS and BS 2,649,502, this can occur by way of decreasing the anode the next 5 to the States of the gates 1 2 3 4, 5, potential of the tube forming the stage 0 to such an G G and G and the last column to the potential at extent that this tube can no longer conduct and its the OK. terminal. As G G and G G are respectively anode-cathode gap is deionized. controlled from the same points, one column for each pair On the other hand, to put the required stage in the on is sufficient. The row k=0 indicates the initial condicondition, the potential from terminal P may be applied tions, when none of the keys are operated and the key to the anode of the tube immediately before the one to be ionized. This will cause a momentary drop of potential at the anode of the preceding tube and when the digit key is released, the corresponding increase of potential at the anode will be transmitted via a capacitive coupling. open make contact, or the absence of an OK. signal, to the grid of the tube to be ionized. This tube, e.g. off
defined by the third row (k=) of the table.
counter GT The release of the digit key brings a state of'a'fiairs BS2 is driven in its O-condition and as the gate G conducts, the gates G and G are also made conductive. For the tube forming stage of counter CT- the grid should be coupled to the anode supply via a capacitive and" resistive coupling identical to those between successive tubes. This is because it cannot be coupled to the anode of the tube forming stage 0 when the gate G is blocked. Make contact k should be connected to the point of thisspecial coupling corresponding to a fictitious anode,
soon-as the correct tube has been ionized in response to the displacement of a key, the pulse which will come through to the grid of the tube forming stage 10 when the gate G is unblocked will be unable to fire this tube.
From the moment that the gates G and G are unblocked, the counters CT and CT will both be driven by the pulses at terminal P In the case where F +a,- ll, a state of affairs, as defined by the fourth row of the table, will be attained when CT reaches condition 0. BS will move to the O-condition, G and G will be blocked, G and G will be unblocked. At this moment CT is in condition (F,- +a,-) (mod. 11), as can be easily verified.
From then on, pulses will continue to be applied from terminal P to GT but GT will be drivenby the pulses from terminal P through gates G and G in series. As these last pulses have twice the frequency of the former, conditions shown on the fifth row of the table will now be reached. Counter GT reaches the O-condition. This blocks the gate G and thereby the gates G and G which means that the counters are no longer driven. Counter CT, is now in condition 2(F,- +a,-) (mod. 11).
Apart from counter CT which has moved from condition F,- to condition 2(F, +a,-') (mod. 11), the
circuit is back to the initial conditions expressed on the first row of the table and the next digit can be keyed or the shift key can be operated to permit the keying of the next number. B8,; is left in its l-condition which permitted GT to reach condition 0 due to the low potential at terminal P having pemitted the last tube of GT to fire.
If F +a =11, instead of going from the condition of the third row of the table to those of the fourth, the condition defined in the eighth row will be reached, since CT, and GT will simultaneously reach the O-conditions and stay there, provided gate G is unblocked with sufficient rapidity so that the gates G G and G are blocked before the next pulse at P has an opportunity to drive CT and GT Otherwise CT would be driven a full cycle and GT two 'full cycles and would then remain in their O-co-nditions.
Supposing, for example, that F, is equal to 3 and a,- is equal to 8, as in the case of keying the last digit (the proof digit) of the number 27 8498-8. Counter GT will be brought to its O-condition.
It is clear that the keying of every digit of an n-digit number will each time result in a similar modification eg 3 in the case of the number 278498. Then, the
keying of the proof digit, e.g. 8, will bring CT 1 to the condition The operation of the shift key will close contact s, whereby the circuit conditions will now be as defined on the .ninthrow (s=1) of the table, i.e. unchanged with respect to those of the previous row, except that the O.K. signal will appear at the corresponding terminal from the O-stage of CT through the unblocked gate G and the closed contact s. This OK. signal can be used in any desired manner to permit the keying of the next number.
In this respect reference can for example be made to the United States Patent No. 1,334,316.
If the shift key is depressed when counter CT is not in its O-condition, a state of affairs, as defined on the sixth row of the table, will be reached. .Device BS will be driven to its 0 condition by a pulse at terminal P passing through the unblocked gate G the closed contact s and the decoupling means R Hence, gate G; will be blocked. Simultaneously, this and further pulses will be applied through the decoupling means R to the counter CT which will be driven to its O-condition for which gate G will be blocked. These conditions are to be found on the seventh row of the table. Thus, despite the closure of contact s, an O.K. signal will not be delivered. The fact that BS is in the O-condition indicates a mistake and can be .used in any desired manner to indicate to the operator that she should repeat her keying. The circuit is now ready for the repeated keying.
It will be observed that in the embodiment described, a value of r==2 has been chosen. This is, of course, not essential, but in the case where only a single source of pulses is available a frequency divided, such as BS or a [frequency multiplier must be used, and these will generally be simpler when r=2. The frequency of the pulses will be chosen so that it is compatible with the keying speed. A frequency of 10 kc./s. for the pulses at terminal P appears amply suflicient.
Some general considerations on whether a particular value of r will produce a group of p-1 distinct numbers from 1 to p-l, such as the group given by (10) where 1:6 and 2:11, can be given. If such a group is :not produced, it means that there will be less than p-l diiferent b coefiicients and not all single transpositions will be checked if the number .of digits of the number (including the proof digit) is greater than the number of different coefficients. First of all it will be observed that the same coefficients may be obtained in one particular order from (8) or in the reverse order from where r is some other common ratio. Relations 8 and 17 immediately give the relation between r and r as i.e. r is the inverse of r. When p=11 the various posobtained'with'r equal to 2 or 6. A well known theorem states that rrzl (mod. p)
q sl (mod. p) (20) when p and q are integers, p is prime and q isynot a multiple of p. Although p need not necessarily beprime for the purpose envisaged in this application, prime numbers such as 11, will nevertheless be advantageous,
as will be clear from the beginning of this description.
When p (p 4) is prime, p1 can be decomposed into prime factors. If P is any one of these factors, one
can write (WV-E p) Obviously, I and p-1 are unsuitable values for r, the last since (pa-U 51 (mod. p) .(22)
Consequently, for p=11, values of 1, 3, 4, 5, 9 and 10 will not produce a group of 12-1 different coefiicients. Values of 2 or 6 and 7 or 8 are suitable in this respect. A value of 2 would still be suitable with p=l3, since 2 and its inverse 7 are not exact powers. It would not be suitable with p=17, since its inverse 9 is a perfect square and 2 is a factor of 16. Of course, when the number of digits exceeds p--1 some transpositions cannot be checked, but these correspond to digits having: p2 digits between them and are the most unlikely. In any event a group of p -l different coefficients is the most efficient solution.
It should be observed that the, circuit shown includes only ten digit keys, which are used for the normal digits and for the proof digit, although there are eleven possible values for the proof digit. This is because the eleventh value for the proof digit is never used. Since the keying of a is made to correspond to 10, whereas the keying of any other digit corresponds to the digital value keyed, this eleventh value which is not used is the 0. Therefore, all normal numbers which would require a true 0 as a proof digit should not be used, since no sign is available for a true zero. For example, the normal number 19 would require a true zero as a proof digit, since 2(1)+1(9)=11-=-0 (mod. 11), and therefore cannot be used as such. However, the normal number 1 will require 9 as a proof digit and therefore, 19 will nevertheless be used, but as 1 followed by the proof digit 9. Such a scheme evidently cannot be applied when all numbers have to be used, e.g. numbers on which calculations are to be performed. But for numbers which represent a designation such as bank account numbers for example, a selection of the numbers to be used is permissible. On the other hand, the scheme has the great advantage that no extra symbol need be introduced and the proof digit is treated exactly as the others, no separation from the normal digits or special sign being necessary. By way of illustration, the first 45 decimal numbers which satisfy For all the numbers above, the last digit is always nonsignificant in so far as the designation conveyed by the number is concerned, but permits the checking of errors in transcription.
Evidently, when all numbers have to be used, an extra symbol should be made available for the eleventh proof digit. It may also happen that even with decimal numbers, an eleventh symbol is already used and available,
e.g. the decimal point. With eleven normal symbols, the circuit shown could still be used, keycontacts for the eleventh symbol, e.g. the decimal point, being used to break the connection between P3 and'BS and that between stage 0 of counter GT and the ten decoupling means such as R and to drive BS BS andBS to the l-condition when the eleventh symbol is keyed. In such a case, the number such as 267.4 would become 267.47 with the proof digit 7 on the extreme right and a wrong position of the decimal point would always be checked.
In general, with p=11, any error. in transcription has 10 chances out of 11 to be detected. Any single wrong digit or any single transposition will always be detected if the number of digits forming a number is limited to 10. A skipped last digit will also be detected in all cases. Several consecutive digits which all suffer the same increase or decrease as a result of a transcription error, e.g. 234 becoming 345, will also be detected in all cases.
Although the proof digits to be initially associated with the numbers can be easily calculated in any desired way, and for example in the case of bank account numbers there would be n'odifliculty in tabulating the ac, count numbers, as shown partially above, the circuit can be used for an automatic determination of the proof digit. It is merely necessary for the operator to key the significant part of the number and by applying a suitable potential at terminal P one of the lamps L will be lit, indicating the value of the proof digit, e.g. if counter 0T has been left with the stage 7 on, lamp L, which is connected between terminal P and a suitable point of stage 7 will glow. The operator can then further key the proof digit, e.g. 4, to bring GT to the 'O-condition and press the shift key to continue with the determination of the proof digit for the next number. In so doing, if the operator keys an incorrect proof digit this will be detected in the manner previously explained, so that an incorrect proof digit can never be assigned.
The embodiment shown carries the computation by means of counters on a dynamic basis as formula 16 is particularly well adapted to such a computation. Although reference has been made to counters using cold cathode tubes, and to a particular type of these, this is merely an example and other types of counters including electro-mechanical counters could also be used. Electro-mechanical counters should however be fast enough for the purpose and the use of step-by-step switches for instance, would be dependent on the keying speed desired and on the value of p.
It will therefore be appreciated that the figure shown can be realized in a multiplicity of ways, the bi-sta'ble circuits for example can be realized electronically as Eccles-Jordan circuits using vacuum or gas tubes, with electro-magnetic relays, or in any desired and suitable manner. Such details as the polarity of the pulses, the eventual need for pulse inverters, capacitive or DC. couplings, and shaping circuits have not been particularly mentioned, since they depend on the various elements which the designer will wish to combine in accordance with his requirements and facilities and in the manner in which these will be best used, e.g. anode or cathode outputs for vacuum tube circuits. It will be appreciated for example that the two-condition device BS permits the avoidance of the undesirable effects which contact vibrations, e.g. k would have on the state of the gates such as G If contact arrangements can be designed in such a way that no vibrations occur, then a trigger device such as BS becomes redundant.
Finally, how the various numbers, such as bank account numbers, are recorded has not been shown or described, as this has no particular bearing on the invention which relates to means for preventing errors in transcription. However, the checking arrangement shown could well be operated from the actually recorded numbers, so as to verify machine errors as well.
whiie theiprinciples of the invention have been described a'bove in-connection with specific apparatus, it is to be'clearly understood that this'description is made only by way of example and not as a limitation on the scope of the invention.
Iclaim: 1. Calculating mcansto'calculate-a function "'wherea w i n) is onev of a set of associated numerical symbols, n+1, the number of symbols, p, a predetermined source having r times the frequency of said first source,
means for successively setting said second ring counter in a condition a, corresponding to a numerical symbol and said first ring counter in a condition F means responsive to the release of said setting means for driving said f'firstand second counters by said first pulse source until "they respectively pass through the condition and Z(F, +a,) (modp), a two-condition device, means re sponsive to said first counter reaching said O-condition for causing said two-condition device to be displaced from itsfirst to its second condition, means responsive to said two-condition device being in its second condition for causing said second pulse source to drive said first counter while said second counter remains driven by said first pulse source until said first and second counters respectively reach their r (F -I-a (modp) and 0 conditions, and means responsive to said first and second countwith said two 'conditi'on device being in its second condi- 'tion, for'causing the disconnection of said pulse sources from said counters, whereby said counters remain in the condition attained.
2. Calculating means comprising a first ring counter and a second ring counter each having a predetermined plurality of stable'conditions, selective means for setting said second counter in a desired condition corresponding to a numerical symbol, means responsive to the release of said setting means for causing both said counters to step successivelyfrom one stable condition to the next stable condition until said first counter reaches a predetermined particular stable condition, means responsive to said first counter reaching said particular stable condition for thereafter altering said stepping means to cause said first counter to step successively from one stable condition to the next at a rate which is a predetermined multiple of the rate at which said second counter is stepped, means responsive to said altering means for thereafter stopping both said counters when said second counter reaches a predetermined particular stable condition, and means for indicating whether or not said first counter has stopped on said particular stable condition.
3. Calculating means, as claimed in claim 2, further comprising means for indicating at which stable condition the first counter has stopped.
References Cited in the file of this patent UNITED STATES PATENTS --Knutsen Aug. 21, 1956
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL777286X | 1954-04-02 | ||
NL2911149X | 1955-09-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
US2886240A true US2886240A (en) | 1959-05-12 |
Family
ID=32396399
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US484715A Expired - Lifetime US2886240A (en) | 1954-04-02 | 1955-01-28 | Check symbol apparatus |
US602857A Expired - Lifetime US2911149A (en) | 1954-04-02 | 1956-08-08 | Calculating means |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US602857A Expired - Lifetime US2911149A (en) | 1954-04-02 | 1956-08-08 | Calculating means |
Country Status (6)
Country | Link |
---|---|
US (2) | US2886240A (en) |
BE (1) | BE551084A (en) |
DE (1) | DE1101819B (en) |
FR (2) | FR1133374A (en) |
GB (2) | GB777286A (en) |
NL (4) | NL200526A (en) |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3028089A (en) * | 1959-10-19 | 1962-04-03 | David L Ringwalt | Delay line function generator |
US3029024A (en) * | 1956-04-11 | 1962-04-10 | Cornelis A S Hamelink | Checking system |
US3040985A (en) * | 1957-12-02 | 1962-06-26 | Ncr Co | Information number and control system |
US3055587A (en) * | 1958-11-24 | 1962-09-25 | Ibm | Arithmetic system |
US3089058A (en) * | 1956-09-11 | 1963-05-07 | Bell Punch Co Ltd | Totalisator system |
US3138701A (en) * | 1959-12-29 | 1964-06-23 | Ibm | Self-checking numbering devices |
US3163748A (en) * | 1961-11-21 | 1964-12-29 | Burroughs Corp | Data checking apparatus |
US3183482A (en) * | 1958-07-03 | 1965-05-11 | Sperry Rand Corp | Check digit verifiers |
US3186639A (en) * | 1961-04-13 | 1965-06-01 | Itt | Mechanically variable elements to calculate check symbols |
US3235716A (en) * | 1961-12-05 | 1966-02-15 | Ncr Co | Data entry checking apparatus |
US3304373A (en) * | 1962-03-30 | 1967-02-14 | Int Standard Electric Corp | Long distance tasi communication systems having answer-back signalling |
US3422250A (en) * | 1964-11-06 | 1969-01-14 | Sperry Rand Corp | Weighted hole count check for punch card equipment |
US3430037A (en) * | 1964-06-30 | 1969-02-25 | Philips Corp | Apparatus for checking code-group transmission |
US3431406A (en) * | 1958-07-03 | 1969-03-04 | Sperry Rand Corp | Check digit verifiers |
US3448254A (en) * | 1965-07-28 | 1969-06-03 | Anker Werke Ag | Data checking system |
US3484744A (en) * | 1967-02-14 | 1969-12-16 | Ultronic Systems Corp | Apparatus for verifying or producing check digit numbers |
US3525073A (en) * | 1967-12-04 | 1970-08-18 | Sylvania Electric Prod | Parity-checking apparatus for coded-vehicle identification systems |
US3531768A (en) * | 1965-01-27 | 1970-09-29 | Philips Corp | Circuit arrangement for calculating control characters for safeguarding series of information characters |
US3582636A (en) * | 1968-12-24 | 1971-06-01 | Philips Corp | Circuit arrangement for calculating a check digit |
US3778766A (en) * | 1971-12-29 | 1973-12-11 | Texaco Inc | Check digit calculator |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL255870A (en) * | 1960-09-14 | 1964-03-25 | ||
DE1295245B (en) * | 1964-08-14 | 1969-05-14 | Philips Patentverwaltung | Device for the calculation of check marks or for the addition of quotients in the number system of the remainder classes |
US3517385A (en) * | 1966-10-31 | 1970-06-23 | Tokyo Shibaura Electric Co | Code checking systems |
US4656633A (en) * | 1985-03-15 | 1987-04-07 | Dolby Laboratories Licensing Corporation | Error concealment system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2684199A (en) * | 1950-02-28 | 1954-07-20 | Theodorus Reumerman | Counting or number registering mechanism |
US2754054A (en) * | 1950-03-10 | 1956-07-10 | Willem H T Helmig | Devices for determining check symbols for symbol groups |
US2759669A (en) * | 1949-11-09 | 1956-08-21 | Bull Sa Machines | Error checking device for recordcontrolled accounting machine |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB709407A (en) * | 1947-06-26 | 1954-05-26 | Eckert Mauchly Comp Corp | Electronic numerical integrator and computer |
USRE24447E (en) * | 1949-04-27 | 1958-03-25 | Diagnostic information monitoring |
-
0
- NL NLAANVRAGE7709279,A patent/NL186474B/en unknown
- NL NL92399D patent/NL92399C/xx active
- NL NL92330D patent/NL92330C/xx active
- NL NL200526D patent/NL200526A/xx unknown
- BE BE551084D patent/BE551084A/xx unknown
-
1955
- 1955-01-28 US US484715A patent/US2886240A/en not_active Expired - Lifetime
- 1955-03-25 GB GB8854/55A patent/GB777286A/en not_active Expired
- 1955-04-02 FR FR1133374D patent/FR1133374A/en not_active Expired
-
1956
- 1956-08-08 US US602857A patent/US2911149A/en not_active Expired - Lifetime
- 1956-09-08 DE DEI12170A patent/DE1101819B/en active Pending
- 1956-09-14 GB GB28144/56A patent/GB817597A/en not_active Expired
- 1956-09-17 FR FR71938D patent/FR71938E/en not_active Expired
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2759669A (en) * | 1949-11-09 | 1956-08-21 | Bull Sa Machines | Error checking device for recordcontrolled accounting machine |
US2684199A (en) * | 1950-02-28 | 1954-07-20 | Theodorus Reumerman | Counting or number registering mechanism |
US2684201A (en) * | 1950-02-28 | 1954-07-20 | Theodorus Reumerman | Device for determining check symbols of symbol groups |
US2754054A (en) * | 1950-03-10 | 1956-07-10 | Willem H T Helmig | Devices for determining check symbols for symbol groups |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3029024A (en) * | 1956-04-11 | 1962-04-10 | Cornelis A S Hamelink | Checking system |
US3089058A (en) * | 1956-09-11 | 1963-05-07 | Bell Punch Co Ltd | Totalisator system |
US3040985A (en) * | 1957-12-02 | 1962-06-26 | Ncr Co | Information number and control system |
US3431406A (en) * | 1958-07-03 | 1969-03-04 | Sperry Rand Corp | Check digit verifiers |
US3183482A (en) * | 1958-07-03 | 1965-05-11 | Sperry Rand Corp | Check digit verifiers |
US3055587A (en) * | 1958-11-24 | 1962-09-25 | Ibm | Arithmetic system |
US3028089A (en) * | 1959-10-19 | 1962-04-03 | David L Ringwalt | Delay line function generator |
US3138701A (en) * | 1959-12-29 | 1964-06-23 | Ibm | Self-checking numbering devices |
US3186639A (en) * | 1961-04-13 | 1965-06-01 | Itt | Mechanically variable elements to calculate check symbols |
US3163748A (en) * | 1961-11-21 | 1964-12-29 | Burroughs Corp | Data checking apparatus |
US3235716A (en) * | 1961-12-05 | 1966-02-15 | Ncr Co | Data entry checking apparatus |
US3304373A (en) * | 1962-03-30 | 1967-02-14 | Int Standard Electric Corp | Long distance tasi communication systems having answer-back signalling |
US3430037A (en) * | 1964-06-30 | 1969-02-25 | Philips Corp | Apparatus for checking code-group transmission |
US3422250A (en) * | 1964-11-06 | 1969-01-14 | Sperry Rand Corp | Weighted hole count check for punch card equipment |
US3531768A (en) * | 1965-01-27 | 1970-09-29 | Philips Corp | Circuit arrangement for calculating control characters for safeguarding series of information characters |
US3448254A (en) * | 1965-07-28 | 1969-06-03 | Anker Werke Ag | Data checking system |
US3484744A (en) * | 1967-02-14 | 1969-12-16 | Ultronic Systems Corp | Apparatus for verifying or producing check digit numbers |
US3525073A (en) * | 1967-12-04 | 1970-08-18 | Sylvania Electric Prod | Parity-checking apparatus for coded-vehicle identification systems |
US3582636A (en) * | 1968-12-24 | 1971-06-01 | Philips Corp | Circuit arrangement for calculating a check digit |
US3778766A (en) * | 1971-12-29 | 1973-12-11 | Texaco Inc | Check digit calculator |
Also Published As
Publication number | Publication date |
---|---|
NL92399C (en) | |
BE551084A (en) | |
US2911149A (en) | 1959-11-03 |
NL200526A (en) | |
DE1101819B (en) | 1961-03-09 |
NL92330C (en) | |
NL186474B (en) | |
GB817597A (en) | 1959-08-06 |
FR1133374A (en) | 1957-03-26 |
GB777286A (en) | 1957-06-19 |
FR71938E (en) | 1960-03-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US2886240A (en) | Check symbol apparatus | |
US2615127A (en) | Electronic comparator device | |
US2697549A (en) | Electronic multiradix counter of matrix type | |
US2703202A (en) | Electronic binary algebraic accumulator | |
US3715746A (en) | Keyboard input device | |
US2861744A (en) | Verification system | |
US2749484A (en) | Function table | |
US2860327A (en) | Binary-to-binary decimal converter | |
US2851219A (en) | Serial adder | |
US3384902A (en) | Circuit arrangement for detecting errors in groups of data by comparison of calculated check symbols with a reference symbol | |
US3413449A (en) | Rate registering circuit | |
US3922587A (en) | Digital feedback relay controller | |
US2891237A (en) | Data processing apparatus | |
US2862660A (en) | Decimal converter | |
US3460117A (en) | Error detecting methods | |
US2761621A (en) | Electric calculating circuits | |
US2626752A (en) | Carry device for electronic calculators | |
US2794970A (en) | Identification of serial stored information | |
US2833476A (en) | Reversible counter | |
US3021066A (en) | Electronic calculator | |
US3278898A (en) | Data transmission system for distinctively modulating given datum bits for parity checking | |
US3512150A (en) | Linear systematic code encoding and detecting devices | |
US3353008A (en) | Calculating machine using pulse actuated counters | |
US3183482A (en) | Check digit verifiers | |
US3017091A (en) | Digital error correcting systems |