US2707590A - Electrical apparatus for adding numbers and registering the total - Google Patents

Description

May 3, 1955 R. E. SPENCER ETAL 2,707,590

ELECTRICAL APPARATUS FOR ADDING NUMBERS AND REGISTERING THE TOTAL Filed March 20, 1951 2 Sheets-Sheet 1 CARRY DE A) ,2?

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- ELECTRICAL APPARATUS FOR ADDING NUMBERS AND REGISTERING THE TOTAL Filed March 20, 1951 2 SheesSheet 2 F JANPJZ FROM 6 INVENTORS B 5 encer BY Tami; E Arrrs. Z

ELECTRICAL ArPARATus Fon ADDING NUM- snns AND REGISTERING THE TOTAL Rolf Edmund Spencer, Ealing, London, and Thomas Julius Rey, Hayes, England, assignors to Electric &

Musical Industries Limited, Hayes, England, a British 3 Claims. (Cl. 23561) This invention relates to electrical apparatus for adding numbers and registering the total.

It is known that the addition of numbers can be effected by a chain of cascade-coupled thermionic valve trigger circuits, each having two states of equilibrium, denoting the values nought and one. The trigger circuits correspond to successive binary digits and are arranged for stimulation by signals representative of a number to be added in such manner that a triggered device changes its state if the corresponding digit in the binary expression for the number has the value one. Moreover, when any trigger circuit reverts to state nought from state one it transmits a pulse representative of a carry which (except in the case of the last circuit of the chain) causes the succeeding trigger circuit to undergo a change of state. The state of the chain thus gives a binary indica tion of the total of numbers which have been previously added but since the chain operates inherently on a binary scale, it is difficult for the total registered to be dislayed in decimal notation, which is often desirable.

It has also been proposed in the R. C. A. Review of September 1946, page 441 et seq., to provide electrical counting apparatus which when fed successively with pulses representative of unity displays the total number of applied pulses in decimal notation. The proposed ap paratus operates on a mixed system of radices, known as the bi-quinary system, and for each decimal digit displayed there is a chain of three triggered circuits for setting up a quinary digit and a further trigger circuit for converting the quinary digit to a decimal digit. Each chain of three circuits has eight possible states but only five are required and so it is arranged that three of the states are prevented from arising, these states being said to be forbidden.

Considerable advantage could be obtained if the apparatus according to the latter proposal were capable of addition, that is if numbers not only equal to but greater than unity could be added to a previously registered number, as distinct from mere counting, that is finding the successor to a previously registered number, but difliculty is encountered due to the aforementioned forbidden states.

The object of the present invention is to reduce such difiiculty.

According to the present invention, there is provided apparatus for adding numbers and registering the total in a scale of radix M, comprising n trigger devices each having two states of equilibrium between which the devices can be caused to alternate on the application of triggering pulses, means coupling said devices in cascade to produce a series counter chain having 2 states, n being such that 2 is greater than M and the values 0 to M-l being assigned to M states of said chain, means for applying triggering pulses individually to the devices in said chain so that the addition of numbers equal to or greater than unity can be represented, the coupling means being so arranged that on the application of pulses representing a number less than M the chain initially changes to the correspondingly higher one of said 2 United States Patent C states and means are provided so arranged that, when the initial changes produce a state other than that whose assigned value represents the resultant total, a further change is produced to the last-mentioned state.

It is to be understood that, in apparatus according to the present invention, it will be necessary to take account of changes of the chain representing a carry to the next higher digital place in the scale of radix M, and when by operation of the last-mentioned means a change occurs from a state whose binary indication is higher than M, the state of the chain after the change will be that whose assigned value represents the resultant total taking account of the carry. It will also be appreciated that numbers having more than one digit in the scale of radix M can be handled by repeating the apparatus required to handle a single digit the appropriate number of times, suitable provision being made for dealing with carry signals.

In the preferred form of apparatus according to the present invention, the values 0 to (M1) are assigned respectively to the states of the chain whose binary indications are the same as the assigned numbers, and said last-mentioned means are so arranged that when the devices are changed to one of the remaining states or to 'a state which is reached by crossing the remaining states, a signal representative of (Z -M) is automatically applied to said devices.

In the application of the preferred form of the invention to apparatus in which there are three triggered devices in a chain as in the counting apparatus previously referred to, 2 would equal 8, M would equal 5 and the remaining, or so called forbidden, states would correspond to the numbers 5, 6 and 7.

Crossing the forbidden states implies the antecedent addition to an already registered number of another number such that the answer equals or exceeds 2 that is if four is added to the chain when it already registers four in the case of the above-mentioned chain of three devices.

In order that the said invention may be clearly understood and readily carried into effect, the same will now be more fully described with reference to the drawings in which:

Figure 1 illustrates symbolically, utilizing what is re ferred to as logical symbolism, one example of apparatus according to the present invention,

Figure 2 illustrates a modification of Figure 1,

Figure 3 illustrates a form of triggered circuit suitable for use in the apparatus of Figures 1 and 2,

Figure 4 illustrates a form of gate having threshold 1 suitable for use in the appaartus of Figures 1 and 2, and

Figure 5 illustrates a form of gate having threshold 2 suitable for use in the appaartus of Figures 1 and 2.

The logical symbols utilized in the drawings are de scribed in chapter 8 of Calculating Instruments and Machines by D. R. Hartree, published by the University of Illinois Press.

Referring to Figure 1, the units 11), 11 and 12 represent triggered circuits of the Eccles-Iordan type having two stable states of equilibrium, each circuit changing from one state to the other each time a pulse is received at its input. For example, the circuits 10, 11 and 12, except as regards the application of input pulses and the feedback connections which will be referred to subsequently, may be arranged as described with reference to Figure 6 in the article entitled Electronic Counters in the R. C. A. Review of September 1946, page 438. The circuits 10, 11 and 12 are arranged to receive information representative of numbers, of single digital significance in the scale of five. The received information is fed in binary code by means of connections 13, 14 and 15 to the circuits 10, 11 and 12 which correspond respectively to 2, 2 and 2 digits a pulse being fed to the respective circuit each time it is required to register a number in which the corresponding binary digit has the value 1. No pulse is received if the corresponding binary digit has the corersponding value nought. One of the two states of each of the circuits 10, 11 and 12 is referred to as the state nought and the other state as the state one and the end elements 16, 17 and 18 indicate that each of the circuits 10, 11 and 12 feeds out a potential excursion each time it reverts to its state nought. It will be appreciated that, with the arrangement disclosed in the R. C. A. Review aforesaid, the end elements have no separate identity, the feeding out of potential excursions with each reversion of the trigger circuit to state being an inherent property of trigger circuits of the Eccles-Iiordan type. The potential excursions from the end elements 16 and 17 are fed respectively to the circuits 11 and 12 as shown while the potential excursion from the cnd element 18 is, it will be assumed, fed to a further chain of triggered circuits which register the digit of next higher order. The highest input which, on operation of the circuit, will be fed to the circuits 10, 11 and 12 by the connections 16, 17 and 18 is four, or 001 in the binary scale where the binary expression is written so that digital order increases from left to right, and when any number from one to four is fed to the circuits 10, 11 and 12, these circuits undergo a change of state to the corresponding higher one of the eight states of the chain representing the addition of the respective number. The circuits can indicate values from nought to seven but since they are required to form a quinary register, values are assigned only to the states nought to four and the states five, six and seven are made forbidden states in a manner which will hereinafter appear. Moreover it will be assumed that the circuits 10, 11 and 12 are preceded by a further trigger circuit whereby the register is arranged to operate in accordance with the decimal scale of notation. However, for simplicity of description, the circuit will be described as operating according to a scale of five.

Connections 19 and 2% are provided from the outputs of the circuits and 11 to a gate 21 which feeds out a pulse if a pulse is received from either of the circuits 10 or 11 or both, that is the gate 21 has the threshold 1. This type of gate is commonly called an or gate. The output pulse from the gate 21 is fed to a gate 22 of threshold two, more commonly known in the U. S. as an and gate, the output of circuit 12 being also fed to the gate 22. If the gate 22 is stimulated, it feeds out a pulse in parallel to the inputs of the circuits 10 and 11, thus automatically adding three (110 in the binary scale) to the number registered by the chain of circuits. The addition of three by the stimulation of the gate 22 thus occurs if any of the (decimal) numbers five, six or seven is registered by the apparatus, and the register then changes automatically to the states representative of nought, one or two, respectively and the circuit 12 reverts to state nought feeding out a carry from 18, representative of five.

By virtue of a connection 23 through a gate 24 of threshold one with an inhibitor input terminal connected to the output of the gate 22, the occurrence of a carry from the end element 18 also causes three to be fed back in the form of pulses at the input of the circuits 10 and 11, unless inhibited by the stimulation of the gate 22. The gate 22 is connected to the inhibitor by a delay device 25 which ensures that the inhibition is delayed until the initial changes in response to pulses applied via 13, 14 and 15 have occurred, that is the inhibition is effective only if the carry is a direct result of the stimulation of 22, no further feedback being then permitted. In the present example such a situation can arise only if four is added when the circuits 10, 11 and 12 are already registering four (i. e. 001). The circuit 12 then reverts to state nought the end element 18 feeds out a carry, (that is the forbidden states five, six and seven have been crossed but not established) and three is added by feedback. The circuits 10, 11 and 12 finally register (+carry), namely eight taking account of the carry. Thus, the principle of operation of the example described is that if, as a result of the addition of a number, the chain changed directly to a state one, two, three or four, no further change is effected as a consequence of the addition. If on the other hand, the addition of a number other than zero changes the chain to a state whose binary indication is five, six, seven or nought, the chain automatically changes to the state whose indication is the transient binary indication less 5. It will be appreciated that the states whose binary indications are five, six and seven are forbidden states to which no quinary digit value is assigned, while state nought reached by crossing the forbidden states as the result of an addition, is a binary indication of eight which is different from the assigned quinary digit value. If the chain undergoes a transition to a forbidden state, or across the forbidden states, the gates 21 and 22, or 24, as the case may be, function as count-advancing means to cause the chain to register the total as a digit of radix 5, and the connection from 22 to 24 via 25 functions as means for inhibiting the gate 24 in response to stimulation of the gate 22.

In order to illustrate the operation of the apparatus, it will be assumed that three is registered and four is added.

The following sequence occurs:

1 1 0 three is registered 0 0 1 four is assumed to be added; 1 l l, i. e. seven is set up, hence the gate 22 Instead of connecting the gate 22 to the inhibitor of the gate 24, the same result can be achieved by connecting the gate 21 to the inhibitor of the gate 24, by a delay device. According to another modification, the inhibitor 24 is omitted entirely so that a carry from 18 will in every case tend automatically to add in three by feedback. However, it is arranged that the feedback path has such a recovery time that if the carry is a direct result of the stimulation of the feedback path, the carry is fed out of 18 before the feedback path has recovered to a condition in which it is capable of further stimulation.

The modification illustrated in Figure 2 is generally similar to the apparatus illustrated in Figure 1 except that feedback from the end element 18 is replaced by feedback to the gate 22 from the input connection 15 of the triggered circuit 12 through gate 27 having an inhibitor connection from the gate 21. The gate 22 is then stimulated when a forbidden state arises, that is when circuit 12 is in state one and either 10 or 11 or both are in state one, and it is also stimulated when the circuit 12 is in state one and four (001) is added. A delay device 28 allows for the finite settling time of the triggered circuits.

Other arrangements for carrying the invention into effect are also possible. For example, to allow for crossing a forbidden state a separate gate of threshold 2 could be provided arranged to feed in three when a carry is fed out of the end element 18, if a pulse has just been fed to the input of the triggered circuit 12. This can be achieved by making connections to the last-mentioned gate from the end element 18 and, via a delay device, from the input connection 15. When, as above-mentioned, the triggered circuits 10, 11 and 12 are preceded by a further triggered circuit, a delay longer than the time of settling of the chain 10, 11 and 12 must be provided between the preceding circuit and the chain, so that an incoming carry will always find the chain in a permitted state. A similar consideration applies to each stage of apparatus following the chain 10, 11 and 12. The additional trigger circuit for translating the register of the chain 10, 11 and 12 to a decimal digit may, if desired, follow the chain instead of precedingit.

The triggered circuit shown in Figure 3 can be used as any of the triggered circuits shown in Figures 1 and 2, and it also performs the function of the corresponding end element. In Figure 3, the circuit shown is assumed to represent the structural form of the elements 11 17, and it is also of the form illustrated in Figure 6, page 442 of the RQA Review, September 1946. The circuit comprises two valves 30 and 31 having their anodes and their control electrodes cross-coupled by resistance 32 to 38 and by capacitors 39 and 4%). The input from the proceeding triggered circuit is applied to the lower end of resistor 32 via capacitor 41, and the output is taken from the anode of the valve 31. Feedback to the circuit is applied to the control electrode of the valve 31 via capacitor 42 and resistor 43. Input signals on the lead 14 can be applied in the same way as the feedback, namely via capacitor 44 and resistor 45.

The gate shown in Figure 4, which may be used for the gate 21, comprises valve 46 whose control electrode is negatively biassed beyond cut-off via resistor 4'7. Signals taken from any suitable point are applied via diodes 48 and 49 connected as shown to the control electrode of valve 46. The input either from the circuit or the circuit 11 switches on the valve 46 and sets up an output signal at the anode of that valve. The gate shown in Figure 4 is of the construction illustrated in Figure 2 (H), page 112 of Electronics, September 1948.

The gate of threshold 2 illustrated in Figure 5, which can be used for the gate 22, comprises a hexode valve 50 having both control electrodes normally biassed beyond cutoff, so that an output can be set up at the anode only when input signals are applied simultaneously to the inner and outer control electrodes respectively. The gate shown in Figure 5 is of the construction illustrated in Figure 2 (A), page 112 of Electronics, September 1948.

The gate 24 can be of the same construction as that shown in Figure 5, arranged in such a way that the application of a signal to the outer control electrode will cause the valve 50 to conduct unless a signal is simuitaneously applied to the inner control electrode. The arrangement of a hexode valve in this way is described with reference to Figure 12, in U. S. patent specification No. 2,224,134 in the name of A. D. Blumlein.

The delay devices and 28 may be of conventional construction such as widely used in the radio art.

The invention is not restricted to applications in which the values nought to four (assuming a quinary register) are assigned to those states whose binary indications are the same as the assigned numbers. For example, the values nought to four may be assigned to those states whose binary indications are, respectively, nought, one, two, three, and six. The forbidden states are not then consecutive and the principle of operation is such that if the state four or five obtains or is crossed, two is added automatically, if state seven obtains or is crossed, unity is added in automatically.

It will be appreciated that other variations are possible.

What we claim is:

1. Electrical apparatus for adding numbers of single digital significance in a scale of radix M and registering the total, where M is greater than 2, comprising n trigger devices each having two states of equilibrium between which the device alternates on the application of successive triggering pulses to the corresponding device, means coupling said devices in cascade to produce a series-counter chain having 2 states of equilibrium, where n is an integer such that 2 is greater than M, means for feeding triggering pulses to said devices individually to represent the addition of binary digits of diiferent digital significances, count-advancing means coupled to said chain and responsive to a potential set up by a change of said chain to any one of 2 M predetermined states to feed triggering pulses to a selection of said trigger devices, further count advancing means coupled to said chain and responsive to a potential set up by a change of said chain across any of said 2 M states to feed triggering pulses to a selection of said triggering devices, and means responsive to operation of said first count advancing means for inhibiting said further count advancing means, said count advancing means being predetermined to register the count in said chain as a digit of radix M.

2. Electrical apparatus for adding numbers of single digital significance in a scale of radix 5 and registering the total, comprising three trigger devices each having two states of equilibrium between which the device alternates on the application of successive triggering pulses to the corresponding device, means coupling said devices in cascade to produce a series-counter chain having eight states of equilibrium, means for feeding triggering pulses to said devices individually to represent the addition of binary digits of different digital significances, count-advancing means coupled to said chain and responsive to a potential set up by a change of said chain to any one of three successive states to feed pulses representative of 3 to said trigger devices, further count-advancing means coupled to said chain and responsive to a potential set up by a change of said chain across said three successive states to feed pulses representative of 3 to said trigger devices, and means responsive to operation of said first count-advancing means for inhibiting said further countadvancing means, whereby said chain registers the totals as a digit of radix 5.

3. Electrical apparatus for adding numbers of single digital significance in a scale of radix 5 and registering the total, comprising three trigger devices each having two states of equilibrium representative respectively of 0 and 1 and between which the device alternates on the application of successive triggering pulses to the correspending device, means coupling said devices in cascade to produce a series-counter chain having eight states of equilibrium, means for feeding triggering pulses to said devices individually to represent the addition of binary digits of different digital significances, count advancing means coupled to each of said devices and responsive to a potential set up by simultaneous changes of the third device and of one other device in said chain to state 1 for feeding pulses representative of 3 to said trigger devices, further count-advancing means coupled to said third device and responsive to a potential set up by a change of said third device ta state 0 for feeding a signal representative of 3 to said trigger devices, and means responsive to operation of said first count-advancing means for inhibiting said further count-advancing means, whereby said chain is caused to register totals as a digit of radix 5.

References Cited in the file of this patent UNITED STATES PATENTS

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