US2461144A

US2461144A - Electrical storage device

Info

Publication number: US2461144A
Application number: US666024A
Authority: US
Inventors: John C Cook
Original assignee: Individual
Current assignee: Individual
Priority date: 1946-04-30
Filing date: 1946-04-30
Publication date: 1949-02-08
Anticipated expiration: 1966-02-08

Description

Feb. 8, 1949. COOK 2,461,144

ELECTRI CAL STORAGE DEVICE Filed April 30, 1946 v 27 JL II I 65 FIG. 2

' i j cRYsTAI. 'j E MEMORY LOCAL MIXER DISCR'MINATOR cIRouIT OSCILLATOR 6o 64 65 Ge 68 TUNABLE MAGNETRON TRIGGER PULSE MODULATOR SOURJE GENERATOR G2 GI 67 INVEI/TOR.

JOHN C. COOK ATTORNEY Patented Feb. 8, 1949 Hurrah stares PATENT OFFICE siisc'rnroenii aoii Device I John C. Cook, Afton, Wy0.,-assignor, by mesne assignments, to the United States of America as represented by the Secretary of War Application April 30, 1946; Serial No. 666,024

H 4 Claims. 1

This invention relates in general to electrical circuits, and, more particularly, to electronic devices known in the art as memory circuits.

When, in electronic and radio apparatus, it becomes necessary or desirable to provide a means of storing a voltage, a memory circuit is indicated. Due to the extent of their use, numerous forms of such circuits have been devised. The mai 'ority of these devices suffer from one or more disadvantages in' accordance with the specialization of their use.

It ie one purpose of the present invention to provide a memory circuit combining advantages separately obtainable with other memory circuits without their disadvantages.

Anothr'object is to provide a memory circuit particularly useful in pulsed radio transmission systems.

Further objects will be apparent to those skilled in the art in the course of perusal of the following specification.

The basic principle of a memory circuit comprises charging a capacitor rapidly through a low impedance path and allowing it to discharge relama slowly through a high impedance path. Iii this way, a voltage is maintained across the capacitor terminals for a relatively long period of time, and maybe used for comparison or contro'l purposes at any time before it has materially dissipated. Clearly, it is desirable to create as high a ratio of storage time to adjustment or chaigin'g' tinie'as possible. o accomplish this, the charging circuit must include a highcurrent generator of low efie'ctiveimp'edance, while the dischafge path must be of ashigheffective impedance as practicable, still allowing rapid dis charge or the memory capacitor under certain conditions. Briefly, the present invention accom: p'li slies these ends by employing pentode yaeuum rates as charge and discharge paths. Thereby,

" current c'afibe readily furnished y capacitor, and the effective impedance of the c'HargeariddiScliarge paths may be regulated at suitable voltages applied to grid electrodes or the vacuum tubes. It will be noted that the high impedance leakage paths from the memory capacitor during the storage period are obtained by' suitable screen g'rid' biasing.

The principles and operation of the present invention will be more apparent to those skilled in the art upon reference to the following specineat-ion and claims, to the drawings, in which:

Fig. 1 is a schematic diagram of one embodimerit of the invention; and

Fig. 2 is a block diagram illustrative of a pos--' sible application of the circuit of Fig. 1. 7

Referring now to Fig. 1, an embodiment of the invention employing similar pentodes 6; !2 in cascade connection; 1; e., the anode of one connected to the cathode of the other, is shown. Anode 5 of tube 5 is biased positively through droppin resistor l; which is connected to a power supply source of steady positive potential. A large-capacitor 8 is connected from anode 5 to ground, to bypass fluctuating currents around the power supply. Gathode ll] of tube Sis directly connected to anode H of tube l2; and memory capacitor I3 is tied from the junction to ground; Output terminal H! is provided in order that'the potential across capacitor l3 may be applied to other circuits; Cathode I6 of tube I2 is connected to arm I! of potentiometer l8; and bypass capacitor i9 is connected from cathode It to ground. One end. of potentiometer I8 is connected to a source of steady negative potential, andgthe other end is connected through resistor 21 to the afore-, mentioned positive bias source. Resistors l8 and 2!, therefore, form a voltage divider network between the positive and negative bias sources. A second direct current path between the positive and negative terminals (3+, B) is provided in potentiometer 22, arm 23 of which is connected through resistor 24 to screen grid 25 of vacuum tube 6; An input terminal 21 is provided to allow pulse voltages to be impressed on screen grid 25 through capacitor 28, and also through capacitor 29 to screen grid 30 of vacuum tube l2. Grid return resistor 32 is connected between screen grid 38 and the negative bias terminal;

Bias on control grid 35 and suppressor grid 36 of tube 6 is provided by a cathode follower circuit consisting of triode vacuum tube 38, anode 39 of which is connected directlyto the positive bias supply and control grid 40 ofwhich is tied to the junction between cathode it of vacuum tube 6 and anode I I of vacuum tube !2. Cathode 4| of tube 35 is connected through potentiometer 4? and resistor 43 to the nfigative bias terminal.

Arm 45 of potentiometer 42 is connected through grid resistor 46 to control grid 3501 Vacuum tube 5, and directly to suppressor grid 36 of the same tube. Signals may be applied to grid 35 through blocking capacitor 48 to which is connectedinput terminal 49. Control grid 5| of tube !2 is connected through resistor 52; to the negative bias terminal, and through blocking capacitor 53 to signalinput terminal 54. Suppressor grid 5 of this tubeis connected directly to the negative bias supply.

In operation, the bias potentials on the grids of tubes 6 and i 2 are adjusted so that practically no current fiows into or out of capacitor i3 when no signals are applied to control

grids

35 and 5!, whether or not positive activating potentials are applied to

grids

25, 30 as described below. This can be readily done by adjustment of potentiometers l8, 22 and 42. If, however, signals of opposite polarity are applied to

terminals

49 and 54, as illustrated by the small waveforms shown adjacent thereto, and, at the same time, screen grids 25 and are raised to a high potential by applicationof a positive-going voltage to terminal 27, current will flow into or away from capacitor !3 according to the type of signals on

terminals

49 and 54. In the case illustrated, vacuum tube 6 will conduct more heavily than will vacuum tube 12. hence, capacitor [3 will receive a higher charge than it had before. It can be readily seen that capacitor I 3 may be made to lose charge in a similar fashion. While best results are obtained when the input signals to

terminals

49 and 54 are opposite in polarity, the circuit is operative as long as there is a diiference in magnitude between the two signals, regardless of polarity.

Since cathode ll) of vacuum tube 6 is always at the potential of the more positive terminal of capacitor I3, it is necessary to provide means for adjusting the bias potentials on grids and 35 of that tube so that they will remain at the same relative potential level with respect to cathode l0. Hence, control grid of cathode follower tube 38 is connected to capacitor l3 so that the voltage across the resistors in the cathode line of this tube will vary in accordance with voltage across capacitor 13. Since the cathode follower has nearly unity gain, once arm of potentiometer 42 is set, a substantially constant potential differential will exist between the control and suppressor grids and the cathode of tube 6. The initial control grid bias on vacuum tube 12 is made by adjusting the arm of potentiometer I 8. No such special adjusting means is required for tube l2 since cathode I6 is at a relatively stable potential level.

To achieve optimum results tubes 6 and 12 should have a capacity for high plate currents of the order of several hundred milliamperes, high transconductance, and should be of multigrid. construction. This latter requirement is necessary to'make the plate current of tube l2 substantially independent of the potential across memory capacitor l3, and to provide for application of the accelerating voltages during active periods to the screen electrodes, thereby making possible a very low quiescent leakage current from the storage capacitor. The pentode vacuum tube of the type commonly known by the designation 6AG7 appears to be the best tube available for the purpose at the present time.

It can be seen that it is not absolutely necessary to have perfect coincidence between the signals applied to the control grids and signal applied to the screen grid in the pentode tubes. The circuit may be adjusted to accommodate continuous si nals on the control grids without causing change in the condition of the storage condenser until suitable accelerating screen voltages are applied.

To illustrate one application of the circuit which has been described above, reference is now made to Fig. 2. This figure is a block diagram of a pulse transmitting and receiving system in which the radiated frequency is continuously changed. .Since a. superheterodyne type of reception is employed, the local oscillator frequency must be adjusted in accordance with the transmitter frequency. The transmitting oscillator 60, which may be of the magnetron type, is rapidly and continuously tuned over a band of frequencies. A master trigger generator 5| triggers a modulator circuit 62 which pulses the oscillator, causing it to send bursts of oscillatory energy to antenna 53. These bursts of energy, when at least partially reflected from a distant object, are returned to antenna 63 during a time when the oscillator is quiescent. These returning signals are fed to a crystal mixer 54 where they are heterodyned. The intermediate frequency signal is passed through an amplifier-discriminator 65, the output of which is fed to the control grids of the pentode tubes in a memory circuit 66 of the type described with reference to Fig, 1. Accelerating voltages for the memory circuit are supplied by a pulse generator 6'! which is triggered by master trigger source M. The output of memory circuit 66, which is the voltage across the storage capacitor, is applied to the reflector electrode of a reflex oscillator tube which serves as the local oscillator 63, thus controlling its frequency. The output of oscillator 68 is fed to mixer 64. Successive transmitter pulses difier in frequency by a few megacycles per second. The automatic frequency control system which includes the penrode memory circuit adjusts the local oscillator frequency to nearly the correct value during each transmitter pulse, and holds this frequency setting for the interval between pulses, Since the energy pulses may be of the order of one microsecond duration, the importance of having a memory circuit with a quick adjustment time is clear. In its present embodiment, this circuit has a maximum rate of potential adjustment of the order of :2 volts per microsecond. In addition, smaller input error signals are required to yield given equilibrium output potentials than with other memory circuits in present use.

While there has been described above what is at present considered to be the preferred embodi ment of the present invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, Hence all such modifications and adaptations are claimed as fall fairly within the spirit and scope of the invention.

What is claimed is:

1. An electronic circuit for developing and storing electrical potentials in accordance with predetermined signal potentials of short duration comprising a first multi-grid vacuum tube having anode and cathode electrodes, a second vacuum tube similar to said first vacuum tube having its anode electrode electrically connected to the cathode electrode of said first vacuum tube,

a storage capacitor connected from the cathode of said first vacuum tube to a point of fixed potential, means for biasing the anode of said first vacuum tube positively with respect to said fixed potential, means for biasing the cathode of said second vacuum tube negatively with respect to said fixed potential, means associated with said positive bias means for biasing at least one grid of said first vacuum tube, cathode follower means for variably biasing at least one additional grid of said first vacuum tube, means for biasing the several grids of said second vacuum tube, means for impressing first signals on at least one grid of each of said first and second vacuum tubes,

means for impressing second signals on at least one grid other than the grid receiving said first signals in each of said first and second vacuum tubes, whereby when said first and said second signals are substantially coincident in time of arrival at said first and second vacuum tubes the amount of charge on said storage capacitor is altered in accordance with the type and magnitude of said first signals, and means for impressing the voltage across said capacitor after said alteration on an external circuit.

2. An electronic circuit for storing electrical potentials comprising first and second electron tube means, each having multigrids, an anode and a cathode, the cathode of the first electron tube means being electrically connected to the anode of the second electron tube means, a storage capacitor connected from the cathode of the first electron tube means to a point of fixed potential, bias means and means to apply bias to the multigrids and anode of the first electron tube means and to the multigrids and cathode of the second electron tube means, means for impressing first signals on at least one grid of each of said first and second electron tube means, means for impressing second signals on at least one other grid of each of said first and second electron tube means so that when said first signals arrive at said electron tube means within the effective period of said second signals the amount of charge placed upon and substantially retained by said storage capacitor will be altered in accordance with the type and magnitude of said first signals.

3. A memory circuit including a storage capacitor, first and second electron tube means, each having multigrids, an anode and a cathode, the cathode of the first electron tube means being connected to the anode of the second electron tube means forming a junction, a storage capacitor connected to said junction of said first and second electron tube means so that said first c electron tube means forms a charging path and said second electron tube means forms a discharging path for said capacitor, means for impressing first signals on at least one grid of each of said first and second electron tube means, means for impressing second signals on at least one other grid of said first and second electron.

tube means so that said second signals will open said charging and discharging path and said first signals, when arriving within the time of said opening will control the state of charge placed upon and substantially retained by said capacitor.

4. A circuit for developing and storing electrical energy comprising first and second electronic switch means responsive to at least first and second signals, a capacitor, means for serially connecting said first and second electronic switch means and connecting said capacitor to the said junction of said electronic switch means so that said first electronic switch means forms a charging path and said second electronic switch means forms a discharging path for said capacitor, means for applying first and second signals to said first and second electronic switch means, so that said second signals will open said electronic switch means and said first signals when arriving within the efieotive time of said opening will cause the charge placed upon and substantially retained by said capacitor to alter in accordance with the nature of said first signals.

JOHN C. COOK.

REFERENCES CITED The following references are of record in the file of this patent:

UNITED STATES PATENTS Number