US2437269A - Translating device and method of making it - Google Patents

Translating device and method of making it Download PDF

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Publication number
US2437269A
US2437269A US530419A US53041944A US2437269A US 2437269 A US2437269 A US 2437269A US 530419 A US530419 A US 530419A US 53041944 A US53041944 A US 53041944A US 2437269 A US2437269 A US 2437269A
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United States
Prior art keywords
layer
silicon
slab
current
making
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Expired - Lifetime
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US530419A
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English (en)
Inventor
Russell S Ohl
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AT&T Corp
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Bell Telephone Laboratories Inc
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Priority to BE476053D priority Critical patent/BE476053A/xx
Application filed by Bell Telephone Laboratories Inc filed Critical Bell Telephone Laboratories Inc
Priority to US530419A priority patent/US2437269A/en
Priority to CH266759D priority patent/CH266759A/fr
Priority to FR950513D priority patent/FR950513A/fr
Priority to GB21763/47A priority patent/GB639476A/en
Application granted granted Critical
Publication of US2437269A publication Critical patent/US2437269A/en
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Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • Applicant's method, thereore, makes it possible to prepare the silicon elements or wafers from available high-purity silicon material and to form on the surface thereof an extremely thin integrai high-impeclance layer having the desired rectification properties.
  • This thin surface layer has the relatively high electrical impedance essential to the desired recticatior performance, yet the thicimess ot' this surface layer is such a minute percentage of the thickness of the waer or element that its efiect on the total impedance is small,
  • Another feature of the invention is the method of making a translation element in which a highimpedance layer of desirecl thickness is formed on the rectification surface of a body, from which it is derived, composed of silicon containing a small percentage of impurities.
  • Another feature is a translating device includa body of silicon containing a small percehtage of impurities and having a thin crystallhe layer oi predeterminccl thiclness at the surilace thereof and a fine contact element making a contact with the surface of this crystal line layer.
  • l g. is a furnace for subjecting the silicon slabs 'for heattreatment
  • Fig. is a cross-sections] View, greatly enlarged, ilir the; the strata formed during the heat ut oi' the slab;
  • Fig. is an enarged View of the slab illustrating the acid treatment for removing the surface cmst;
  • 'Z is an eniarged assembly view of the translator
  • Figs. 8 and il are comparative Operating ch acterstics
  • V is the applied voltage.
  • e is the electronic charge,
  • m is the mass of the electron.
  • n is the maximum number of electrons available at the tungsten surface and is equal to the number of tungsten atoms at the surface layer multiplied by the number of valence electrons. which is a maximum of 6 for tungsten.
  • n e multiplied by the number of atoms per square centimeter multiplied by the area of the contact point
  • n 6NA
  • the approximate number of atoms per square centlmeter can be determined from the radius of a neutral tungsten atom which is given as 1.37 angstroms.
  • the measured diameter of the tungsten contactng area of rectiers of the type above mentioned was found to average about &lxwcentimeters.
  • V can not be measured directly because of the potential drop in the silicon itself, although it can be determined indirectly from the current-voltage curve. The point, no doubt, will have unequally divided currents due to surface irregularities. However, neglectirg the possibility of non-uniform current distribution. the greatest expected current which can flow at 2 volts will be about 78 millarnperes. Actually the unts show signs of impairment at lower current values, which is to be expected especially if the current density at the boundary is not uniform.
  • the first step in the process is to prepare an ingot of crystallized silicon of the positive type.
  • the ingot is prepared by iusing powdered silicon of a high degree of chemical purity in an electric 'furnace under carefully regulated conditions.
  • One suitable method of fusing these high-purity silicon ingots is disclosed in the application of J. Scai'f, Serial No. :386,835, filed April 4, 1941, Patent Number 2402582, datecl June 25, 1946.
  • the ingot is sha'ped into a block i of desirecl dimensions.
  • the dimcnsions of the slab 2 may be varied to suit the requirements, it may be explained that these slabs 'may have a thickness oi' l or 2 millimeters and a sidedimension of l or 2 centimete'z's.
  • the two large faces of the slab are given a preliminary smcothing ona cast-inoti lap with some suitable abrasive.
  • One of the fiat surface-s of the slab 2 is now fixed to the disc 3 by means ofshellac or other adhesive material.
  • the disc 3 is then lowcred into a polishing bath i. until the other flat surface of the slab 2 rests upon the surface of the polishing lap 5.
  • the lap 5, which is preferably of tin, is provided With a series of V-shaped concentric grooves and is rotated by the shaft 6.
  • the sha'ft i, to which the disc 3 is attached rotates in the same direction as the shaft E but at a. different speed and is also arranged to participate in an oscillatory movement as indicated by the arrow.
  • the bath 4 consists of any suitable liquids and abrasive materials.
  • the disc 3 and lap 5 By rotating the disc 3 and lap 5 in the same direction at different speeds and by introducing the oscillatory movement of the disc 3 the surface of the slab 2 is given an extremely smooth finish o' optical polish. 'In fact, when polished in this manner, it is found that the whole face of the slab does not vary more than :Vi wavelength of green light and is flmost perfectly free of any signs of scratches.
  • the next step in the' process is to subject the poished slab to a heat treatment To this end it is detached from the disc 3, cleaned, and placed in'the electric furnace 8.
  • the temperature of the heat chamber is carefully regulated I by thermostat 9 and is held at 1050 C., for the desired length of time.
  • a suitable atmosphere containing oxygen is maintained in the heat chamber throughout the period by means of inlet and outlet pipes ao and ii and by suitable external controlling apparatus.
  • Fig. 5 The effect of heating the slab 2 under these conditions is to cause the formation of a vitreous layer or crust of silicon dioxide, mingled with crystalline aggregates of silicon, over the polished surface.
  • This oxidized layer i shown highly magnified in Fig. 5, is derived by the chemical reaction between the silicon atoms from the body of the slab'and the oxygen atoms in the chambe' atmosphere. The silicon molecules move up through the body of the slab and concentrate at the surface Where some of them immediately combine with the oxygen atoms and form silica, which deposits on the surface. As the silica layer i? develops in thickness migrating silicon molecules continue to pass up through the silica layer until they reach the surface and join With the oxygen atoms in the chamber atmosphere.
  • the optimum temperature for producing this cilect is around 1050 C.
  • temperature the iormation of the high-impedance layer takes place at the surface of the slab without impairing to any great extent the optical asetet@ finish which was gven the polishihg process.
  • the silicon molecules appear so rapidly that buhhles form and physical irregularities cccur, imparing the finish of the surface and rendering the slab unsuitable for best rectication performance.
  • the thickness of the crystalline layer at the ootlcal surface of the slah and the thickness of the overiylng vitreous crust are functions of the time of the heat treatment.
  • the crystalline layer becomes thicher mel thicker and likewise the excess of silicon molecules at the surface comhincs with oxygen to progresslvely increase the thickness of the vltreous 'overlying crust
  • the time factor of the heat treatment therefore, :hay be utilized to control the electrical cl'aracteristics oi* the slicon slab.
  • appllcant has :found that a heat treatment of about four hours gives rectiying elements having excellent cha'acteristics for certain uses.
  • the layers thue iormed are illustrated roughly in Fig. 5.
  • the thi layer iii represents the slicon crystal concentratioi at opticai surfwe of the slah 2; and overlying layer i?? of silica is considerably
  • the next step in the process isto remove the vitreous layer ccvering the surface of the hoat treated slab to expose the surface layer.
  • the siab is immersed in a bath of hych'ofiuoric ac'd solution in a was: container l'l.
  • the which the vitreous layer i? is removed depeicls upon the co'scentration of the so mon.
  • suhstantlal thickriess consistlhg of silicoa a high degree of urity but containing a small percentage of impurities, including metallic elements such as alumizum and iron, a a thiri uroi-orari high-impedance surface of crystals with a finish that is extremely si'icoth.
  • the i' surface of the slab is how electro- ;olated with such as nickel, and the slab is cut small. individual elements or waters. C ne of these waters, for example the wafer is then soldered or otherwise aflixed to the stud i@ of the metallic base i@ (Fig. i). The stud is now screwed into the ceramic cylineier t. In a similar manner, the stucl which is integral with the cap 22, is firmy screwed into the opposite end of the cylnder' The cap contains a central bore for receivihg the cylindrical contact holder 23.
  • the holder is edjusted until the tip end of the tmgsten contact wire 26, the cpposite end of which is eoldered into the 'holder 23, makes contact the prepared surface of the wafer 323. a desired degree of force has been applied to the contact engagement of the wire i with the silcon wafer, the set screws 25 are tlghtenecl to sclze the holcler.
  • the high power-carrying capacity of this rectler makes it especially suitable for a number of applications.
  • One such use, illustrated in Fig. 10, is the generation of harmonic waves.
  • a generating circuit which is designed to suppress the flow of current throughout a large part of the cycle of the applied fundamental wave and to permit its flow for a brief interval during the more efiectlve portion of the wave has an output rich in waves of harmonic frequencies. This is particularly true if the generating clrcuit is capable of passing current during that portion of the 'undamental cycle when the wave is in the region of its maximum amplitude.
  • simple harmonc generating circuit including a source of fundamental frequency Zt, a rectifying unit 27, a load resistance 28, a condenser 29 and abiasng circuit 38.
  • the biasing battery 38 is poled in such a manner that it applies a negative biasing potential to the rectifier 2?.
  • the effect of this biasing voltage is to fix the zero line of the applied fundamental Wave at the proper point along the fiat portion 32, of the characteristic curve.
  • the method of 'making a translating device for electric waves of high requency which comprises forming a crystalline body of silicon having definite electrical characteristics and heat-treating said body to form on the surface therect a layer having electrcal characteristics which difier from those of the remaining part of said body.
  • the method of making a translating device for electric waves of high frequency which comprises forming a crystallne body of silicon having clenite electrcal characteristics and subjecting said body to heat treatment to form on the surface thereof a thin integral layer of material having electrcal characteristics which differ from those of the remaining part of said body.
  • the method of making a translating device for electric waves which comprises formng a body of crystailine silicon having a definite electrical impeclance, and heat-treating said body to form on the surface thereof a layer having a relatively high electrical impedance.
  • the method of making a translating device for electric waves which comprises forming a crystalline body of silicon, heat-treating said body to form on the surface thereof a thin layer of high-resistarce material, and fixing the duration and temperature of said beat treatment to control the thickness of said surface layer.
  • the method of making a translating device for electric waves which comprises forming a crystalline body of silicon having definite electr'cal characteristlcs and heat-treating said body to form on the surface thereof a thin layer of material derived from the body and having a, high electrlcal impedance.
  • a translator for ultra-high frequency elect'lc waves including a body of sillcon containing impurlties and having a thin integral layer of high electrica impedance at the surface thereof, and a 'fine conducting element making a. point con tact with said surface layer.
  • a translator for ultra-high frequency electric waves including a body of sllicon of a high degree of purty said body having a highly polished surface and a thin uniform crystalline layer at said polished surface, and a fine conducting elew ment making a point contact with said Crystal layer.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
US530419A 1944-04-10 1944-04-10 Translating device and method of making it Expired - Lifetime US2437269A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
BE476053D BE476053A (en, 2012) 1944-04-10
US530419A US2437269A (en) 1944-04-10 1944-04-10 Translating device and method of making it
CH266759D CH266759A (fr) 1944-04-10 1947-07-29 Procédé de fabrication d'un redresseur électrique.
FR950513D FR950513A (fr) 1944-04-10 1947-07-30 Dispositif de conversion
GB21763/47A GB639476A (en) 1944-04-10 1947-08-07 Improvements in electric wave translating devices

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Application Number Priority Date Filing Date Title
US530419A US2437269A (en) 1944-04-10 1944-04-10 Translating device and method of making it

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US2437269A true US2437269A (en) 1948-03-09

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US530419A Expired - Lifetime US2437269A (en) 1944-04-10 1944-04-10 Translating device and method of making it

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US (1) US2437269A (en, 2012)
BE (1) BE476053A (en, 2012)
CH (1) CH266759A (en, 2012)
FR (1) FR950513A (en, 2012)
GB (1) GB639476A (en, 2012)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2603692A (en) * 1945-12-29 1952-07-15 Bell Telephone Labor Inc Rectifier and method of making it
US2701326A (en) * 1949-11-30 1955-02-01 Bell Telephone Labor Inc Semiconductor translating device
US2864729A (en) * 1954-03-03 1958-12-16 Int Standard Electric Corp Semi-conducting crystals for rectifiers and transistors and its method of preparation
US2935453A (en) * 1957-04-11 1960-05-03 Sylvania Electric Prod Manufacture of semiconductive translating devices
US3036006A (en) * 1958-01-28 1962-05-22 Siemens Ag Method of doping a silicon monocrystal

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1058634B (de) * 1956-06-07 1959-06-04 Ibm Deutschland Gasdiffusionsverfahren zur Herstellung eines Transistors
DE1095401B (de) * 1958-04-16 1960-12-22 Standard Elektrik Lorenz Ag Verfahren zum Eindiffundieren von Fremdstoffen in einen Halbleiterkoerper zur Herstellung einer elektrischen Halbleiteranordnung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2603692A (en) * 1945-12-29 1952-07-15 Bell Telephone Labor Inc Rectifier and method of making it
US2701326A (en) * 1949-11-30 1955-02-01 Bell Telephone Labor Inc Semiconductor translating device
US2864729A (en) * 1954-03-03 1958-12-16 Int Standard Electric Corp Semi-conducting crystals for rectifiers and transistors and its method of preparation
US2935453A (en) * 1957-04-11 1960-05-03 Sylvania Electric Prod Manufacture of semiconductive translating devices
US3036006A (en) * 1958-01-28 1962-05-22 Siemens Ag Method of doping a silicon monocrystal

Also Published As

Publication number Publication date
CH266759A (fr) 1950-02-15
BE476053A (en, 2012)
FR950513A (fr) 1949-09-29
GB639476A (en) 1950-06-28

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