US20240014016A1

US20240014016A1 - Semiconductor processing apparatus for generating plasma

Info

Publication number: US20240014016A1
Application number: US18/472,267
Authority: US
Inventors: Chien-Hsiang Chen; Ching-Horng CHEN; Yen-Ji Chen; Cheng-Yi Huang; Chih-shen Yang
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-08-28
Filing date: 2023-09-22
Publication date: 2024-01-11
Also published as: CN112447482A; TW202109593A; US20210066054A1

Abstract

A Faraday shield, a semiconductor processing apparatus, and an etching apparatus are provided. The Faraday shield includes a plurality of conductive slices and a spacer interposed between adjacent two of the conductive slices to electrically isolate the adjacent two of conductive slices from one another. The conductive slices are separately arranged aside one another and oriented along a circumference of the Faraday shield. A coil is wound around the circumference of the Faraday shield.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of and claims the priority benefit of a prior application Ser. No. 16/928,008, filed on Jul. 14, 2020. The prior application Ser. No. 16/928,008 claims the priority benefit of U.S. provisional application Ser. No. 62/893,131, filed on Aug. 28, 2019. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Plasma technology is widely used in semiconductor manufacturing processes. For example, plasma etching is one etching technique that is commonly used for selective processing, forming fine-pitched pattern, photoresist stripping, or the like. A radio frequency (RF) coil may be utilized in the plasma etching system for supplying plasma-creating power, and plasma generated in the plasma etching system may react with a surface of a target (e.g., a wafer, any layer overlying the wafer, etc.) to create a byproduct that is removed, thereby yielding an etched surface of the target. As semiconductor devices are being scaled down, the complexity of integrated circuit manufacturing is increased. Although the existing technologies have been adequate for their intended purposes, they have not been satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor processing apparatus according to some embodiments of the present disclosure.

FIG. 2 is a schematic perspective view illustrating a state that a shield is installed according to some embodiments of the present disclosure.

FIG. 3A is a schematic perspective view illustrating a shield of a semiconductor processing apparatus according to some embodiments of the present disclosure.

FIG. 3B is a schematic enlarged view illustrating conductive slices of a shield according to some embodiments of the present disclosure.

FIG. 4 is a schematic enlarged view illustrating a dashed box outlined in FIG. 3A according to some embodiments of the present disclosure.

FIG. 5 is a schematic top view illustrating a shield and a coil of a semiconductor processing apparatus according to some embodiments of the present disclosure.

FIG. 6 is a schematic perspective view illustrating a shield of a semiconductor processing apparatus according to some embodiments of the present disclosure.

FIG. 7 is a schematic view illustrating a shield including a casing and a block before assembled according to some embodiments of the present disclosure.

FIG. 8 is a schematic perspective view illustrating a shield of a semiconductor processing apparatus according to some embodiments of the present disclosure.

FIG. 9 is a schematic perspective view illustrating a shield of a semiconductor processing apparatus according to some embodiments of the present disclosure.

FIG. 10 is a schematic perspective view illustrating a shield of a semiconductor processing apparatus according to some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
FIG. 1 is a schematic cross-sectional view illustrating a semiconductor processing apparatus according to some embodiments of the present disclosure. Referring to FIG. 1 , a semiconductor processing apparatus 100 includes an assembly utilized for generating plasma. In some embodiments, the semiconductor processing apparatus 100 is configured to perform plasma etching on a semiconductor workpiece. Alternatively, the semiconductor processing apparatus 100 is used to performed plasma processes including plasma enhanced chemical vapor deposition, sputtering, ashing, cleaning, etc.
For example, the semiconductor processing apparatus 100 includes a shield 110 surrounding a plasma-generating chamber 10, a coil 120 disposed around the shield 110 and connected to a power source 20, and a gas inlet 130 disposed at the upstream side 10 a of the plasma-generating chamber 10. In some embodiments, the coil 120 is coupled to the power source 20 and may have other end coupled to a ground 25. For example, the ground 25 is a grounding tab attached to a portion of the chamber lid, or some other conductor to ground. In some embodiments, the power source 20 provides radio frequency (RF) power to the coil 120 at a desired frequency to generate the RF current flowing through the coil 120. The plasma density may be controlled by the applied RF current or power delivered to the coil 120. An electric field may be generated in the plasma-generating chamber 10 based on time variation of the magnetic fields. The RF current generates the axial magnetic field B and the resultant azimuthal electric field E as indicated in FIG. 1 .
The high voltage applied to the coil 120 may yield the electrostatic field along the coil 120. For example, the electric field generated by the coil 120 ionizes the gas flowing from the gas inlet 130 to produce the plasma 30 in the plasma-generating chamber 10. It should be noted that the gas inlet 130 including pipelines and gas supply system is simplified in FIG. 1 for ease of illustration, and the gas (e.g., the inert gas, the processing gas, or the like) may be supplied from the gas inlet 130 for plasma generation. The term “plasma” used herein may refer to plasma products including ions, electrons, and neutral species, or the like. In some embodiments, generation of the plasma 30 is confined to the plasma-generating chamber 10 surrounded by the coil 120.
In some embodiments, the shield 110 is disposed on an exterior wall 10 w of the plasma-generating chamber 10 and located between the plasma-generating chamber 10 and the coil 120. The shield 110 may be referred to as a Faraday shield which plays an important role in optimizing the RF power efficiency. The improved RF power efficiency may facilitate producing high density plasmas in the plasma-generating chamber 10 for semiconductor processing, thereby increasing the productivity and the yield of the semiconductor manufacturing process. In some embodiments, the shield 110 has the shape of a circular cylindrical shell. In other embodiments, the shield 110 is formed in shape of hollow square column. The shield 110 may take various forms, and may be built in a variety of ways as will be described later in other embodiments. In the case of the shield 110 having a cylindrical shape, the coil 120 is wound into a ring shape, or wound in a helical manner to surround the shield 110. It should be noted that other types of the coil may be used in other embodiments, including without limitation, spiral coils in a flat plane or above the plasma-generating chamber 10, or other coils for inductively coupling power into the plasma-generating chamber 10.
In some embodiments, the semiconductor processing apparatus 100 includes a screen 140 disposed at the downstream side 10 b (e.g., opposing to the upstream side 110 a) of the plasma-generating chamber 10 for preventing the workpiece W directly exposed to the plasma 30. The screen 140 may be an ion screen and/or an ultraviolet (UV) light screen. For example, the plasma 30 flows through the screen 140, so that electrons in the plasma 30 may be repelled and positive ions may be collected. In some embodiments, the screen 140 serves as a baffle so that no energetic photons (e.g., UV light) can pass through the screen 140. In some embodiments, the screen 140 is separated the plasma-generating chamber 10 from a processing chamber 15. For example, below the plasma-generating chamber 10 is the processing chamber 15 in which is contained the workpiece W for processing.
In some embodiments, the plasma 30 passes through the screen 140 to the processing chamber 15 and reacts with a surface of the workpiece W to create a byproduct that is removed, thereby yielding an etched surface of the workpiece W. Any variety of other processes may be performed according to other embodiments. For example, the workpiece W is a semiconductor wafer or includes a semiconductor substrate on which a layer (e.g., a dielectric layer, a conductive layer, a semiconductor material layer, etc.) is formed. In some embodiments, a chuck 40 (e.g., an electrostatic chuck or the like) is provided in the processing chamber 15 for supporting the workpiece W when present. In some embodiments, a gas exhaust 150 is coupled to the processing chamber 15, and at least a portion of the reaction products are exhausted along with used reactant gas form the processing chamber 15 through the gas exhaust 150. It should be noted that the gas exhaust 150 including pipelines and pump or other exhaust system is simplified in FIG. 1 for ease of illustration.
FIG. 2 is a schematic perspective view illustrating a state that a shield is installed according to some embodiments of the present disclosure, where some elements of the semiconductor processing apparatus are omitted for ease of illustration, FIG. 3A is a schematic perspective view illustrating a shield of a semiconductor processing apparatus according to some embodiments of the present disclosure, FIG. 3B is a schematic enlarged view illustrating conductive slices of a shield according to some embodiments of the present disclosure, FIG. 4 is a schematic enlarged view illustrating a dashed box outlined in FIG. 3A according to some embodiments of the present disclosure, and FIG. 5 is a schematic top view illustrating a shield and a coil of a semiconductor processing apparatus according to some embodiments of the present disclosure, where the number of conductive slices of the shield is shown for illustrative purposes.
With reference to FIG. 2 , FIG. 3A, FIG. 3B, and FIG. 4 , the shield 110 includes a plurality of conductive slices 112 oriented along the circumference of the plasma-generating chamber 10 and substantially parallel to one another in a winding direction WD of the coil 120. It is understood that although the winding direction WD is illustrated as a counter-clockwise direction, the coil may be wound around the shield in a clockwise direction in other embodiments. In some embodiments, the conductive slices 112 are spaced and axially extending segments surrounded by the coil 120. For example, as shown in FIG. 3B, the respective conductive slices 112 have a length along a first axis A1 which is perpendicular to a second axis A2 that the coil 120 is disposed. For example, the first axis A1 is the Z axis. The conductive slices 112 may be any material or combination of materials provided they are conductive. For example, the material of the conductive slices 112 includes aluminum, iron, copper, silicon steel sheet, silver, gold, platinum, metallic alloys, combination of these, or the like.
In some embodiments, each of the conductive slices 112 has facets 112 s substantially parallel to the exterior wall 10 w of the plasma-generating chamber 10 (labelled in FIG. 1 ). Each facet 112 s of the respective conductive slice 112 may have a facet width defined by two side edges (1121 and 1122) extending along the first axis A1, where the first axis A1 is substantially perpendicular to the second axis A2 in which the coil 120 is wound. The facet width may be viewed as the thickness T of the respective conductive slice 112. In some embodiments, two opposing facets 112 s, which are respectively proximal to and distal to the exterior wall 10 w of the plasma-generating chamber 10, have approximately the same facet width. For example, the top surface or the bottom surface of the respective conductive slice 112 is formed in the shape of a rectangular (or square). In other embodiments, the opposing facets 112 s have different facet widths. For example, the facet width of the facet 112 s proximal to the exterior wall 10 w of the plasma-generating chamber 10 is greater than the facet width of the facet 112 s distal to the exterior wall 10 w of the plasma-generating chamber 10. For example, the top surface or the bottom surface of the first type of conductive slice 112 is formed in the shape of a trapezoid which is tapered in a direction away from the exterior wall 10 w of the plasma-generating chamber 10. Alternatively, the facet width of the facet 112 s distal to the exterior wall 10 w of the plasma-generating chamber 10 is greater than the facet width of the facet 112 s proximal to the exterior wall 10 w of the plasma-generating chamber 10. For example, the top surface or the bottom surface of the respective conductive slice 112 is formed in the shape of a trapezoid which is tapered toward the exterior wall 10 w of the plasma-generating chamber 10.
It is understood that the magnetic field intersecting the shield 110 produces eddy currents, and the eddy currents may consume power which produces losses due to a resistance of the shield 110. For example, during operation, each of the conductive slices 112 including the side edges 1121 and 1122 forms therebetween an eddy current as indicated by arrow ED. It is appreciated that the eddy current losses of the shield 110 are proportional to the square of the thickness T of the shield 110. It follows from the eddy current loss formula that the reduction of the eddy current losses is effective if the thickness T of the respective conductive slice 112 is small. For example, losses due to eddy currents may be minimized by a discontinuous or sliced shield, thereby efficiently generating the magnetic fields. In some embodiments, the thickness T of the respective conductive slice 112 ranges from about 0.01 mm to about 10 mm. It should be noted that the thickness T of the respective conductive slice 112 may be selected depending on the technique(s) that is employed to fabricate the shield 110 and/or the process requirements of the semiconductor processing apparatus 100.
In some embodiments, as shown in FIG. 3B, the shield 110 includes different types of conductive slices (e.g., 112 a, 112 b, 112 c, and 112 d) which are separately arranged and extend out radially from the center of the plasma-generating chamber 10. For example, one type of conductive slices (e.g., 112 a, 112 b, and 112 c) is of an approximately cuboid shape. In some embodiments, the first type of conductive slices (e.g., 112 a, 112 b, and 112 c) is of different lengths. For example, the facet 112 s of the respective conductive slice 112 has a facet length defined by a top edge 1123 and a bottom edge 1124 extending along the second axis A2 and connected to the side edges 1121 and 1122. The facet length may be viewed as the length L of the first type of conductive slices (e.g., 112 a, 112 b, and 112 c). In some embodiments, the first type of conductive slices (e.g., 112 a, 112 b, and 112 c) is of varying lengths. For example, the conductive slice 112 a located at the top of the shield 110 is shorter than the conductive slice 112 b located at the middle of the shield 110 and/or shorter than the conductive slice 112 c located at the bottom of the shield 110. In other embodiments, the lengths of the first type of conductive slices (e.g., 112 a, 112 b, and 112 c) are substantially the same or similar depending on the product requirements. It should be noted that the lengths L of the conductive slices 112 depend on the product requirement and construe no limitation in the disclosure.
In some embodiments, the shield 110 includes another type of conductive slices (e.g., 112 d). For example, the respective conductive slice 112 d is of a cuboid shape having a recess. For example, the respective conductive slice 112 d includes the elongated facet 112 s proximal to the exterior wall 10 w of the plasma-generating chamber 10 and more than one discrete facet 112 s distal to the exterior wall 10 w of the plasma-generating chamber 10. In some embodiments, the elongated facet 112 s and the discrete facets 112 s of the respective conductive slice 112 d are opposite to one another and the facet width of the elongated facet 112 s may be substantially equal to the facet widths of the discrete facets 112 s. Alternatively, the facet width of the elongated facet 112 s is different from the facet widths of the discrete facets 112 s. For example, the facet width of the elongated facet 112 s proximal to the exterior wall 10 w of the plasma-generating chamber 10 is greater than the facet widths of the respective discrete facets 112 s distal to the exterior wall 10 w of the plasma-generating chamber 10. For example, the top surface or the bottom surface of the second type of conductive slice 112 d is formed in the shape of a trapezoid which is tapered in a direction away from the exterior wall 10 w of the plasma-generating chamber 10. Alternatively, the facet width of the respective discrete facet 112 s distal to the exterior wall 10 w of the plasma-generating chamber 10 is greater than the facet width of the elongated facet 112 s proximal to the exterior wall 10 w of the plasma-generating chamber 10. For example, the top surface or the bottom surface of the respective conductive slice 112 d is formed in the shape of a trapezoid which is tapered toward the exterior wall 10 w of the plasma-generating chamber 10. The top surface or the bottom surface of the respective conductive slice 112 d may be tapered toward the same direction to the top surface or the bottom surface of the first type of the conductive slices (e.g., 112 a, 112 b, and 112 c). In other embodiments, the top surface or the bottom surface of the respective conductive slice 112 d may be tapered toward the opposing direction to the top surface or the bottom surface of the first type of the conductive slices (e.g., 112 a, 112 b, and 112 c).
In some embodiments, the first type of the conductive slices (112 a, 112 b, and 112 c) and the second type of the conductive slice 112 d are of the same or similar thickness to facilitate producing a uniform magnetic field. The respective conductive slice 112 d may include an upper portion, a lower portion, and a middle portion connected to the upper portion and the lower portion. The upper portion of the respective conductive slice 112 d may have the same or similar shape(s) to the conductive slice 112 a located at the top of the shield 110, and the lower portion of the respective conductive slice 112 d may have the same or similar shape to the conductive slice 112 c located at the bottom of the shield 110. The middle portion of the respective conductive slice 112 d may be longer than the conductive slice 112 b located at the middle of the shield 110. In some embodiments, the conductive slices (112 a, 112 b, and 112 c) are separately arranged along the first axis A1, and the total length of the respective conductive slice 112 d is greater than the total length of the conductive slices (112 a, 112 b, and 112 c). The total length of the conductive slice 112 d may be considered as the height of the shield 110.
In some embodiments, the conductive slice 112 d may be configured to adjoin with the conductive slices (112 a, 112 b, and 112 c). For example, the conductive slice 112 d is substantially parallel to the conductive slices (112 a, 112 b, and 112 c) which are discontinuously and vertically arranged. In an embodiment, the first type and the second type of the conductive slices 112 are alternately arranged along the circumference of the plasma-generating chamber 10. In some embodiments, a group of the first types of the conductive slices 112 and a group of the second types of the conductive slices are configured in a repetitive arrangement, where the group of first types of the conductive slices includes the conductive slices (e.g., 112 a located at the top of the shield, 112 b located at the middle of the shield, and 112 c located at the bottom of the shield) separately arranged along the circumference of the plasma-generating chamber 10, and the group of the second type of the conductive slices includes the conductive slices 112 d separately arranged along the circumference of the plasma-generating chamber 10. Alternatively, the first type and the second type of the conductive slices 112 are arranged in non-repetitive patterns such as random patterns.
In some embodiments, a width (e.g., W and W′) of the first type of the conductive slices (e.g., 112 a, 112 b, and 112 c) is a distance of the side edge 1125 extending along a third axis A3, where the third axis A3 is perpendicular to the first axis A1 and the second axis A2. In some embodiments, the conductive slices (e.g., 112 a and 112 c respectively located at the top and the bottom of the shield 110) are of the same or similar widths W. In some embodiments, the widths W of the conductive slices (112 a and 112 c) are greater than the width W′ of the conductive slice 112 b located at the middle of the shield 110. In some embodiments, the widths W of the conductive slices (112 a and 112 c) correspond to the widths of the upper portion and the lower portion of the conductive slice 112 d, and the width W′ of the conductive slice 112 b corresponds to the width of the middle portion of the conductive slice 112 d. It should be noted that the shape of the shield illustrated herein is an example. The shield 110 may include more than two types of conductive slices or may include a single type (e.g., the first type, the second type, or other type) of the conductive slice. In addition, other shapes, sizes, and configurations of the conductive slices are possible as long as the eddy current loss is efficiently diminished in the shield 110.
Continue to FIG. 3A, FIG. 4 , and FIG. 5 , adjacent conductive slices 112 may be electrically isolated from one another. For example, two adjacent conductive slices 112 are spatially separated from one another. In some embodiment, every adjacent two conductive slices 112 may define therebetween the respective gap G which is defined by the first edge 1121 of one conductive slice 112 and the second edge 1122 of another conductive slice 112. For example, each of the conductive slices 112 separated from any other of the conductive slices 112 may avoid the generation of a large amount of eddy current on the conductive slices 112 so as to diminish the eddy current loss generated by the shield 110. It should be noted that the figures provided herein are not drawn to scale and are for illustrative purposes. In some embodiments, the gap G is less than the thickness T of the respective conductive slice 112. Alternatively, the gap G is greater than or substantially equal to the thickness T of the conductive slice 112.
In some embodiments, the gaps G are low conductivity areas which may restrict the flow of eddy currents in the shield 110. For example, the shield 110 includes a spacer 114 formed in the gaps G to space apart every adjacent two conductive slices 112. The conductive slices 112 may be embedded in the spacer 114, and at least the facets 112 s of the conductive slices 112 that face the coil 120 may be exposed by the spacer 114. In some embodiments, the spacer 114 includes a plurality of spacer slices, and the conductive slices 112 and the spacer slices may be alternately arranged. The material of the spacer 114 may be either much less conductive than the conductive slice 112 or may be an insulator. The union of the plurality of conductive slices 112 and the spacer 114 forms the shield 110.
For example, the material of the spacer 114 includes plastic polymer, rubber, epoxy, ceramic, combination of these, any electrically insulating material, or the like. In some embodiments, the adjacent conductive slices 112 are joined by the spacer 114. For example, the spacer 114 includes adhesive material(s) which may be formed of a glue layer, a coated layer, a thin adhering film, or the like. A number of techniques may be employed alone or in conjunction to fabricate the shield 110. For example, the shield 110 may be fabricated by injection molding, three-dimensional (3D) printing, or any suitable techniques. In some embodiments in which injection molding is employed, the conductive slices 112 are pre-formed and inserted in a mold cavity (not shown) with an intended arrangement as mentioned above, and then the material of spacer 114 is injected into the mold cavity to create the final integrated assembly of the shield 110.
In some embodiments, the cavity C1 is formed between the row of the conductive slices 112 a at the top of the shield 110 and the row of the conductive slices 112 b at the middle of the shield 110. The cavity C2 may be or may not be also formed between the row of the conductive slices 112 c at the bottom of the shield 110 and the row of the conductive slices 112 b at the middle of the shield 110. The cavity (e.g., C1 and/or C2) may be air cavity or may be filled by an insulator. In other embodiments, the gap G and the cavities (C1 and C2) between any adjacent conductive slices (e.g., 112 a, 112 b, 112 c, and 112 d) are filled by the spacer 114 to create the shield 110 with integral outer surface.
In certain embodiments in which the shield 110 having the cylindrical shape is surrounded by the coil 120, the shield 110 may have an inner diameter Di that is large enough to process a semiconductor workpiece (e.g., a semiconductor wafer having about 300 mm diameters or having other dimension). The shield including conductive slices discontinuously arranged may be applied to an induced coupled plasma (ICP) tool or a transformer coupled plasma (TCP) reactor which is not limited thereto. It should be noted that the number, the shape, and the size of conductive slices 112 and the spacer 114 may be varied to accommodate different process requirements. The shield shown herein is provided as an example and variations thereof may be carried out while still remaining within the scope of the disclosure.
FIG. 6 is a schematic perspective view illustrating a shield of a semiconductor processing apparatus according to some embodiments of the present disclosure and FIG. 7 is a schematic view illustrating a shield including a casing and a block before assembled according to some embodiments of the present disclosure.
Referring to FIG. 6 and FIG. 7 , a shield 210 adapted to be surrounded by the coil of the semiconductor processing apparatus is provided. The configuration of the shield 210 in the semiconductor processing apparatus may be similar to the shield 110 of the semiconductor processing apparatus 100 as described above, so the detailed description is omitted for brevity. The shield 210 may be referred to as a Faraday shield which plays an important role in improving the RF power efficiency for the semiconductor processing apparatus. For example, the shield 210 is designed to suppress or diminish eddy currents so as to avoid the shield 210 from generating eddy current losses.
In some embodiments, the shield 210 includes a casing 212 and a plurality of blocks 214 embedded in the casing 212. For example, the casing 212 includes an upper portion 212 a, a lower portion 212 c, and a plurality of middle portions 212 b respectively connected to the upper portion 212 a and the lower portion 212 c. In some embodiments, the upper portion 212 a and the lower portion 212 c are circular in shape, and the middle portions 212 b are separately oriented along the circumferences of the upper portion 212 a and the lower portion 212 c. Alternatively, the upper portion 212 a and the lower portion 212 c may be any shape such as circular, square, rectangular, oval, etc. The upper portion 212 a and the lower portion 212 c includes the same or similar conductive material including aluminum, iron, copper, silicon steel sheet, silver, gold, platinum, metallic alloys, combination of these, etc.
In some embodiments, the middle portions 212 b are separately distributed around the middle of the shield 210. For example, adjacent two of the middle portions 212 b are spatially apart from one another by a gap C3. The gaps C3 may be air gaps or filled by an insulator (not shown). In an embodiment, the respective gap C3 is formed as an approximately I-shaped gap between adjacent two of the middle portions 212 b. The shape of the respective gap C3 may depend on the shape of the adjacent middle portions 212 b, which is not limited thereto. In some embodiments, the coil 120 is wound around the middle portions 212 b of the shield 210. For example, each of the middle portions 212 b includes a middle frame b1 and at least two posts b2 respectively extending to be connected to the upper portion 212 a and the lower portion 212 c. The middle frames b1 of the middle portions 212 b may be surrounded by the coil 120. The middle frame b1 and the posts b2 may be integratedly formed and may include the same or similar conductive material including aluminum, iron, copper, silicon steel sheet, silver, gold, platinum, metallic alloys, combination of these, etc.
In some embodiments, one of the post b2 of the respective middle portion 212 b is connected to the upper middle edge of the middle frame b1 and the upper portion 212 a, and the other one of the post b2 of the respective middle portion 212 b is connected to the lower middle edge of the middle frame b1 and the lower portion 212 c. In other embodiments, more than two posts b2 are distributed at the upper edge (and/or the lower edge) of the middle frame b1. In some embodiments, the width b1 w of the middle frame b1 is substantially the same or similar to the width b2 w of the respective posts b2. Alternatively, the width b1 w of the middle frame b1 is greater than or less than the width b2 w of the respective posts b2. The width b1 w of the middle frame b1 and the width b2 w of the respective posts b2 are designed to suppress or minimize eddy currents within the shield 210. It should be noted that the number and the shape of the respective post b2 construe no limitation in the disclosure as long as the posts b2 can provide support to the middle frame b1 for connecting the upper portion 212 a and the lower portion 212 c.
The middle frame b1 may be provided with a window opening b1 a. In some embodiments, the middle frame b1 is a substantially rectangular middle frame with a hollow central section. It should be noted that the shape of each middle frame b1 of the respective middle portion 212 b is not necessarily limited to rectangular, circular, elliptical, triangular, polygonal, or the like. In some embodiments, each of the plurality of blocks 214 is held in place within one of the window openings b1 a of the respective middle frame b1 of the middle portions 212 b. For example, the respective block 214 is complimentary in shape to the corresponding window opening b1 a of the middle frame b1.
In some embodiments, each of the blocks 214 includes a plurality of conductive slices 214 a discontinuously arranged aside one another. The conductive slices 214 a may be separately arranged along a winding direction of the coil 120 and overlap with the coil 120. For example, the conductive slices 214 a are spaced and longitudinally extending segments surrounded by the coil 120. The respective slice may be formed in the shape of a rectangular (or square). For example, the conductive slices 214 a are arranged side by side with a gap, and the respective conductive slice 214 a extends along the first axis A1 perpendicular to the second axis A2 in which the coil 120 is wound. The conductive slices 214 a may be any material or combination of materials provided which are conductive, such as aluminum, iron, copper, silicon steel sheet, silver, gold, platinum, metallic alloys, combination of these, or the like. In some embodiments, each of the conductive slices 214 a has a facet 214 s facing the coil 120, and a facet width 214 sw of the facet 214 s may be defined by two side edges (2141 and 2142) extending along the first axis A1.
In some embodiments, the facet width 214 sw of the respective conductive slice 214 a is substantially the same or similar to the width b1 w of the middle frame b1. Alternatively, the width b1 w of the middle frame b1 is greater than or less than the facet width 214 sw of the conductive slices 214 a. In some embodiments, the facet widths 214 sw of the conductive slices 214 a are substantially uniform. For example, the facet width 214 sw of the respective conductive slice 214 a ranges from about 0.01 mm to about 10 mm. It should be noted that the facet widths 214 sw of the conductive slices 214 a may be adjusted depending on the technique(s) that is employed to fabricate the shield 210 and the process requirements of the semiconductor processing apparatus. The number of conductive slices, slice shapes, and slice sizes of the blocks may be varied as necessary to accommodate different semiconductor processing requirements.
In some embodiments, during operation, each of the conductive slices 214 a including the side edges (2141 and 2142) forms therebetween an eddy current as indicated by arrow ED in FIG. 7 . It is understood that the eddy current losses of the shield 210 are proportional to the square of the facet width 214 sw of the conductive slices 214 a. By dividing the middle portions 212 b of the shield 210 into multiple blocks 214 having sliced conductive material in the window openings b1 a of the middle frame b1, eddy current losses generated in the shield 210 by the RF power emitted by the coil 120 may be minimized, thereby efficiently generating the magnetic fields and enhancing the RF power efficiency. The improved RF power efficiency may generate the plasma with higher density, thereby increasing the productivity and the yield of the semiconductor manufacturing process.
In some embodiments, the respective block 214 includes a spacer 214 b disposed between adjacent conductive slices 214 a. In some embodiments, the spacers 214 b of the blocks 214 are made of material(s) which is much less conductive than the conductive slices 214 a to restrict the flow of eddy currents in the middle portions 212 b of the shield 110. In some embodiments, the spacer 214 b includes plastic polymer, rubber, epoxy, ceramic, and combination of these or any electrically insulating material that may electrically isolate the conductive slices 214 a from one another. In some embodiments, the respective conductive slice 214 a is surrounded by the spacer 214 b. For example, the conductive slices 214 a are embedded in the spacer 214 b, and at least the facets 214 s of the conductive slices 214 a that face the coil 120 may be exposed by the spacer 214 b. The width of a portion of the spacer 214 b between adjacent two of the conductive slices 214 a may be less than the facet width 214 sw of the respective conductive slice 214 a. In other embodiments, the width of a portion of the spacer 214 b between adjacent conductive slices 214 a is substantially equal to or greater than the facet width 214 sw of the respective conductive slice 214 a.
For example, the spacer 214 b at least covers the side edges (2141 and 2142) of the respective conductive slice 214 a. In some embodiments, the top and bottom edges (2143 and 2144) connected to the side edges (2141 and 2142) are also covered by the spacer 214 b so that the conductive slices 214 a inserted into the window openings b1 a is spaced apart from the corresponding middle frame b1. In an embodiment in which the spacer 214 b is made of an electrically insulating material, the conductive slices 214 a of the respective block 214 is electrically isolated from the corresponding middle frame b1. In some embodiments, the spacer 214 b is formed with a uniform width. In an embodiments, a portion of the spacer 214 b between the side edges of adjacent conductive slices 214 a is narrower than a portion of the spacer between the top edge (or the bottom edge) of the respective conductive slice 214 a and the middle frame b1. Alternatively, a portion of the spacer 214 b between the side edges of adjacent conductive slices 214 a is wider than a portion of the spacer between the top edge (or the bottom edge) of the respective conductive slice 214 a and the middle frame b1.
In some embodiments, the adjacent conductive slices 214 a are joined by the spacer 214 b. For example, the spacer 214 b includes adhesive material(s) which may be formed of a glue layer, a coated layer, a thin adhering film, or the like. The material, the shape, and the size of the spacer may be varied as necessary to accommodate different semiconductor processing requirements. In some embodiments, the casing 212 and the blocks 214 are separately formed. The window openings b1 a of the middle frames b1 may be formed of a shape substantially complementary to the shape of the block 214. It should be noted that only one block 214 is shown in FIG. 7 for illustrative purposes. Once assembled, the respective block 214 is fit into the corresponding window opening b1 a of the middle frame b1, and the facets 214 s of the conductive slices 214 a exposed by the spacer 214 b may face an inner peripheral surface of the coil 120. In certain embodiments in which the spacer 214 b of the respective block 214 includes adhesive material(s) and wrapping around at least the edges of the conductive slices 214 a, so that the respective block 214 may be adhered to the middle frame b1 through the spacer 214 b. It should be noted that the block 214 and the casing 212 of the shield 210 shown in FIG. 7 is an illustrative examples and should not be considered as limiting to the disclosure.
FIG. 8 is a schematic perspective view illustrating a shield of a semiconductor processing apparatus according to some embodiments of the present disclosure. Referring to FIG. 8 and also with reference to FIG. 6 , a shield 310 adapted to be surrounded by the coil of the semiconductor processing apparatus is provided. The shield 310 may be referred to as a Faraday shield which plays an important role in improving the RF power efficiency for the semiconductor processing apparatus. For example, the shield 310 is designed to suppress or diminish eddy currents so as to avoid the shield 310 from generating eddy current losses. The shield 310 in the semiconductor processing apparatus may be similar to the shield 210 described in FIG. 6 , so the detailed description is omitted for brevity. The difference between the shields 210 and 310 includes the configuration of the middle portion 312 b.
For example, a plurality of middle portions 312 b is respectively connected to the upper portion 212 a and the lower portion 212 c. In some embodiments, the middle portions 312 b are separately distributed around the middle of the shield 310. For example, adjacent two of the middle portions 312 b are spatially apart from one another by the gap C3. The gaps C3 may be air gaps or filled by an insulator (not shown). In an embodiment, the respective gap C3 is formed as an approximately I-shaped gap between adjacent two of the middle portions 312 b. The shape of the respective gap C3 may depend on the shape of the adjacent middle portions 312 b, which is not limited thereto. In some embodiments, the coil 120 is wound around the middle portions 312 b of the shield 310. For example, each of the middle portions 312 b includes a middle frame b1′ and at least two posts b2 respectively extending to be connected to the upper portion 212 a and the lower portion 212 c. The middle frames b1′ of the middle portions 312 b may be surrounded by the coil 120. The middle frame b1′ and the posts b2 may be integratedly formed and may include the same or similar conductive material including aluminum, iron, copper, silicon steel sheet, silver, gold, platinum, metallic alloys, combination of these, etc.
In some embodiments, the respective middle frame b1′ is provided with a plurality of conductive slices 3122 separately arranged along the widthwise direction (i.e. the second axis A2). For example, the respective conductive slice 3122 extends along in the lengthwise direction (i.e. the first axis A1). The conductive slices 3122 may be made of the same or similar conductive material as the middle frame b1′. For example, the conductive slices 3122 are integratedly formed with or secured to the middle frame b1′. In some embodiments, the conductive slices 3122 have the uniform dimension. In other embodiments, the conductive slices are of different dimensions as will be described later. It should be noted that the shapes of middle frame and the conductive slices are not necessarily limited to rectangular, circular, elliptical, triangular, polygonal, or the like. In some other embodiments, a single conductive slice 3122 is disposed on the middle frame b1′. It is also noted that the numbers of the conductive slices 3122 illustrated in FIG. 8 is merely an example and construe no limitation in the disclosure.
In some embodiments, the middle frame b1′ and the conductive slice 3122 adjacent to the middle frame b1′ may be spaced apart from each other by a gap G1. The neighboring conductive slices 3122 may be spaced apart from one another by a gap G2. In some embodiments, the conductive slices 3122 are evenly distributed by the uniform gaps G1 and G2. In some other embodiments, the dimension of the gap G1 is greater than or less than that of the gap G2. In some embodiments, the spacer 3126 fills the gaps G1 and G2 to laterally separate the neighboring conductive slices 3122 from one another and also separate the conductive slices 3122 from the middle frame b1′. For example, the spacer 3126 includes plastic polymer, rubber, epoxy, ceramic, combination of these, or other suitable electrically insulating material. Again, the configuration of the middle portion 312 b illustrated in FIG. 8 is merely an example and may be adjusted depending on the product and process requirements.
FIG. 9 is a schematic perspective view illustrating a shield of a semiconductor processing apparatus according to some embodiments of the present disclosure. Referring to FIG. 9 and also with reference to FIG. 8 , a shield 410 adapted to be surrounded by the coil of the semiconductor processing apparatus is provided. The shield 410 may be referred to as a Faraday shield which plays an important role in improving the RF power efficiency for the semiconductor processing apparatus. For example, the shield 410 is designed to suppress or diminish eddy currents so as to avoid the shield 310 from generating eddy current losses. The shield 410 in the semiconductor processing apparatus may be similar to the shield 310 described in FIG. 8 , so the detailed description is omitted for brevity. The difference between the shields 310 and 410 includes the configuration of the middle portion 412 b.
The middle frames b1″ of the middle portions 412 b may be surrounded by the coil 120. The middle frame b1″ and the posts b2 may be integratedly formed and may include the same or similar conductive material including aluminum, iron, copper, silicon steel sheet, silver, gold, platinum, metallic alloys, combination of these, etc. In some embodiments, the respective middle frame b1″ is provided with a plurality of first conductive slices 4122 and a plurality of second conductive slices 4124 alternately and separately arranged along the widthwise direction (i.e. the second axis A2). For example, the respective first conductive slice 4122 and the respective second conductive slice 4124 extend along in the lengthwise direction (i.e. the first axis A1). The first conductive slices 4122 and the second conductive slices 4124 may be made of the same or similar conductive material as the middle frame b1′. For example, the first conductive slices 4122 and the second conductive slices 4124 are integratedly formed with or secured to the middle frame b1″.
In some embodiments, the first conductive slices 4122 and the second conductive slices 4124 have the same or similar lengths, while the widths 4122 w of the first conductive slices 4122 are greater than the widths 4124 w of the second conductive slices 4124. In other embodiments, the widths 4122 w of the first conductive slices 4122 are substantially equal to or less than the widths 4124 w of the second conductive slices 4124. It should be noted that the shapes of middle frame and the conductive slices are not necessarily limited to rectangular, circular, elliptical, triangular, polygonal, or the like. In some other embodiments, a single first conductive slice 4122 and a single second conductive slice 4124 may be separately disposed on the middle frame b1′. It is also noted that the numbers of the first conductive slices 4122 and the second conductive slices 4124 illustrated in FIG. 9 is merely an example and construe no limitation in the disclosure.
The middle frame b1″ and the second conductive slice 4124 adjacent to the middle frame b1″ may be spaced apart from each other by a gap G1′, and the first conductive slice 4122 and the second conductive slice 4124 adjacent to the first conductive slice 4122 may be spaced apart from each other by a gap G2′. In some embodiments, the dimension of the gap G1′ is greater than or substantially equal to that of the gap G2′. Alternatively, the dimension of the gap G1′ is less than that of the gap G2′. The gaps G1′ between the middle frames b1″ and the second conductive slices 4124 may vary from one area to another. The gaps G2′ between the first conductive slices 4122 and the second conductive slices 4124 may also vary from one area to another. In some embodiments, the spacer 4126 fills the gaps G2′ to laterally separate the first conductive slice 4122 from the adjacent second conductive slice 4124. The spacer 4126 may also fill the gaps G1′ between the middle frames b1′ and the second conductive slices 4124. The material of the spacer 4126 may be similar to the spacer 3126 described in FIG. 8 . In some embodiments, the first conductive slices 4122 are disposed aside the middle frame b1″, and the middle frame b1″ and the first conductive slice 4122 adjacent to the middle frame b1″ may be spaced apart from each other by a gap. Under such scenario, the spacer 4126 may fill the gaps between the middle frames b1′ and the first conductive slices 4122. Again, the configuration of the middle portion 412 b illustrated in FIG. 9 is merely an example and may be adjusted depending on the product and process requirements.
FIG. 10 is a schematic perspective view illustrating a shield of a semiconductor processing apparatus according to some embodiments of the present disclosure. Referring to FIG. 10 and also with reference to FIG. 3A, a shield 510 including a plurality of first conductive slices 5112 and a plurality of second conductive slices 5114 separately and alternately arranged is provided. The shield 510 may be similar to the shield 110 described in FIG. 3A, so the detailed descriptions are not repeated for the sake of brevity. The difference between the shields 510 and 110 includes that the thickness of the respective first conductive slice 5112 is different from that of the thickness of the respective second conductive slice 5114.
For example, the thickness T1 of the respective first conductive slice 5112 is greater than the thickness T2 of the respective second conductive slice 5114. In some embodiments, the thickness T1 of the first conductive slice 5112 is a few times or a hundred times greater than the thickness T2 of the second conductive slice 5114. Alternatively, the thickness T1 of the first conductive slice 5112 may be a thousand times greater than the thickness T2 of the second conductive slice 5114. It is noted that the dimensions of the first conductive slice 5112 and the second conductive slice 5114 may vary depending on the product and process requirements. In some embodiments, a gap G′ is formed between the neighboring first conductive slice 5112 and second conductive slice 5114. For example, the first conductive slices 5112 and the second conductive slices 5114 are spaced apart from one another by the uniform gaps G′. In some embodiments, the gaps G′ vary from one area to another along the circumference of the plasma-generating chamber 10.
In some embodiments, the spacer 5116 is formed in the gaps G′ to physically separate the neighboring first conductive slice 5112 and second conductive slice 5114. In some embodiments, the first conductive slices 5112 and the second conductive slices 5114 are embedded in the spacer 5116, and at least the facets of the respective first conductive slice 5112 and the respective second conductive slice 5114 that face the coil may be exposed by the spacer 5116. In some embodiments, the spacer 5116 includes a plurality of spacer slices, and the conductive slices (e.g., 5112 and 5114) and the spacer slices are alternately arranged. The material of the spacer 5116 may be either much less conductive than the conductive slice or may be an insulator. In some embodiments, the material of the spacer 5116 is similar to the spacer 114 described in FIG. 3A. A number of techniques may be employed alone or in conjunction to fabricate the shield 510. For example, the shield 510 may be fabricated by injection molding, three-dimensional (3D) printing, or any suitable techniques. The union of the first conductive slices 5112, the second conductive slices 5114, and the spacer 5116 forms the shield 510.
According to some embodiments, a Faraday shield is provided. The Faraday shield includes a plurality of conductive slices and a spacer interposed between adjacent two of the conductive slices to electrically isolate the adjacent two of the conductive slices from one another. The conductive slices are separately arranged aside one another and oriented along a circumference of the Faraday shield. A coil is wound around the circumference of the Faraday shield.
According to some alternative embodiments, a semiconductor processing apparatus is provided. The semiconductor processing apparatus includes a plasma-generating chamber adapted to generate plasma therein, a coil surrounding the plasma-generating chamber and coupled to a power source, and a shield interposed between the coil and the plasma-generating chamber. The shield includes a plurality of conductive slices discontinuously arranged along an exterior wall of the plasma-generating chamber.
According to some alternative embodiments, an etching apparatus is provided. The etching apparatus includes a plasma-generating chamber adapted to generate plasma therein, a processing chamber disposed below the plasma-generating chamber and adapted to process a semiconductor workpiece, a shield disposed on an exterior wall of the plasma-generating chamber, and a coil coupled to a power source to supply a plasma-creating power. The shield includes a plurality of conductive slices arranged parallel to one another along the exterior wall of the plasma-generating chamber. The coil is wound around the conductive slices of the shield.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

What is claimed is:

1. A semiconductor processing apparatus, comprising:

a plasma-generating chamber adapted to generate plasma therein;

a shield disposed on an exterior wall of the plasma-generating chamber and comprising:

a plurality of conductive slices separately arranged aside one another and oriented along a circumference of the shield; and

a spacer interposed between adjacent two of the plurality of conductive slices; and

a coil wound around the circumference of the shield.

2. The semiconductor processing apparatus of claim 1, wherein the adjacent two of the plurality of conductive slices are electrically isolated from one another through the spacer.

3. The semiconductor processing apparatus of claim 1, wherein the adjacent two of the plurality of conductive slices are adhered to one another through the spacer.

4. The semiconductor processing apparatus of claim 1, wherein each of the plurality of conductive slices comprises a facet facing the coil, and a facet width of the facet is defined by two side edges of each of the plurality of conductive slices extending along a height direction of the shield.

5. The semiconductor processing apparatus of claim 1, wherein the shield further comprises:

a casing provided with a window opening, the plurality of conductive slices and the spacer being disposed within the window opening of the casing.

6. The semiconductor processing apparatus of claim 5, wherein the window of the casing is at a middle portion of the casing, and the coil overlaps the window.

7. A semiconductor processing apparatus, comprising:

a plasma-generating chamber adapted to generate plasma therein;

a coil wound around an exterior wall of the plasma-generating chamber and coupled to a power source; and

a shield interposed between the coil and the plasma-generating chamber and comprising:

a casing provided with a window opening; and

a plurality of conductive slices discontinuously arranged along a winding direction of the coil in the window opening.

8. The semiconductor processing apparatus of claim 7, wherein the shield further comprises:

a spacer disposed between any adjacent two of the plurality of conductive slices to spaced apart any adjacent two of the plurality of conductive slices from one another along the winding direction of the coil.

9. The semiconductor processing apparatus of claim 8, wherein the spacer comprises an adhesive material to adhere the any adjacent two of the plurality of conductive slices.

10. The semiconductor processing apparatus of claim 8, wherein the plurality of conductive slices is electrically isolated from the casing by the spacer.

11. The semiconductor processing apparatus of claim 8, wherein the spacer fills a first gap spacing apart the casing and one of the plurality of conductive slices adjacent to the casing, and a second gap spacing apart adjacent two of the plurality of conductive slices.

12. The semiconductor processing apparatus of claim 11, wherein a dimension of the first gap is different from a dimension of the second gap.

13. The semiconductor processing apparatus of claim 7, wherein each of the plurality of conductive slices of the shield comprises a facet facing the coil, and a length of the facet extends along a height direction of the shield.

14. An etching apparatus, comprising:

a plasma-generating chamber adapted to generate plasma therein;

a processing chamber disposed below the plasma-generating chamber and adapted to process a semiconductor workpiece;

a plurality of conductive slices arranged parallel to one another along the exterior wall of the plasma-generating chamber;

a casing provided with a window opening, the plurality of conductive slices separately disposed within the window opening; and

an insulating spacer provided with the window opening, wherein the plurality of conductive slices are separated from one another through the insulating spacer; and

a coil surrounding the plurality of conductive slices of the shield and coupled to a power source to supply a plasma-creating power.

15. The etching apparatus of claim 14, wherein any adjacent two of the plurality of conductive slices are electrically isolated from one another through the insulating spacer.

16. The etching apparatus of claim 14, wherein each of the plurality of conductive slices is surrounded by the insulating spacer.

17. The etching apparatus of claim 14, wherein each of the plurality of conductive slices of the shield comprises a length extending along the exterior wall of the plasma-generating chamber and a width extending along a circumference of the plasma-generating chamber.

18. The etching apparatus of claim 14, wherein each of the plurality of conductive slices of the shield comprises a facet exposed by the insulating spacer and facing an inner peripheral surface of the coil.

19. The etching apparatus of claim 14, wherein the plurality of conductive slices comprises a plurality of first conductive slices and a plurality of second conductive slices alternately arranged within the window opening, and a width of the plurality of first conductive slices is different from a width of the plurality of second conductive slices.

20. The etching apparatus of claim 14, wherein the plurality of conductive slices is made of the same conductive material as the casing.