US20230393926A1 - BIOS Error Locating Method and Apparatus, Device and Non-Volatile Storage Medium - Google Patents

BIOS Error Locating Method and Apparatus, Device and Non-Volatile Storage Medium Download PDF

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Publication number
US20230393926A1
US20230393926A1 US18/256,806 US202118256806A US2023393926A1 US 20230393926 A1 US20230393926 A1 US 20230393926A1 US 202118256806 A US202118256806 A US 202118256806A US 2023393926 A1 US2023393926 A1 US 2023393926A1
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target
base address
error
function
address
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US12032436B2 (en
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Hongbo Zhang
Zhiyuan Xu
Bing Wang
Shaojun Yang
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Suzhou Wave Intelligent Technology Co Ltd
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Suzhou Wave Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0778—Dumping, i.e. gathering error/state information after a fault for later diagnosis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/079—Root cause analysis, i.e. error or fault diagnosis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring

Definitions

  • the present disclosure relates to the technical field of computers, and in particular to a Basic Input Output System (BIOS) error locating method and apparatus, a computer device and a non-volatile storage medium.
  • BIOS Basic Input Output System
  • BIOS research and development personnel are required to handle, locate and solve the problems.
  • the research and development personnel mainly analyze and locate the problems with the help of a Serial Log.
  • the cause of the crash may be checked in the Serial Log of the BIOS.
  • error reporting information such as ERROR/ASSERT/EXCEPTION is found in the Serial Log, it means that there are some logical problems in the codes of the BIOS, and thus the research and development personnel need to locate and search for the cause of the problem, so as to solve the problem.
  • the error reporting information such as ERROR/ASSERT/EXCEPTION is automatically recorded in the Serial Log of the BIOS.
  • BIOS error locating method includes:
  • executing the Exception handling function, so as to determine, according to the base address log file and the one or more MAP files, the target function that results in the EXCEPTION error includes:
  • comparing the routing information protocol value with the values in the base address column in the base address log file, so as to determine the target base address includes:
  • verifying the target MAP file by using the target base address and the target entry address includes:
  • determining the target function and a name corresponding to the target function according to the routing information protocol value, the target base address and the target MAP file includes:
  • the method may further include:
  • the method may further include:
  • BIOS error locating apparatus includes:
  • a computer device is further provided, wherein the computer device includes a memory and one or more processors, computer-readable instructions are stored in the memory, and when the computer-readable instructions are executed by the processor, the one or more processors execute the following operations:
  • One or more non-volatile storage media storing computer-readable instructions, wherein the computer-readable instructions, when being executed by one or more processors, cause the one or more processors to execute the following operations:
  • FIG. 1 is a diagram of an application scenario of a BIOS error locating method provided according to one or more embodiments of the present disclosure
  • FIG. 2 is a schematic flowchart of a BIOS error locating method provided according to one or more embodiments of the present disclosure
  • FIG. 3 is an overall implementation flowchart of a BIOS error locating method provided in another embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart of executing an Exception handling function to determine a target function provided in yet another embodiment of the present disclosure
  • FIG. 4 a is a schematic diagram of file content of a base address log file (IB.log) provided in another embodiment of the present disclosure
  • FIG. 4 b is a schematic diagram of content of a certain piece of EXCEPTION error information provided in another embodiment of the present disclosure
  • FIG. 4 c is a schematic diagram of content of a certain MAP file provided in another embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a BIOS error locating apparatus provided in another embodiment of the present disclosure.
  • FIG. 6 is a block diagram of an internal structure of a computer device in another embodiment of the present disclosure.
  • a BIOS error locating method provided in the embodiments of the present disclosure may be applied to an application environment shown in FIG. 1 .
  • a terminal 102 communicates with a server 104 through a network.
  • the terminal 102 may be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers or portable wearable devices, and the server 104 may be implemented by using an independent server or a server cluster composed of a plurality of servers.
  • the embodiment of the present disclosure provides a BIOS error locating method, which is described taking the implementation of the method to the server in FIG. 1 as an example. As shown in FIG. 2 , the method includes the following operations S 100 to S 400 .
  • MAP files which are generated during a compilation process of a BIOS and used for recording an entry address offset of each function are acquired.
  • the MAP file is one of file formats, and the MAP file is a mapping file which is generated after compilation by compilation software and records all programs, data and Input/Output (IO) spaces used by a Digital Signal Processor (DSP).
  • An entry address is denoted as EntryPoint, which refers to an address in a memory during execution of a function module.
  • a base address of each function module after the BIOS is started is recorded, so as to obtain a base address log file.
  • the base address is an ImageBase, which is an address of a code after the code is loaded into a memory.
  • the ImageBase of each executed function module and the size of the ImageBase are recorded in a special log which has a file name of, for example, IB.log.
  • an Exception handling function is executed so as to determine, according to the base address log file and the one or more MAP files, a target function that results in the EXCEPTION error.
  • a name of the target function is recorded in a serial log, and the serial log is sent to a BMC.
  • the BIOS error locating method one or more MAP files which are generated during the compilation process of the BIOS and used for recording the entry address offset of each function are acquired, the base address of each function module after the BIOS is started is recorded so as to obtain the base address log file, when the EXCEPTION error occurs, the Exception handling function is executed to determine, according to the base address log file and the one or more MAP files, the target function that results in the EXCEPTION error, the name of the target function is recorded in the serial log, and the serial log is sent to the BMC.
  • the function resulting in the EXCEPTION error is automatically analyzed and recorded, the efficiency of solving the EXCEPTION-type error may be improved, and the BIOS error locating time may be shortened.
  • the operation S 300 may include the following sub-operations S 310 to S 350 .
  • EXCEPTION error information is acquired and parsed, so as to obtain a routing information protocol value, wherein the routing information protocol value is denoted as an RIP value.
  • the routing information protocol value is compared with values in a base address column in the base address log file, so as to determine a target base address.
  • a target entry address and a target MAP file are determined according to the routing information protocol value and a preset PE specification.
  • PE refers to Portable Executable (i.e., a portable executable file), which is an executable format utilized by Microsoft.
  • the preset PE specification refers to “Microsoft PE COFF Specification”, and according to the specification for a PE Image in the preset PE specification, the PE Image may be parsed by an existing function, so as to obtain the EntryPoint of the function module and the MAP file name corresponding to the PE Image.
  • the target MAP file is verified by using the target base address and the target entry address.
  • the target function and a name corresponding to the target function are determined according to the routing information protocol value, the target base address and the target MAP file.
  • the foregoing operation S 320 may include the following sub-operations S 321 to S 322 .
  • the first base address greater than the routing information protocol value among the values in the base address column in the base address log file is used as a reference base address.
  • a previous base address of the reference base address in the base address log file is acquired as the target base address.
  • the foregoing operation S 340 may include the following sub-operations S 341 to S 343 .
  • a first difference value between the target entry address and the target base address is calculated.
  • the first difference value is matched with the entry address offset in the target MAP file.
  • the foregoing operation S 350 may include the following sub-operations S 351 to S 353 .
  • a second difference value between the routing information protocol value and the target base address is calculated.
  • the first value greater than the second difference value among values in an address column in the target MAP file is used as a reference entry offset address.
  • a function corresponding to a previous entry offset address of the reference entry offset address in the target MAP file is used as the target function, and the name corresponding to the target function is read.
  • the method may further include the following operation S 510 .
  • an ERROR function and/or an ASSERT function which results in the ERROR error and/or the ASSERT error is recorded in the serial log.
  • the method may further include the following operations S 520 and S 530 .
  • the serial log is acquired from the BMC.
  • the serial log is parsed to respectively determine functions which result in the EXCEPTION error, the ERROR error, and/or the ASSERT error.
  • a server architecture of an Intel platform is taken as an example for illustration of the method. It should be noted that the method is not limited to be applied on the server of the Intel platform or a server system, and may also be applied on server systems of other platforms or other computer systems. As shown in FIG. 3 and FIG. 4 , the BIOS error locating method may include the following exemplary implementation operations 1 to 6 .
  • a base address and a size of each executed module are recorded in a base address log file (for example, in a special log file having a file name of IB.log).
  • a base address log file for example, in a special log file having a file name of IB.log.
  • the IB.log file includes the following information from left to right: serial number, base address, module size and module name.
  • an Exception handling function is executed.
  • the process of executing the Exception handling function includes the following operations 31 to 37 .
  • FIG. 4 b shows the EXCEPTION error information, which includes the RIP value corresponding to the EXCEPTION error.
  • the RIP value (i.e., the value in A, referred to as A value hereinafter) is compared with values in an Imagebase column in the IB.log file one by one, so as to find the first value greater than the RIP value, and a previous value of the found value is stored in B as a target base address.
  • the PE Image is parsed through an existing function, so as to find a target entry address of the function module and a target MAP file name corresponding to the PE Image, and the target entry address value is stored in C.
  • the target MAP file found in operation 34 is opened, an offset address of the EntryPoint relative to the ImageBase is calculated according to the target entry address value C ⁇ the target base address B, the offset address is denoted as a first difference value D, the first difference value D is compared with an EntryPoint offset in the target MAP file, when there is a same value as the first difference value in the target MAP file, it confirms that the target MAP file found in operation 34 is correct, and the next operation may be performed. Specific reference may be made to the content of a certain MAP file shown in FIG. 4 c.
  • an offset value between the RIP value and the target base address B is calculated, the offset value is denoted as a second difference value, the second difference value is stored in E, the first value greater than the second difference value E is searched in an address column in the target MAP file, and a function corresponding to a previous value of the found value is the function that results in the EXCEPTION error.
  • the function name is recorded in a Serial Log, and crash information is sent to the BMC.
  • operation 4 the execution results of operation 31 to operation 37 are recorded in the Serial Log of the BIOS.
  • the Serial Log is sent to the BMC and is stored by the BMC.
  • the function that results in the EXCEPTION error reporting is located and recorded according to the existing RIP information is combination with MAP information recorded in the BIOS execution process, thereby realizing automatic problem analysis and locating, improving the efficiency of solving the EXCEPTION error, and shortening the locating time of the BIOS error.
  • BIOS error locating apparatus 60 wherein the apparatus includes:
  • BIOS error locating apparatus may be implemented by software, hardware and a combination thereof.
  • the above modules may be embedded into or independent of a processor in a computer device in the form of hardware, and may also be stored in a memory in the computer device in the form of software, so that the processor calls corresponding operations for executing the above modules.
  • a computer device may be a server, and an internal structure diagram thereof is shown in FIG. 6 .
  • the computer device includes a processor, a memory, a network interface and a database, which are connected by a system bus.
  • the processor of the computer device is used for providing computing and control capabilities.
  • the memory of the computer device includes a non-volatile storage medium and an internal memory.
  • the non-volatile storage medium stores an operating system, a computer-readable instruction and a database.
  • the internal memory provides an environment for the operation of the operating system and the computer-readable instruction in the non-volatile storage medium.
  • the database of the computer device is used for storing data.
  • the network interface of the computer device is used for communicating with an external terminal through a network connection. When executed by the processor, the computer-readable instruction implements the above BIOS error locating method.
  • the computer device includes a memory and one or more processors, wherein computer-readable instructions are stored in the memory, and when the computer-readable instructions are executed by the processor, the one or more processors execute the above method.
  • one or more non-volatile storage media storing computer-readable instructions
  • the computer-readable instructions when being executed by one or more processors, cause the one or more processors to execute the above method.
  • the computer-readable instructions when being executed by one or more processors, cause the one or more processors to execute the above method.
  • Those having ordinary skill in the art may understand that all or some processes in the methods in the foregoing embodiments may be implemented by computer-readable instructions instructing related hardware, and the computer-readable instructions may be stored in a non-volatile computer-readable storage medium, and when executed, the computer-readable instructions may include the processes of the embodiments of the foregoing methods.
  • Any reference to the memory, the storage, the database or other media used in the embodiments provided in the present disclosure may include non-volatile and/or volatile memories.
  • the non-volatile memory may include a Read-Only Memory (ROM), a Programmable ROM (PROM), an Electrically Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), or a flash memory.
  • ROM Read-Only Memory
  • PROM Programmable ROM
  • EPROM Electrically Programmable ROM
  • EEPROM Electrically Erasable Programmable ROM
  • flash memory a flash memory.
  • the volatile memory may include a Random Access Memory (RAM) or an external cache.
  • the RAM may be available in various forms, such as a Static RAM (SRAM), a Dynamic RAM (DRAM), a Synchronous DRAM (SDRAM), a Dual-Data Rate SDRAM (DDRSDRAM), an Enhanced SDRAM (ESDRAM), a Synchlink DRAM (SLDRAM), a memory bus (Rambus) Direct RAM (RDRAM), a Direct memory bus (Rambus) Dynamic RAM (DRDRAM), and a memory bus (Rambus) Dynamic RAM (RDRAM), etc.
  • SRAM Static RAM
  • DRAM Dynamic RAM
  • SDRAM Synchronous DRAM
  • DDRSDRAM Dual-Data Rate SDRAM
  • ESDRAM Enhanced SDRAM
  • SLDRAM Synchlink DRAM
  • RDRAM Direct RAM
  • DRAM Direct memory bus
  • DRAM Dynamic RAM
  • RDRAM Dynamic RAM
  • RDRAM Dynamic RAM

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CN202011447497.3A CN112463431B (zh) 2020-12-11 2020-12-11 一种bios错误定位方法、装置、设备及存储介质
CN202011447497.3 2020-12-11
PCT/CN2021/127324 WO2022121548A1 (zh) 2020-12-11 2021-10-29 一种bios错误定位方法、装置、设备及非易失性存储介质

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CN112463431B (zh) 2020-12-11 2022-07-19 苏州浪潮智能科技有限公司 一种bios错误定位方法、装置、设备及存储介质

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