US20230393334A1 - Vertical grating structures placed between a waveguide core and a substrate - Google Patents
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- US20230393334A1 US20230393334A1 US17/831,065 US202217831065A US2023393334A1 US 20230393334 A1 US20230393334 A1 US 20230393334A1 US 202217831065 A US202217831065 A US 202217831065A US 2023393334 A1 US2023393334 A1 US 2023393334A1
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- NTPSYCFWEYOKTG-UHFFFAOYSA-N dioxosilane;tetraethyl silicate Chemical compound O=[Si]=O.CCO[Si](OCC)(OCC)OCC NTPSYCFWEYOKTG-UHFFFAOYSA-N 0.000 description 1
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Definitions
- the disclosure relates to photonics chips and, more specifically, to structures including a waveguide core and methods of fabricating a structure including a waveguide core.
- Photonics chips are used in many applications and systems including, but not limited to, data communication systems and data computation systems.
- a photonics chip integrates optical components and electronic components into a unified platform. Among other factors, layout area, cost, and operational overhead may be reduced by the integration of both types of components on the same chip. Waveguide cores used in photonics chips may suffer from significant leakage loss of propagating light to the substrate, which may degrade performance.
- a structure comprises a substrate, a waveguide core, and a grating disposed in a vertical direction between the waveguide core and the substrate.
- the grating includes a first plurality of layers and a second plurality of layers that alternate in the vertical direction with the first plurality of layers.
- the first plurality of layers comprise a first material having a first refractive index
- the second plurality of layers comprise a second material having a second refractive index that is greater than the first refractive index.
- a method comprises forming a grating on a substrate and forming a waveguide core over the grating in a vertical direction.
- the grating includes a first plurality of layers and a second plurality of layers that alternate in the vertical direction with the first plurality of layers.
- the first plurality of layers comprise a first material having a first refractive index
- the second plurality of layers comprise a second material having a second refractive index that is greater than the first refractive index.
- FIG. 1 is a cross-sectional view of a structure at an initial fabrication stage of a processing method in accordance with embodiments of the invention.
- FIG. 2 is a cross-sectional view of the structure at a fabrication stage of the processing method subsequent to FIG. 1 .
- FIG. 3 is a cross-sectional view of a structure in accordance with alternative embodiments of the invention.
- a structure 10 includes a waveguide core 12 positioned over a dielectric layer 13 , a substrate 14 , and a grating 16 disposed in a vertical direction between the waveguide core 12 and the substrate 14 .
- the dielectric layer 13 may be comprised of a dielectric material, such as silicon dioxide
- the substrate 14 may be comprised of a semiconductor material, such as single-crystal silicon.
- the dielectric layer 13 may be a buried oxide layer of a silicon-on-insulator substrate.
- the waveguide core 12 may be comprised of a material having a refractive index that is greater than the refractive index of silicon dioxide.
- the waveguide core 12 may be comprised of a dielectric material, such as silicon nitride.
- the waveguide core 12 may be comprised of silicon oxynitride.
- the waveguide core 12 may be comprised of a semiconductor material, such as silicon.
- other materials such as a polymeric material or a III-V compound semiconductor material, may be used to form the waveguide core 12 .
- the waveguide core 12 may be formed by patterning a layer of the material with lithography and etching processes.
- the waveguide core 12 may be formed by patterning the single-crystal silicon device layer of a silicon-on-insulator substrate with lithography and etching processes.
- the waveguide core 12 is a ridge waveguide core.
- the waveguide core 12 may be a rib waveguide core, a slot waveguide core, or a different type of waveguide core.
- waveguide core 12 may include linear sections, curved sections, and/or tapered sections.
- the grating 16 includes multiple layers 18 and multiple layers 20 that are arranged in a layer stack in which the layers 20 alternate in a vertical direction with the layers 18 .
- the waveguide core 12 is positioned on the dielectric layer 13 to overlap with the layers 18 , 20 of the grating 16 .
- the layers 20 may fully separate the layers 18 from each other. Due to the alternating arrangement, adjacent pairs of the layers 18 , 20 may define respective periods of the grating 16 .
- the grating 16 may include five or more periods each including an adjacent pair of the layers 18 , 20 .
- one of the layers 18 may be positioned adjacent to the dielectric layer 13 .
- one of the layers 18 may directly contact the dielectric layer 13 .
- one of the layers 18 may be positioned adjacent to the substrate 14 .
- one of the layers 18 may be in direct contact with the substrate 14 .
- the layers 18 may be comprised of a material having a refractive index (i.e., index of refraction) that is greater than the refractive index of the material constituting the layers 20 to provide an index contrast or variation.
- the layers 20 may be comprised of a dielectric material, such as silicon dioxide, that has a lower refractive index than the waveguide core 12 .
- the layers 18 may be comprised of a material having a refractive index that is greater than the refractive index of silicon dioxide.
- the layers 18 may be comprised of a III-V compound semiconductor material, such as gallium nitride, aluminum nitride, indium nitride, or a combination of these materials.
- the layers 18 may be comprised of gallium nitride. In an embodiment, the layers 18 may be comprised of a Group IV semiconductor material, such as silicon. In an embodiment, the layers 18 may be comprised of silicon carbide. In an embodiment, the layers 18 may be comprised of amorphous silicon. In an embodiment, the layers 18 may be comprised of an optical gain material, such as a material including indium nitride quantum dots. In an embodiment, the layers 18 may be comprised of a two-dimensional (2D) material, such as graphene, having a thickness of less than or equal to about 2 nanometers. In an embodiment, the layers 18 may be comprised of a nanostructured material, such as a layered superlattice.
- a Group IV semiconductor material such as silicon.
- the layers 18 may be comprised of silicon carbide.
- the layers 18 may be comprised of amorphous silicon.
- the layers 18 may be comprised of an optical gain material, such as a material including indium nitride quantum dots.
- the grating 16 may be formed by multiple wafer-bonding processes that laminate the layers 18 onto the substrate 14 using the layers 20 to promote bonding. In an alternative embodiment, the grating 16 may be formed by sequentially depositing the layers 18 and the layers 20 onto the substrate 14 .
- the layers 18 may be planar films having a uniform thickness between a planar top surface and a planar bottom surface.
- the pitch and thickness of the layers 18 may be uniform to define a periodic arrangement having a periodic variation in the index contrast.
- the layers 18 may have a thickness of about 200 nanometers to about 700 nanometers.
- a dielectric layer 22 is formed over the waveguide core 12 .
- the dielectric layer 22 may be comprised of a dielectric material, such as silicon dioxide, that is deposited and then planarized following deposition.
- the waveguide core 12 is embedded in the dielectric layer 22 .
- the dielectric material constituting the dielectric layer 22 may have a refractive index that is less than the refractive index of the material constituting the waveguide core 12 .
- a back-end-of-line stack 24 may be formed over the dielectric layer 22 .
- the back-end-of-line stack 24 may include multiple dielectric layers that are each comprised of a dielectric material, such as silicon dioxide, silicon nitride, tetraethylorthosilicate silicon dioxide, or fluorinated-tetraethylorthosilicate silicon dioxide.
- the grating 16 may provide efficient optical isolation from the substrate 14 for light propagating in the waveguide core 12 , which may be effective to reduce mode leakage to the substrate 14 and improve performance.
- the grating 16 may permit the thickness of the dielectric layer 13 to be reduced, which may be effective to reduce self-heating of the waveguide core 12 and which may allow electrical back biasing for an optical component incorporating the waveguide core 12 .
- the grating 16 may also provide the ability to intentionally alter or tailor the mode size of light propagating in the waveguide core 12 .
- the pitch and/or the thickness of the layers 18 may be apodized (i.e., non-uniform) to define a non-periodic arrangement having an aperiodic variation in the index contrast.
- the grating 16 with apodized layers 18 may, for example, provide sidelobe suppression in addition to efficient optical isolation from the substrate 14 .
- the methods as described above are used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
- the end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
- references herein to terms modified by language of approximation such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified.
- the language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/ ⁇ 10% of the stated value(s).
- references herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference.
- the term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation.
- the terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined.
- the term “lateral” refers to a direction within the horizontal plane.
- a feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present.
- a feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent.
- a feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present.
- a feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present.
- a feature may be “directly on” or in “direct contact” with another feature if intervening features are absent.
- a feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present.
- Different features “overlap” if a feature extends over, and covers a part of, another feature.
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Abstract
Structures including a waveguide core and methods of fabricating a structure including a waveguide core. The structure comprises a substrate, a waveguide core, and a grating disposed in a vertical direction between the waveguide core and the substrate. The grating includes a first plurality of layers and a second plurality of layers that alternate in the vertical direction with the first plurality of layers. The first plurality of layers comprise a first material having a first refractive index, and the second plurality of layers comprise a second material having a second refractive index that is greater than the first refractive index.
Description
- The disclosure relates to photonics chips and, more specifically, to structures including a waveguide core and methods of fabricating a structure including a waveguide core.
- Photonics chips are used in many applications and systems including, but not limited to, data communication systems and data computation systems. A photonics chip integrates optical components and electronic components into a unified platform. Among other factors, layout area, cost, and operational overhead may be reduced by the integration of both types of components on the same chip. Waveguide cores used in photonics chips may suffer from significant leakage loss of propagating light to the substrate, which may degrade performance.
- Improved structures including a waveguide core and methods of fabricating a structure including a waveguide core are needed.
- In an embodiment of the invention, a structure comprises a substrate, a waveguide core, and a grating disposed in a vertical direction between the waveguide core and the substrate. The grating includes a first plurality of layers and a second plurality of layers that alternate in the vertical direction with the first plurality of layers. The first plurality of layers comprise a first material having a first refractive index, and the second plurality of layers comprise a second material having a second refractive index that is greater than the first refractive index.
- In an embodiment of the invention, a method comprises forming a grating on a substrate and forming a waveguide core over the grating in a vertical direction. The grating includes a first plurality of layers and a second plurality of layers that alternate in the vertical direction with the first plurality of layers. The first plurality of layers comprise a first material having a first refractive index, and the second plurality of layers comprise a second material having a second refractive index that is greater than the first refractive index.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.
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FIG. 1 is a cross-sectional view of a structure at an initial fabrication stage of a processing method in accordance with embodiments of the invention. -
FIG. 2 is a cross-sectional view of the structure at a fabrication stage of the processing method subsequent toFIG. 1 . -
FIG. 3 is a cross-sectional view of a structure in accordance with alternative embodiments of the invention - With reference to
FIG. 1 and in accordance with embodiments of the invention, astructure 10 includes awaveguide core 12 positioned over adielectric layer 13, asubstrate 14, and agrating 16 disposed in a vertical direction between thewaveguide core 12 and thesubstrate 14. In an embodiment, thedielectric layer 13 may be comprised of a dielectric material, such as silicon dioxide, and thesubstrate 14 may be comprised of a semiconductor material, such as single-crystal silicon. In an embodiment, thedielectric layer 13 may be a buried oxide layer of a silicon-on-insulator substrate. - In an embodiment, the
waveguide core 12 may be comprised of a material having a refractive index that is greater than the refractive index of silicon dioxide. In an embodiment, thewaveguide core 12 may be comprised of a dielectric material, such as silicon nitride. In an alternative embodiment, thewaveguide core 12 may be comprised of silicon oxynitride. In an alternative embodiment, thewaveguide core 12 may be comprised of a semiconductor material, such as silicon. In alternative embodiments, other materials, such as a polymeric material or a III-V compound semiconductor material, may be used to form thewaveguide core 12. In an embodiment, thewaveguide core 12 may be formed by patterning a layer of the material with lithography and etching processes. In an embodiment, thewaveguide core 12 may be formed by patterning the single-crystal silicon device layer of a silicon-on-insulator substrate with lithography and etching processes. - In the representative embodiment, the
waveguide core 12 is a ridge waveguide core. In alternative embodiments, thewaveguide core 12 may be a rib waveguide core, a slot waveguide core, or a different type of waveguide core. In embodiments,waveguide core 12 may include linear sections, curved sections, and/or tapered sections. - The
grating 16 includesmultiple layers 18 andmultiple layers 20 that are arranged in a layer stack in which thelayers 20 alternate in a vertical direction with thelayers 18. Thewaveguide core 12 is positioned on thedielectric layer 13 to overlap with thelayers grating 16. In an embodiment, thelayers 20 may fully separate thelayers 18 from each other. Due to the alternating arrangement, adjacent pairs of thelayers grating 16. In an embodiment, thegrating 16 may include five or more periods each including an adjacent pair of thelayers layers 18 may be positioned adjacent to thedielectric layer 13. In an embodiment, one of thelayers 18 may directly contact thedielectric layer 13. In an embodiment, one of thelayers 18 may be positioned adjacent to thesubstrate 14. In an embodiment, one of thelayers 18 may be in direct contact with thesubstrate 14. - In an embodiment, the
layers 18 may be comprised of a material having a refractive index (i.e., index of refraction) that is greater than the refractive index of the material constituting thelayers 20 to provide an index contrast or variation. In an embodiment, thelayers 20 may be comprised of a dielectric material, such as silicon dioxide, that has a lower refractive index than thewaveguide core 12. In an embodiment, thelayers 18 may be comprised of a material having a refractive index that is greater than the refractive index of silicon dioxide. In an embodiment, thelayers 18 may be comprised of a III-V compound semiconductor material, such as gallium nitride, aluminum nitride, indium nitride, or a combination of these materials. In an embodiment, thelayers 18 may be comprised of gallium nitride. In an embodiment, thelayers 18 may be comprised of a Group IV semiconductor material, such as silicon. In an embodiment, thelayers 18 may be comprised of silicon carbide. In an embodiment, thelayers 18 may be comprised of amorphous silicon. In an embodiment, thelayers 18 may be comprised of an optical gain material, such as a material including indium nitride quantum dots. In an embodiment, thelayers 18 may be comprised of a two-dimensional (2D) material, such as graphene, having a thickness of less than or equal to about 2 nanometers. In an embodiment, thelayers 18 may be comprised of a nanostructured material, such as a layered superlattice. - In an embodiment, the
grating 16 may be formed by multiple wafer-bonding processes that laminate thelayers 18 onto thesubstrate 14 using thelayers 20 to promote bonding. In an alternative embodiment, thegrating 16 may be formed by sequentially depositing thelayers 18 and thelayers 20 onto thesubstrate 14. - In an embodiment, the
layers 18 may be planar films having a uniform thickness between a planar top surface and a planar bottom surface. In an embodiment, the pitch and thickness of thelayers 18 may be uniform to define a periodic arrangement having a periodic variation in the index contrast. In an embodiment, thelayers 18 may have a thickness of about 200 nanometers to about 700 nanometers. - With reference to
FIG. 2 in which like reference numerals refer to like features inFIG. 1 and at a subsequent fabrication stage, adielectric layer 22 is formed over thewaveguide core 12. Thedielectric layer 22 may be comprised of a dielectric material, such as silicon dioxide, that is deposited and then planarized following deposition. In the representative embodiment, thewaveguide core 12 is embedded in thedielectric layer 22. The dielectric material constituting thedielectric layer 22 may have a refractive index that is less than the refractive index of the material constituting thewaveguide core 12. - A back-end-of-
line stack 24 may be formed over thedielectric layer 22. The back-end-of-line stack 24 may include multiple dielectric layers that are each comprised of a dielectric material, such as silicon dioxide, silicon nitride, tetraethylorthosilicate silicon dioxide, or fluorinated-tetraethylorthosilicate silicon dioxide. - The grating 16 may provide efficient optical isolation from the
substrate 14 for light propagating in thewaveguide core 12, which may be effective to reduce mode leakage to thesubstrate 14 and improve performance. The grating 16 may permit the thickness of thedielectric layer 13 to be reduced, which may be effective to reduce self-heating of thewaveguide core 12 and which may allow electrical back biasing for an optical component incorporating thewaveguide core 12. The grating 16 may also provide the ability to intentionally alter or tailor the mode size of light propagating in thewaveguide core 12. - With reference to
FIG. 3 and in accordance with alternative embodiments of the invention, the pitch and/or the thickness of thelayers 18 may be apodized (i.e., non-uniform) to define a non-periodic arrangement having an aperiodic variation in the index contrast. The grating 16 withapodized layers 18 may, for example, provide sidelobe suppression in addition to efficient optical isolation from thesubstrate 14. - The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
- References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/−10% of the stated value(s).
- References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane.
- A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. Different features “overlap” if a feature extends over, and covers a part of, another feature.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (23)
1. A structure comprising:
a substrate;
a waveguide core; and
a grating disposed in a vertical direction between the waveguide core and the substrate, the grating including a first plurality of layers and a second plurality of layers that alternate in the vertical direction with the first plurality of layers, the first plurality of layers comprising a first material having a first refractive index, and the second plurality of layers comprising a second material having a second refractive index that is greater than the first refractive index,
wherein the first material is silicon dioxide, the second material is gallium nitride, the waveguide core comprises a third material having a third refractive index, and the first refractive index is less than the third refractive index.
2-7. (canceled)
8. The structure of claim 1 further comprising:
a dielectric layer positioned in the vertical direction between the grating and the waveguide core.
9. The structure of claim 8 wherein one of the second plurality of layers directly contacts the dielectric layer.
10. The structure of claim 9 wherein one of the second plurality of layers directly contacts the substrate.
11. The structure of claim 1 wherein one of the second plurality of layers directly contacts the substrate.
12. The structure of claim 1 wherein the second plurality of layers have a uniform thickness.
13. The structure of claim 1 wherein the second plurality of layers have a non-uniform thickness.
14. (canceled)
15. A structure comprising:
a substrate;
a waveguide core; and
a grating disposed in a vertical direction between the waveguide core and the substrate, the grating including a first plurality of layers and a second plurality of layers that alternate in the vertical direction with the first plurality of layers, the first plurality of layers comprising a first material having a first refractive index, and the second plurality of layers comprising a second material having a second refractive index that is greater than the first refractive index,
wherein the second material is a two-dimensional material.
16. A structure comprising:
a substrate;
a waveguide core; and
a grating disposed in a vertical direction between the waveguide core and the substrate, the grating including a first plurality of layers and a second plurality of layers that alternate in the vertical direction with the first plurality of layers, the first plurality of layers comprising a first material having a first refractive index, and the second plurality of layers comprising a second material having a second refractive index that is greater than the first refractive index,
wherein the second material is a nanostructured material.
17. The structure of claim 1 wherein the third material is silicon.
18. The structure of claim 1 wherein the third material is silicon nitride.
19-20. (canceled)
21. The structure of claim 8 wherein the dielectric layer is a buried oxide layer of a silicon-on-insulator substrate.
22. The structure of claim 15 wherein the first material is a dielectric material that is an electrical insulator.
23. The structure of claim 15 wherein the second plurality of layers have a uniform thickness.
24. The structure of claim 15 wherein the second plurality of layers have a non-uniform thickness.
25. The structure of claim 15 further comprising:
a dielectric layer positioned in the vertical direction between the grating and the waveguide core.
26. The structure of claim 16 wherein the first material is a dielectric material that is an electrical insulator.
27. The structure of claim 16 wherein the second plurality of layers have a uniform thickness.
28. The structure of claim 16 wherein the second plurality of layers have a non-uniform thickness.
29. The structure of claim 16 further comprising:
a dielectric layer positioned in the vertical direction between the grating and the waveguide core.
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JP2726424B2 (en) | 1988-02-09 | 1998-03-11 | 株式会社日立製作所 | Optical element and manufacturing method thereof |
JP4168910B2 (en) | 2003-11-04 | 2008-10-22 | 日本電気株式会社 | Optical waveguide and optical waveguide manufacturing method |
US10718905B2 (en) | 2018-01-25 | 2020-07-21 | Poet Technologies, Inc. | Optical dielectric planar waveguide process |
US11609379B2 (en) | 2020-10-21 | 2023-03-21 | Globalfoundries U.S. Inc. | Structures for managing light polarization states on a photonics chip |
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US20050067625A1 (en) * | 2003-09-29 | 2005-03-31 | Sanyo Electric Co., Ltd. | Semiconductor light-emitting device |
US7321713B2 (en) * | 2004-09-17 | 2008-01-22 | Massachusetts Institute Of Technology | Silicon based on-chip photonic band gap cladding waveguide |
US20180081206A1 (en) * | 2016-09-20 | 2018-03-22 | Honeywell International Inc. | Optical waveguide having a wide brillouin bandwidth |
US10585245B1 (en) * | 2018-11-26 | 2020-03-10 | Globalfoundries Inc. | Multiple-layer arrangements using tunable materials to provide switchable optical components |
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