US20230362084A1

US20230362084A1 - Rational value rate limiter

Info

Publication number: US20230362084A1
Application number: US18/106,933
Authority: US
Inventors: Natan Manevich; Dotan David Levi; Alex Vainman; Roee Moyal
Original assignee: Mellanox Technologies Ltd
Current assignee: Mellanox Technologies Ltd
Priority date: 2022-05-09
Filing date: 2023-02-07
Publication date: 2023-11-09
Also published as: US20230361900A1; US20230362096A1

Abstract

A system includes a device configured to execute workloads coupled to a processing device. The processing device is to receive a request to execute one or more workloads, the request comprising two or more numbers corresponding to a rational value associated with a rate to execute the one or more workloads. The processing device is further to determine the rate to execute the one or more workloads responsive to receiving the two or more numbers corresponding to the rational values. The processing device is to execute the one or more workloads at the determined rate.

Description

TECHNICAL FIELD

At least one embodiment pertains to processing resources used to perform and facilitate rate limiting and pacing. For example, at least one embodiment pertains to technology for rational value rate limiting. For example, at least one embodiment relates to scheduling or executing workloads based on receiving a rational value at a rate limiter.

BACKGROUND

A device can receive and execute workload requests—e.g., transmit packets, perform an operation on data, etc. Some devices can include a rate limiter or rate pacing mechanism to control a rate of requests received or workloads executed—e.g., the device can include a rate limiter or rate pacing mechanism to ensure a number of workload requests does not exceed a threshold limit of the device. This can ensure the device is able to handle the workload requests in an efficient manner. Rate limiting, traffic shaping, rate pacing can be critical in computer network applications such as data center communication, media streaming, and congestion control algorithms—e.g., rate limiting can be used to avoid burst traffic and reduce congestion. For example, the device can be a network device that transmits packets—e.g., the device can transmit packets associated with video streaming to user devices. To ensure the packets are transmitted reliably and without congestion, the device can use a rate limiter to execute workloads at a desired rate. For example, the device can include a rate limiter to have a constant bit rate transmitted and to ensure bandwidth is not exceeded. In some examples, the rate at which to execute workloads or transmit packets is received from an operating system. Conventional devices can receive a single number corresponding to the rate value. However, some workload requests can include a rate limiting value that cannot be represented by a single number. Accordingly, conventional devices can fail to accurately limit at the rate indicated by the workload.

BRIEF DESCRIPTION OF DRAWINGS

Various embodiments in accordance with the present disclosure will be described with reference to the drawings, in which:

FIGS. 1A and 1B are examples of communication systems, in accordance with at least some embodiments;

FIG. 2 is a flow diagram of a method for a rational value rate limiter, in accordance with at least some embodiments

FIG. 3 is a flow diagram for a method for a rational value rate limiter, in accordance with at least some embodiments;

FIG. 4 is a flow diagram for a method for a rational value rate limiter, in accordance with at least some embodiments

FIG. 5 illustrates an example computer system including a transceiver including a chip-to-chip interconnect, in accordance with at least some embodiments.

DETAILED DESCRIPTION

As described above, devices can include a rate limiter to limit workloads received or executed at a respective time. The device can be used in data center communications, media streaming, or to enforce congestion control algorithms. In some examples, the device can receive a rate value or rate limit at which to receive or execute the workloads to reduce congestion. The device can also associate the rate value or limit with resources such as network flows, virtual machines (VM), with a host device in a multi-host system, with certain memory space ranges, link priority, etc. In some examples, the device can be a network device (e.g., network interface card (NIC), network adapter, network switch, data processing unit (DPU), etc.). The device can be responsible for transmitting data to coupled user devices in a reliable and efficient manner. For example, the device can be used to transmit packets of data associated with video streaming to the coupled user devices at a respective rate to ensure the packets are transmitted reliably and without exceeding bandwidth—e.g., the device can be at a data center and be used to transmit packets from the data center to user devices.
Conventional devices can include rate limiters or pacing mechanisms that support single number values associated with a respective rate due to hardware limitations and software configuration. For example, the conventional device can limit the rate to execute packets or transmit packets at a certain bits per second—e.g., the device can use the rate limiter to transmit bursts of packets every certain nanoseconds based on the rate. However, certain applications can use rate values that cannot be represented in a single fixed point or single number. For example, video streaming applications can use rate values that cannot be represented by a single number to support certain frame rate—e.g., a rate of 7/11 where 7 packets are sent every 11 seconds. Accordingly, conventional devices may use approximations rather than an actual value associated with the rate—e.g., approximate an infinite number associated with the rate as a finite number. Using approximate numbers instead of the actual value can cause inaccuracies and additional resources. For example, a device may approximate an infinite number corresponding to the rate value with a single 32 bit number. Over the course of billions of transmissions, using the 32 bit number approximation will result in an error between an actual execution or transmission rate and a desired execution or transmission rate. Accordingly, the device may be forced to periodically monitor or update the approximate 32 bit number to reduce a number of errors. This can consume additional resources and cause additional latencies to execute workloads.
Advantageously, aspects of the present disclosure can address the deficiencies above and other challenges by providing a rate limiter that can utilize a rational value. For example, the rate limiter of the device can be configured to receive a workload and a rate value or limit at which to execute the workload, where the rate value is rational value. In some embodiments, the rate value can be represented by two or more numbers—e.g., by a numerator and denominator, or an integer plus a numerator and denominator. Additionally, the rational value can represent bits per second, packets per second, bursts per second, inter packet gap (e.g., time between packet transmission), or inter burst gap (e.g., time between bursts). In some embodiments, the rate limiter of the device can include logic to utilize the rational value. For example, the rate limiter can include counter logic to transmit at the rate as described with reference to FIG. 2 . In other examples, the device can use other algorithms, calculations, or logic to utilize the rational value.
By utilizing a rate limiter capable of receiving a rational value, the device can accurately execute workloads according to a desired rate. For example, the device could transmit seven (7) packets every 11 (eleven) seconds based on a rational value 7/11 received. As the rational value is the desired rate, the device can avoid adjusting the rate continuously and avoid consuming additional resources.
FIG. 1A illustrates an example communication system 100 according to at least one example embodiment. The system 100 includes a device 110, a communication network 108 including a communication channel 109, and a device 112. In at least one embodiment, devices 110 and 112 are two end-point devices in a computing system, such as processing devices including a central processing unit (CPU), graphics processing unit (GPU) and/or data processing unit (DPU). In at least one embodiment, devices 110 and 112 are two servers. In at least one example embodiment, devices 110 and 112 correspond to one or more of a Personal Computer (PC), a laptop, a tablet, a smartphone, a server, a collection of servers, or the like. In some embodiments, the devices 110 and 112 may correspond to any appropriate type of device that communicates with other devices connected to a common type of communication network 108. According to embodiments, the receiver 104 of devices 110 or 112 may correspond to a GPU, a switch (e.g., a high-speed network switch), a network adapter, a CPU, a memory device, an input/output (I/O) device, other peripheral devices or components on a system-on-chip (SoC), or other devices and components at which a signal is received or measured, etc. As another specific but non-limiting example, the devices 110 and 112 may correspond to servers offering information resources, services, and/or applications to user devices, client devices, or other hosts in the system 100.
Examples of the communication network 108 that may be used to connect the devices 110 and 112 include an Internet Protocol (IP) network, an Ethernet network, an InfiniBand (IB) network, a Fibre Channel network, the Internet, a cellular communication network, a wireless communication network, a ground referenced signaling (GRS) link, combinations thereof (e.g., Fibre Channel over Ethernet), variants thereof, and/or the like. In one specific but non-limiting example, the communication network 108 is a network that enables data transmission between the devices 110 and 112 using data signals (e.g., digital, optical, wireless signals). In some embodiments, the communication network 108 can include one or more paths associated with transmitting data and one more paths associated with transmitting a clock signal.
The device 110 may include a transceiver 116 for sending and receiving signals, for example, data signals. The data signals may be digital or optical signals modulated with data or other suitable signals for carrying data.
The transceiver 116 may include a digital data source 120, a transmitter 102, a receiver 104, and processing circuitry 132 that controls the transceiver 116. The digital data source 120 may include suitable hardware and/or software for outputting data in a digital format (e.g., in binary code and/or thermometer code). The digital data output by the digital data source 120 may be retrieved from memory (not illustrated) or generated according to input (e.g., user input).
The transmitter 102 may include suitable software and/or hardware for receiving digital data from the digital data source 120 and outputting data signals according to the digital data for transmission over the communication network 108 to a receiver 104 of device 112. In at least one embodiment, the transmitter 102 can include a rational value rate limiter 115—e.g., a hardware component that can receive rational value rates and limit workload execution accordingly. In at least one embodiment, the rational value rate limiter 115 is configured to limit a rate of workloads executed (e.g., packets transmitted). In some examples, the rational value rate limiter 115 is configured to receive a rate from a software component that corresponds to a rational value. That is, the rational value rate limiter 115 can receive two or more numbers—e.g., a fractional value that has a numerator and a denominator or an integer plus a numerator and denominator. Additional details regarding the rational value rate limiter 115 are described with reference to FIG. 1B.
The receiver 104 of device 110 and 112 may include suitable hardware and/or software for receiving signals, such as data signals from the communication network 108. For example, the receiver 104 may include components for receiving processing signals to extract the data for storing in a memory, as described in detail below with respect to FIG. 2 -FIG. 4 .
The processing circuitry 132 may comprise software, hardware, or a combination thereof. For example, the processing circuitry 132 may include a memory including executable instructions and a processor (e.g., a microprocessor) that executes the instructions on the memory. The memory may correspond to any suitable type of memory device or collection of memory devices configured to store instructions. Non-limiting examples of suitable memory devices that may be used include Flash memory, Random Access Memory (RAM), Read Only Memory (ROM), variants thereof, combinations thereof, or the like. In some embodiments, the memory and processor may be integrated into a common device (e.g., a microprocessor may include integrated memory). Additionally or alternatively, the processing circuitry 132 may comprise hardware, such as an application-specific integrated circuit (ASIC). Other non-limiting examples of the processing circuitry 132 include an Integrated Circuit (IC) chip, a Central Processing Unit (CPU), a General Processing Unit (GPU), a microprocessor, a Field Programmable Gate Array (FPGA), a collection of logic gates or transistors, resistors, capacitors, inductors, diodes, or the like. Some or all of the processing circuitry 132 may be provided on a Printed Circuit Board (PCB) or collection of PCBs. It should be appreciated that any appropriate type of electrical component or collection of electrical components may be suitable for inclusion in the processing circuitry 132. The processing circuitry 132 may send and/or receive signals to and/or from other elements of the transceiver 116 to control the overall operation of the transceiver 116.
The transceiver 116 or selected elements of the transceiver 116 may take the form of a pluggable card or controller for the device 110. For example, the transceiver 116 or selected elements of the transceiver 116 may be implemented on a network interface card (NIC).
The device 112 may include a transceiver 136 for sending and receiving signals, for example, data signals over a channel 109 of the communication network 108. The same or similar structure of the transceiver 116 may be applied to transceiver 136, and thus, the structure of transceiver 136 is not described separately.
Although not explicitly shown, it should be appreciated that devices 110 and 112 and the transceivers 116 and 120 may include other processing devices, storage devices, and/or communication interfaces generally associated with computing tasks, such as sending and receiving data.
FIG. 1B illustrates an example communication system 150 according to at least one example embodiment. The system 150 can include a device 110 and an operating system 155. In some embodiments, the device 110 can include a rational value rate limiter 115. In some embodiments, the operating system 155 can be included in the device 110, and the rational value rate limiter 115 can be included in transceiver 116 as described with reference to FIG. 1A. In some embodiments, the operating system 155 can be included in a host device or host system that includes the device 110 or is coupled to the device 110.
In at least one embodiment, the operating system 155 is configured to transmit workload request(s) 160 to device 110. In some embodiments, the operating system 155 can also transmit a rational rate value 165 corresponding to the workload request(s) 160 to device 110. In some embodiments, the operating system 155 can select the rational rate value 165 based on specification or workload requirements—e.g., select a rational rate value 165 that conforms with a video streaming application specification. In some embodiments, the rational rate value 165 is transmitted within the workload request(s) 160. In at least one embodiment, the rational rate value 165 includes two or more numbers—e.g., the rational rate value 165 can be a fractional value including a numerator and a denominator. In at least one embodiment, the rational value 165 can include an integer plus a numerator and a denominator.
In some embodiments, the operating system 155 is configured to transmit the rational rate value 165 to device 110 to configure the rational rate value 165 to certain resources or components of device 110. For example, the operating system 155 can transmit the rational rate value 165 to associate the rational rate value 165 to a work queue of device 110, a network flow of device 110, to a virtual machine (VM) of device 110, to a host device of a multi-host system within system 150, to a respective memory space range (e.g., to a respective memory address range), or to a link priority—e.g., the operating system 155 can configure the rational rate value 165 to an Ethernet priority of device 110. In some embodiments, the operating system 155 can transmit multiple rational rate values 165 in parallel—e.g., the operating system 155 can transmit multiple workload requests 160 in parallel and a respective rational rate value 165 for each workload request 160. Accordingly, the device 110 can be configured to process multiple workloads each having a different rational rate value 165 in parallel.
In at least one embodiment, device 110 is configured to receive workload requests 160 and one or more rational rate values 165 from the operating system 155. In some embodiments, the device 110 is configured to execute one or more workloads received—e.g., execute an application, service, capability, or collection of resources and code. For example, the device 110 can be configured to process data or perform an operation responsive to receiving the workload request(s) 160. In some embodiments, the device 110 can be an example of a network device— e.g., a network interface card (NIC), network switch, network adapter, data processing unit (DPU), etc. In such embodiments, the device 110 can transmit and receive packets as part of executing a workload request—e.g., transmit packets to coupled user devices in response to receiving the workload request(s) 160. In other embodiments, the device 110 can encrypt received data at the rational rate value 165. In at least one embodiment, the device 110 can use the rational rate value 165 for a respective resource indicated in the workload request(s) 160— e.g., use the rational rate value 165 for work queue, a network flow, a VM, a host device, a link priority, etc.
In at least one embodiment, the rational value rate limiter 115 is configured to execute the workload request(s) 160 (e.g., or use an indicated resource) according to the rational rate value 165. For example, the rational rate value 165 can represent bits per second, packets per second, bursts (e.g., a number of bits/bytes or a number of packets) per second, inter packet gap (e.g., time between packet transmission), or inter burst gap (e.g., time between bursts). Accordingly, the rational value rate limiter 115 can receive the rational rate value 165 and determine the rate at which to execute the workloads. Although not illustrated, the rational rate value limiter 115 can include one or more logic components to utilize the rational rate value. FIG. 2 illustrates a possible example of logic utilized to implement the rational rate value 165. However, other possible calculations, logic, algorithms, etc., can be used to implement the rational rate value 165.
FIG. 2 illustrates a flow diagram of a method 200 for rational value rate limiter. The method 200 can be performed by processing logic comprising hardware, software, firmware, or any combination thereof. In at least one embodiment, the method 200 is performed by device 110 or rational value rate limiter 115 as described with reference to FIGS. 1A and 1B. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. FIG. 2 illustrates one possible example of implementing a rational value at the rate limiter. Other ways to implement the rational value using additional logic, other calculations or algorithms, are possible.
At operation 205, processing logic can receive a rational rate value—e.g., a rational rate value 165 as described with reference to FIG. 2 . In some embodiments, processing logic can receive the rational rate value in parallel with a workload request. In other embodiments, the processing logic can receive the rational rate value in a workload request. In at least one embodiment, the processing logic can receive the rational rate value to configure the rational rate value to a work queue, to a virtual machine (VM), to a host device of a multi-host system, to a respective memory space range (e.g., to a respective memory address range), or to a link priority. In least one embodiment, the rational rate value can be two or more numbers. In some embodiments, the rational rate value can correspond to a fractional value—e.g., the rational rate value can include a first number corresponding to a numerator and a second number corresponding to a denominator. In some embodiments, the rational rate value can be three or more numbers. For example, the rational rate value can include an integer plus a numerator and denominator—e.g., a value X Y/Z for example. In at least one embodiment, the rational rate value can represent the rate itself—e.g., it can represent bits per second units, packets per second, bursts per second (e.g., where the burst indicates a number of bits/bytes or a number of packets transmitted at a given time), an inter packet gap (e.g., time between transmitting packets or frames), or an burst gap (e.g., time between transmitting a burst). For example, the processing logic can receive a value A/B, where “A” is a first number and “B” is a second number, and the value indicates to transmit “A” packets or burst of data (e.g., a burst of 10,000 bytes) every B seconds—e.g., seconds, milliseconds, nanoseconds, picoseconds, etc. As an illustrative example, the processing logic could receive a value 7/11 that indicates to transmit 7 packets every 11 seconds.
At operation 210, processing logic increments a counter by a first number included in the rational rate value. For example, the processing logic increments a counter by the first number “A.” In at least one embodiment, the processing logic increments the counter by the first number after a predetermined duration passes or elapses. For example, the processing logic can increment the counter by the first number every one (1) second. In other embodiments, the processing logic can increment the counter by the first number at a different rate—e.g., once every couple of seconds, once every nanosecond, once every millisecond, etc. In at least one embodiment, the predetermined duration is associated with the rational rate value received. For example, the processing logic can increment the counter by the first number based on the units of the rational rate value. That is, if the processing logic receives a rational rate value 7/11 that indicates to transmit 7 packets every 11 seconds, the processing logic can increment the counter every second. If the processing logic receives a rational rate value 7/11 that indicates to transmit that indicates to transmit 7 packets every 11 milliseconds, the processing logic can increment the counter every millisecond. In at least one embodiment, the processing logic can increment the counter to a first value based on incrementing the counter by the first number.
At operation 215, processing logic can determine whether the first value of the counter (e.g., a counter value) satisfies a second number. For example, the processing device can determine whether the first value of the counter satisfies the second number “B” of the rational rate value. In at least one embodiment, the processing logic can determine if the first value satisfies the second number by comparing the first value to the second number. In such embodiments, the processing logic can determine the first value satisfies the second number if the first value is greater than or equal to the second number (e.g., if the first value matches or exceeds the second number). In other embodiments, the processing logic can determine the first value satisfies the second number if the first value is greater than the second value (e.g., if the first value exceeds the second number). In at least one embodiment, the processing logic can proceed to operation 220 if the first value of the counter satisfies the second number. In some embodiments, the processing logic can proceed to operation 230 if the first value of the counter fails to satisfy the second number.
At operation 220, processing logic can execute a workload 220 received at the rate indicated by the rational rate value. In least one embodiment, the processing logic can execute a workload (e.g., or a portion of a workload) each time the counter value satisfies the second number. Accordingly, the processing logic can execute the workload at the indicated rational rate value. In some embodiments, the processing logic can execute a portion of the workload during operation 220. For example, the processing logic can receive a workload to transmit packets at the respective rational rate value. The processing logic can execute the workload by continuously transmitting packets at the respective rational value rate. In such embodiments, the processing logic can proceed to operation 225. In embodiments the processing logic full executes the workload, the processing logic can conclude the operation.
At operation 225, processing logic decrements the counter by the second number included in the rational rate value. For example, the processing logic decrements the counter by the second number “B.” In at least one embodiment, the processing logic decrements the counter by the second number after executing a portion of the workload. For example, the processing logic can decrement the counter by the second number each time a packet is transmitted. In at least one embodiment, after decrementing the counter by the second number, the processing logic can proceed to operation 210 and continue operations 210-230 until the workload is full executed.
At operation 230, processing logic increments counter by a first number included in the rational rate value. For example, the processing logic increments the counter by the first number “A.” In at least one embodiment, the processing logic increments the counter by the first number after a predetermined duration passes or elapses. For example, the processing logic can increment the counter by the first number every one (1) second. In other embodiments, the processing logic can increment the counter by the first number at a different rate—e.g., once every couple of seconds, once every nanosecond, once every millisecond, etc. In at least one embodiment, the predetermined duration is associated with the rational rate value received. For example, the processing logic can increment the counter by the first number based on the units of the rational rate value. That is, if the processing logic receives a rational rate value 7/11 that indicates to transmit 7 packets every 11 seconds, the processing logic can increment the counter every second. If the processing logic receives a rational rate value 7/11 that indicates to transmit 7 packets every 11 milliseconds, the processing logic can increment the counter every millisecond. In at least one embodiment, the processing logic can increment the counter to a second value based on incrementing the counter by the first number a second time.
Table 1 below illustrates one example of executing a workload as described with reference to operations 205-230. In the illustrate example, the processing logic can receive a rational rate value of 7/11 where the value indicates to transmit 7 packets every 11 seconds. Accordingly, the processing logic can increment the counter by the first value (e.g., 7) each second. The processing logic can then compare the counter value to the second number (e.g., 11). If the processing logic determines the counter value fails to satisfy the second number, the processing logic can increment by the first number again—e.g., the processing logic can compare the counter value of 7 with the second number (e.g., 11) after one (1) second and determine the counter value fails to satisfy the second number and increment the counter value by the first number again. If the processing logic determines the counter value satisfies the second number, the processing logic can transmit a packet and decrement the counter value by the second number—e.g., the processing logic can determine the counter value 14 at two (2) seconds satisfies the second number, transmit a packet, and then decrement the counter value by the second number. The processing logic can continue this process until all packets are transmitted. Accordingly, the processing logic can execute the workload at the respective rational rate value (e.g., transmit 7 packets every 11 seconds as shown in Table 1).

TABLE 1

Second	Counter Value	Transmit Packet?

0	0	No
1	7	No
2	14 − 11 = 3	Yes
3	10	No
4	17 − 11 = 6	Yes
5	13 − 11 = 2	Yes
6	9	No
7	16 − 11 = 5	Yes
8	12 − 11 = 1	Yes
9	8	No
10	15 − 11 = 4	Yes
11	11 − 11 = 0	Yes
12	7	No
. . .

FIG. 3 illustrates a flow diagram of a method 300 for a rational value rate limiter, in accordance with at least some embodiments. The method 300 can be performed by processing logic comprising hardware, software, firmware, or any combination thereof. In at least one embodiment, the method 300 is performed by device 110 or rate limiter 115 as described with reference to FIGS. 1A-1B. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments.
At operation 305, processing logic receives a request to execute one or more workloads. In some embodiments, the request can include two or more numbers corresponding to a rational value associated with a rate to execute the one or more workloads. For example, the processing logic can receive a workload request 160 and a rational rate value 165 as described with reference to FIG. 1 . In some embodiments, the two or more numbers are associated with a fraction (e.g., a fractional value A/B as described with reference to FIG. 2 ). In such embodiments, a first number of the two or more numbers is a numerator and a second number of the two or more numbers is a denominator. In some embodiments, the processing logic can receive three or more numbers corresponding to a rational value associated with the rate. In such embodiments, the first number of the three or more numbers can be an integer, a second number of the three or more numbers is a numerator, and a third number of the three or more numbers is denominator (e.g., value X Y/Z as described with reference to FIG. 2 . In some embodiments, the processing logic can receive the request and rational value from an operating system (e.g., software). In at least one embodiment, the rate associated with two or more numbers corresponding to the rational value indicates at least one of a bits per bits per second rate, a packets per second rate, a bursts per second rate, an inter packet gap rate, or an inter burst gap rate. In at least one embodiment, the two or more numbers correspond to a rational value that is a repeating decimal number—e.g., corresponds to a number that is infinite. In at least one embodiment, the processing logic is in a device. In such embodiments, the device can be an example of a network interface card, a network device, or a data processing unit. In some embodiments, the rate is associated with a network flow, a work queue, a virtual machine (VM), a host device of a multi-host system, a memory space range, or a link priority. That is, the operating system (e.g., software) can configure the rational value rate to a respective resource as described with reference to FIG. 1B. In some embodiments, the processing logic can receive a plurality of requests to execute one or more workloads, each request of the plurality of requests including two or more numbers corresponding to a respective rational value associated with a rate to execute the one or more workloads. In that, the processing logic is configured to receive multiple rates in parallel. In some embodiments, each received rate is different than the others—e.g., the processing logic can handle multiple different rational value rates in parallel.
At operation 310, processing logic can determine the rate to execute the one or more workloads responsive to receiving the two or more numbers corresponding to the rational value. For example, the processing logic can determine the received rate is indicating to execute an “A” number of workloads every “B” unit of time—e.g., execute 7 workloads every 11 seconds as described with reference to FIG. 2 . In at least one embodiment, the processing logic can determine, for each request of the plurality of requests, the rate to execute the one or more respective workloads—e.g., the processing logic can determine the rates for the plurality of workloads received in parallel.
At operation 315, the processing logic can execute the one or more workloads at the determined rate. In at least one embodiment, the processing logic can execute the workloads as described with reference to FIG. 2 . For example, the processing logic can increment a counter by a first number (e.g., to a count value) of the two or more numbers after a predetermined duration elapses—e.g., increment the counter value of the counter. The processing logic can then determine whether the count value satisfies or fails to satisfy a second number of the two or more numbers after the predetermined duration elapses. In at least one embodiment, the processing logic can determine the count value satisfies (e.g., exceeds or is equal to) the second number of the two or more numbers. In such embodiments, the processing logic can execute a workload of the one or more workloads responsive to determining the count value satisfies the second number and decrement the counter by the second number of the two or more numbers responsive to executing the workload—e.g., decrement the counter value of the counter. In some embodiments, the processing logic can determine the count value fails to satisfy the second number of the two or more numbers and refrain from executing a workload of the one or more workloads responsive to determining the count value fails to satisfy the second number. In such embodiments, the processing logic can increment the counter by the first number of the two or more numbers to produce a second count value after the predetermined duration elapses and determine whether the second count value satisfies or fails to satisfy the second number of the two or more numbers after the predetermined duration elapses.
FIG. 4 illustrates a flow diagram of a method 400 for a rational value rate limiter, in accordance with at least some embodiments. The method 400 can be performed by processing logic comprising hardware, software, firmware, or any combination thereof. In at least one embodiment, the method 400 is performed by device 110 or rate limiter 115 as described with reference to FIGs. 1A-1B. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments.
At operation 405, processing logic receives a request to transmit one or more packets. In some embodiments, the request can include two or more numbers corresponding to a rational value associated with a rate to transmit the one or more packets. In some embodiments, the two or more numbers are associated with a fraction (e.g., a fractional value A/B as described with reference to FIG. 2 ). In such embodiments, a first number of the two or more numbers is a numerator and a second number of the two or more numbers is a denominator. In some embodiments, the processing logic can receive three or more numbers corresponding to a rational value associated with the rate. In such embodiments, the first number of the three or more numbers can be an integer, a second number of the three or more numbers is a numerator, and a third number of the three or more numbers is denominator (e.g., value X Y/Z as described with reference to FIG. 2 . In some embodiments, the processing logic can receive the request and rational value from an operating system (e.g., software). In at least one embodiment, the rate associated with two or more numbers corresponding to the rational value indicates at least one of a bits per bits per second rate, a packets per second rate, a bursts per second rate, an inter packet gap rate, or an inter burst gap rate. In at least one embodiment, the two or more numbers correspond to a rational value that is a repeating decimal number—e.g., corresponds to a number that is infinite. In at least one embodiment, the processing logic is in a device. In such embodiments, the device can be an example of a network interface card, a network device, or a data processing unit. In some embodiments, the rate is associated with a network flow, a work queue, a virtual machine (VM), a host device of a multi-host system, a memory space range, or a link priority. That is, the operating system (e.g., software) can configure the rational value rate to a respective resource as described with reference to FIG. 1B. In some embodiments, the processing logic can receive a plurality of requests to transmit one or more packets, each request of the plurality of requests including two or more numbers corresponding to a respective rational value associated with a rate to transmit the one or more packets. In that, the processing logic is configured to receive multiple rates in parallel. In some embodiments, each received rate is different than the others—e.g., the processing logic can handle multiple different rational value rates in parallel.
At operation 410, processing logic can determine the rate to transmit the one or more packets responsive to receiving the two or more numbers corresponding to the rational value. For example, the processing logic can determine the received rate is indicating to transmit an “A” number of packets every “B” unit of time—e.g., transmit 7 packets every 11 seconds as described with reference to FIG. 2 . In at least one embodiment, the processing logic can determine, for each request of the plurality of requests, the rate to transmit the one or more respective packets—e.g., the processing logic can determine the rates for the plurality of requests to transmit packets received in parallel.
At operation 415, the processing logic can transmit the one or more packets at the determined rate. In at least one embodiment, the processing logic can transmit the packets as described with reference to FIG. 2 . For example, the processing logic can increment a counter by a first number of the two or more numbers after a predetermined duration elapses—e.g., increment the count value of the counter. The processing logic can then determine whether the count value satisfies or fails to satisfy a second number of the two or more numbers after the predetermined duration elapses. In at least one embodiment, the processing logic can determine the count value satisfies (e.g., exceeds or is equal to) the second number of the two or more numbers. In such embodiments, the processing logic can transmit a packet of the one or more packets responsive to determining the count value satisfies the second number and decrement the counter by the second number of the two or more numbers responsive to transmitting the packet—e.g., decrement the count value of the counter. In some embodiments, the processing logic can determine the count value fails to satisfy the second number of the two or more numbers and refrain from transmitting a packets of the one or more packets responsive to determining the count value fails to satisfy the second number. In such embodiments, the processing logic can increment the counter by the first number of the two or more numbers to produce a second count value after the predetermined duration elapses and determine whether the second count value satisfies or fails to satisfy the second number of the two or more numbers after the predetermined duration elapses.
FIG. 5 illustrates a computer system 500 in accordance with at least one embodiment. In at least one embodiment, computer system 500 may be a system with interconnected devices and components, an SOC, or some combination. In at least one embodiment, computer system 500 is formed with a processor 502 that may include execution units to execute an instruction. In at least one embodiment, computer system 500 may include, without limitation, a component, such as processor 502 to employ execution units including logic to perform algorithms for processing data. In at least one embodiment, computer system 500 may include processors, such as PENTIUM® Processor family, Xeon™, Itanium®, XScale™ and/or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system 500 may execute a version of WINDOWS' operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used.
In at least one embodiment, computer system 500 may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (DSP), an SoC, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may perform one or more instructions. In an embodiment, computer system 500 may be used in devices such as graphics processing units (GPUs), network adapters, central processing units and network devices such as switch (e.g., a high-speed direct GPU-to-GPU interconnect such as the NVIDIA GH100 NVLINK or the NVIDIA Quantum 2 64 Ports InfiniBand NDR Switch).
In at least one embodiment, computer system 500 may include, without limitation, processor 502 that may include, without limitation, one or more execution units 507 that may be configured to execute a Compute Unified Device Architecture (“CUDA”) (CUDA® is developed by NVIDIA Corporation of Santa Clara, CA) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in a CUDA programming language. In at least one embodiment, computer system 500 is a single processor desktop or server system. In at least one embodiment, computer system 500 may be a multiprocessor system. In at least one embodiment, processor 502 may include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor 502 may be coupled to a processor bus 510 that may transmit data signals between processor 502 and other components in computer system 500.
In at least one embodiment, processor 502 may include, without limitation, a Level 1 (“L1”) internal cache memory (“cache”) 504. In at least one embodiment, processor 502 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 502. In at least one embodiment, processor 502 may also include a combination of both internal and external caches. In at least one embodiment, a register file 506 may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer register.
In at least one embodiment, execution unit 507, including, without limitation, logic to perform integer and floating point operations, also resides in processor 502. Processor 502 may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 502 may include logic to handle a packed instruction set 509. In at least one embodiment, by including packed instruction set 509 in an instruction set of a general-purpose processor 502, along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in a general-purpose processor 502. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using full width of a processor's data bus for performing operations on packed data, which may eliminate a need to transfer smaller units of data across a processor's data bus to perform one or more operations one data element at a time.
In at least one embodiment, an execution unit may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 500 may include, without limitation, a memory 520. In at least one embodiment, memory 520 may be implemented as a DRAM device, an SRAM device, flash memory device, or other memory device. Memory 520 may store instruction(s) 519 and/or data 521 represented by data signals that may be executed by processor 502.
In at least one embodiment, a system logic chip may be coupled to processor bus 510 and memory 520. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 516, and processor 502 may communicate with MCH 516 via processor bus 510. In at least one embodiment, MCH 516 may provide a high bandwidth memory path 518 to memory 520 for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH 516 may direct data signals between processor 502, memory 520, and other components in computer system 500 and to bridge data signals between processor bus 510, memory 520, and a system I/O 522. In at least one embodiment, system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 516 may be coupled to memory 520 through high bandwidth memory path 518 and graphics/video card 512 may be coupled to MCH 516 through an Accelerated Graphics Port (“AGP”) interconnect 514.
In at least one embodiment, computer system 500 may use system I/O 522 that is a proprietary hub interface bus to couple MCH 516 to I/O controller hub (“ICH”) 530. In at least one embodiment, ICH 530 may provide direct connections to some I/O devices via a local I/O bus. In at least one embodiment, local I/O bus may include, without limitation, a high-speed I/O bus for connecting peripherals to memory 520, a chipset, and processor 502. Examples may include, without limitation, an audio controller 529, a firmware hub (“flash BIOS”) 528, a transceiver 526, a data storage 524, a legacy I/O controller 523 containing a user input interface 525 and a keyboard interface, a serial expansion port 527, such as a USB, and a network controller 534. Data storage 524 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device. In an embodiment, the transceiver 526 includes a constrained FFE 508.
In at least one embodiment, FIG. 5 illustrates a system, which includes interconnected hardware devices or “chips” in a transceiver 526—e.g., the transceiver 526 includes a chip-to-chip interconnect including the first device 110 and second device 112 as described with reference to FIG. 1 ). In at least one embodiment, FIG. 5 may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in FIG. 5 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof and utilize a GRS link. In at least one embodiment, one or more components of system 500 are interconnected using compute express link (“CXL”) interconnects. In an embodiment, the transceiver 526 can include a rational value rate limiter 115 as described with reference to FIG. 1 . In such embodiments, the rational value rate limiter 115 is configured to receive a rate that can include two or more numbers. For example, rational value rate limiter 115 can receive a rate value that is fractional—e.g., includes a numerator and a denominator. In some embodiments, the rational value rate limiter 115 can receive an integer plus a numerator and a denominator. In at least one embodiment, the rational value rate limiter is configured to execute workloads at the rate value received. For example, the rational rate value limiter 115 can enable transceiver 526 to transmit packets at the rate value received.
Other variations are within spirit of present disclosure. Thus, while disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to a specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure, as defined in appended claims.
Use of terms “a” and “an” and “the” and similar referents in the context of describing disclosed embodiments (especially in the context of following claims) are to be construed to cover both singular and plural, unless otherwise indicated herein or clearly contradicted by context, and not as a definition of a term. Terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (meaning “including, but not limited to,”) unless otherwise noted. “Connected,” when unmodified and referring to physical connections, is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitations of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. In at least one embodiment, the use of the term “set” (e.g., “a set of items”) or “subset” unless otherwise noted or contradicted by context, is to be construed as a nonempty collection comprising one or more members. Further, unless otherwise noted or contradicted by context, the term “subset” of a corresponding set does not necessarily denote a proper subset of the corresponding set, but subset and corresponding set may be equal.
Conjunctive language, such as phrases of the form “at least one of A, B, and C,” or “at least one of A, B and C,” unless specifically stated otherwise or otherwise clearly contradicted by context, is otherwise understood with the context as used in general to present that an item, term, etc., may be either A or B or C, or any nonempty subset of the set of A and B and C. For instance, in an illustrative example of a set having three members, conjunctive phrases “at least one of A, B, and C” and “at least one of A, B and C” refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one of A, at least one of B and at least one of C each to be present. In addition, unless otherwise noted or contradicted by context, the term “plurality” indicates a state of being plural (e.g., “a plurality of items” indicates multiple items). In at least one embodiment, the number of items in a plurality is at least two, but can be more when so indicated either explicitly or by context. Further, unless stated otherwise or otherwise clear from context, the phrase “based on” means “based at least in part on” and not “based solely on.”
Operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process such as those processes described herein (or variations and/or combinations thereof) is performed under control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues) within transceivers of transitory signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having stored thereon executable instructions (or other memory to store executable instructions) that, when executed (i.e., as a result of being executed) by one or more processors of a computer system, cause a computer system to perform operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media comprises multiple non-transitory computer-readable storage media and one or more of individual non-transitory storage media of multiple non-transitory computer-readable storage media lack all of the code while multiple non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, executable instructions are executed such that different instructions are executed by different processors.
Accordingly, in at least one embodiment, computer systems are configured to implement one or more services that singly or collectively perform operations of processes described herein and such computer systems are configured with applicable hardware and/or software that enable the performance of operations. Further, a computer system that implements at least one embodiment of present disclosure is a single device and, in another embodiment, is a distributed computer system comprising multiple devices that operate differently such that distributed computer system performs operations described herein and such that a single device does not perform all operations.
Use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate embodiments of the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.
All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.
In description and claims, terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in particular examples, “connected” or “coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
Unless specifically stated otherwise, it may be appreciated that throughout specification terms such as “processing,” “computing,” “calculating,” “determining,” or like, refer to action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within computing system's registers and/or memories into other data similarly represented as physical quantities within computing system's memories, registers or other such information storage, transmission or display devices.
In a similar manner, the term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory and transform that electronic data into other electronic data that may be stored in registers and/or memory. A “computing platform” may comprise one or more processors. As used herein, “software” processes may include, for example, software and/or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Also, each process may refer to multiple processes, for carrying out instructions in sequence or in parallel, continuously or intermittently. In at least one embodiment, terms “system” and “method” are used herein interchangeably insofar as the system may embody one or more methods and methods may be considered a system.
In the present document, references may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways such as by receiving data as a parameter of a function call or a call to an application programming interface. In at least one embodiment, processes of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a serial or parallel interface. In at least one embodiment, processes of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a computer network from providing entity to acquiring entity. In at least one embodiment, references may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, processes of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transferring data as an input or output parameter of a function call, a parameter of an application programming interface or inter-process communication mechanism.
Although descriptions herein set forth example embodiments of described techniques, other architectures may be used to implement described functionality, and are intended to be within the scope of this disclosure. Furthermore, although specific distributions of responsibilities may be defined above for purposes of description, various functions and responsibilities might be distributed and divided in different ways, depending on circumstances.
Furthermore, although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that subject matter claimed in appended claims is not necessarily limited to specific features or acts described. Rather, specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

What is claimed is:

1. A system comprising:

a device configured to execute workloads coupled to a processing device, the processing device to:

receive a request to execute one or more workloads, the request comprising two or more numbers corresponding to a rational value associated with a rate to execute the one or more workloads;

determine the rate to execute the one or more workloads responsive to receiving the two or more numbers corresponding to the rational value; and

execute the one or more workloads at the determined rate.

2. The system of claim 1, wherein the rate associated with the two or more numbers corresponding to the rational value indicates at least one of a bits per second rate, a packets per second rate, a bursts per second rate, an inter packet gap rate, or an inter burst gap rate.

3. The system of claim 1, wherein the two or more numbers correspond to a rational value that is a repeating decimal number.

4. The system of claim 1, wherein to execute the one or more workloads at the rate, the processing device is to:

increment a count value of a counter by a first number of the two or more numbers after a predetermined duration elapses; and

determine whether the count value satisfies or fails to satisfy a second number of the two or more numbers after the predetermined duration elapses.

5. The system of claim 4, wherein the processing device is to:

determine the count value satisfies the second number of the two or more numbers;

execute a workload of the one or more workloads responsive to determining the count value satisfies the second number; and

decrement the count value at the counter by the second number of the two or more numbers responsive to executing the workload.

6. The system of claim 4, wherein the processing device is to:

determine the count value fails to satisfy the second number of the two or more numbers;

refrain from executing a workload of the one or more workloads responsive to determining the count value fails to satisfy the second number;

increment the count value by the first number of the two or more numbers to produce a second count value after the predetermined duration elapses; and

determine whether the second count value satisfies or fails to satisfy the second number of the two or more numbers after the predetermined duration elapses.

7. The system of claim 1, wherein the two or more numbers are associated with a fraction and a first number of the two or more numbers is a numerator and a second number of the two or more numbers is a denominator.

8. The system of claim 1, wherein the processing device is to:

receive a plurality of requests to execute one or more workloads, each request of the plurality of requests comprising two or more numbers corresponding to a respective rational value associated with a rate to execute the one or more workloads; and

determine, for each request of the plurality of requests, the rate to execute the one or more respective workloads.

9. The system of claim 1, wherein the rate is associated with a network flow, a work queue, a virtual machine (VM), a host device of a multi-host system, a memory space range, or a link priority.

10. The system of claim 1, wherein the device is a network interface card, a network device, or a data processing unit.

11. A method, comprising:

receiving a request to execute one or more workloads, the request comprising two or more numbers corresponding to a rational value associated with a rate to execute the one or more workloads;

determining the rate to execute the one or more workloads responsive to receiving the two or more numbers corresponding to the rational values; and

executing the one or more workloads at the determined rate.

12. The method of claim 11, wherein the rate associated with the two or more numbers corresponding to the rational value indicates at least one of a bits per second rate, a packets per second rate, a bursts per second rate, an inter packet gap rate, or an inter burst gap rate.

13. The method of claim 11, wherein the two or more numbers correspond to a rational value that is a repeating decimal number.

14. The method of claim 11, further comprising:

incrementing a count value of a counter by a first number of the two or more numbers after a predetermined duration elapses; and

determining whether the count value satisfies or fails to satisfy a second number of the two or more numbers after the predetermined duration elapses.

15. The method of claim 14, further comprising:

determining the count value satisfies the second number of the two or more numbers;

executing a workload of the one or more workloads responsive to determining the count value satisfies the second number; and

decrementing the count value at the counter by the second number of the two or more numbers responsive to executing the workload.

16. The method of claim 14, further comprising:

determining the count value fails to satisfy the second number of the two or more numbers;

refraining from executing a workload of the one or more workloads responsive to determining the count value fails to satisfy the second number;

incrementing the count value by the first number of the two or more numbers to produce a second count value after the predetermined duration elapses; and

determining whether the second count value satisfies or fails to satisfy the second number of the two or more numbers after the predetermined duration elapses.

17. A system comprising:

a network device coupled to a processing device, the processing device to:

receive a request to transmit one or more packets, the request comprising two or more numbers corresponding to a rational value associated with a rate to transmit the one or more packets;

determine the rate to transmit the one or more packets responsive to receiving the two or more numbers corresponding to the rational value; and

transmit the one or more packets at the determined rate.

18. The system of claim 17, wherein the rate associated with the two or more numbers corresponding to the rational value indicates at least one of a bits per second rate, a packets per second rate, a bursts per second rate, an inter packet gap rate, or an inter burst gap rate.

19. They system of claim 17, wherein the two or more numbers correspond to a rational value that is a repeating decimal number.

20. The system of claim 17, wherein the network device is a transceiver, a network adapter, a network switch, a network interface card, or a data processing unit.