US20230276632A1 - Semiconductor memory structure and method of manufacturing the same - Google Patents
Semiconductor memory structure and method of manufacturing the same Download PDFInfo
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- US20230276632A1 US20230276632A1 US18/312,766 US202318312766A US2023276632A1 US 20230276632 A1 US20230276632 A1 US 20230276632A1 US 202318312766 A US202318312766 A US 202318312766A US 2023276632 A1 US2023276632 A1 US 2023276632A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/10—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/50—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the boundary region between the core and peripheral circuit regions
Definitions
- Non-volatile memory is electronic memory that is able to store data in the absence of power.
- a promising candidate for the next generation of non-volatile memory is ferroelectric random-access memory (FeRAM).
- FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes.
- CMOS complementary metal-oxide-semiconductor
- FIG. 1 is a schematic perspective view illustrating a semiconductor memory structure in accordance with some embodiments of the present disclosure.
- FIG. 2 is a schematic perspective view illustrating a cell array region of the semiconductor memory structure of FIG. 1 , according to the present disclosure.
- FIG. 3 is a schematic perspective view illustrating the unit cell A in the cell array region of FIG. 2 according to the present disclosure.
- FIG. 4 is a cross-sectional top view of the unit cell A in the cell array region of FIG. 2 according to the present disclosure.
- FIG. 5 is a flow diagram of a method of manufacturing a semiconductor memory structure in accordance with some embodiments of the present disclosure.
- FIGS. 6 , 7 , 8 , 9 , 10 A, 11 A, 12 A, 13 A, 14 A, 15 , 16 and 17 are perspective views illustrating various stages in a method for forming a semiconductor memory structure according to aspects of one or more embodiments of the present disclosure.
- FIG. 10 B is a perspective view of a portion of a semiconductor memory structure of FIG. 10 A .
- FIGS. 11 B, 12 B, 13 B and 14 B are schematic cross-sectional views taken along line I-I′ of FIGS. 11 A, 12 A, 13 A and 14 A .
- FIGS. 18 , 19 , 20 , 21 , 22 , 23 and 24 are perspective views of a portion of a semiconductor memory structure in various stages subsequent to FIG. 17 in the method for forming a semiconductor memory structure according to aspects of one or more embodiments of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the device may be otherwise oriented (rotated 100 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- first,” “second” and “third” describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another.
- the terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.
- Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data when power is on, while non-volatile memory (NVM) is able to store data when power is off.
- NVM non-volatile memory
- FeRAM ferroelectric random-access memory
- NVM technology uses memory cells that are located within a back-end-of-the-line (BEOL) of an integrated chip (e.g., located between metal interconnect layers overlying a semiconductor substrate). The memory cells are stacked into multiple layers to create a three-dimensional (3D) structure.
- a source line (SL) and a bit line (BL) are formed on a channel stack in one memory cell.
- the channel stack comprises a word line (WL), a ferroelectric layer and a channel layer and the SL and BL are formed on the channel layer.
- the contact area (so called “channel lens”) between the SL and the channel layer as well as the contact area between the BL and the channel layer are small, so the SL and BL are usually formed on the channel layer symmetrically and separated from each other with a considerable distance.
- the polarization may not be switched unless a sufficiently large field (voltage) is applied at the word line. For example, a negative polarization (due to most negative voltage drop in the channel layer) may not be switched back to a positive polarization.
- the present disclosure relates to a design of 3D non-volatile memory structures for enhancing the switching performance and read speed.
- the provided structure can be applied to FeRAM and extendable to other memories such as flash, resistive random access memory (RRAM), magnetic random access memory (MRAM) with decent process and structure modifications. Accordingly, a stable type of 3D stackable nonvolatile memory devices can be formed, so that the device property can be enhanced.
- FIG. 1 is a schematic drawing illustrating a semiconductor memory structure 100 in accordance with one or more embodiments of the present disclosure.
- FIG. 2 shows a perspective view illustrating a cell array region of the semiconductor memory structure of FIG. 1 ; and FIGS. 3 and 4 show perspective and top views illustrating a unit cell A depicted in FIG. 2 .
- the semiconductor memory structure 100 includes a cell array region 200 sandwiched by two connection regions 300 .
- the cell array region 200 includes a plurality of stacking portions 210 and a plurality of cell regions 220 .
- the substrate 101 is a silicon substrate.
- the substrate 101 includes germanium, an alloy semiconductor (for example, SiGe), another suitable semiconductor material, or a combination thereof.
- the substrate 101 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.
- SOI silicon-on-insulator
- SGOI silicon germanium-on-insulator
- GOI germanium-on-insulator
- Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.
- the substrate 101 can include various devices, such as CMOS devices.
- the substrate 101 can include CMOS devices under array (CUA), but the disclosure is not limited thereto.
- the stacking portion 210 can be formed on the substrate 101 and includes a plurality of insulating layers 211 and a plurality of first conductive layers 212 stacking along a first direction D 1 . Further, the insulating layers 211 and the first conductive layers 212 are alternately arranged and are configured in a staircase structure (as shown in FIG. 1 ). The number of the alternating layers included in the stacking portion 210 can be as great as the number of layers needed for the semiconductor memory structure. Further, in some embodiments, the topmost layer and the bottommost layer can both be the insulating layers 211 , as shown in FIG. 1 , but the disclosure is not limited thereto.
- Thicknesses of the insulating layers 211 and thicknesses of the first conductive layers 212 can be similar or different, depending on different product requirements.
- the insulating layers 211 include an insulating material, such as silicon oxide, but the disclosure is not limited thereto.
- the first conductive layer 212 may include metals, but the disclosure is not limited thereto.
- the first conductive layers 212 correspond to word lines (WL).
- each first conductive layer 212 may be divided to two sublayers by glue layers 213 .
- Each glue layer 213 partially surrounds one sublayer so as to not only separate two adjacent sublayers from each other, but also separate the first conductive layer 212 from the adjacent insulating layers 211 .
- Each glue layer 213 may have a U shape, V shape, W shape and so on, but the disclosure is not limited thereto.
- the glue layer 213 may include oxides, such as Al 2 O 3 . The glue layer 213 can be used to improve adhesion of the metal portion in the stacking portion 210 .
- Each cell region 220 in the cell array region 200 can be formed over the substrate 101 and extend along a second direction D 2 and can be sandwiched by the stacking portions 210 , so that the cell regions 220 and the stacking portions 210 are alternately arranged along a third direction D 3 .
- each cell region 220 comprises a plurality of unit cells A.
- each cell region 220 comprises at least one central portion 221 extending through the cell array region 200 along the first direction D 1 , cell isolation structures 222 separating two or more central portions 221 from each other, and at least one ferroelectric layer 223 formed along sidewalls of the cell region 220 and besides the stacking portion 210 .
- the central portion 221 comprises a first conductive structure 224 , a second conductive structure 225 , a channel isolation structure 226 separating the first conductive structure 224 from the second conductive structure 225 , and two semiconductor layers 227 formed along the ferroelectric layers 223 , so that the first conductive structure 224 , the second conductive structure 225 and the channel isolation structure 226 are separated from the ferroelectric layers 223 through the semiconductor layer 227 .
- the first conductive structure 224 and the second conductive structure 225 independently penetrate through the cell array region 200 along the first direction D 1 to contact the substrate 101 .
- the first conductive structure 224 and the second conductive structure 225 are formed in a column shape, e.g., flat column or rectangular column shape, extending in the cell array region 200 along the first direction D 1 .
- the first conductive structure 224 corresponds to source lines and the second conductive structure 225 corresponds to bit lines.
- the first conductive structure 224 corresponds to bit lines and the second conductive structure 225 corresponds to source lines.
- the bit lines and the source lines can independently include various conductive materials, e.g., metal such as aluminum (Al), titanium (Ti), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), rhodium (Ru), tungsten (W), platinum (Pt) and/or alloys thereof, or a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or the like, but the disclosure is not limited thereto.
- metal such as aluminum (Al), titanium (Ti), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), rhodium (Ru), tungsten (W), platinum (Pt) and/or alloys thereof
- a metal nitride such as titanium nitride (TiN), tant
- the first conductive structures 224 correspond to source lines and the second conductive structures 225 correspond to bit lines.
- the first conductive structure 224 presents a T-shape from the top view and comprises a contact portion 2241 and an extension portion 2242 as shown in FIGS. 3 and 4 , which show perspective and top views of the unit cell A depicted in FIG. 2 .
- the contact portion 2241 of the first conductive structure 224 formed between the semiconductor layers 227 and has a contact area contacting the semiconductor layer 227 , which is substantially identical to the contact area of the second conductive structure 225 contacting the semiconductor layer 227 .
- the extension portion 2242 extends from the contact portion 2241 to the channel isolation structure 226 and can be separated from the semiconductor layers 227 through a dielectric layer 2243 .
- the dielectric layer 2243 may have a thickness from about 0.1 nm to about 50 nm. In some embodiments, the dielectric layer 2243 may have a thickness from about 1 nm to about 30 nm. In some embodiments, the dielectric layer 2243 may have a thickness from about 5 nm to about 20 nm.
- the dielectric layer 2243 may include, but not limited to, silicon oxide or silicon dioxide (SiO 2 ), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbide, carbon-containing silicon oxide, silicon oxycarbide (SiO x C y ), a high-k dielectric material, other suitable dielectric material, or combinations thereof.
- Exemplary high-k dielectric materials include hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), gallium oxide (Ga 2 O 3 ), titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), gadolinium oxide (Gd 2 O 3 ), yttrium oxide (Y 2 O 3 ), hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy, hafnium aluminum oxide (HfAlO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), titanium aluminum oxide (TiAlO), lanthanum aluminum oxide (such as LaAlO 3 ), other high-k dielectric
- the contact portion 2241 has a length L 1 from the cell isolation structures 222 to the extension portion 2242 and the extension portion 2242 has a length L 2 from the contact portion 2241 to the channel isolation structure 226 .
- L 1 may be longer than L 2 .
- L 2 may be longer than L 1 .
- L 1 may be similar or substantially equal to L 2 .
- the semiconductor layer 227 has a length L 4 in the central portion 221 and the length L 2 of the extension portion 2242 may range from about 10% to about 90% with respect to the length L 4 of the semiconductor layer 227 .
- the length L 2 of the extension portion 2242 may range from about 20% to about 80% with respect to the length L 4 of the semiconductor layer 227 . In some embodiments, the length L 2 of the extension portion 2242 may range from about 30% to about 70% with respect to the length L 4 of the semiconductor layer 227 .
- An asymmetric structure can be obtained by the extension of first conductive structure 224 (i.e. the source line).
- first conductive structure 224 i.e. the source line.
- a contact area between the first conductive structure 224 and the semiconductor layer 227 is similar to a contact area between the second conductive structure and the semiconductor layer 227 ; therefore the asymmetric first conductive structure 224 renders less impact to electrical resistances of the source line and the bit line and the read speed.
- the extension portion 2242 helps to enhance electric field, and thus, switching speed can be accelerated.
- the channel isolation structure 226 may be disposed between the semiconductor layers 227 and electrically isolates the first conductive structure 224 and the second conductive structure 225 . From the top view as shown in FIG. 4 , the channel isolation structure 226 has a length L 3 . In some embodiments, L 3 may be longer than, equal to or less than the length L 2 of the extension portion 2242 . In some embodiments, L 3 is equal to or less than the length L 2 of the extension portion 2242 . In some embodiments, L 3 is longer than, equal to or less than the length L 1 of the contact portion 2241 . In some embodiments, L 3 may range from about 1 nm to about 100 nm. In some embodiments, L 3 may range from about 3 nm to about 75 nm. In some embodiments, L 3 may range from about 5 nm to about 50 nm.
- the semiconductor layers 227 may include a semiconductor material.
- the semiconductor layers 227 may include various materials, such as an amorphous silicon (a-Si) material, a polycrystalline silicon (poly-Si) material, an oxide semiconductor material (e.g., indium zinc oxide (IZO), indium-gallium-zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), zinc oxide (ZnO), stannous oxide (SnO), and copper oxide (CuO)), or the like, but the disclosure is not limited to the above-mentioned materials.
- the semiconductor layers 227 may serve as channel. From the cross-sectional side view as shown in FIG.
- the semiconductor layer 227 has an L-shaped vertical cross section and comprises a longitudinal portion and a horizontal bottom.
- the dielectric layers 2243 may be formed along the longitudinal portion of the semiconductor layers 227 and formed on the horizontal bottom, so the dielectric layer 2243 may be substantially aligned with the end of the horizontal bottom of the semiconductor layers 227 as shown in FIG. 2 .
- the cell isolation structures 222 separate the central portions 221 from each other when there are two or more central portions 221 in one cell region 220 .
- the cell isolation structures 222 are arranged in an array configuration or a staggered array configuration.
- the cell isolation structures 222 penetrate through the cell array region 200 and contact the substrate 101 .
- the cell isolation structures 222 may include dielectric materials, including oxides, nitrides and the like, such as silicon oxide, silicon nitride, SiCN, Al 2 O 3 , HfO 2 , SiON, and La 2 O 3 , but the disclosure is not limited to the above-mentioned materials.
- the ferroelectric layer 223 can be formed besides the stacking portion 210 and thus can be sandwiched by the stacking portion 210 and the central portion 221 and also sandwiched by the stacking portion 210 and the cell isolation structures 222 .
- the ferroelectric layer 223 penetrates through the cell array region 200 along the first direction D 1 and is in contact with the substrate 101 .
- the first conductive layers 212 may correspond to word lines.
- the ferroelectric layers 223 are disposed between the first conductive layer 212 (i.e. word line) and the first conductive structure 224 (i.e. source line) or between the first conductive layer 212 (i.e. word line) and the second conductive structure 225 (i.e. bit line).
- the first conductive layers 212 can control the adjacent unit cell A in the same level as shown in FIGS. 3 and 4 .
- the ferroelectric layer 223 From the cross-sectional side view as shown in FIG. 2 , the ferroelectric layer 223 has an L-shaped vertical cross section; correspondingly, the semiconductor layer 227 formed along the ferroelectric layer 223 also has an L-shaped vertical cross section.
- the ferroelectric layer 223 comprises a longitudinal portion and a horizontal bottom to form the L-shaped vertical cross section.
- the longitudinal portion of the semiconductor layers 227 may be formed along the longitudinal portion of the ferroelectric layer 223 and the horizontal portion of the semiconductor layers 227 may be formed on the horizontal portion of the ferroelectric layer 223 , so an end of the horizontal portion of the semiconductor layers 227 may be substantially aligned with the end of the horizontal portion of the ferroelectric layer 223 as shown in FIG. 2 .
- the first conductive structure 224 and the second conductive structure 225 can contact the substrate 101 through a gap between the horizontal portions of two ferroelectric layers 223 beside the first and second conductive structures 224 and 225 .
- FIG. 5 is a flowchart representing a method 400 for forming a semiconductor memory structure according to various aspects of the present disclosure.
- the semiconductor memory structure 100 can be formed by the method 400 , but the disclosure is not limited thereto.
- the method 400 includes a number of operations ( 401 , 402 , 403 , 404 , 405 , 406 and 407 ) and the description and illustration are not deemed as a limitation as the sequence of the operations and the structure of the semiconductor memory structure.
- FIGS. 6 to 24 the reference numerals will be given like those, which have already been described above so as to omit the repetition of similar descriptions.
- Method 400 begins at operation 401 by forming a stack 210 a of alternating insulating layers 211 and first sacrificial layers 214 over a substrate 101 , as shown in FIG. 6 .
- the substrate 101 is provided as having already undergone several processing steps.
- the substrate 101 may be any suitable substrate such as a silicon, germanium, silicon-germanium, undoped, doped, bulk, silicon-on-insulator (“SOI”) or other substrate with or without additional circuitry.
- the stack 210 a includes a plurality of insulating layers 211 and a plurality of first sacrificial layers 214 , which are parallel to each other and sequentially stacked along a first direction D 1 .
- the uppermost layer of the stack 210 a is the insulating layer 211 .
- the number of the alternating layers included in the stack 210 a can be made as high as the number of layers needed.
- the stack 210 a may include between 16 and 512 layers of alternating insulating layers 211 and first sacrificial layers 214 , whereby each insulating or sacrificial layer constitutes one layer.
- the insulating layers 211 include an insulating material, such as oxides (e.g., silicon oxide (SiO 2 )).
- the first sacrificial layers 214 may include nitrides (e.g., silicon nitride (SiN)) or amorphous silicon. Other insulating materials may be used instead of silicon oxide. Other sacrificial materials may be used instead of silicon nitride. In some embodiments, each of the insulating layers 211 and the first sacrificial layers 214 may have substantially identical thickness.
- nitrides e.g., silicon nitride (SiN)
- Other insulating materials may be used instead of silicon oxide.
- Other sacrificial materials may be used instead of silicon nitride.
- each of the insulating layers 211 and the first sacrificial layers 214 may have substantially identical thickness.
- the insulating layers 211 and the first sacrificial layers 214 for forming the alternating stack 210 a may be deposited using any suitable technique, such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and sputtering.
- ALD atomic layer deposition
- PEALD plasma enhanced atomic layer deposition
- CVD chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- sputtering atomic layer deposition
- the insulating layers 211 and the first sacrificial layers 214 may be deposited by PECVD.
- portions of the insulating layers 211 and portions of the first sacrificial layers 214 are removed, such that remaining insulating layers 211 and remaining first sacrificial layers 214 form a staircase structure over the substrate 101 .
- portions of the first sacrificial layers 214 are exposed, and areas of the exposed portions of the first sacrificial layers 214 can be similar.
- the remaining portion of the topmost insulating layer 211 can be used to define a location and a dimension of a cell array region 200 .
- a dielectric structure 310 can be formed over the stack 210 a . Further, a top surface of the dielectric structure 310 can be aligned with a top surface of the topmost insulating layer 211 . Consequently, an even and flush surface can be obtained and the cell array region 200 is disposed between two connection regions 300 .
- a plurality of first trenches 510 are formed in the cell array region 200 and the connection regions 300 .
- each of the trenches 510 extends along a second direction D 2 and the first trenches 510 are arranged along a third direction D 3 , which is different from the first and second directions D 1 and D 2 .
- the first direction D 1 and the second direction D 2 are perpendicular to each other.
- the third direction D 3 is perpendicular to the first direction D 2 and is also perpendicular to the first direction D 1 . Further, widths and depths of the first trenches 510 are similar to each other.
- the substrate 101 can be exposed through a bottom of each trench 510 , but the disclosure is not limited thereto.
- the insulating layers 211 and the first sacrificial layers 214 can be exposed from the sidewalls of each trench 510 .
- the first sacrificial layers 214 can be replaced by metal to form first conductive layers 212 (i.e. word lines). As shown in FIGS. 10 A and 10 B , some portions of the first sacrificial layers 214 may be removed from the first trenches 510 to form first recesses 511 , so that the first sacrificial layers 214 will be replaced with conductive materials to form word lines.
- the first sacrificial layers 214 e.g., silicon nitride
- insulating layers 211 e.g., silicon oxide
- the removal of the first sacrificial layers 214 may involve introducing an etchant via the first trenches 510 .
- etching may be performed using a selective dry etch process, such as by exposing the substrate to any one or more of the following gases: chlorine (Cl 2 ), oxygen (O 2 ), nitrous oxide (N 2 O), or the like, but the disclosure is not limited thereto.
- the selective etching involves etching a first sacrificial layers 214 at a rate faster than etching materials for insulating layers 211 . Any suitable etching process and etchant may be used.
- first conductive layers 212 can be formed in the first recesses 511 via the first trenches 510 to form word lines.
- a metal/oxide stack is formed, in which the insulating layers 211 (e.g., silicon oxide (SiO 2 )) can separate the metal word lines.
- the first conductive layers 212 include various conductive materials, e.g., metal such as aluminum (Al), titanium (Ti), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), rhodium (Ru), tungsten (W), platinum (Pt) and/or alloys thereof, or a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or the like, but the disclosure is not limited thereto.
- CVD chemical vapor deposition
- ALD atomic layer deposition
- the excessive conductive material e.g., the materials outside the recesses, at the bottom of the first trenches 510 , and on the surface of the uppermost insulating layers 211 , can be removed, e.g., by etching, so that the bottom surfaces of the first trenches 510 , the sidewalls of the insulating layers 211 , and the surface of the uppermost insulating layers 211 can be exposed.
- glue layers 213 may be formed along the sidewall of the first recesses 511 , so that the shape of glue layers 213 corresponds to the sidewall of the first recesses 511 .
- each glue layer 213 may have a U shape, V shape, W shape and so on, depending on the shape of the sidewalls of the recesses 511 , but the disclosure is not limited thereto.
- the glue layers 213 may be formed by using ALD, CVD, physical vapor deposition (PVD) or other methods.
- Each glue layer 213 partially surrounds the corresponding first conductive layer 212 , so that the first conductive layer 212 can be exposed from the first trench 510 but not contact the adjacent insulating layers 211 and/or dielectric structure 310 .
- the glue layer 213 can improve adhesion of the first conductive layer 212 with adjacent insulating layers 211 and/or dielectric structure 310 .
- Operation 404 includes filling each of the first trenches 510 with a multi-layered structure.
- the multi-layered structure can be formed by any suitable methods that are known in the art.
- the first trenches 510 may be filled in by sequentially depositing a ferroelectric layer 223 , a semiconductor layer 227 and a dielectric layer 2243 along the sidewalls and bottoms of the first trenches 510 , e.g., using ALD.
- other suitable layers such as an interfacial layer, e.g., SiO 2 , SiON, or Al 2 O 3 , can be formed in combination with the ferroelectric layer 223 .
- portions of the ferroelectric layer 223 and portions of the semiconductor layer 227 may be removed from the bottom of the first trenches 510 , so as to expose the substrate 101 from the first trenches 510 .
- the ferroelectric layer 223 has an L-shaped vertical cross section; correspondingly, the semiconductor layer 227 forming along the ferroelectric layer 223 also has an L-shaped vertical cross section as shown in FIG. 13 B .
- the first trenches 510 can be filled with a first sacrificial material 610 .
- a chemical mechanical polishing (CMP) may be carried out to planarize the surface of the structure.
- the first sacrificial material 610 may include nitrides (e.g., silicon nitride (SiN)) or amorphous silicon, but the disclosure is not limited thereto.
- FIG. 15 shows that second trenches 520 can be formed in the cell array region 200 and the connection regions 300 to expose the first sacrificial layers 214 from the second trenches 520 .
- Each second trench 520 can be formed at a location between two multi-layered structure filled in the first trenches 510 .
- FIG. 16 shows that the first sacrificial layers 214 can be replaced by metal to form first conductive layers 212 (i.e. word lines); and, in some embodiments, glue layers 213 may be formed to adhere the first conductive layers 212 to adjacent insulating layers 211 and/or adjacent glue layers 213 previously formed through the first trenches 510 .
- FIG. 15 shows that second trenches 520 can be formed in the cell array region 200 and the connection regions 300 to expose the first sacrificial layers 214 from the second trenches 520 .
- Each second trench 520 can be formed at a location between two multi-layered structure filled in the first trenches 510 .
- FIG. 16 shows that
- each of the second trenches 520 are filled with a multi-layered structure, including a ferroelectric layer 223 , a semiconductor layer 227 , a dielectric layer 2243 and a second sacrificial material 620 , identical or similar to the multi-layered structure formed in the first trenches 510 ; therefore, repeated descriptions of such details are omitted for brevity.
- the second sacrificial material 620 may include nitrides (e.g., silicon nitride (SiN)) or amorphous silicon, but the disclosure is not limited thereto.
- widths of the multi-layered structure in the first trenches 510 and widths of the multi-layered structure in the second trenches 520 are similar.
- the multi-layered structures in the first trenches 510 and the multi-layered structures in the second trenches 520 are alternately arranged along the third direction D 3 . Further, distances between the adjacent multi-layered structures in the first trench 510 and the second trench 520 are similar.
- portions of the first sacrificial material 610 , portions of the second sacrificial material 620 , and portions of the dielectric layer 2243 can be removed to form a plurality of third trenches 530 .
- the third trenches 530 are separated from each other by remaining portions 700 , which is used to define the location of extension portions 2242 of first conductive structures 224 to be formed and is described below.
- the third trenches 530 and the remaining portions 700 are arranged alternately.
- the third trenches 530 are formed to expose a portion of the substrate 101 .
- Each remaining portion 700 can be disposed between two semiconductor layers 227 and includes two dielectric layer 2243 formed separately along two semiconductor layers 227 .
- the dielectric layer 2243 is sectioned by the third trenches 530 .
- the first and second sacrificial materials 610 and 620 are sandwiched by the two dielectric layers 2243 .
- each remaining portion 700 has two opposite sides exposed from the third trenches 530 .
- the third trenches 530 may be filled with a third sacrificial materials 630 .
- the third sacrificial materials 630 may be identical to or different from the first and second sacrificial materials 610 and 620 .
- a plurality of channel isolation trenches 550 can be formed next to one side of the remaining portions 700 by removing some portions of the third sacrificial materials 630 .
- the channel isolation trenches 550 can extend downwardly from the top surface of the cell array region 200 to expose the substrate 101 , so one side of each remaining portion 700 and two semiconductor layers 227 can be exposed from the channel isolation trenches 550 .
- the channel isolation trenches 550 can be filled with isolation material, such as an isolation oxide (e.g., SiO 2 ) or other suitable materials, to form channel isolation structure 226 .
- cell isolation trenches 560 can be formed in the third sacrificial materials 630 by removing some portions of the third sacrificial materials 630 as well as the semiconductor layers 227 , so that the third sacrificial materials 630 can be divided into two parts.
- One part of the third sacrificial materials 630 next to the remaining portion 700 defines the location of a contact portion 2241 of the first conductive structure 224 to be formed, and the other part of the third sacrificial materials 630 next to the channel isolation structure 226 defines the location of a second conductive structure 225 to be formed.
- the cell isolation trenches 560 can extend downwardly from the top surface of the cell array region 200 to expose the substrate 101 , so that one side of each part of the third sacrificial materials 630 and two ferroelectric layers 223 can be exposed from each cell isolation trench 560 .
- the cell isolation trenches 560 can be filled with isolation material, such as an isolation oxide (e.g., SiO 2 ) or other suitable materials, to form cell isolation structure 222 .
- the first and second sacrificial materials 610 and 620 in the remaining portion 700 and the third sacrificial materials 630 can be replaced with conductive materials to form first conductive structures 224 and second conductive structures 225 .
- the first and second sacrificial materials 610 and 620 in the remaining portions 700 can be replaced with conductive materials to form an extension portion 2242 of the first conductive structures 224 .
- One part of the third sacrificial materials 630 next to the remaining portion 700 can be replaced with conductive materials to form a contact portion 2241 of the first conductive structures 224 .
- the contact portion 2241 of the first conductive structure 224 is disposed between two semiconductor layers 227 and the extension portion of the first conductive structures 224 is disposed between two dielectric layers 2243 , so that the first conductive structures 224 partially contact the semiconductor layer 227 and partially contact the dielectric layer 2243 .
- the contact portion 2241 and the extension portion 2242 may present a T-shape.
- the other part of the third sacrificial materials 630 next to the channel isolation structure 226 can be replaced with conductive materials to form the second conductive structure 225 .
- Materials for dielectric layers 2243 may have different etching selectivity to the sacrificial materials 610 , 620 and 630 , so that when the sacrificial materials 610 , 620 and 630 are removed by etching procedure, the dielectric layers 2243 can be less impacted or consumed.
- a method of manufacturing a semiconductor memory structure comprises: forming a stack of alternating insulating layers and sacrificial layers over a substrate; forming a plurality of trenches in the stack; replacing the sacrificial layers with first conductive layers; filling each of the plurality of trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, and a dielectric layer; removing portions of the multi-layered structure to leave remaining portions, so that the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers; forming cell isolation structures between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and forming channel isolation structures between the semiconductor layers of each two adjacent multi-layered structures of the multi-layered structures; and forming first conductive structures and second conductive structures, wherein each of the first conductive structures is disposed between one of the cell isolation structures and an adjacent channel isolation structure of the channel isolation structures, and
- a method of manufacturing a semiconductor memory structure comprises: forming a stack of alternating insulating layers and sacrificial layers over a substrate; forming a plurality of first trenches in the stack; replacing the sacrificial layers with conductive layers; sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of first trenches; removing portions of the dielectric layer, portions of the semiconductor layer and portions of the ferroelectric layer to expose the substrate from the plurality of first trenches; filling the plurality of first trenches with a first sacrificial material; forming a plurality of second trenches in the stack, wherein the plurality of second trenches and the plurality of first trench are arranged alternately; sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of second trenches; removing portions of the dielectric layer,
- a method of manufacturing a semiconductor memory structure comprises: forming a stack of alternating insulating layers and conductive layers over a substrate, wherein the stack has a plurality of first trenches; filling each of the plurality of first trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, a dielectric layer, and first sacrificial materials; removing portions of the multi-layered structure to form a plurality of second trenches and a plurality of remaining portions, wherein the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers; filling the plurality of second trenches with second sacrificial materials; forming cell isolation structures and channel isolation structures by removing portions of the second sacrificial materials, wherein the cell isolation structures are positioned between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and the channel isolation structures are positioned between the semiconductor layers of each two adjacent
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- Semiconductor Memories (AREA)
Abstract
A semiconductor memory structure and a method of manufacturing a semiconductor memory structure are provided. The semiconductor memory structure includes alternatively arranged stacking portions and cell regions. Each cell region includes two ferroelectric layers formed along the adjacent stacking portions; and at least one central portion disposed between the ferroelectric layers and includes a first conductive structure and a second conductive structure separated by a channel isolation structure as well as two semiconductor layers formed along the ferroelectric layers. The first conductive structure includes a contact portion and an extension portion. The contact portion is disposed between the semiconductor layers. The extension portion extends from the contact portion to the channel isolation structure and is separated from the semiconductor layers through dielectric layers.
Description
- This application is a divisional application of U.S. patent application Ser. No. 17/141,915 filed on Jan. 5, 2021, entitled of “SEMICONDUCTOR MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME”; this application is incorporated herein by reference in their entireties.
- Many modern-day electronic devices include non-volatile memory. Non-volatile memory is electronic memory that is able to store data in the absence of power. A promising candidate for the next generation of non-volatile memory is ferroelectric random-access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying Figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 is a schematic perspective view illustrating a semiconductor memory structure in accordance with some embodiments of the present disclosure. -
FIG. 2 is a schematic perspective view illustrating a cell array region of the semiconductor memory structure ofFIG. 1 , according to the present disclosure. -
FIG. 3 is a schematic perspective view illustrating the unit cell A in the cell array region ofFIG. 2 according to the present disclosure. -
FIG. 4 is a cross-sectional top view of the unit cell A in the cell array region ofFIG. 2 according to the present disclosure. -
FIG. 5 is a flow diagram of a method of manufacturing a semiconductor memory structure in accordance with some embodiments of the present disclosure. -
FIGS. 6, 7, 8, 9, 10A, 11A, 12A, 13A, 14A, 15, 16 and 17 are perspective views illustrating various stages in a method for forming a semiconductor memory structure according to aspects of one or more embodiments of the present disclosure. -
FIG. 10B is a perspective view of a portion of a semiconductor memory structure ofFIG. 10A . -
FIGS. 11B, 12B, 13B and 14B are schematic cross-sectional views taken along line I-I′ ofFIGS. 11A, 12A, 13A and 14A . -
FIGS. 18, 19, 20, 21, 22, 23 and 24 are perspective views of a portion of a semiconductor memory structure in various stages subsequent toFIG. 17 in the method for forming a semiconductor memory structure according to aspects of one or more embodiments of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 100 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- As used herein, the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.
- Many modern day electronic devices contain electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data when power is on, while non-volatile memory (NVM) is able to store data when power is off. For example, ferroelectric random-access memory (FeRAM) devices are one promising candidate for a next generation NVM technology. This is because FeRAM devices provide many advantages, including fast write time, high endurance, low power consumption, and low susceptibility to damage from radiation. NVM technology uses memory cells that are located within a back-end-of-the-line (BEOL) of an integrated chip (e.g., located between metal interconnect layers overlying a semiconductor substrate). The memory cells are stacked into multiple layers to create a three-dimensional (3D) structure.
- For the FeRAM, an electric field is required to switch the polarization between positive and negative voltages to store information. In some embodiments, a source line (SL) and a bit line (BL) are formed on a channel stack in one memory cell. The channel stack comprises a word line (WL), a ferroelectric layer and a channel layer and the SL and BL are formed on the channel layer. To retain low resistance, the contact area (so called “channel lens”) between the SL and the channel layer as well as the contact area between the BL and the channel layer are small, so the SL and BL are usually formed on the channel layer symmetrically and separated from each other with a considerable distance. The polarization may not be switched unless a sufficiently large field (voltage) is applied at the word line. For example, a negative polarization (due to most negative voltage drop in the channel layer) may not be switched back to a positive polarization.
- The present disclosure relates to a design of 3D non-volatile memory structures for enhancing the switching performance and read speed. In some embodiments, the provided structure can be applied to FeRAM and extendable to other memories such as flash, resistive random access memory (RRAM), magnetic random access memory (MRAM) with decent process and structure modifications. Accordingly, a stable type of 3D stackable nonvolatile memory devices can be formed, so that the device property can be enhanced.
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FIG. 1 is a schematic drawing illustrating asemiconductor memory structure 100 in accordance with one or more embodiments of the present disclosure. To take a closer look,FIG. 2 shows a perspective view illustrating a cell array region of the semiconductor memory structure ofFIG. 1 ; andFIGS. 3 and 4 show perspective and top views illustrating a unit cell A depicted inFIG. 2 . - In some embodiments, as shown in
FIG. 1 , thesemiconductor memory structure 100 includes acell array region 200 sandwiched by twoconnection regions 300. With further reference toFIG. 2 , thecell array region 200 includes a plurality of stackingportions 210 and a plurality ofcell regions 220. In some embodiments, thesubstrate 101 is a silicon substrate. Alternatively or additionally, thesubstrate 101 includes germanium, an alloy semiconductor (for example, SiGe), another suitable semiconductor material, or a combination thereof. Alternatively, thesubstrate 101 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. In some embodiments, thesubstrate 101 can include various devices, such as CMOS devices. For example, thesubstrate 101 can include CMOS devices under array (CUA), but the disclosure is not limited thereto. - In some embodiments, the
stacking portion 210 can be formed on thesubstrate 101 and includes a plurality ofinsulating layers 211 and a plurality of firstconductive layers 212 stacking along a first direction D1. Further, the insulatinglayers 211 and the firstconductive layers 212 are alternately arranged and are configured in a staircase structure (as shown inFIG. 1 ). The number of the alternating layers included in the stackingportion 210 can be as great as the number of layers needed for the semiconductor memory structure. Further, in some embodiments, the topmost layer and the bottommost layer can both be the insulatinglayers 211, as shown inFIG. 1 , but the disclosure is not limited thereto. Thicknesses of the insulatinglayers 211 and thicknesses of the firstconductive layers 212 can be similar or different, depending on different product requirements. In some embodiments, the insulatinglayers 211 include an insulating material, such as silicon oxide, but the disclosure is not limited thereto. In some embodiments, the firstconductive layer 212 may include metals, but the disclosure is not limited thereto. In some embodiments, the firstconductive layers 212 correspond to word lines (WL). - In some embodiments, each first
conductive layer 212 may be divided to two sublayers by glue layers 213. Eachglue layer 213 partially surrounds one sublayer so as to not only separate two adjacent sublayers from each other, but also separate the firstconductive layer 212 from the adjacent insulatinglayers 211. Eachglue layer 213 may have a U shape, V shape, W shape and so on, but the disclosure is not limited thereto. In some embodiments, theglue layer 213 may include oxides, such as Al2O3. Theglue layer 213 can be used to improve adhesion of the metal portion in the stackingportion 210. - Each
cell region 220 in thecell array region 200 can be formed over thesubstrate 101 and extend along a second direction D2 and can be sandwiched by the stackingportions 210, so that thecell regions 220 and the stackingportions 210 are alternately arranged along a third direction D3. In some embodiments, eachcell region 220 comprises a plurality of unit cells A. In some embodiments, eachcell region 220 comprises at least onecentral portion 221 extending through thecell array region 200 along the first direction D1,cell isolation structures 222 separating two or morecentral portions 221 from each other, and at least oneferroelectric layer 223 formed along sidewalls of thecell region 220 and besides the stackingportion 210. - In some embodiments, the
central portion 221 comprises a firstconductive structure 224, a secondconductive structure 225, achannel isolation structure 226 separating the firstconductive structure 224 from the secondconductive structure 225, and twosemiconductor layers 227 formed along theferroelectric layers 223, so that the firstconductive structure 224, the secondconductive structure 225 and thechannel isolation structure 226 are separated from theferroelectric layers 223 through thesemiconductor layer 227. - In some embodiments, the first
conductive structure 224 and the secondconductive structure 225 independently penetrate through thecell array region 200 along the first direction D1 to contact thesubstrate 101. The firstconductive structure 224 and the secondconductive structure 225 are formed in a column shape, e.g., flat column or rectangular column shape, extending in thecell array region 200 along the first direction D1. In some embodiments, the firstconductive structure 224 corresponds to source lines and the secondconductive structure 225 corresponds to bit lines. In some embodiments, the firstconductive structure 224 corresponds to bit lines and the secondconductive structure 225 corresponds to source lines. In some embodiments, the bit lines and the source lines can independently include various conductive materials, e.g., metal such as aluminum (Al), titanium (Ti), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), rhodium (Ru), tungsten (W), platinum (Pt) and/or alloys thereof, or a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or the like, but the disclosure is not limited thereto. - In some embodiments, the first
conductive structures 224 correspond to source lines and the secondconductive structures 225 correspond to bit lines. The firstconductive structure 224 presents a T-shape from the top view and comprises acontact portion 2241 and anextension portion 2242 as shown inFIGS. 3 and 4 , which show perspective and top views of the unit cell A depicted inFIG. 2 . In some embodiments, thecontact portion 2241 of the firstconductive structure 224 formed between the semiconductor layers 227 and has a contact area contacting thesemiconductor layer 227, which is substantially identical to the contact area of the secondconductive structure 225 contacting thesemiconductor layer 227. Theextension portion 2242 extends from thecontact portion 2241 to thechannel isolation structure 226 and can be separated from the semiconductor layers 227 through adielectric layer 2243. In some embodiments, thedielectric layer 2243 may have a thickness from about 0.1 nm to about 50 nm. In some embodiments, thedielectric layer 2243 may have a thickness from about 1 nm to about 30 nm. In some embodiments, thedielectric layer 2243 may have a thickness from about 5 nm to about 20 nm. In some embodiments, thedielectric layer 2243 may include, but not limited to, silicon oxide or silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbide, carbon-containing silicon oxide, silicon oxycarbide (SiOxCy), a high-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary high-k dielectric materials include hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), gallium oxide (Ga2O3), titanium oxide (TiO2), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), gadolinium oxide (Gd2O3), yttrium oxide (Y2O3), hafnium dioxide-alumina (HfO2—Al2O3) alloy, hafnium aluminum oxide (HfAlO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), titanium aluminum oxide (TiAlO), lanthanum aluminum oxide (such as LaAlO3), other high-k dielectric material, or combinations thereof. - From the top view of the first
conductive structure 224 as shown inFIG. 4 , thecontact portion 2241 has a length L1 from thecell isolation structures 222 to theextension portion 2242 and theextension portion 2242 has a length L2 from thecontact portion 2241 to thechannel isolation structure 226. In some embodiments, L1 may be longer than L2. In some embodiments, L2 may be longer than L1. In some embodiments, L1 may be similar or substantially equal to L2. In some embodiments, thesemiconductor layer 227 has a length L4 in thecentral portion 221 and the length L2 of theextension portion 2242 may range from about 10% to about 90% with respect to the length L4 of thesemiconductor layer 227. In some embodiments, the length L2 of theextension portion 2242 may range from about 20% to about 80% with respect to the length L4 of thesemiconductor layer 227. In some embodiments, the length L2 of theextension portion 2242 may range from about 30% to about 70% with respect to the length L4 of thesemiconductor layer 227. - An asymmetric structure can be obtained by the extension of first conductive structure 224 (i.e. the source line). In some embodiments, a contact area between the first
conductive structure 224 and thesemiconductor layer 227 is similar to a contact area between the second conductive structure and thesemiconductor layer 227; therefore the asymmetric firstconductive structure 224 renders less impact to electrical resistances of the source line and the bit line and the read speed. Further, theextension portion 2242 helps to enhance electric field, and thus, switching speed can be accelerated. - The
channel isolation structure 226 may be disposed between the semiconductor layers 227 and electrically isolates the firstconductive structure 224 and the secondconductive structure 225. From the top view as shown inFIG. 4 , thechannel isolation structure 226 has a length L3. In some embodiments, L3 may be longer than, equal to or less than the length L2 of theextension portion 2242. In some embodiments, L3 is equal to or less than the length L2 of theextension portion 2242. In some embodiments, L3 is longer than, equal to or less than the length L1 of thecontact portion 2241. In some embodiments, L3 may range from about 1 nm to about 100 nm. In some embodiments, L3 may range from about 3 nm to about 75 nm. In some embodiments, L3 may range from about 5 nm to about 50 nm. - In some embodiments, the semiconductor layers 227 may include a semiconductor material. In some embodiments, the semiconductor layers 227 may include various materials, such as an amorphous silicon (a-Si) material, a polycrystalline silicon (poly-Si) material, an oxide semiconductor material (e.g., indium zinc oxide (IZO), indium-gallium-zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), zinc oxide (ZnO), stannous oxide (SnO), and copper oxide (CuO)), or the like, but the disclosure is not limited to the above-mentioned materials. In some embodiments, the semiconductor layers 227 may serve as channel. From the cross-sectional side view as shown in
FIG. 2 , thesemiconductor layer 227 has an L-shaped vertical cross section and comprises a longitudinal portion and a horizontal bottom. In some embodiments, thedielectric layers 2243 may be formed along the longitudinal portion of the semiconductor layers 227 and formed on the horizontal bottom, so thedielectric layer 2243 may be substantially aligned with the end of the horizontal bottom of the semiconductor layers 227 as shown inFIG. 2 . - The
cell isolation structures 222 separate thecentral portions 221 from each other when there are two or morecentral portions 221 in onecell region 220. In some embodiments, thecell isolation structures 222 are arranged in an array configuration or a staggered array configuration. In some embodiments, thecell isolation structures 222 penetrate through thecell array region 200 and contact thesubstrate 101. In some embodiments, thecell isolation structures 222 may include dielectric materials, including oxides, nitrides and the like, such as silicon oxide, silicon nitride, SiCN, Al2O3, HfO2, SiON, and La2O3, but the disclosure is not limited to the above-mentioned materials. - The
ferroelectric layer 223 can be formed besides the stackingportion 210 and thus can be sandwiched by the stackingportion 210 and thecentral portion 221 and also sandwiched by the stackingportion 210 and thecell isolation structures 222. In some embodiments, theferroelectric layer 223 penetrates through thecell array region 200 along the first direction D1 and is in contact with thesubstrate 101. As mentioned above, the firstconductive layers 212 may correspond to word lines. In some embodiments, theferroelectric layers 223 are disposed between the first conductive layer 212 (i.e. word line) and the first conductive structure 224 (i.e. source line) or between the first conductive layer 212 (i.e. word line) and the second conductive structure 225 (i.e. bit line). In some embodiments, the first conductive layers 212 (i.e. word lines) can control the adjacent unit cell A in the same level as shown inFIGS. 3 and 4 . From the cross-sectional side view as shown inFIG. 2 , theferroelectric layer 223 has an L-shaped vertical cross section; correspondingly, thesemiconductor layer 227 formed along theferroelectric layer 223 also has an L-shaped vertical cross section. In some embodiments, theferroelectric layer 223 comprises a longitudinal portion and a horizontal bottom to form the L-shaped vertical cross section. In some embodiments, the longitudinal portion of the semiconductor layers 227 may be formed along the longitudinal portion of theferroelectric layer 223 and the horizontal portion of the semiconductor layers 227 may be formed on the horizontal portion of theferroelectric layer 223, so an end of the horizontal portion of the semiconductor layers 227 may be substantially aligned with the end of the horizontal portion of theferroelectric layer 223 as shown inFIG. 2 . The firstconductive structure 224 and the secondconductive structure 225 can contact thesubstrate 101 through a gap between the horizontal portions of twoferroelectric layers 223 beside the first and secondconductive structures -
FIG. 5 is a flowchart representing amethod 400 for forming a semiconductor memory structure according to various aspects of the present disclosure. In some embodiments, thesemiconductor memory structure 100 can be formed by themethod 400, but the disclosure is not limited thereto. Themethod 400 includes a number of operations (401, 402, 403, 404, 405, 406 and 407) and the description and illustration are not deemed as a limitation as the sequence of the operations and the structure of the semiconductor memory structure. InFIGS. 6 to 24 , the reference numerals will be given like those, which have already been described above so as to omit the repetition of similar descriptions. In addition, portions about which no particular description will be made have the similar constructions to those of thesemiconductor memory structure 100 described above and provide the same advantages provided thereby. It should be noted that the operations of themethod 400 may be rearranged or otherwise modified within the scope of the various aspects. It should further be noted that additional processes may be provided before, during, and after themethod 400, and that some other processes may be only briefly described herein. - With reference to
FIG. 5 ,method 400 of forming a stack of alternating insulating layers and sacrificial layers over asubstrate 401; forming trenches in thestack 402; replacing the sacrificial layers with firstconductive layers 403; filling each trench with a multi-layered structure including a ferroelectric layer, a semiconductor layer, and adielectric layer 404; removing portions of the multi-layered structure to leave remaining portions including thedielectric layer 405; forming cell isolation structures between the ferroelectric layers and forming channel isolation structures between the semiconductor layers 406; and forming first conductive structures and secondconductive structures 407. -
Method 400 begins atoperation 401 by forming astack 210 a of alternating insulatinglayers 211 and firstsacrificial layers 214 over asubstrate 101, as shown inFIG. 6 . In some embodiments, thesubstrate 101 is provided as having already undergone several processing steps. In some embodiments, thesubstrate 101 may be any suitable substrate such as a silicon, germanium, silicon-germanium, undoped, doped, bulk, silicon-on-insulator (“SOI”) or other substrate with or without additional circuitry. In some embodiments, thestack 210 a includes a plurality of insulatinglayers 211 and a plurality of firstsacrificial layers 214, which are parallel to each other and sequentially stacked along a first direction D1. In some embodiments, the uppermost layer of thestack 210 a is the insulatinglayer 211. In some embodiments, the number of the alternating layers included in thestack 210 a can be made as high as the number of layers needed. In some embodiments, thestack 210 a may include between 16 and 512 layers of alternating insulatinglayers 211 and firstsacrificial layers 214, whereby each insulating or sacrificial layer constitutes one layer. In some embodiments, the insulatinglayers 211 include an insulating material, such as oxides (e.g., silicon oxide (SiO2)). In some embodiments, the firstsacrificial layers 214 may include nitrides (e.g., silicon nitride (SiN)) or amorphous silicon. Other insulating materials may be used instead of silicon oxide. Other sacrificial materials may be used instead of silicon nitride. In some embodiments, each of the insulatinglayers 211 and the firstsacrificial layers 214 may have substantially identical thickness. In some embodiments, the insulatinglayers 211 and the firstsacrificial layers 214 for forming the alternatingstack 210 a may be deposited using any suitable technique, such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and sputtering. In some embodiments, the insulatinglayers 211 and the firstsacrificial layers 214 may be deposited by PECVD. - Referring to
FIG. 7 , portions of the insulatinglayers 211 and portions of the firstsacrificial layers 214 are removed, such that remaining insulatinglayers 211 and remaining firstsacrificial layers 214 form a staircase structure over thesubstrate 101. In some embodiments, portions of the firstsacrificial layers 214 are exposed, and areas of the exposed portions of the firstsacrificial layers 214 can be similar. In some embodiments, the remaining portion of the topmost insulatinglayer 211 can be used to define a location and a dimension of acell array region 200. - Referring to
FIG. 8 , in some embodiments, adielectric structure 310 can be formed over thestack 210 a. Further, a top surface of thedielectric structure 310 can be aligned with a top surface of the topmost insulatinglayer 211. Consequently, an even and flush surface can be obtained and thecell array region 200 is disposed between twoconnection regions 300. - At
operation 402 with reference toFIG. 9 , in some embodiments, a plurality offirst trenches 510 are formed in thecell array region 200 and theconnection regions 300. In some embodiments, each of thetrenches 510 extends along a second direction D2 and thefirst trenches 510 are arranged along a third direction D3, which is different from the first and second directions D1 and D2. In some embodiments, the first direction D1 and the second direction D2 are perpendicular to each other. In some embodiments, the third direction D3 is perpendicular to the first direction D2 and is also perpendicular to the first direction D1. Further, widths and depths of thefirst trenches 510 are similar to each other. In some embodiments, thesubstrate 101 can be exposed through a bottom of eachtrench 510, but the disclosure is not limited thereto. In some embodiments, the insulatinglayers 211 and the firstsacrificial layers 214 can be exposed from the sidewalls of eachtrench 510. - At
operation 403, the firstsacrificial layers 214 can be replaced by metal to form first conductive layers 212 (i.e. word lines). As shown inFIGS. 10A and 10B , some portions of the firstsacrificial layers 214 may be removed from thefirst trenches 510 to formfirst recesses 511, so that the firstsacrificial layers 214 will be replaced with conductive materials to form word lines. In some embodiments, the first sacrificial layers 214 (e.g., silicon nitride) can be selectively etched relative to insulating layers 211 (e.g., silicon oxide) over thesubstrate 101 via thefirst trenches 510. In some embodiments, the removal of the firstsacrificial layers 214 may involve introducing an etchant via thefirst trenches 510. In some embodiments, etching may be performed using a selective dry etch process, such as by exposing the substrate to any one or more of the following gases: chlorine (Cl2), oxygen (O2), nitrous oxide (N2O), or the like, but the disclosure is not limited thereto. It will be understood that the selective etching involves etching a firstsacrificial layers 214 at a rate faster than etching materials for insulatinglayers 211. Any suitable etching process and etchant may be used. - With further reference to
FIGS. 11A and 11B , firstconductive layers 212 can be formed in thefirst recesses 511 via thefirst trenches 510 to form word lines. After replacing the firstsacrificial layers 214 with the firstconductive material 212, a metal/oxide stack is formed, in which the insulating layers 211 (e.g., silicon oxide (SiO2)) can separate the metal word lines. In some embodiments, the firstconductive layers 212 include various conductive materials, e.g., metal such as aluminum (Al), titanium (Ti), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), rhodium (Ru), tungsten (W), platinum (Pt) and/or alloys thereof, or a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or the like, but the disclosure is not limited thereto. In some embodiments, chemical vapor deposition (CVD) or atomic layer deposition (ALD) may be used to deposit the firstconductive layers 212. In some embodiments, the excessive conductive material, e.g., the materials outside the recesses, at the bottom of thefirst trenches 510, and on the surface of the uppermost insulatinglayers 211, can be removed, e.g., by etching, so that the bottom surfaces of thefirst trenches 510, the sidewalls of the insulatinglayers 211, and the surface of the uppermost insulatinglayers 211 can be exposed. - In some embodiments, before forming the first
conductive layers 212 in thefirst recesses 511, glue layers 213 may be formed along the sidewall of thefirst recesses 511, so that the shape of glue layers 213 corresponds to the sidewall of the first recesses 511. For example, eachglue layer 213 may have a U shape, V shape, W shape and so on, depending on the shape of the sidewalls of therecesses 511, but the disclosure is not limited thereto. The glue layers 213 may be formed by using ALD, CVD, physical vapor deposition (PVD) or other methods. Eachglue layer 213 partially surrounds the corresponding firstconductive layer 212, so that the firstconductive layer 212 can be exposed from thefirst trench 510 but not contact the adjacent insulatinglayers 211 and/ordielectric structure 310. Theglue layer 213 can improve adhesion of the firstconductive layer 212 with adjacent insulatinglayers 211 and/ordielectric structure 310. -
Operation 404 includes filling each of thefirst trenches 510 with a multi-layered structure. The multi-layered structure can be formed by any suitable methods that are known in the art. In some embodiments, referring toFIGS. 12A and 12B , thefirst trenches 510 may be filled in by sequentially depositing aferroelectric layer 223, asemiconductor layer 227 and adielectric layer 2243 along the sidewalls and bottoms of thefirst trenches 510, e.g., using ALD. In some embodiments, other suitable layers, such as an interfacial layer, e.g., SiO2, SiON, or Al2O3, can be formed in combination with theferroelectric layer 223. - In some embodiments, with reference to
FIGS. 13A and 13B , portions of theferroelectric layer 223 and portions of thesemiconductor layer 227 may be removed from the bottom of thefirst trenches 510, so as to expose thesubstrate 101 from thefirst trenches 510. Hence, from the cross-sectional side view, theferroelectric layer 223 has an L-shaped vertical cross section; correspondingly, thesemiconductor layer 227 forming along theferroelectric layer 223 also has an L-shaped vertical cross section as shown inFIG. 13B . - Referring to
FIGS. 14A and 14B , thefirst trenches 510 can be filled with a firstsacrificial material 610. In some embodiments, after filling thefirst trenches 510 with these layers, a chemical mechanical polishing (CMP) may be carried out to planarize the surface of the structure. The firstsacrificial material 610 may include nitrides (e.g., silicon nitride (SiN)) or amorphous silicon, but the disclosure is not limited thereto. -
Operations 402 to 404 may be performed twice or more times.FIG. 15 shows thatsecond trenches 520 can be formed in thecell array region 200 and theconnection regions 300 to expose the firstsacrificial layers 214 from thesecond trenches 520. Eachsecond trench 520 can be formed at a location between two multi-layered structure filled in thefirst trenches 510.FIG. 16 shows that the firstsacrificial layers 214 can be replaced by metal to form first conductive layers 212 (i.e. word lines); and, in some embodiments, glue layers 213 may be formed to adhere the firstconductive layers 212 to adjacent insulatinglayers 211 and/oradjacent glue layers 213 previously formed through thefirst trenches 510.FIG. 17 shows that each of thesecond trenches 520 are filled with a multi-layered structure, including aferroelectric layer 223, asemiconductor layer 227, adielectric layer 2243 and a secondsacrificial material 620, identical or similar to the multi-layered structure formed in thefirst trenches 510; therefore, repeated descriptions of such details are omitted for brevity. The secondsacrificial material 620 may include nitrides (e.g., silicon nitride (SiN)) or amorphous silicon, but the disclosure is not limited thereto. In some embodiments, widths of the multi-layered structure in thefirst trenches 510 and widths of the multi-layered structure in thesecond trenches 520 are similar. As shown inFIG. 17 , the multi-layered structures in thefirst trenches 510 and the multi-layered structures in thesecond trenches 520 are alternately arranged along the third direction D3. Further, distances between the adjacent multi-layered structures in thefirst trench 510 and thesecond trench 520 are similar. - At
operation 405, with reference toFIG. 18 , in some embodiments, portions of the firstsacrificial material 610, portions of the secondsacrificial material 620, and portions of thedielectric layer 2243 can be removed to form a plurality ofthird trenches 530. In some embodiments, thethird trenches 530 are separated from each other by remainingportions 700, which is used to define the location ofextension portions 2242 of firstconductive structures 224 to be formed and is described below. Thethird trenches 530 and the remainingportions 700 are arranged alternately. Thethird trenches 530 are formed to expose a portion of thesubstrate 101. Each remainingportion 700 can be disposed between twosemiconductor layers 227 and includes twodielectric layer 2243 formed separately along two semiconductor layers 227. In other words, thedielectric layer 2243 is sectioned by thethird trenches 530. Further, the first and secondsacrificial materials dielectric layers 2243. Hence, each remainingportion 700 has two opposite sides exposed from thethird trenches 530. - At
operation 406, with reference toFIG. 19 , thethird trenches 530 may be filled with a thirdsacrificial materials 630. The thirdsacrificial materials 630 may be identical to or different from the first and secondsacrificial materials FIG. 20 , a plurality ofchannel isolation trenches 550 can be formed next to one side of the remainingportions 700 by removing some portions of the thirdsacrificial materials 630. Thechannel isolation trenches 550 can extend downwardly from the top surface of thecell array region 200 to expose thesubstrate 101, so one side of each remainingportion 700 and twosemiconductor layers 227 can be exposed from thechannel isolation trenches 550. Referring toFIG. 21 , thechannel isolation trenches 550 can be filled with isolation material, such as an isolation oxide (e.g., SiO2) or other suitable materials, to formchannel isolation structure 226. - Referring to
FIG. 22 ,cell isolation trenches 560 can be formed in the thirdsacrificial materials 630 by removing some portions of the thirdsacrificial materials 630 as well as the semiconductor layers 227, so that the thirdsacrificial materials 630 can be divided into two parts. One part of the thirdsacrificial materials 630 next to the remainingportion 700 defines the location of acontact portion 2241 of the firstconductive structure 224 to be formed, and the other part of the thirdsacrificial materials 630 next to thechannel isolation structure 226 defines the location of a secondconductive structure 225 to be formed. Thecell isolation trenches 560 can extend downwardly from the top surface of thecell array region 200 to expose thesubstrate 101, so that one side of each part of the thirdsacrificial materials 630 and twoferroelectric layers 223 can be exposed from eachcell isolation trench 560. Referring toFIG. 23 , thecell isolation trenches 560 can be filled with isolation material, such as an isolation oxide (e.g., SiO2) or other suitable materials, to formcell isolation structure 222. - At
operation 407, with reference toFIG. 24 , the first and secondsacrificial materials portion 700 and the thirdsacrificial materials 630 can be replaced with conductive materials to form firstconductive structures 224 and secondconductive structures 225. The first and secondsacrificial materials portions 700 can be replaced with conductive materials to form anextension portion 2242 of the firstconductive structures 224. One part of the thirdsacrificial materials 630 next to the remainingportion 700 can be replaced with conductive materials to form acontact portion 2241 of the firstconductive structures 224. Hence, thecontact portion 2241 of the firstconductive structure 224 is disposed between twosemiconductor layers 227 and the extension portion of the firstconductive structures 224 is disposed between twodielectric layers 2243, so that the firstconductive structures 224 partially contact thesemiconductor layer 227 and partially contact thedielectric layer 2243. From the top view, thecontact portion 2241 and theextension portion 2242 may present a T-shape. The other part of the thirdsacrificial materials 630 next to thechannel isolation structure 226 can be replaced with conductive materials to form the secondconductive structure 225. Materials fordielectric layers 2243 may have different etching selectivity to thesacrificial materials sacrificial materials dielectric layers 2243 can be less impacted or consumed. - In some embodiments, a method of manufacturing a semiconductor memory structure comprises: forming a stack of alternating insulating layers and sacrificial layers over a substrate; forming a plurality of trenches in the stack; replacing the sacrificial layers with first conductive layers; filling each of the plurality of trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, and a dielectric layer; removing portions of the multi-layered structure to leave remaining portions, so that the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers; forming cell isolation structures between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and forming channel isolation structures between the semiconductor layers of each two adjacent multi-layered structures of the multi-layered structures; and forming first conductive structures and second conductive structures, wherein each of the first conductive structures is disposed between one of the cell isolation structures and an adjacent channel isolation structure of the channel isolation structures, and each of the second conductive structures is disposed between one of the cell isolation structures and the other adjacent channel isolation structure of the channel isolation structures, wherein the first conductive structures partially contact the semiconductor layers and partially contact the dielectric layers.
- In some embodiments, a method of manufacturing a semiconductor memory structure comprises: forming a stack of alternating insulating layers and sacrificial layers over a substrate; forming a plurality of first trenches in the stack; replacing the sacrificial layers with conductive layers; sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of first trenches; removing portions of the dielectric layer, portions of the semiconductor layer and portions of the ferroelectric layer to expose the substrate from the plurality of first trenches; filling the plurality of first trenches with a first sacrificial material; forming a plurality of second trenches in the stack, wherein the plurality of second trenches and the plurality of first trench are arranged alternately; sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of second trenches; removing portions of the dielectric layer, portions of the semiconductor layer and portions of the ferroelectric layer to expose the substrate from the second trench; filling each of the plurality of second trench with a second sacrificial material; removing portions of the first sacrificial material, portions of the second sacrificial material, and portions of the dielectric layer to form a plurality of third trenches and a plurality of remaining portions, wherein the plurality of third trenches and the plurality of remaining portions are arranged alternately, and wherein the each of the plurality of remaining portion is disposed between two semiconductor layers and comprises the dielectric layers formed separately along the two semiconductor layers; filling the plurality of third trenches with a third sacrificial material; removing portions of the third sacrificial material to form a plurality of channel isolation trenches so that one side of each of the plurality of remaining portions and the two semiconductor layers are exposed from the plurality of channel isolation trenches; filling the plurality of channel isolation trenches with isolation materials to form channel isolation structures; removing portions of the third sacrificial materials and the semiconductor layers to form cell isolation trenches so that the third sacrificial materials is divided into two parts, wherein one part of the third sacrificial materials next to the remaining portion is replaced with conductive materials to form a contact portion, and the other part of the third sacrificial materials next to the channel isolation structure is replaced with conductive materials to form a conductive structure; filling the cell isolation trenches with isolation materials to form cell isolation structure; and replacing the first and second sacrificial materials in the remaining portions with conductive materials to form an extension portion.
- In some embodiments, a method of manufacturing a semiconductor memory structure comprises: forming a stack of alternating insulating layers and conductive layers over a substrate, wherein the stack has a plurality of first trenches; filling each of the plurality of first trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, a dielectric layer, and first sacrificial materials; removing portions of the multi-layered structure to form a plurality of second trenches and a plurality of remaining portions, wherein the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers; filling the plurality of second trenches with second sacrificial materials; forming cell isolation structures and channel isolation structures by removing portions of the second sacrificial materials, wherein the cell isolation structures are positioned between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and the channel isolation structures are positioned between the semiconductor layers of each two adjacent multi-layered structures of the multi-layered structures; forming first conductive structures and second conductive structures by replacing the second sacrificial materials in the remaining portions and in the plurality of second trenches with conductive materials, wherein each of the first conductive structures is disposed between one of the cell isolation structures and an adjacent channel isolation structure of the channel isolation structures, and each of the second conductive structures is disposed between one of the cell isolation structures and the other adjacent channel isolation structure of the channel isolation structures.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. A method of manufacturing a semiconductor memory structure, the method comprising:
forming a stack of alternating insulating layers and sacrificial layers over a substrate;
forming a plurality of trenches in the stack;
replacing the sacrificial layers with first conductive layers;
filling each of the plurality of trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, and a dielectric layer;
removing portions of the multi-layered structure to leave remaining portions, so that the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers;
forming cell isolation structures between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and forming channel isolation structures between the semiconductor layers of each two adjacent multi-layered structures of the multi-layered structures; and
forming first conductive structures and second conductive structures, wherein each of the first conductive structures is disposed between one of the cell isolation structures and an adjacent channel isolation structure of the channel isolation structures, and each of the second conductive structures is disposed between one of the cell isolation structures and the other adjacent channel isolation structure of the channel isolation structures,
wherein the first conductive structures partially contact the semiconductor layers and partially contact the dielectric layers.
2. The method of claim 1 , wherein replacing the sacrificial layers with first conductive layers comprises:
replacing materials disposed between the dielectric layers in the remaining portions with conductive materials to form extension portions of the first conductive structures; and
replacing materials disposed between the remaining portions and the cell isolation structures with the conductive materials to form contact portions, wherein the extension portion extends from one of the contact portion to one of the channel isolation structures and is separated from the semiconductor layers through the dielectric layers.
3. The method of claim 1 , wherein each of the contact portions of the first conductive structures has a contact area contacting the semiconductor layers, each of the second conductive structures has a contact area contacting the semiconductor layers, and the contact area of the contact portion of the first conductive structure and the contact area of the second conductive structure are similar.
4. The method of claim 1 , wherein after the remaining portions are formed, portions of the ferroelectric layer and portions of the semiconductor layer are removed from bottoms of the plurality of trenches to expose the substrate from the plurality of trenches.
5. The method of claim 4 , wherein both of ferroelectric layer and semiconductor layer have an L-shaped vertical cross section formed along sidewalls of the plurality of trenches and partially covering the bottoms of the plurality of trenches whereby the substrate exposes from the plurality of trenches.
6. The method of claim 1 , wherein replacing the sacrificial layers with first conductive layers through the plurality of trenches further comprises:
forming a plurality first recesses by partially removing the sacrificial layers; and
forming glue layers along sidewalls of the plurality first recesses before forming the first conductive layers.
7. The method of claim 6 , wherein the glue layers comprise oxides.
8. A method of manufacturing a semiconductor memory structure, the method comprising:
forming a stack of alternating insulating layers and sacrificial layers over a substrate;
forming a plurality of first trenches in the stack;
replacing the sacrificial layers with conductive layers;
sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of first trenches;
removing portions of the dielectric layer, portions of the semiconductor layer and portions of the ferroelectric layer to expose the substrate from the plurality of first trenches;
filling the plurality of first trenches with a first sacrificial material;
forming a plurality of second trenches in the stack, wherein the plurality of second trenches and the plurality of first trench are arranged alternately;
sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of second trenches;
removing portions of the dielectric layer, portions of the semiconductor layer and portions of the ferroelectric layer to expose the substrate from the second trench; filling each of the plurality of second trench with a second sacrificial material; removing portions of the first sacrificial material, portions of the second sacrificial material, and portions of the dielectric layer to form a plurality of third trenches and a plurality of remaining portions, wherein the plurality of third trenches and the plurality of remaining portions are arranged alternately, and wherein the each of the plurality of remaining portion is disposed between two semiconductor layers and comprises the dielectric layers formed separately along the two semiconductor layers;
filling the plurality of third trenches with a third sacrificial material;
removing portions of the third sacrificial material to form a plurality of channel isolation trenches so that one side of each of the plurality of remaining portions and the two semiconductor layers are exposed from the plurality of channel isolation trenches;
filling the plurality of channel isolation trenches with isolation materials to form channel isolation structures;
removing portions of the third sacrificial materials and the semiconductor layers to form cell isolation trenches so that the third sacrificial materials is divided into two parts, wherein one part of the third sacrificial materials next to the remaining portion is replaced with conductive materials to form a contact portion, and the other part of the third sacrificial materials next to the channel isolation structure is replaced with conductive materials to form a conductive structure;
filling the cell isolation trenches with isolation materials to form cell isolation structure; and
replacing the first and second sacrificial materials in the remaining portions with conductive materials to form an extension portion.
9. The method of claim 8 , wherein the extension portion extends from the contact portion to the channel isolation structure and is separated from the two semiconductor layers through the dielectric layers.
10. The method of claim 9 , wherein the channel isolation structure has a length equal to or less than a length of the extension portion.
11. The method of claim 9 , wherein the contact portion has a contact area contacting the two semiconductor layers, the second conductive structure has a contact area contacting the two semiconductor layers, and the contact area of the contact portion and the contact area of the conductive structure are similar.
12. The method of claim 9 , wherein the extension portion has a length from the contact portion to the channel isolation structure, which is 10% to 90% of a length of each of the two semiconductor layers.
13. The method of claim 9 , wherein the contact portion and the extension portion present a T-shape top view.
14. The method of claim 8 , wherein each of the ferroelectric layers has an L-shaped vertical cross section.
15. The method of claim 8 , wherein each of the two semiconductor layers has an L-shaped vertical cross section.
16. A method of manufacturing a semiconductor memory structure, the method comprising:
forming a stack of alternating insulating layers and conductive layers over a substrate, wherein the stack has a plurality of first trenches;
filling each of the plurality of first trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, a dielectric layer, and first sacrificial materials;
removing portions of the multi-layered structure to form a plurality of second trenches and a plurality of remaining portions, wherein the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers;
filling the plurality of second trenches with second sacrificial materials;
forming cell isolation structures and channel isolation structures by removing portions of the second sacrificial materials, wherein the cell isolation structures are positioned between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and the channel isolation structures are positioned between the semiconductor layers of each two adjacent multi-layered structures of the multi-layered structures;
forming first conductive structures and second conductive structures by replacing the second sacrificial materials in the remaining portions and in the plurality of second trenches with conductive materials, wherein each of the first conductive structures is disposed between one of the cell isolation structures and an adjacent channel isolation structure of the channel isolation structures, and each of the second conductive structures is disposed between one of the cell isolation structures and the other adjacent channel isolation structure of the channel isolation structures.
17. The method of claim 16 , wherein forming the first conductive structures comprises:
replacing the second sacrificial materials disposed between the dielectric layers in the remaining portions with conductive materials to form extension portions of the first conductive structures; and
replacing the second sacrificial materials disposed between the remaining portions and the cell isolation structures with the conductive materials to form contact portions, wherein the extension portion extends from one of the contact portion to one of the channel isolation structures and is separated from the semiconductor layers through the dielectric layers.
18. The method of claim 17 , wherein the channel isolation structure has a length equal to or less than a length of the extension portion; and the extension portion has a length from the contact portion to the channel isolation structure, which is 10% to 90% of a length of each of the two semiconductor layers.
19. The method of claim 16 , wherein each of the conductive layer comprises two sublayers and a glue layer; and the glue layer is disposed between the conductive layer and an adjacent insulating layer of the insulating layers.
20. The method of claim 19 , wherein the glue layer comprises oxides.
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