US20230178427A1 - Semiconductor interconnection structures and methods of forming the same - Google Patents
Semiconductor interconnection structures and methods of forming the same Download PDFInfo
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- US20230178427A1 US20230178427A1 US18/106,623 US202318106623A US2023178427A1 US 20230178427 A1 US20230178427 A1 US 20230178427A1 US 202318106623 A US202318106623 A US 202318106623A US 2023178427 A1 US2023178427 A1 US 2023178427A1
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Abstract
An interconnection structure is provided. The interconnection structure includes an etching-process-free first dielectric layer, a first conductive structure extending within the first dielectric layer, a second dielectric layer formed under the first dielectric layer, and a second conductive structure extending through both the first dielectric layer and the second conductive layer.
Description
- This application is a continuation-in-part of U.S. patent application Ser. No. 17/698,743 entitled “Semiconductor Interconnection Structures and Methods of Forming the Same,” filed Mar. 18, 2022, which claims priority to US Provisional Application Ser. No. 63/212,002 filed Jun. 17, 2021, which are incorporated by reference in their entirety.
- As the semiconductor industry introduces new generations of integrated circuits (IC) having higher performance and more functionality, the density of the elements forming the ICs increases, while the dimensions, sizes and spacing between components or elements are reduced. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area.
- For manufacturing different conductive layers on the substrate, various structures and manufacturing methods are utilized to form the interconnection structures between the conductive layers. However, the integrated fabrication also brings out some issues, such as reliability, high capacitance, or high resistance. Therefore, there is a need in the art to provide improved devices or methods that can address the issues mentioned above.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 is a perspective view of one of the various stages of manufacturing a semiconductor device structure, in accordance with some embodiments. -
FIGS. 2A-2B are cross-sectional side views of one of various stages of manufacturing a semiconductor device structure, in accordance with some embodiments. -
FIGS. 3A-3L are cross-sectional side views of various stages of manufacturing a semiconductor structure, in accordance with some embodiments. -
FIGS. 4A-4H are cross-sectional side views of various stages of manufacturing another semiconductor structure, in accordance with some embodiments. -
FIG. 5 is a flow chart of a method for manufacturing a semiconductor interconnection structure in accordance with some embodiments. -
FIG. 6 is a flow chart of another method for manufacturing a semiconductor interconnection structure in accordance with some embodiments. -
FIGS. 7A-7K are cross-sectional side views of various stages of manufacturing a semiconductor structure, in accordance with some embodiments. -
FIG. 8 is a flow chart of a method for manufacturing a semiconductor interconnection structure in accordance with some embodiments. -
FIGS. 9A to 9D are cross-sectional side views of various stages of manufacturing a semiconductor structure, in accordance with some embodiments. -
FIGS. 10A-10C are cross-sectional views of various stages of manufacturing a semiconductor structure in according to some embodiments. -
FIGS. 11A to 11E are cross-sectional views of various stages of manufacturing a semiconductor structure in according to some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
-
FIG. 1 is a perspective view of one of the various stages of manufacturing asemiconductor device structure 100, in accordance with some embodiments. As shown inFIG. 1 , thesemiconductor device structure 100 includes asubstrate 101 having at least a plurality of devices formed thereover. The devices, such as transistors, diodes, imaging sensors, resistors, capacitors, inductors, memory cells, a combination thereof, and/or other suitable devices, may be formed on thesubstrate 101. In some embodiments, the interconnection structures may be formed on or below the devices. -
FIGS. 2A-2B are cross-sectional side views of various stages of manufacturing thesemiconductor device structure 100, in accordance with some embodiments.FIG. 2A is a cross-sectional side view of thesemiconductor device structure 100 taken along line A-A ofFIG. 1 , andFIG. 2B is a cross-sectional side view of thesemiconductor device structure 100 taken along line B-B ofFIG. 1 . The line A-A ofFIG. 1 extends along a direction that is substantially perpendicular to the longitudinal direction of agate stack 106, and the line B-B ofFIG. 1 extends along the longitudinal direction of thegate stack 106. As shown inFIGS. 2A and 2B , thesemiconductor device structure 100 includes thesubstrate 101, and one ormore devices 102 are formed on thesubstrate 101. The interconnection structures may be formed over thedevices 102. - The
substrate 101 may be a semiconductor substrate. In some embodiments, thesubstrate 101 includes a crystalline semiconductor layer on at least the surface of thesubstrate 101. Thesubstrate 101 may include a crystalline semiconductor material such as, but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), and indium phosphide (InP). In some embodiment, thesubstrate 101 is made of Si. In some embodiments, thesubstrate 101 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxygen-containing material, such as an oxide. - The
substrate 101 may include various regions that have been suitably doped with impurities (e.g., p-type or n-type impurities). The dopants are, for example phosphorus for an n-type fin field effect transistor (FinFET) and boron for a p-type FinFET. - As described above, the
devices 102 may be any suitable devices, such as transistors, diodes, imaging sensors, resistors, capacitors, inductors, memory cells, or a combination thereof. In some embodiments, thedevices 102 are transistors, such as planar field effect transistors (FETs), FinFETs, nanostructure transistors, or other suitable transistors. The nanostructure transistors may include nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistors having the gate electrode surrounding the channels. An example of thedevice 102 formed between thesubstrate 101 and the interconnection structures (such as the interconnection structure 200 shown inFIGS. 3A-3L or 4A-4D ) may be a FinFET or a nanostructure, which is shown inFIGS. 2A and 2B . Anexemplary device 102 may include source/drain (S/D)regions 104 and agate stack 106 disposed between the S/D regions 104 serving as source regions and the S/D regions 104 serving as drain regions. S/D region(s) may refer to a source or a drain, individually or collectively dependent upon the context. While there is only onegate stack 106 formed on thesubstrate 101, it is contemplated that two or more gate stacks 106 may also be formed on thesubstrate 101.Channel regions 108 are formed between the S/D regions 104 serving as source regions and the S/D regions 104 serving as drain regions. - The S/
D regions 104 may include a semiconductor material, such as Si or Ge, a III-V compound semiconductor, an II-VI compound semiconductor, or other suitable semiconductor material. Exemplary S/D region 104 may include, but are not limited to, Ge, SiGe, GaAs, AlGaAs, GaAsP, SiP, InAs, AlAs, InP, GaN, InGaAs, InAlAs, GaSb, AlP, GaP, and the like. The S/D regions 104 may include p-type dopants, such as boron; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. The S/D regions 104 may be formed by an epitaxial growth method using CVD, atomic layer deposition (ALD) or molecular beam epitaxy (MBE). Thechannel regions 108 may include one or more semiconductor materials, such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, or InP. In some embodiments, thechannel regions 108 include the same semiconductor material as thesubstrate 101. In some embodiments, thedevices 102 are FinFETs, and thechannel regions 108 are a plurality of fins each having at least three surfaces wrapped around by thegate stack 106. In some other embodiments, thedevices 102 are nanosheet transistors, and thechannel regions 108 include two or more nanosheets surrounded by thegate stack 106. - Each
gate stack 106 includes agate electrode layer 110 disposed over thechannel region 108 or partially/fully surrounding thechannel region 108. Thegate electrode layer 110 may be a metal-containing material such as tungsten, cobalt, aluminum, ruthenium, copper, multilayers thereof, or the like, and can be deposited by ALD, plasma enhanced chemical vapor deposition (PECVD), MBD, physical vapor deposition (PVD), or any suitable deposition technique. Eachgate stack 106 may include aninterfacial dielectric layer 112, agate dielectric layer 114 disposed on theinterfacial dielectric layer 112, and one or moreconformal layers 116 disposed on thegate dielectric layer 114. Thegate electrode layer 110 may be disposed on theconformal layers 116. Theinterfacial dielectric layer 112 may include a dielectric material, such as an oxygen-containing material or a nitrogen-containing material, or multilayers thereof, and may be formed by any suitable deposition method, such as CVD, PECVD, or ALD. Thegate dielectric layer 114 may include a dielectric material such as an oxygen-containing material or a nitrogen-containing material, a high-k dielectric material having a k value greater than that of silicon dioxide, or multilayers thereof. Thegate dielectric layer 114 may be formed by any suitable method, such as CVD, PECVD, or ALD. Theconformal layers 116 may include one or more barrier layers and/or capping layers, such as a nitrogen-containing material, for example tantalum nitride (TaN), titanium nitride (TiN), or the like. Theconformal layers 116 may further include one or more work-function layers, such as aluminum titanium carbide, aluminum titanium oxide, aluminum titanium nitride, or the like. The term “conformal” may be used herein for ease of description upon a layer having substantial same thickness over various regions. Theconformal layers 116 may be deposited by ALD, PECVD, MBD, or any suitable deposition technique. - One or
more gate spacers 118 are formed along sidewalls of the gate stack 106 (e.g., sidewalls of the gate dielectric layers 114). The gate spacers 118 may include silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbon nitride, the like, multi-layers thereof, or a combination thereof, and may be deposited by CVD, PVD, ALD, or other suitable deposition technique. - Portions of the gate stacks 106 and the
gate spacers 118 may be formed onisolation regions 103. Theisolation regions 103 are formed on thesubstrate 101. Theisolation regions 103 may include an insulating material such as an oxygen-containing material, a nitrogen-containing material, or a combination thereof. The insulating material may be formed by a high-density plasma chemical vapor deposition (HDP-CVD), a flowable chemical vapor deposition (FCVD), or other suitable deposition process. In one aspect, theisolation regions 103 includes silicon oxide that is formed by a FCVD process. - A contact etch stop layer (CESL) 124 is formed on a portion of the S/
D regions 104 and theisolation region 103, and a first interlayer dielectric (ILD) 126 is formed on theCESL 124. TheCESL 124 can provide a mechanism to stop an etch process when forming openings in thefirst ILD 126. TheCESL 124 may be conformally deposited on surfaces of the S/D regions 104 and theisolation regions 103. TheCESL 124 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof, and may be deposited by CVD, PECVD, PVD, ALD, or any suitable deposition technique. Thefirst ILD 126 may include an oxide formed by tetraethylorthosilicate (TEOS), un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), organosilicate glass (OSG), SiOC, and/or any suitable low-k dielectric materials (e.g., a material having a dielectric constant lower than silicon dioxide), and may be deposited by spin-on, CVD, FCVD, PECVD, PVD, or any suitable deposition technique. - A
silicide layer 120 is formed on at least a portion of each S/D region 104, as shown inFIGS. 2A and 2B . Thesilicide layer 120 may include a material having one or more of WSi, CoSi, NiSi, TiSi, MoSi and TaSi. In some embodiments, thesilicide layer 120 includes a metal or metal alloy silicide, and the metal includes a noble metal, a refractory metal, a rare earth metal, alloys thereof, or combinations thereof. Aconductive contact 122 is disposed on eachsilicide layer 120. Theconductive contact 122 may include a material having one or more of Ru, Mo, Co, Ni. W, Ti, Ta, Cu, Al, TiN or TaN, and theconductive contact 122 may be formed by any suitable method, such as electro-chemical plating (ECP), or PVD. Thesilicide layer 120 and theconductive contact 122 may be formed by first forming an opening in thefirst ILD 126 and theCESL 124 to expose at least a portion of the S/D region 104, then forming thesilicide layer 120 on the exposed portion of the S/D region 104, and then formingconductive contact 122 on thesilicide layer 120. -
FIGS. 3A-3L are cross-sectional side views of various stages of manufacturing asemiconductor structure 300, including aninterconnection structure 301, in accordance with some embodiments. In some embodiments, theinterconnection structure 301 may be formed on or below thesemiconductor device structure 100.FIG. 5 is a flow chart of amethod 500 for manufacturing theinterconnection structure 301 in accordance with some embodiments. For the purpose of better describing the present disclosure, the cross-sectional side view of thesemiconductor structure 300 inFIGS. 3A-3L and themethod 500 inFIG. 5 will be discussed together. It is understood that the operations shown in themethod 500 are not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIGS. 3A-3L andFIG. 5 . - As shown in
FIG. 3A , asemiconductor substrate 302 is provided. Thesemiconductor substrate 302 may be similar tosubstrate 101 discussed above. A plurality ofdevices 304 and a middle end of the line (MEOL)structure 306 may be formed on thesemiconductor substrate 302. In some embodiments, the plurality ofdevices 304 may be thedevices 102 shown inFIGS. 2A and 2B . - In the
MEOL structure 306, low level interconnects (contacts), such as theconductive contacts 122 shown inFIGS. 2A and 2B , are formed over the S/D regions 104 and thegate electrode layer 110. TheMEOL structure 306 may have smaller critical dimensions and may be spaced closer together compared to a later formed back end of the line (BEOL) counterparts. A purpose of the contact layers of theMEOL structure 306 is to electrically connect the various regions of the transistors, i.e., the source/drain and metal gate electrode, to higher level interconnects in the BEOL. - As shown in
FIG. 3A andoperation 502 inFIG. 5 , aconductive layer 308 is formed over theMEOL structure 306, an etch stop layer (ESL) 310 may be formed over theconductive layer 308, and adielectric layer 312 is formed over theESL 310. In some embodiments, theconductive layer 308 may be a conductive layer of other interconnection structures of thesemiconductor structure 300. In some embodiments, theconductive layer 308 may be a conductive layer above theMEOL structure 306. In some embodiments, theconductive layer 308 may include Cu, Al, CuAl, Ru, Mo, W, and related alloys formed in a dielectric material (not shown). In some embodiments, theconductive layer 308 may be formed by ALD, CVD, PVD, electroless deposition (ELD), ECP, or other suitable processes. - In some embodiments, the
ESL 310 may be used to control the etching depth in thedielectric layer 312 and serve as an etch stop when forming a later formed conductive feature in thedielectric layer 312. In some embodiments, theESL 310 may include SiNx, SiCxNy, AlNx, AlOx, AOxNy, SiOx, SiCx, SiOxCy, or other suitable materials. In some embodiments, theESL 310 may be formed by CVD, PVD, ALD, spin coating, or other suitable processes. In some embodiments, thedielectric layer 312 may include or be made of porous SiCOH, dense SiCOH, BN, BC, or other suitable materials. In some embodiments, thedielectric layer 312 may formed by PECVD, ALD, PVD, or other suitable processes. - As shown in
FIG. 3B andoperation 504 inFIG. 5 , afirst opening 314 and asecond opening 316 are formed in thedielectric layer 312. Thefirst opening 314 is formed in thedielectric layer 312, and thesecond opening 316 penetrates thedielectric layer 312 to expose a portion of theconductive layer 308. In some embodiments, thefirst opening 314 and thesecond opening 316 may be formed by dry etch, wet etch, or other suitable processes. In some embodiments, thefirst opening 314 may include a trench formed in thedielectric layer 312. In some embodiments, thesecond opening 316 may include a via and a trench formed sequentially in thedielectric layer 312 to expose a portion of theconductive layer 308. In some embodiments, the trench of thefirst opening 314 and the trench of thesecond opening 316 may be formed first, and then the via of thesecond opening 316 may be formed under the trench of thesecond opening 316 to expose a portion of theconductive layer 308. In some embodiments, the via of thesecond opening 316 may be formed first penetrating thedielectric layer 312 and theESL 310 to expose a portion of theconductive layer 308, and the trench of thefirst opening 314 and the trench of thesecond opening 316 may be formed thereafter. - As shown in
FIG. 3C andoperation 506 inFIG. 5 , aliner layer 318 is conformally formed over thedielectric layer 312. Theliner layer 318 may cover the top surface of thedielectric layer 312, thefirst opening 314, and thesecond opening 316 including the exposed surface of theconductive layer 308. In some embodiments, theliner layer 318 may include metal oxide, metal nitride, silicon oxide doped carbide (ODS), or other suitable materials. In some embodiments, theliner layer 318 may include AlOx, ZrOx, YOx, AlNx, TiNx, SiNx, SiCxNy, ODS, or other suitable materials. In some embodiments, theliner layer 318 may have a thickness between 5 Angstroms and 40 Angstroms. In some embodiments, theliner layer 318 may be formed by PECVD, ALD, PVD, or other suitable processes. Theliner layer 318 may prevent the damage on sidewalls of the later formed barrier layer or conductive materials during a later etch process. - As shown in
FIG. 3D andoperation 508 inFIG. 5 , a portion of theliner layer 318 that covers theconductive layer 308 is removed. In other words, theliner layer 318 at the bottom of theopening 316 is removed to expose theconductive layer 308. In some embodiments, the removal of the portion of theliner layer 318 may be performed by dry etch, or other suitable processes. - Then, as shown in
FIG. 3E andoperation 510 inFIG. 5 , abarrier layer 320 is deposited over theliner layer 318 and the exposedconductive layer 308. In some embodiments, thebarrier layer 320 may be conformally formed over theliner layer 318. In other words, thebarrier layer 320 may cover not only theliner layer 318 but also the exposedconductive layer 308 at the bottom of thesecond opening 316. In some embodiments, thebarrier layer 320 may include TaN, TiN, or other suitable materials. In some embodiments, thebarrier layer 320 may have a thickness between 10 Angstroms and 30 Angstroms. In some embodiments, thebarrier layer 320 may be formed by thermal ALD, or other suitable processes. - Then, as shown in
FIG. 3E andoperation 512 inFIG. 5 , a firstconductive feature 322 is formed in thefirst opening 314, and a secondconductive feature 326 is formed in thesecond opening 316. A conductive material may be deposited over thebarrier layer 320 and fills thefirst opening 314 and thesecond opening 316. Then, a planarization operation, e.g., chemical mechanical polishing (CMP), may be performed so that the firstconductive feature 322 and the secondconductive feature 326 are formed, as shown inFIG. 3E . - In some embodiments, the first
conductive feature 322 and the secondconductive feature 326 may include Cu, Al, CuAl, Ru, Mo, W, and related alloys. In some embodiments, the firstconductive feature 322 and the secondconductive feature 326 may be formed by ALD, CVD, PVD, ELD, ECP, or other suitable processes. Theliner layer 318 is disposed between the firstconductive feature 322 and thedielectric layer 312 and between the secondconductive feature 326 and the dielectric layer. - Then, as shown in
FIG. 3F , acapping layer 324 is formed on the firstconductive feature 322 and the secondconductive feature 326. In some embodiments, thecapping layer 324 may include Cobalt (Co), or other suitable materials. In some embodiments, thecapping layer 324 may be formed by CVD, ALD, or other suitable processes. - In some embodiments, the
capping layer 324 is selectively formed on the firstconductive feature 322 and the secondconductive feature 326 but not on thedielectric layer 312. In some embodiments, before the formation of thecapping layer 324, a pretreatment operation may be performed to clean the surfaces of the firstconductive feature 322 and the secondconductive feature 326. For example, a wet clean process may be performed to remove copper oxide on top surfaces of the firstconductive feature 322 and the secondconductive feature 326, some post CMP residue on thedielectric layer 312, and/or organic contamination from the CMP on thedielectric layer 312, the firstconductive feature 322 and the secondconductive feature 326. - In some embodiments, the
capping layer 324 may be formed by CVD process with Co precursor and H2. In some embodiments, the firstconductive feature 322 and the secondconductive feature 326 may include copper (Cu). For example, during the CVD process, H2 strips the dicarbonyl groups from the Co precursor resulting in cobaltocene plus H2. The Cu surfaces of the firstconductive feature 322 and the secondconductive feature 326 then bond with the hydrogen. Then, the cobaltocene replaces the hydrogen on the surfaces of the firstconductive feature 322 and the secondconductive feature 326 and forms Co capping layer (the capping layer 324) on the firstconductive feature 322 and the secondconductive feature 326. In some embodiments, thecapping layer 324 may be formed by CVD, ALD, or other suitable processes. - As shown in
FIG. 3G andoperation 514 inFIG. 5 , ablocking layer 328 is formed on thedielectric layer 312. In some embodiments, theblocking layer 328 is formed by molecules with silicon-based function groups, and therefore theblocking layer 328 is formed on thedielectric layer 312, e.g., low k materials, but not on thecapping layer 324, e.g., Co. For example, theblocking layer 328 may include a head group connected to a function group by way of a molecular chain. The head group is configured to adhere to preferred surfaces such as the surface of thedielectric layer 312 while not adhering to other surfaces such as the surfaces of thecapping layer 324. In some embodiments, the head group may include butyltriethoxysilane, cyclohexyltrimethoxysilane, cyclopentyltrimethoxysilane, dodecyltriethoxysilane, dodecyltrimethoxysilane, decyltriethoxysilane, dimethoxy(methyl)-n-octylsilane, triethoxyethyl silane, ethyltrimethoxysilane, hexyltrimethoxysilane, hexyltriethoxysilane, hexadecyltrimethoxysilane, hexadecyltriethoxysilane, triethoxymethylsilane, trimethoxy(methyl)silane, methoxy(dimethyl)octadecylsilane, methoxy(dimethyl)-n-octyl silane, octadecyltriethoxysilane, triethoxy-n-octylsilane, octadecyltrimethoxysilane, trimethoxy(propyl)silane, trimethoxy-n-octylsilane, triethoxy(propyl)silane, methane, ethane, propane, butane, pentane, hexane, heptane, octane, nonane, decane, undecane, dodecane, pentadecane, hexadecane, any combination of the foregoing, or the like. In some embodiments, the function group may include a hydrophobic interfacial property that repels dielectric material, thereby preventing dielectric material from adhering to theblocking layer 328, in a later dielectric on metal (DoM) process. In some embodiments, the function group may include a methyl group, which provides the hydrophobic interfacial property. In some embodiments, theblocking layer 328 may be formed by a wet process, such as dip coating, spin coating, spraying coating, or other suitable processes. - As shown in
FIG. 3H andoperation 516 inFIG. 5 , adielectric layer 330 is formed on thecapping layer 324. In some embodiments, thedielectric layer 330 may include metal oxide, metal nitride, or other suitable materials. In some embodiments, thedielectric layer 330 may be formed by thermal ALD, or other suitable processes. In some embodiments, thedielectric layer 330 may be formed by DoM selective deposition. As described above, because of the function group of theblocking layer 328 prevents dielectric material from adhering to theblocking layer 328. Thedielectric layer 330 is formed only on thecapping layer 324. In some embodiments, thedielectric layer 330 may prevent damage to the below layers, such as thecapping layer 324, the firstconductive feature 322, and the secondconductive feature 326, during subsequent processing steps. - As shown in
FIG. 3I , theblocking layer 328 is removed and anESL 332 is conformally formed over thedielectric layer 312, theliner layer 318, thebarrier layer 320, and thedielectric layer 330. In some embodiments, theESL 332 may be formed by PVD, CVD, PECVD, ALD, plasma enhanced ALD (PEALD), or other suitable processes. In some embodiments, theESL 332 may include silicon oxycarbide, silicon carbon nitride, silicon nitride, silicon carbon oxynitride, silicon dioxide, silicon carbide, silicon oxynitride, aluminum nitride, aluminum oxynitride, aluminum oxide, another dielectric material, or other suitable materials. In some embodiments, theESL 332 may have a thickness between 5 Angstroms and 200 Angstroms. Then, as shown inFIG. 3J , a portion of theESL 332 is removed to expose portions of thedielectric layer 312. - As shown in
FIG. 3K , athird opening 334 is formed in thedielectric layer 312 between the firstconductive feature 322 and the secondconductive feature 326. In some embodiments, an etch operation is performed on theESL 332, thedielectric layer 312, theliner layer 318, thebarrier layer 320, and thedielectric layer 330. In some embodiments, the etch operation may include dry etch, wet etch, or other suitable processes. Because the sidewalls of thebarrier layer 320 are covered and protected by theliner layer 318, theliner layer 318 can prevent the damage on sidewalls of thebarrier layer 320 during the etch operation. - As shown in
FIG. 3L , adielectric layer 336 is formed over thethird opening 334 and anair gap 338 is formed between the firstconductive feature 322 and the secondconductive feature 326 in thedielectric layer 336. In some embodiment, thedielectric layer 336 may partially fill thethird opening 334 resulting theair gaps 338. In some embodiments, thedielectric layer 336 may be the same material as thedielectric layer 312. In some embodiments, thedielectric layer 336 may include or be made of porous SiCOH, dense SiCOH, boron nitride (BN), boron carbide (BC), or other suitable materials. In some embodiments, thedielectric layer 336 may formed by PECVD, ALD, PVD, or other suitable processes. - In some embodiments, for forming the
air gap 338 in thedielectric layer 336, a non-conformal deposition process may be performed to form thedielectric layer 336 in thethird opening 334 duringoperation 516. For example, the PECVD process may be performed to form thedielectric layer 336 in thethird opening 334 and form theair gap 338 in thedielectric layer 336. In some embodiments, because of the deposition process is non-conformal, theair gap 338 may be triangle shaped or like triangle shaped, as shown inFIG. 3L . As shown inFIG. 3L , theair gap 338 is wider near a lower portion of thethird opening 334 and narrower near an upper portion of thethird opening 334. In some embodiments, theair gap 338 is defined by thedielectric layer 336 and thedielectric layer 312. - In some embodiments, the
air gap 338 may reduce an effective dielectric constant of thedielectric layer 336. In some embodiments, the effective dielectric constant of thedielectric layer 336 may be reduced to a range between 2 and 3.6. By reducing the effective dielectric constant of thedielectric layer 336, the capacitance between the firstconductive feature 322 and the secondconductive feature 326 is reduced, and thereby the performance of thesemiconductor structure 300 may be increased. -
FIGS. 4A-4G are cross-sectional side views of various stages of manufacturing anothersemiconductor structure 400, including aninterconnection structure 401, in accordance with some embodiments. In some embodiments, theinterconnection structure 401 may be formed on or below thesemiconductor device structure 100.FIG. 6 is a flow chart of amethod 600 for manufacturing theinterconnection structure 401 in accordance with some embodiments. For the purpose of better describing the present disclosure, the cross-sectional side view of thesemiconductor structure 400 inFIGS. 4A-4G and themethod 600 inFIG. 6 will be discussed together. It is understood that the operations shown in themethod 600 are not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIGS. 4A-4G andFIG. 6 . - As shown in
FIG. 4A , the structure and manufacturing process of thesemiconductor structure 400 are similar to those of thesemiconductor structure 300 inFIG. 3D . In other words, theoperations method 600 may be similar to theoperations method 500. However, as shown inFIG. 4A andoperation 610 inFIG. 6 , after removing a portion of theliner layer 318 that covers theconductive layer 308, ablocking layer 402 is formed at the bottom of thesecond opening 316 on the exposedconductive layer 308. - In some embodiments, the
blocking layer 402 is formed by molecules with sulfur (S) or phosphorus (P) function groups. For example, theblocking layer 402 may include a head group connected to a function group by way of a molecular chain. In some embodiments, the head group has a high affinity to the metal surface (e.g., the exposed conductive layer 308), and thus adhere and/or anchor to the exposedconductive layer 308 rather than theliner layer 318. - As shown in
FIG. 4B andoperation 612 inFIG. 6 , abarrier layer 404 is formed over theliner layer 318 but not on theblocking layer 402. In some embodiments, since theblocking layer 402 is formed by molecules with S or P function groups, the S or P function group may repel the deposition of thebarrier layer 404 on theblocking layer 402. In some embodiments, thebarrier layer 404 may include TaN, TiN, or other suitable materials. In some embodiments, thebarrier layer 404 may have a thickness between 10 Angstroms and 30 Angstroms. In some embodiments, thebarrier layer 404 may be formed by thermal ALD, or other suitable processes. - As shown in
FIG. 4C andoperation 614 inFIG. 6 , theblocking layer 402 is removed. Then, as shown inoperation 616 inFIG. 6 , a firstconductive feature 406, a secondconductive feature 408, and acapping layer 410 are formed in thefirst opening 314 and thesecond opening 316 over thebarrier layer 404. In some embodiments, the materials and the manufacturing processes of the firstconductive feature 406, the secondconductive feature 408, and thecapping layer 410 may be similar to the materials and the manufacturing processes of the firstconductive feature 322, the secondconductive feature 326, and thecapping layer 324. Because theblocking layer 402 prevents the formation of thebarrier layer 404 at the bottom of thesecond opening 316, after forming the secondconductive feature 408, the secondconductive feature 408 can in direct contact with theconductive layer 308. Therefore, the resistance between the via structure (the second conductive feature 408) and theconductive layer 308 may be reduced. - As shown in
FIG. 4D , adielectric layer 412 is formed on thecapping layer 410. AnESL 414 is formed over thedielectric layer 312, theliner layer 318, thebarrier layer 404, and thedielectric layer 412. Adielectric layer 416 is formed and anair gap 418 is formed between the firstconductive feature 406 and the secondconductive feature 408 in thedielectric layer 416. In some embodiments, the materials and the manufacturing processes of thedielectric layer 412, theESL 414, thedielectric layer 416, and theair gap 418 may be similar to the materials and the manufacturing processes of thedielectric layer 330, theESL 332, thedielectric layer 336, and theair gap 338 shown inFIGS. 3F-3L . - The
air gap 418 may reduce an effective dielectric constant of thedielectric layer 416. In some embodiments, the effective dielectric constant of thedielectric layer 416 may be reduced to a range between 2 and 3.6. By reducing the effective dielectric constant of thedielectric layer 416, the capacitance between the firstconductive feature 406 and the secondconductive feature 408 is reduced, and thereby the performance of thesemiconductor structure 400 may be increased. - In addition, the
liner layer 318 may prevent the damage at the sidewalls of thebarrier layer 404, or the firstconductive feature 406 and the secondconductive feature 408, during the etch process of forming the opening between the firstconductive feature 406 and the secondconductive feature 408. Thedielectric layer 412 may prevent top side damage of the firstconductive feature 406 and the secondconductive feature 408 during the etch process of forming the opening between the firstconductive feature 406 and the secondconductive feature 408. - Furthermore, in the
semiconductor structure 400, because theblocking layer 402 prevents the formation of thebarrier layer 404 at the bottom of thesecond opening 316, the secondconductive feature 408 can in direct contact with theconductive layer 308. Therefore, the resistance of the via structure may be reduced. The resistance-capacitance (RC) delay of the semiconductor structure may be further reduced. -
FIG. 4E illustrates an example of thesemiconductor structure 400. In some embodiments, thesemiconductor structure 400 may include thesemiconductor substrate 302. Thedevice 304, such as a transistor shown inFIG. 4E , may be formed on thesemiconductor substrate 302. TheMEOL 306 may include one or more than one conductive structure, such as one or more than one conductive layer and via, in contact with the terminals of thedevice 304. Theinterconnection structure 401 is formed on theMEOL 306. -
FIG. 4F illustrates another example of thesemiconductor structure 400. Aconductive feature 450 may be formed above theinterconnection structure 401 and in electric contact with the secondconductive feature 408.FIG. 4F illustrates a further example of thesemiconductor structure 400. Anotherinterconnection structure 452 may be further formed on theinterconnection structure 401. Furthermore, theinterconnection structure 452 may include the air gap, or without the air gap as shown inFIG. 4G . -
FIG. 4H is schematic cross-sectional side view of thesemiconductor device structure 100 in accordance with some embodiments. Thesemiconductor device structure 100 may include thedevice layer 102 formed on and in thesubstrate 302 and aninterconnection structure 460 formed over thedevice layer 102. Theinterconnection structure 460 includes various conductive features, such as a first plurality ofconductive features 464 and second plurality ofconductive features 466, and an intermetal dielectric (IMD)layer 462 to separate and isolate variousconductive features conductive features 464 are conductive lines and the second plurality ofconductive features 466 are conductive vias. Theinterconnection structure 460 includes multiple levels of theconductive features 464, and theconductive features 464 are arranged in each level to provide electrical paths tovarious devices layer 102 disposed below. The conductive features 466 provide vertical electrical routing from the device layer 200 to theconductive features 464 and between conductive features 464. For example, the bottom-mostconductive features 466 of theinterconnection structure 460 may be electrically connected to the conductive contacts disposed over the S/D regions 104 (FIG. 2A ) and the gate electrode layer 110 (FIG. 1B ). The conductive features 464 andconductive features 466 may be made from one or more electrically conductive materials, such as metal, metal alloy, metal nitride, or silicide. For example, theconductive features 464 and theconductive features 466 are made from copper, aluminum, aluminum copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, titanium silicon nitride, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, tungsten silicon nitride, platinum, chromium, molybdenum, hafnium, iridium, other suitable conductive material, or a combination thereof. - The
IMD layer 462 includes one or more dielectric materials to provide isolation functions to variousconductive features IMB layer 462 may include multiple dielectric layers embedding multiple levels ofconductive features IMB layer 462 is made from a dielectric material, such as SiOx, SiOxCyHz, SiOCN, SiON, or SiOxCy, where x, y and z are integers or non-integers. In some embodiments, theIMD layer 462 includes a low-k dielectric material having a k value less than that of silicon dioxide. - In some embodiments, the
conductive features 464 disposed in a level of theinterconnection structure 460 are partially overlapping with respect to the x-axis, which is substantially parallel to a major surface of thesubstrate 302, as shown inFIG. 4H . A level of theinterconnection structure 460 may be a layer of theIMB layer 462. The layers are sometimes referred to as M1, M2, . . . M10, M11, et, with M1 being closest to thedevice layer 102. Theair gap 418 described above may be included in any layers in theinterconnection structure 460. Pitch of theconductive features lower portion 470 to anupper portion 472. In some embodiments, air gaps, such as theair gaps 418, may be located in one or more metal layers in thelower portion 470, for example M1, M2, but not presented in metal layers located in theupper portion 472, for example M10, M11. In some embodiments, the top metal layer does not include air gap. The partially overlapping conductive features 464 are described in detail below. Additional materials, such as glue layers, etch stop layers, and barrier layers, may be included in theinterconnection structure 460 but are not shown inFIG. 4H for clarity. - In semiconductor devices, interconnects often account for more than half of the capacitance of a semiconductor chip and dissipate more than 50% of dynamic power of the semiconductor chip. The capacitance C of a capacitor filled with a dielectric layer having a dielectric constant k can be calculated as kC0, where C0 is the value of capacitance of the capacitor filled with vacuum. As discussed above, the air gap may be formed within the dielectric layer, for example, the
dielectric layer 312 as shown inFIGS. 3A-3L , in which thevias 316 andtrenches 314 are formed (seeFIG. 3D ). Theair gap 338 may reduce the dielectric constant k of the dielectric layer 312 (seeFIG. 3L ), and the reduced dielectric constant reduces the capacitance of the interconnection structure. As the RC time constant τ is equal to the product of the resistance R and the circuit capacitance C, the reduced capacitance shortens the RC delay. Although formation of the air gap may reduce the capacitance C of the interconnection structure by reducing the dielectric constant k of the dielectric layer, during dual damascene process, the low-k dielectric layer, particularly, the upper portion of the dielectric layer in which the trenches are formed, is inevitably damaged. The dielectric constant k of the damaged dielectric layer may be higher than the original dielectric constant k of the dielectric layer before the dual damascene process. As a result, the formation of air gaps may be insufficient to reduce the RC delay to a desired value. -
FIGS. 7A-7K are cross-sectional side views of various stages of manufacturing asemiconductor structure 700 including an interconnection structure according to one embodiment. In the embodiment, the issues of longer RC delay caused by increased dielectric constant k of a dielectric layer damaged by etching process are resolved. In some embodiments, the interconnection structure may be formed on and/or under thesemiconductor device structure 700.FIG. 8 is a flow chart of a method 800 for manufacturing the interconnection structure in accordance with some embodiments. For the purpose of better describing the present disclosure, the cross-sectional side view of thesemiconductor structure 700 inFIGS. 7A-7K and the method 800 inFIG. 8 will be discussed together. It is understood that the operations shown in the method 800 are not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIGS. 7A-7K andFIG. 8 . - As shown in
FIG. 7A , asemiconductor substrate 702 including adevice layer 704 and a middle end of the line (MOEL)layer 706 formed thereon is provided. Thesemiconductor substrate 702 may be similar tosubstrate 101 discussed above. Thedevice layer 704 may include a plurality of devices formed therein. In some embodiment, the plurality of devices may include thedevices 102 shown inFIGS. 2A and 2B . In theMEOL structure 706, low level interconnects (contacts) such as theconductive contacts 122 shown inFIGS. 2A and 2B are formed over the S/D regions 104 and thegate electrode layer 110. TheMEOL structure 706 may have smaller critical dimensions and may be spaced closer together compared to a later formed back end of the line (BEOL) counterparts. TheMEOL structure 706 may include various contacts used to electrically connect the various regions of the transistors, i.e., the source/drain features and metal gate electrode, to higher level interconnects to be formed in the BEOL. - As shown in
FIG. 7A andoperation 802 inFIG. 8 , aconductive layer 708 is formed over theMEOL structure 706, an etch stop layer (ESL) 710 may be formed over theconductive layer 708, and adielectric layer 712 is formed over theESL 710. In some embodiments, theconductive layer 708 may be a conductive layer of other interconnection structures of thesemiconductor structure 700. In some embodiments, theconductive layer 708 may be a conductive layer above theMEOL structure 706. In some embodiments, theconductive layer 708 may include Cu, Al, CuAl, Ru, Mo, W, and related alloys formed in a dielectric material (not shown). In some embodiments, theconductive layer 708 may be formed by ALD, CVD, PVD, electroless deposition (ELD), ECP, or other suitable processes. - In some embodiments, the
ESL 710 may be used to control the etching depth in thedielectric layer 712 and serve as an etch stop when forming a later formed conductive feature in thedielectric layer 712. In some embodiments, theESL 710 may include SiNx, SiCxNy, AlNx, AlOx, AOxNy, SiOx, SiCx, SiOxCy, or other suitable materials. In some embodiments, theESL 710 may be formed by CVD, PVD, ALD, spin coating, or other suitable processes. In some embodiments, thedielectric layer 712 may include or be made of porous SiCOH, dense SiCOH, BN, BC, or other suitable materials. In some embodiments, thedielectric layer 712 may be formed by PECVD, ALD, PVD, or other suitable processes. The thickness of thedielectric layer 712 may range from about 100Å to about 150Å, for example. - In
FIG. 7B andoperation 804 inFIG. 8 , asacrificial dielectric layer 713 is formed on thedielectric layer 712. Thesacrificial dielectric layer 713 may be formed by low-k dielectric materials such as carbon-rich film or polymer that may be deposited by PECVD, ALD, MLD (molecular layer deposition), or other suitable processes. The thickness of thesacrificial dielectric layer 713 may range from about 300Å to about 500Å. - In
FIG. 7C andoperation 806 inFIG. 8 ,first openings 714 are formed to expose thedielectric layer 712. In one embodiment, thefirst openings 714 may be formed by plasma etching process using CxFy, NFx, CxCl, followed by wet clean using solution with a PH value lager than 10. In the embodiment as shown inFIG. 7C , some of thefirst openings 714 are designated as trenches where interconnection structures such as conductive wires that extend within the same level, for example, within thedielectric layer 712 parallel to a top or bottom surface of thesemiconductor device 700. - In
FIG. 7D andoperation 808 inFIG. 8 , asecond opening 716 is formed by extending at least one of thefirst openings 714 through thedielectric layer 712 and theunderneath ESL 710 to expose the underneathconductive layer 708. Thesecond opening 716 extending through thedielectric layer 712 may be designated as a via where contacts between metal layers or other conductive structures at different level of thesemiconductor device 700 are formed. In some embodiments, thesecond opening 716 may be formed by dry etch, wet etch, or other suitable processes performed on thedielectric layer 712 exposed by the at least onefirst opening 714. Plasma etching process using CxFy, NFx, CxCl followed by wet clean using solution with a PH value lager than 10 may be performed to form thesecond opening 716. In the embodiment as shown inFIGS. 7C and 7D , thefirst openings 714 are formed prior to forming thesecond openings 716. In some embodiments, a via may be formed to penetrate through both thesacrificial dielectric layer 713 and thedielectric layer 712, followed by etching process performed on thesacrificial dielectric layer 713 to form thefirst openings 714 and thesecond openings 716. - In one embodiment, a liner layer (see the
liner layer 721 as shown inFIG. 10A ) may be conformally formed over thesacrificial dielectric layer 713. The liner layer may cover the top surface of thesacrificial dielectric layer 713, thefirst openings 714, and thesecond opening 716 including the exposed surface of theconductive layer 708. The liner layer may prevent the damage on sidewalls of the later formed barrier layer or conductive materials during a later etch process. A portion of the liner layer (if present) that covers theconductive layer 708 may be removed to expose theconductive layer 708. The removal of the portion of the liner layer may be performed by dry etch, or other suitable processes. - Then, as shown in
FIG. 7D andoperation 810 inFIG. 8 , abarrier layer 720 is deposited over the remainingsacrificial dielectric layer 713, the remainingdielectric layer 712, and the exposedconductive layer 708. Thebarrier layer 720 may be conformally formed along a surface profile of thesemiconductor device 700. In some embodiments, thebarrier layer 720 may be formed with materials such as TaN, TiN, or other suitable materials. Thebarrier layer 720 may have a thickness between 10 Angstroms and 30 Angstroms or about 15 Angstroms to about 20 Angstroms. In some embodiments, thebarrier layer 720 may be formed by thermal ALD or other suitable processes. - Then, as shown in
FIG. 7E andoperation 812 inFIG. 8 , thefirst openings 714 and thesecond openings 716 are filled withconductive materials 722 to form a firstconductive feature 724 and a secondconductive feature 726, respectively. The conductive material may be deposited over thebarrier layer 720 and overfills thefirst openings 714 and thesecond openings 716. Then, as shown inFIG. 7F andoperation 813 inFIG. 8 , a planarization operation, e.g., chemical mechanical polishing (CMP), may be performed so that the firstconductive feature 724 and the secondconductive feature 726 are formed, as shown inFIG. 7E . - In some embodiments, the first
conductive feature 724 and the secondconductive feature 726 may include Cu, Al, CuAl, Ru, Mo, W, and related alloys. In one embodiment, the firstconductive feature 724 may include conductive wires extending at the same level, for example, within thedielectric layer 713 or a low-k dielectric layer 723 to be formed later. The secondconductive feature 726 may include an interlayer contact structure that extends from one metal layer at one level to another metal layer at a different level. The first and secondconductive features - As discussed above, the
sacrificial dielectric layer 713 may be damaged during the dual damascene process for forming the first andsecond openings conductive features FIG. 7G andoperation 814 inFIG. 8 , the sacrificial low-k dielectric layer 713 is burned out or evaporated by thermal process or removed by plasma treatment to expose thebarrier layer 720 and the low-k dielectric layer 712. In some embodiment, the sacrificial low-k dielectric 713 may be removed using a heating process with a comparable temperature, for example, about 400° C. that is comparable to the BOEL process. Gaps are then formed between the neighboring first conductive feature724 and secondconductive feature 726. - As shown in
FIG. 7H andoperation 816 inFIG. 8 , agap fill layer 723 is formed to fill the gaps between the first and secondconductive features gap fill layer 723 is formed as a low-k dielectric layer without damage. Thegap fill layer 723 may be formed to fill gaps between adjacent firstconductive features 724, adjacent secondconductive features 726, and/or between adjacent firstconductive feature 724 and secondconductive feature 726. Thegap fill material 723 may be formed and overflows above the first and secondconductive features gap fill layer 723 may be formed by flowable low-k deposition, flowable oxide deposition, or spin-on dielectric deposition, ALD, or other suitable processes. The material of thegap fill layer 723 may be selected from materials with low dielectric constant k, for example, k≤3.6, such as porous SiCOH, dense SiCOH, BN, or BC. By using flowable low-k deposition, flowable oxide deposition, or spin-on dielectric deposition, ALD, or other suitable processes with good gap fill effect, thegap fill layer 723 may be formed to completely fill the gaps without significant air gaps formed therein. - The
gap fill layer 723 is then planarized to level with the top surface of the first conductive feature 224 and the second conductive feature 226. Then, as shown inFIG. 7I andoperation 818 inFIG. 8 , acapping layer 725 is formed on the firstconductive feature 724 and the secondconductive feature 726. In some embodiments, thecapping layer 725 may include Cobalt (Co), or other suitable materials. In some embodiments, thecapping layer 725 may be formed by CVD, ALD, or other suitable processes. In some embodiments, thecapping layer 725 is selectively formed on the firstconductive feature 722 and the secondconductive feature 726, but not on thegap fill layer 723. In some embodiments, before the formation of thecapping layer 725, a pretreatment operation may be performed to clean the surfaces of the firstconductive feature 724 and the secondconductive feature 726. For example, a wet clean process may be performed to remove copper oxide on top surfaces of the firstconductive feature 722 and the secondconductive feature 726, some post CMP residue on thegap fill layer 723, and/or organic contamination from the CMP on thegap fill layer 723, the firstconductive feature 724 and the secondconductive feature 726. - In some embodiments, the
capping layer 725 may be formed by CVD process with Co precursor and H2. The Co cap is selectively deposited on the metal, but not on dielectric material. For example, the firstconductive feature 724 and the secondconductive feature 726 may include copper (Cu) surfaces. During the CVD process, H2 strips the dicarbonyl groups from the Co precursor resulting in cobaltocene plus H2. The Cu surfaces of the firstconductive feature 724 and the secondconductive feature 726 is then bonded with the hydrogen. The cobaltocene may replace the hydrogen on the surfaces of the firstconductive feature 722 and the secondconductive feature 726 to form Co capping layer (the capping layer 725) on the firstconductive feature 724 and the secondconductive feature 726. In some embodiments, thecapping layer 725 may be formed by CVD, ALD, or other suitable processes. - As shown in
FIG. 7J andoperation 820 inFIG. 8 , anESL 728 is conformally formed over thegap fill layer 723 and thecapping layer 725. In some embodiments, theESL 728 may be formed by PVD, CVD, PECVD, ALD, plasma enhanced ALD (PEALD), or other suitable processes. In some embodiments, theESL 728 may include silicon oxycarbide, silicon carbon nitride, silicon nitride, silicon carbon oxynitride, silicon dioxide, silicon carbide, silicon oxynitride, aluminum nitride, aluminum oxynitride, aluminum oxide, another dielectric material, or other suitable materials. - In
FIG. 7K andoperation 822 inFIG. 8 , a low-k dielectric layer 730 is formed on theESL layer 728. In the BOEL process, multiple metallization layers are often formed to provide appropriate interconnection between various components or structures in thesemiconductor device 700 and to provide electric path to external devices. In the embodiment as shown inFIG. 7K , two metallization layers, including the Mx and Mx+1 are illustrated. The Mx metallization layer includes theESL layer 710, the secondconductive feature 726, the low-k dielectric layer 712 through which the secondconductive feature 726 extends to connect with theconductive layer 708, the firstconductive feature 724, thegap fill layer 723 through which both the first and secondconductive features conductive feature 726. The Mx+1 metallization layer includes thebarrier layer 720 formed along the surfaces of the firstconductive feature 724 and the secondconductive feature 726, thecapping layer 725, theESL 728, the low-k dielectric layer 730, and other conductive structures which may be formed in the similar manners for forming the first and secondconductive features gap fill layer 723 is not damaged by etching or patterning process, the original low dielectric constant of thegap fill layer 723 remains unchanged. Therefore, the capacitance of the metallization of the Mx metallization layer is not increased to cause high RC delay. The etch-free and damage-free low-kgap fill layer 723 further improves the reliability, such as the time-dependent dielectric breakdown (TDDB) and voltage breakdown (VBD) of thesemiconductor device 700. - In the embodiments as shown in
FIGS. 7A to 7K , the gaps between neighboring first and secondconductive features FIGS. 9A to 9C illustrate one embodiment of a semiconductor device 700-1 of which the capacitance of interconnection structure is reduced not only by filling the gaps with damage-free low-k dielectric material, but also by formation of air gaps within the damage-free low-k dielectric material. The processes as shown inFIGS. 7A-7G may be applied to form the structure as shown inFIG. 9A . InFIG. 9A , agap fill layer 723A, for example, a low-k dielectric layer, is deposited within the gaps and over the firstconductive features 724 over thedielectric layer 712. In the embodiment as shown inFIG. 9A , deposition processes with poor gap fill effects such as PECVD or other suitable processes is performed to form thegap fill layer 723A. As a result, thegap fill layer 723A is formed withair gaps 732 between the neighboring first and second conductive features 24 and 26, particular in the gaps with small pitch as shown inFIG. 9A . - In
FIG. 9A , the gap between the firstconductive feature 724 and another first conductive feature (not shown) may be completely filled by thegap fill layer 723A as the pitch of the gap is larger than a predetermined value. For example, as shown inFIG. 7H-I , no air gap is formed at the side of the firstconductive features 724 distant to the secondconductive feature 726. The structures as shownFIGS. 9A to 9C are formed by processes substantially the same as those as shown inFIGS. 7I to 7K . Detailed descriptions are thus omitted herein. -
FIGS. 10A to 10C illustrate another embodiment for forming asemiconductor device 900. Thesemiconductor structure 900 as shown inFIG. 10A may be formed by the same processes used for forming thesemiconductor structure 900 inFIG. 7G . In the embodiment as shown inFIG. 10B , aconformal barrier layer 702 is formed along the surface of thesemiconductor structure 900, followed by formation of an etch stop layer (ESL) 734. TheESL 734 may be formed with a predetermined thickness to avoid punch when a via is formed in the next metallization layer. In some embodiment, PECVD is used due to its poor conformality (poor gap fill effect) caused by high reaction rate of radical in plasma which often results in higher deposition rate at an upper position of an opening and lower deposition rate at a bottom position of the opening. - As shown in
FIG. 10B , no additional gap filling process is performed before forming theESL 734. That is, empty spaces orair gaps 736 are formed between the neighboring first and secondconductive features ESL 734 may be a bi-layer or a tri-layer structure with two or three layers formed over the first and secondconductive layers air gaps 736 may be enclosed between the neighboring first and secondconductive features FIG. 9C , a low-k dielectric layer 738 is formed on theESL 734. -
FIGS. 11A to 11E are cross-sectional side views of various stages of manufacturing anothersemiconductor structure 900 including an interconnection structure in accordance with some embodiments. In some embodiments, the interconnection structure may be formed on or below thesemiconductor device structure 100. It is understood that the operations as shown inFIGS. 11A to 10E are not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIGS. 11A-11E . - As shown in
FIG. 11A , aliner layer 721 is formed on asemiconductor device 900. Processes as shown inFIGS. 7A to 7C for forming thesemiconductor device 700 may be used for forming thesemiconductor structure 900 as shown inFIG. 11A . In the embodiment as shown inFIG. 10A , theliner layer 721 may be conformally formed along the top surface of thesacrificial dielectric layer 713, the surfaces offirst openings 714 and thesecond opening 716, and the exposed surface of theconductive layer 708 within thesecond opening 716. Theliner layer 721 may prevent the damage on sidewalls of the subsequently formed barrier layer 720 (seeFIG. 10B ) or conductive materials during a later etch process. Theliner layer 721 may include metal oxide, metal nitride, silicon oxide doped carbide (ODS), or other suitable materials. In some embodiments, theliner layer 721 may include AlOx, ZrOx, YOx, AlNx, TiNx, SiNx, SiCxNy, ODS, or other suitable materials. In some embodiments, theliner layer 721 may be formed by PECVD, ALD, PVD, or other suitable processes. Theliner layer 721 may prevent the damage on sidewalls of the later formed barrier layer or conductive materials during a later etch process. - In
FIG. 11B , the portion of theliner layer 721 covering theconductive layer 708 and theunderneath ESL 710 may be removed to expose theconductive layer 708. The removal of the portion of theliner layer 721 may be performed by dry etch or other suitable processes. After removing the portion of theliner layer 721 that covers theconductive layer 708 and theunderneath ESL 710, ablocking layer 901 is formed at the bottom of thesecond opening 716 on the exposedconductive layer 708. In some embodiments, theblocking layer 901 is formed by molecules with sulfur (S) or phosphorus (P) function groups. For example, theblocking layer 702 may include a head group connected to a function group by way of a molecular chain. In some embodiments, the head group has a high affinity to the metal surface (e.g., the exposed conductive layer 308), and thus adhere and/or anchor to the exposedconductive layer 708 rather than theliner layer 721. - Further referring to
FIG. 11B , abarrier layer 720 is formed over theliner layer 721 but not on theblocking layer 901. In some embodiments, since theblocking layer 901 is formed by molecules with S or P function groups, the S or P function group may repel the deposition of thebarrier layer 720 on theblocking layer 901. In some embodiments, thebarrier layer 720 may include TaN, TiN, or other suitable materials. In some embodiments, thebarrier layer 720 may have a thickness between 10 Angstroms and 30 Angstroms. In some embodiments, thebarrier layer 720 may be formed by thermal ALD, or other suitable processes. - As shown in
FIG. 11C , theblocking layer 901 is removed. A firstconductive feature 724 and a secondconductive feature 726 are formed in thefirst opening 714 and thesecond opening 716 over thebarrier layer 720. In some embodiments, the materials and the manufacturing processes for forming the firstconductive feature 724, the secondconductive feature 726 may be similar to the materials and the manufacturing processes of the firstconductive feature 322 and the secondconductive feature 326 as shown inFIGS. 7E-7K . Because theblocking layer 901 prevents the formation of thebarrier layer 720 at the bottom of thesecond opening 716, the subsequently formed secondconductive feature 726 can in direct contact with theconductive layer 708. Therefore, the resistance between the via structure (the second conductive feature 726) and theconductive layer 708 may be reduced. The RC delay may thus be reduced. - In some embodiments, the first
conductive feature 724 and the secondconductive feature 726 may include Cu, Al, CuAl, Ru, Mo, W, and related alloys. In some embodiments, the firstconductive feature 724 and the secondconductive feature 726 may include the conductive wires formed on the same level and the interlayer contact structure, respectively, deposited by ECP, ELD, PVD, or other suitable processes. - In
FIG. 11C , thesacrificial dielectric layer 713 may have been damaged during the dual damascene process for forming thesecond opening 716. Therefore, the sacrificial low-k dielectric layer 713 is burned out or evaporated by thermal process or removed by plasma treatment to expose thebarrier layer 720 and the low-k dielectric layer 712. In one embodiment, the sacrificial low-k dielectric 713 may be removed using a heating process with a comparable temperature, for example, about 400° C. that is comparable to the BOEL process. - A low-k
gap fill layer 902 is formed to fill the gaps between the first and secondconductive features FIG. 10D . The low-kgap fill layer 902 may be formed to overflow above the first and secondconductive features FIG. 11D , by using deposition with poor gap filling effect,air gaps 904 are formed in thegap fill layer 902 between the gaps with smaller pitches. For example, the gaps between the secondconductive feature 726 and the two immediately neighboring firstconductive features 724 that have a pitch smaller than a predetermined value may be incompletely or partially filled with the low-kgap fill layer 902. In other embodiment, thegap fill layer 904 may be formed by flowable low-k deposition, flowable oxide deposition, or spin-on dielectric deposition, ALD, or other suitable processes. The material of thegap fill layer 902 may be selected from porous SiCOH, dense SiCOH, BN, or BC, for example. By using flowable low-k deposition, flowable oxide deposition, or spin-on dielectric deposition, ALD, or other suitable processes with good gap fill effect, thegap fill layer 902 may be formed without significant air gaps formed therein similar to the embodiment as shown inFIGS. 7A to 7K . In yet another embodiment, the deposition of thegap fill layer 902 is skipped, leaving the gaps unfilled similar to the embodiment as shown inFIGS. 10A to 10C . - The
gap fill layer 902 is then planarized to level with the top surface of the firstconductive feature 724 and the secondconductive feature 726. Acapping layer 906 is formed on the firstconductive feature 724 and the secondconductive feature 726. In some embodiments, thecapping layer 906 may include Cobalt (Co), or other suitable materials. In some embodiments, thecapping layer 906 may be formed by CVD, ALD, or other suitable processes. - In some embodiments, the
capping layer 906 is selectively formed on the firstconductive feature 724 and the secondconductive feature 726 but not on thegap fill layer 902. In some embodiments, before the formation of thecapping layer 906, a pretreatment operation may be performed to clean the surfaces of the firstconductive feature 724 and the secondconductive feature 726. For example, a wet clean process may be performed to remove copper oxide on top surfaces of the firstconductive feature 724 and the secondconductive feature 726, some post CMP residue on thegap fill layer 902, and/or organic contamination from the CMP on thegap fill layer 902, the firstconductive feature 724 and the secondconductive feature 726. - In some embodiments, the
capping layer 906 may be formed by CVD process with Co precursor and H2. The Co cap is selectively deposited on the metal, but not on dielectric material. For example, the firstconductive feature 724 and the secondconductive feature 726 may include copper (Cu) surfaces. For example, during the CVD process, H2 strips the dicarbonyl groups from the Co precursor resulting in cobaltocene plus H2. The Cu surfaces of the firstconductive feature 724 and the secondconductive feature 726 then bond with the hydrogen. Then, the cobaltocene replaces the hydrogen on the surfaces of the firstconductive feature 724 and the secondconductive feature 726 and forms Co capping layer (the capping layer 906) on the firstconductive feature 724 and the secondconductive feature 726. In some embodiments, thecapping layer 906 may be formed by CVD, ALD, or other suitable processes. - In
FIG. 11D , adielectric layer 908 is formed on thecapping layer 906. In some embodiments, thedielectric layer 908 may include metal oxide, metal nitride, or other suitable materials. In some embodiments, thedielectric layer 908 may be formed by thermal ALD, or other suitable processes. In some embodiments, thedielectric layer 908 may be formed by DoM selective deposition. Before forming thedielectric layer 908, a blocking layer similar to theblocking layer 328 as shown inFIG. 3G may be formed on thegap fill layer 902. Because of the function group of the blocking layer prevents dielectric material from adhering to the blocking layer. Thedielectric layer 908 is formed only on thecapping layer 906. In some embodiments, thedielectric layer 906 may prevent damage to the underneath layers, such as thecapping layer 906, the firstconductive feature 724, and the secondconductive feature 726, during subsequent processing steps. - As shown in
FIG. 11E , the blocking layer (if present) is removed and anESL 910 is conformally formed over thedielectric layer 902, theliner layer 721, thebarrier layer 720, and thedielectric layer 908. In some embodiments, theESL 910 may be formed by PVD, CVD, PECVD, ALD, plasma enhanced ALD (PEALD), or other suitable processes. In some embodiments, theESL 910 may include silicon oxycarbide, silicon carbon nitride, silicon nitride, silicon carbon oxynitride, silicon dioxide, silicon carbide, silicon oxynitride, aluminum nitride, aluminum oxynitride, aluminum oxide, another dielectric material, or other suitable materials. In some embodiments, theESL 910 may have a thickness between about 5 Angstroms and about 200 Angstroms. - In
FIG. 11E , a portion of theESL 910 is removed to expose portions of thedielectric layer 908 on thecapping layer 906 and portions of thedielectric layer 902. Adielectric layer 912 is formed on the remainingESL 910, the exposeddielectric layer 908 on thecapping layer 906, and the exposed portions ofdielectric layer 902. Similar to the structures as shown inFIG. 7K , two of multiple metallization layers, including the Mx and Mx+1, are illustrated inFIG. 10E . The Mx metallization layer includes theESL 910, the secondconductive feature 726, the low-k dielectric layer 712 through which the secondconductive feature 726 extends to connect with theconductive layer 708, the firstconductive feature 724, thegap fill layer 902 through which both the first and secondconductive features conductive feature 726. The Mx+1 metallization layer includes theliner layer 721,barrier layer 720, thecapping layer 906, thedielectric layer 908, theESL 910, the low-k dielectric layer 921, and conductive structures to be formed in subsequent processes. In some embodiment, similar metallization processes for forming the Mx and Mx+1 may be repeatedly performed until a top metallization layer is formed. As thegap fill layer 902 has not been damaged by etching or patterning process, the original low dielectric constant of thegap fill layer 902 remains unchanged. Therefore, the capacitance of the metallization of the Mx metallization layer is not increased to cause high RC delay. The damage-free low-kgap filling layer 902 further improves the reliability, such as the time-dependent dielectric breakdown (TDDB) and voltage breakdown (VBD) of thesemiconductor device 700. Theair gaps 904 further reduces the capacitance of the metallization structure and subsequently shortens the RC delay. - An interconnection structure is provided according to one embodiment. The interconnection structure includes an etching-process-free first dielectric layer, a first conductive structure extending within the first dielectric layer, a second dielectric layer formed under the first dielectric layer, and a second conductive structure extending through both the first dielectric layer and the second conductive layer. The first dielectric layer may be a layer of dry air. Alternatively, the first dielectric layer may include a low-k dielectric layer made of porous SiCOH, BN, or BC. In some embodiment, the low-k dielectric layer may include air gap therein.
- The first dielectric layer may be formed by flowable low-dielectric deposition, flowable oxide deposition, spin on dielectric process, or atomic layer deposition (ALD). In other embodiments, the first dielectric structure includes an air gap between a pair of adjacent first conductive structure and second conductive structure by using plasma enhanced chemical vapor deposition (PECVD). In some embodiment, the first dielectric layer may an air gap therein if the aspect ratio of the first dielectric layer is smaller than a predetermined value. The first dielectric layer may be formed after the first conductive structure and the second conductive structures have been formed. The first conductive structure includes conductive wires made of Cu, Al, CuAl, Ru, Mo, W, or an alloy thereof.
- The second dielectric layer is formed of a low-k dielectric selected from SiCOH, BM, or BC. The second dielectric layer may be formed by PECVD, ALD, or PVD. The second conductive structure includes a conductive contact made of Cu, Al, CuAl, Ru, Mo, W, or an alloy thereof. The second conductive structure includes a conductive contact for interconnect conductive layers formed at different levels.
- A semiconductor device comprising a plurality of metallization layers. At least one of the metallization layers comprises a first dielectric layer, a first conductive structure, a second dielectric layer, and a second conductive structure. The first conductive structure may extend horizontally within the first dielectric layer, while the second conductive structure may extend vertically through the first dielectric layer and second dielectric layer. The first dielectric layer is formed within a gap between the first conductive layer and the second conductive layer without being subjected to an etching process. The first dielectric layer may include an air gap formed therein. The first dielectric layer may be a layer of dry air.
- A method of forming an interconnection structure is provided. The method includes forming a second dielectric layer over a substrate, forming a sacrificial dielectric layer on the second dielectric layer, forming a plurality of first openings extending through sacrificial dielectric layer, and extending at least one of the first openings further through the second dielectric layer to form a second opening. The first opening and the second opening are then filled with conductive material to form a first conductive structure and a second conductive structure, respectively. The sacrificial dielectric layer remained in gaps between the first and second conductive structures is then removed, and the gaps are filled with dielectric materials. The method may further comprise forming a conformal barrier before forming the first and the second conductive structures, forming an etch stop layer to cover at least portions of the first conductive structure; and forming a conductive layer over the etch stop layer. After removing the sacrificial dielectric layer, the gaps may be filled with dielectric materials with a dielectric constant smaller than a predetermined value. The gaps may also be partially or completely filled with dry air.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. An interconnection structure, comprising:
an etching-process-free first dielectric layer;
a first conductive structure extending within the first dielectric layer;
a second dielectric layer formed under the first dielectric layer; and
a second conductive structure extending through both the first dielectric layer and the second conductive layer.
2. The interconnection structure of claim 1 , wherein the first dielectric layer is a layer of air.
3. The interconnection structure of claim 1 , wherein the first dielectric layer includes a low-k dielectric layer made of porous SiCOH, BN, or BC.
4. The interconnection structure of claim 1 , wherein the first dielectric layer is formed by flowable low-dielectric deposition, flowable oxide deposition, spin on dielectric process, or atomic layer deposition (ALD).
5. The interconnection structure of claim 1 , wherein the first dielectric structure includes an air gap between a pair of adjacent first conductive structure and second conductive structure.
6. The interconnection structure of claim 5 , wherein the first dielectric structure is formed by plasma enhanced chemical vapor deposition (PECVD).
7. The interconnection structure of claim 1 , wherein the first dielectric layer includes an air gap therein when the first dielectric layer is formed to fill a space with a pitch smaller than a predetermined value.
8. The interconnection structure of claim 1 , wherein the first dielectric layer is formed after the first conductive structure and the second conductive structures have been formed.
9. The interconnection structure of claim 1 , wherein the first conductive structure includes conductive wires made of Cu, Al, CuAl, Ru, Mo, W, or an alloy thereof.
10. The interconnection structure of claim 1 , wherein the second dielectric layer is formed of a low-k dielectric selected from SiCOH, BM, or BC.
11. The interconnection structure of claim 1 , wherein the second dielectric layer is formed by PECVD, ALD, or PVD.
12. The interconnection structure of claim 1 , wherein the second conductive structure includes a conductive contact made of Cu, Al, CuAl, Ru, Mo, W, or an alloy thereof.
13. The interconnection structure of claim 1 , wherein the second conductive structure includes a conductive contact for interconnect conductive layers formed at different levels.
14. A semiconductor device, comprising:
a plurality of metallization layers, wherein at least one of the metallization layers comprises:
a first dielectric layer;
a first conductive structure, extending horizontally within the first dielectric layer;
a second dielectric layer; and
a second conductive structure extending vertically through the second dielectric layer, wherein the first dielectric layer is formed within a gap between the first conductive layer and the second conductive layer without being subjected to an etching process.
15. The semiconductor device of claim 14 , wherein the first dielectric layer includes an air gap formed therein.
16. The semiconductor device of claim 14 , wherein the first dielectric layer is a layer of air.
17. A method of forming an interconnection structure, comprising:
forming a dielectric layer over a substrate;
forming a sacrificial dielectric layer on the second dielectric layer;
forming a plurality of first openings extending through sacrificial dielectric layer;
extending at least one of the first openings further through the second dielectric layer to form a second opening;
filling the first opening and the second opening with conductive material to form a first conductive structure and a second conductive structure, respectively;
removing the sacrificial dielectric layer remained in gaps between the first and second conductive structures; and
filling the gaps with a dielectric material.
18. The method of claim 17 , further comprising:
forming a conformal barrier and a blocking layer at a bottom of the second opening before forming the second conductive structures;
removing the blocking layer for forming the second conductive structure;
forming an etch stop layer to cover at least portions of the first conductive structure; and
forming a conductive layer over the etch stop layer.
19. The method of claim 18 , further comprising filling the gaps with dielectric materials with a dielectric constant smaller than a predetermined value.
20. The method of claim 18 , further comprising filling the gaps partially or completely with air.
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