US20230155516A1 - Secondary-side flyback converter controller - Google Patents
Secondary-side flyback converter controller Download PDFInfo
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- US20230155516A1 US20230155516A1 US17/665,272 US202217665272A US2023155516A1 US 20230155516 A1 US20230155516 A1 US 20230155516A1 US 202217665272 A US202217665272 A US 202217665272A US 2023155516 A1 US2023155516 A1 US 2023155516A1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/322—Means for rapidly discharging a capacitor of the converter for protecting electrical components or for preventing electrical shock
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
- H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
- H02M1/342—Active non-dissipative snubbers
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
- H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present disclosure relates generally to flyback converters, and more specifically to a flyback converter using a controller on the secondary winding side to facilitate zero-voltage switching and synchronous rectification.
- FIG. 1 shows an active clamp flyback converter 100 using an active clamp at the primary winding of the transformer according to the prior art.
- the flyback converter 100 receives input voltage VIN from a voltage source 101 and delivers output voltage VO to a load 200 .
- the flyback converter 100 includes a flyback transformer 102 having a primary winding PRI and a secondary winding SEC, a primary switch 103 activated by a first control circuit 112 , a synchronous rectifier switch 104 activated by a second control circuit 108 , an output smoothing capacitor 105 , a clamp diode 194 , and a clamp capacitor 110 .
- the flyback converter 100 further includes an active clamp switch 193 .
- the active clamp switch 193 is coupled across the clamp diode 194 to provide a path for reverse current in the primary winding PRI of the transformer 102 .
- the inductance 192 represents leakage inductance reflected to the primary winding PRI.
- the active clamp flyback converter 100 recirculates energy stored in the leakage inductance 192 .
- it suffers added cost and complexity of driving the active clamp switch 193 , which is activated by an active clamp control circuit 111 .
- the reverse current of the primary winding PRI recirculates the energy stored in parasitic capacitance 109 back to the input voltage source 101 before the primary switch 103 turns on.
- FIG. 2 An example of such a converter 180 is depicted in FIG. 2
- the converter 180 includes all elements of the converter 100 of FIG. 1 , with the exception of the clamp diode 194 , clamp capacitor 110 , active clamp switch 193 . and active clamp control circuit 111 .
- the flyback transformer 102 of the converter 180 further comprises an auxiliary winding AUX coupled in series with a clamp capacitor 107 and an active clamp switch 106 , the active clamp switch activated by a control circuit 111 a .
- the reverse current is developed in the auxiliary winding AUX by means of coupling it across the clamp capacitor 107 via the active clamp switch 106 for a brief period.
- the active clamp switch 106 turns off, the resulting negative magnetic flux induces reverse current in the primary winding PRI, recirculating the energy stored in the parasitic capacitance 109 back to the input voltage source 101 .
- the converter 180 does not recirculate the leakage inductance energy, and it must be absorbed by some other means. However, the solution offers a lower overall cost
- FIG. 3 illustrates the operating principle of the converters of FIGS. 1 and 2 with the active clamp switches 193 and 106 . respectively, activated for a brief period preceding the turn on of the primary switch 103 .
- the waveform 301 represents the voltage across the primary switch 103 .
- the waveforms 302 and 303 represent the conductive states of the primary switch 103 and the synchronous rectifier device 104 , respectively.
- the conductive state of the synchronous rectifier device 104 may be followed by post-conduction oscillation of the voltage across the primary switch 103 illustrated by the waveform 301 .
- the oscillation period is determined primarily by the inductance of the primary winding PRI and the parasitic capacitance 109 .
- the waveform 304 represents the ZVT Pulse activating the active clamp switches 193 and 106 , respectively.
- the delay between the trailing edge of the ZVT Pulse and the rising edge of the waveform 302 represents the Dead Time allowing for discharging of the parasitic capacitance 109 .
- the synchronous rectifier device 104 can also be utilized to allow for the reverse magnetic flux in the transformer 102 , thus eliminating the need for an extra active clamp switch and an auxiliary winding and reducing the cost of the overall solution, driving the synchronous rectifier device 104 introduces excessive gate drive losses having an adverse effect on the converter efficiency. Therefore, a control method is needed to reduce the synchronous rectifier device 104 gate drive power losses when the synchronous rectifier device 104 is used for this dual purpose. Separately, an appropriate control algorithm is needed for generation of the ZVT Pulse for driving the synchronous rectifier device 104 when the synchronous rectifier device 104 is used for this dual purpose.
- a flyback converter to receive an input voltage and provide an output voltage.
- the flyback converter may include a transformer having a primary winding and secondary winding, a primary switch coupled to the primary winding, a synchronous rectifier device coupled to the secondary winding, and a secondary side control circuit to turn on the synchronous rectifier device by outputting a control signal at a first amplitude, subsequently modify the control signal to maintain substantially constant voltage across the synchronous rectifier device until a predicted time that precedes a current in the synchronous rectifier device reaching zero, subsequently turn off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero, and subsequently turn on the synchronous rectifier device by outputting the control signal at a second amplitude, before the primary switch is turned on.
- the second amplitude may be less than the first amplitude.
- the secondary side control circuit may include a synchronous rectifier control circuit that may predict the predicted time that precedes a time at which the current in the synchronous rectifier device reaches substantially zero.
- the synchronous rectifier control circuit may have a transconductance error amplifier, and the synchronous rectifier control circuit may store a voltage level at an output of the transconductance error amplifier sampled at the predicted time. The second amplitude may substantially equal the stored voltage level at the predicted time.
- the synchronous rectifier control circuit may predict the predicted time that precedes the time at which the current in the synchronous rectifier device reaches substantially zero by integrating a difference between the voltage across the synchronous rectifier device and the output voltage.
- the synchronous rectifier control circuit may predict the predicted time that precedes the time at which the current in the synchronous rectifier device reaches substantially zero by integrating the voltage across the secondary winding.
- the secondary side control circuit may turn on the synchronous rectifier device by outputting the control signal at the first amplitude in response to detecting that the voltage across the synchronous rectifier device is negative, and may reduce the control signal from the first amplitude as the current in the synchronous rectifier device decreases.
- the secondary side control circuit may hold the control signal at a substantially constant level after the predicted time, before turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero.
- the voltage across the synchronous rectifier device may enter oscillation when the synchronous rectifier device is turned off.
- the secondary side control circuit may turn on the synchronous rectifier device at the last valley of the oscillation of the voltage across the synchronous rectifier device before the primary switch is turned on.
- the secondary side control circuit may include a pulse generator circuit that may detect a period of the oscillation of the voltage across the synchronous rectifier device.
- the secondary side control circuit may turn on the synchronous rectifier device before the primary switch is turned on for a duration of time based on the detected period of oscillation of the voltage across the synchronous rectifier device.
- the flyback converter may also include a primary switch control circuit that may turn on the primary switch after a dead time delay following the turn off of the synchronous rectifier device.
- a method of controlling a flyback converter that includes a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, and a synchronous rectifier device coupled to the secondary winding.
- the method may include outputting a control signal at a first amplitude to turn on the synchronous rectifier device, subsequently modifying the control signal to maintain substantially constant voltage across the synchronous rectifier device until a predicted time that precedes a current in the synchronous rectifier device reaching substantially zero, subsequently turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero, subsequently turning on the synchronous rectifier device by outputting the control signal at a second amplitude, before the primary switch is turned on.
- the second amplitude may be less than the first amplitude.
- the method may also include predicting a predicted time that precedes a time at which a current in the synchronous rectifier device reaches substantially zero.
- the method may also include storing a voltage level of the output of a transconductance error amplifier at the predicted time.
- the output of the transconductance error amplifier may be based on a difference between the voltage across the synchronous rectifier device and a reference voltage.
- the second amplitude may substantially equal the stored voltage level at the predicted time.
- Predicting the predicted time may include integrating a difference between the voltage across the synchronous rectifier device and an output voltage across the secondary winding.
- Predicting the predicted time may include integrating a voltage across the secondary winding.
- the outputting of the control signal at the first amplitude to turn on the synchronous rectifier device may occur in response to detecting the voltage across the synchronous rectifier device is negative.
- the method may include, after the outputting of the control signal at the first amplitude to turn on the synchronous rectifier device, reducing the control signal from the first amplitude as the current in the synchronous rectifier device decreases.
- the method may include, at the predicted time, holding the control signal at a substantially constant level, before turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero.
- the voltage across the synchronous rectifier device may enter oscillation when the synchronous rectifier device is turned off, and the subsequent turning off of the synchronous rectifier device may occur at the last valley of the oscillation of the voltage across the synchronous rectifier device before the primary switch is turned on.
- the method may include detecting a period of the oscillation of the voltage across the synchronous rectifier device.
- the subsequent turning on of the synchronous rectifier device may be for a duration based on the detected period of oscillation of the voltage across the synchronous rectifier device.
- the method may include turning on the primary switch after a dead time delay following the turning off of the synchronous rectifier device.
- a method of generating an auxiliary pulse signal for controlling a synchronous rectifier device coupled to a secondary winding of a transformer in a flyback converter may include outputting a control signal at a first amplitude, reducing the control signal from the first amplitude as the current in the synchronous rectifier device decreases, predicting a predicted time that precedes a time at which the current in the synchronous rectifier device reaches substantially zero, storing a voltage level of the output of a transconductance amplifier at the predicted time, wherein the output of the transconductance error amplifier is based on a difference between the voltage across the synchronous rectifier device and a reference voltage.
- the method may also include generating the auxiliary pulse signal so as to output the control signal to turn on the synchronous rectifier device before the primary switch is turned on, the control signal responsive to the auxiliary pulse signal at an amplitude substantially equal to the stored voltage level of the output of the transconductance error amplifier at the predicted time.
- a method of generating an auxiliary pulse signal for controlling a synchronous rectifier device coupled to a secondary winding of a transformer in a flyback converter may include detecting a period of oscillation of a voltage across the synchronous rectifier device, detecting a peak voltage across the synchronous rectifier device, and generating the auxiliary pulse signal having a pulse width determined based on the detected period of oscillation of the voltage across the synchronous the rectifier device, and a difference between the peak voltage across the synchronous rectifier device and an output voltage of the flyback converter.
- FIG. 1 shows an active clamp flyback converter according to the prior art.
- FIG. 2 shows a flyback converter having an auxiliary winding according to the prior art.
- FIG. 3 shows a waveform diagram illustrating the operation of the flyback converters of FIGS. 1 and 2 .
- FIG. 4 shows a circuit diagram of a flyback converter according to various examples of the present disclosure.
- FIG. 5 shows a waveform diagram illustrating the operation of the flyback converter shown in FIG. 4 .
- FIG. 6 shows a waveform diagram illustration the operation of a pulse generator circuit according to various examples of the present disclosure.
- FIG. 7 shows a circuit diagram of a pulse generator circuit according to various examples of the present disclosure.
- FIG. 8 shows a circuit diagram of a synchronous rectifier control circuit according to various examples of the present disclosure.
- FIG. 9 shows a circuit diagram of a zero current prediction circuit according to various examples of the present disclosure.
- FIG. 4 is a circuit schematic of a flyback converter 400 in accordance with various examples of the present disclosure.
- the example flyback converter 400 receives input voltage V IN from an input voltage source 101 and delivers galvanically isolated output voltage V O to a load 200 .
- the flyback converter 400 includes: a transformer 102 having a primary winding PRI and a secondary winding SEC; a primary switch 103 ; a primary switch control circuit 112 ; a synchronous rectifier device 104 coupled to the secondary winding SEC; a secondary side control circuit 199 , which may include a synchronous rectifier control circuit 117 and a pulse generator circuit 116 ; and an output smoothing capacitor 105 .
- the converter 400 also includes effective parasitic capacitance 109 .
- FIG. 4 depicts the capacitance 109 reflected to the primary switch 103 , while it needs to be understood as total parasitic capacitance distributed across all elements of the flyback converter 400 and its physical construction.
- the primary switch control circuit 112 activates the primary switch 103 repetitively to couple the primary winding PRI to the input voltage source 101 for receiving electrical energy from the input voltage source 101 and storing it in the transformer 102 .
- the secondary side control circuit 199 drives the synchronous rectifier device 104 .
- the secondary side control circuit 199 may include the pulse generator circuit 116 that generates an auxiliary pulse signal in accordance with the output voltage V O and the voltage V D across the synchronous rectifier device 104 .
- the secondary side control circuit 199 may also include the synchronous rectifier control circuit 117 that controls the synchronous rectifier device 104 in accordance with the voltage V D across the synchronous rectifier device 104 and the auxiliary pulse signal received from the pulse generator circuit 116 .
- the synchronous rectifier control circuit 117 may also control the synchronous rectifier device 104 based on the output voltage V O , as represented by the dotted line in FIG. 4 connecting the output voltage V O to the synchronous rectifier control circuit 117 .
- the operating principle of the flyback converter 400 is illustrated by FIG. 5 .
- the waveform 301 represents the voltage across the primary switch 103 .
- the waveform 311 represents the voltage V D across the synchronous rectifier device 104 , whereas its exploded portion in the vicinity of the common return voltage is shown by the waveform 311 a .
- the waveform 399 represents the current in the synchronous rectifier device 104 , which substantially equals the current in the secondary winding SEC of the transformer 102 .
- the waveform 302 shows the primary control signal to the primary switch 103 generated by the primary switch control circuit 112
- the waveform 312 represents the control voltage to the synchronous rectifier device 104 generated by the synchronous rectifier control circuit 117 .
- the synchronous rectifier control circuit 117 maintains this Plateau level of voltage V D across the synchronous rectifier device 104 by reducing the control voltage to the synchronous rectifier device 104 as shown by waveform 312 so as to increase the on resistance of the synchronous rectifier device 104 as the current through the synchronous rectifier device 104 (shown as waveform 399 ), i.e. the current through secondary winding SEC, falls towards zero.
- the synchronous rectifier control circuit 117 further predicts a predicted time that precedes the current in the synchronous rectifier device 104 reaching substantially zero by, for example, integrating the difference between voltage V D across the synchronous rectifier device 104 and the output voltage V O .
- the synchronous rectifier control circuit 117 may alternatively predict a predicted time that precedes the current in the synchronous rectifier device 104 reaching substantially zero by integrating the voltage across the secondary winding SEC, i.e. V O - V D .
- this predicted time designated on the waveform 312 as ZCP
- the synchronous rectifier control circuit 117 changes its output to a high impedance, thus no longer driving the control voltage to the synchronous rectifier device 104 as shown by waveform 312 .
- the synchronous rectifier control circuit 117 turns the synchronous rectifier device 104 off by driving the control voltage to the synchronous rectifier device 104 as shown by waveform 312 to substantially zero voltage.
- the level of the control voltage to the synchronous rectifier device 104 as shown by waveform 312 to the synchronous rectifier device 104 is sampled at ZCP, and is stored to subsequently set the amplitude of the control signal based on an auxiliary pulse signal, having pulse width t NEG , as illustrated by the waveform 312 .
- the auxiliary pulse signal having pulse width t NEG , may be generated by the pulse generator circuit 116 at the last peak of oscillation of the waveform 301 , i.e. the last peak of oscillation of the voltage across the primary switch 103 , or the last valley of oscillation of the waveform 311 , i.e. the last valley of oscillation of the V D across the synchronous rectifier device 104 , that precedes the next turn on of the primary switch 103 , and further propagated by the synchronous rectifier control circuit 117 as the control signal to the synchronous rectifier device 104 at the stored amplitude.
- the auxiliary pulse signal having pulse width t NEG , may reduce switching losses in the synchronous rectifier device 104 , by activating the synchronous rectifier device 104 in the last valley of oscillation of the voltage V D across the synchronous rectifier device 104 that precedes the next turn on of the primary switch 103 .
- the principle of operation of the pulse generator circuit 116 is illustrated by FIG. 6 .
- the waveform 311 represents the voltage V D across the synchronous rectifier device 104 , referenced to the output voltage level V O .
- the pulse width of the waveform 322 represents the half-cycle of the oscillation of the voltage V D across the synchronous rectifier device 104 , which is measured by the pulse generator circuit 116 .
- the waveform 323 is the auxiliary pulse signal having pulse width t NEG generated by the pulse generator circuit 116 .
- the parasitic capacitance 109 may be non-linear since it includes the output capacitance of the primary switch 103 , which increases substantially at a lower voltage across it. Therefore, the energy stored in the parasitic capacitance 109 is greater by a factor of k er >1 as compared to one calculated as CV 2 /2.
- the pulse generator circuit 116 monitors the voltage V D across the synchronous rectifier device 104 and the output voltage V O , and may generate a pulse width t NEG of the auxiliary pulse signal based on the following equation:
- V D(PK) is a sampled peak voltage at the synchronous rectifier device 104
- T/2 is the half-cycle of the oscillation of the voltage V D across the synchronous rectifier device 104 detected by the pulse generator circuit 116 .
- the auxiliary pulse signal When generated in accordance with the above equation under the condition of k er (V D(PK) -V O ) 2 /V O 2 >>1, the auxiliary pulse signal may result in a reverse magnetic flux in the transformer 102 that discharges the parasitic capacitance 109 to substantially zero, and may reduce switching power losses.
- the pulse generator circuit 116 may generate the auxiliary pulse signal having a pulse width t NEG that is adaptive to the levels of the voltage V D across the synchronous rectifier device 104 and the output voltage V O , as well as the parasitic capacitance 109 and inductance of the transformer 102 .
- the primary switch control circuit 112 provides a delay between the trailing edge of the control voltage, generated responsive to auxiliary pulse signal, to the synchronous rectifier device 104 , as shown by waveform 312 , and the leading edge of the primary control signal, as shown by waveform 302 of FIG. 5 , designated as Dead Time in FIGS. 5 and 6 .
- the primary switch control circuit 112 may be coupled to receive an indication of the control signal for the synchronous rectifier device 104 via magnetic, capacitive, or optical devices.
- the Dead Time delay may be a predetermined delay, and may allow for discharging the parasitic capacitance 109 to substantially zero.
- the Dead Time delay may be adaptively calculated as a function of the sampled period of oscillation T of the voltage V D across the synchronous rectifier device 104 , as shown in waveform 322 , which sampling may be done by the synchronous rectifier control circuit 117 .
- the Dead Time delay may be programmed to be T/4 from when the voltage V D across the synchronous rectifier device 104 exceeds the output voltage V O .
- a pulse generator circuit 116 is depicted in FIG. 7 .
- the pulse generator circuit 116 repetitively generates an auxiliary pulse signal based on the voltage V D across the synchronous rectifier device 104 , and the output voltage V O .
- the pulse generator circuit 116 may include a leading-edge blanking circuit 401 , a peak detector 402 , a subtractor circuit 405 , a comparator 403 , and a pulse width modulation (PWM) circuit 406 .
- the peak detector 402 samples the peak voltage at the synchronous rectifier device 104 V D(PK) after a blanking delay generated by the leading-edge blanking circuit 401 .
- the subtractor 405 further subtracts the output voltage V O from the sampled peak voltage V D(PK) .
- the comparator 403 compares the voltage V D across the synchronous rectifier device 104 with the output voltage V O and outputs a pulse width equal to a half-cycle T/2 of the oscillation of the voltage V D across the synchronous rectifier device 104 responsive to the voltage V D across the synchronous rectifier device 104 exceeding the output voltage V O .
- the PWM circuit 406 generates the auxiliary pulse signal having a pulse width t NEG proportional to:
- a synchronous rectifier control circuit 117 is shown in FIG. 8 .
- the synchronous rectifier control circuit 117 depicted in FIG. 8 generates a control signal SR_Ctrl for driving the synchronous rectifier device 104 by monitoring the voltage V D across the synchronous rectifier device 104 .
- the synchronous rectifier control circuit 117 may also monitor the output voltage V O , and also propagates the auxiliary pulse signal having pulse width t NEG received from the pulse generator circuit 116 to its output, as the control signal SR_Ctrl, at a controlled amplitude.
- the synchronous rectifier control circuit 117 includes: a first comparator 504 having a non-inverting terminal configured to receive a first reference threshold -V TH1 and an inverting terminal configured to receive the voltage V D across the synchronous rectifier device 104 , a second comparator 505 having an inverting terminal configured to receive a second reference threshold -V TH2 and a non-inverting terminal configured to receive the voltage V D across the synchronous rectifier device 104 , a transconductance error amplifier 501 having a non-inverting terminal configured to receive a reference voltage -V REF , an inverting terminal configured to receive the voltage V D across the synchronous rectifier device 104 , and a tri-state control input HI-Z, a zero current prediction circuit 509 , a frequency compensator circuit 502 , a voltage buffer 503 , a latch circuit 506 , an OR gate 507 , and an output buffer 508 .
- the first comparator 504 detects negative voltage VD across the synchronous rectifier device 104 falling below the first threshold -VTH1 and sets the latch circuit 506 .
- Transconductance amplifier 501 receives voltage VD across the synchronous rectifier device 104 at its inverting input, a reference voltage -VREF at its non-inverting input, and outputs an amplified error voltage as a function of the difference between VD and -VREF.
- the frequency compensator circuit 502 may be an RC network having an impedance Z(s).
- the output voltage of the transconductance amplifier 104 takes the highest magnitude, as dictated by the output voltage range of the transconductance amplifier 104 .
- the output of the latch circuit 506 then propagates via the gate 507 and the output buffer 508 at the highest output magnitude of the transconductance error amplifier 501 , as buffered by voltage buffer 503 .
- the magnitude of the voltage VD across the synchronous rectifier device 104 begins falling until it reaches substantially the reference level -VREF.
- the magnitude of the voltage VD across the synchronous rectifier device 104 reaches substantially the reference level -VREF, the voltage at the output of the transconductance error amplifier 501 decreases.
- the decreasing voltage at the output of the transconductance error amplifier 501 which is buffered by voltage buffer 503 , reduces the magnitude of the control signal SR_Ctrl to maintain a substantially constant voltage VD across the synchronous rectifier device 104 .
- the zero current prediction circuit 509 seeks to predict a predicted time that precedes the time at which the current in the synchronous rectifier device 104 reaches zero.
- the zero current prediction circuit 509 When this predicted time is reached, the zero current prediction circuit 509 outputs a signal to the high-impedance state input of the error amplifier 501 , placing the output of transconductance error amplifier 501 into a high impedance state.
- the frequency compensator circuit 502 stores the voltage at the output of the transconductance error amplifier 501 at a substantially constant level, i.e. substantially at the voltage level appearing at the output of the transconductance error amplifier 501 when the predicted time is reached. Since the voltage V D across the synchronous rectifier device 104 is no longer regulated, it begins falling.
- the second comparator 505 detects the voltage V D across the synchronous rectifier device reaching the second threshold -V TH2 and resets the latch circuit 506 , terminating the control signal SR_Ctrl through OR gate 507 .
- the synchronous rectifier control circuit 117 When the synchronous rectifier control circuit 117 receives the auxiliary pulse signal having a pulse width t NEG , it propagates the auxiliary pulse signal to the control signal SR_Ctrl output via the OR gate 507 and the output buffer 508 at the magnitude of the voltage V D across the synchronous rectifier device 104 held by the frequency compensator circuit 502 and buffered by the voltage buffer 503 .
- FIG. 9 depicts a zero current prediction circuit 509 according to various examples.
- the zero current prediction circuit 509 depicted in FIG. 9 by monitoring the output voltage V O and the voltage V D across the synchronous rectifier device 104 , generates a HI-Z command for putting the error amplifier 501 of FIG. 8 into a high-impedance output state.
- the zero current prediction circuit 509 of FIG. 9 includes: a subtractor 601 ; an integrator 602 having a reset input; a first comparator 603 with a first threshold voltage V TH3 ; and a latch 605 .
- the integrator 602 integrates over time the difference between the voltage V D across the synchronous rectifier device 104 and the output voltage V O derived by the subtraction node 601 .
- the output of the integrator 602 is monitored by the first comparator 603 and compared to the first reference voltage V TH3 to predict demagnetization of the transformer 102 .
- the first comparator 603 sets the latch 605 when the output of the integrator 602 reaches the first threshold V TH3 .
- the latch 605 can be reset at any arbitrary moment following the auxiliary pulse signal.
- the zero current prediction circuit 509 of FIG. 9 shows a second comparator 604 with a second threshold voltage -V TH4 .
- the second comparator 604 detects the voltage V D across the synchronous rectifier device 104 falling below the second reference voltage -V TH4 and resets the latch 605 , terminating the HI-Z command.
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Abstract
A flyback converter to receive an input voltage and provide an output voltage is provided, and may include a transformer having a primary winding and secondary winding, a primary switch coupled to the primary winding, a synchronous rectifier device coupled to the secondary winding, and a secondary side control circuit to turn on the synchronous rectifier device by outputting a control signal at a first amplitude, subsequently modify the control signal to maintain a voltage across the synchronous rectifier device substantially constant until a predicted time that precedes a current in the synchronous rectifier device reaching substantially zero, subsequently turn off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero, and subsequently turn on the synchronous rectifier device by outputting the control signal at a second amplitude, before the primary switch is turned on. The second amplitude is less than the first amplitude.
Description
- This application claims the benefit of U.S. Provisional Pat. Application No. 63/281,001, filed on Nov. 18, 2021, which is incorporated herein by reference in its entirety.
- The present disclosure relates generally to flyback converters, and more specifically to a flyback converter using a controller on the secondary winding side to facilitate zero-voltage switching and synchronous rectification.
- Increased demand for high-efficiency flyback converters gave rise to various solutions using an active clamp to facilitate zero-voltage switching (ZVS) of the switching device. Some of these active clamp flyback converters maintain a complimentary drive of the clamp switch; others only activate the clamp switch for a brief period immediately before turning the controlled switching device on. Both types of solutions are intended to develop current in reverse direction in the power transformer windings and then provide a dead time to allow for discharging the parasitic capacitance of the switching node to substantially zero voltage.
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FIG. 1 shows an activeclamp flyback converter 100 using an active clamp at the primary winding of the transformer according to the prior art. Theflyback converter 100 receives input voltage VIN from avoltage source 101 and delivers output voltage VO to aload 200. Theflyback converter 100 includes aflyback transformer 102 having a primary winding PRI and a secondary winding SEC, aprimary switch 103 activated by afirst control circuit 112, asynchronous rectifier switch 104 activated by asecond control circuit 108, anoutput smoothing capacitor 105, aclamp diode 194, and aclamp capacitor 110. Theflyback converter 100 further includes anactive clamp switch 193. Theactive clamp switch 193 is coupled across theclamp diode 194 to provide a path for reverse current in the primary winding PRI of thetransformer 102. Theinductance 192 represents leakage inductance reflected to the primary winding PRI. The active clamp flyback converter 100 recirculates energy stored in theleakage inductance 192. However, it suffers added cost and complexity of driving theactive clamp switch 193, which is activated by an activeclamp control circuit 111. The reverse current of the primary winding PRI recirculates the energy stored inparasitic capacitance 109 back to theinput voltage source 101 before theprimary switch 103 turns on. - Other types of converters use an auxiliary winding to generate the reverse current. An example of such a
converter 180 is depicted inFIG. 2 Theconverter 180 includes all elements of theconverter 100 ofFIG. 1 , with the exception of theclamp diode 194,clamp capacitor 110,active clamp switch 193. and activeclamp control circuit 111. Instead, theflyback transformer 102 of theconverter 180 further comprises an auxiliary winding AUX coupled in series with aclamp capacitor 107 and anactive clamp switch 106, the active clamp switch activated by acontrol circuit 111 a. The reverse current is developed in the auxiliary winding AUX by means of coupling it across theclamp capacitor 107 via theactive clamp switch 106 for a brief period. Once theactive clamp switch 106 turns off, the resulting negative magnetic flux induces reverse current in the primary winding PRI, recirculating the energy stored in theparasitic capacitance 109 back to theinput voltage source 101. Theconverter 180 does not recirculate the leakage inductance energy, and it must be absorbed by some other means. However, the solution offers a lower overall cost -
FIG. 3 illustrates the operating principle of the converters ofFIGS. 1 and 2 with theactive clamp switches primary switch 103. Thewaveform 301 represents the voltage across theprimary switch 103. Thewaveforms primary switch 103 and thesynchronous rectifier device 104, respectively. The conductive state of thesynchronous rectifier device 104 may be followed by post-conduction oscillation of the voltage across theprimary switch 103 illustrated by thewaveform 301. The oscillation period is determined primarily by the inductance of the primary winding PRI and theparasitic capacitance 109. Thewaveform 304 represents the ZVT Pulse activating theactive clamp switches waveform 302 represents the Dead Time allowing for discharging of theparasitic capacitance 109. - Although the
synchronous rectifier device 104 can also be utilized to allow for the reverse magnetic flux in thetransformer 102, thus eliminating the need for an extra active clamp switch and an auxiliary winding and reducing the cost of the overall solution, driving thesynchronous rectifier device 104 introduces excessive gate drive losses having an adverse effect on the converter efficiency. Therefore, a control method is needed to reduce thesynchronous rectifier device 104 gate drive power losses when thesynchronous rectifier device 104 is used for this dual purpose. Separately, an appropriate control algorithm is needed for generation of the ZVT Pulse for driving thesynchronous rectifier device 104 when thesynchronous rectifier device 104 is used for this dual purpose. - According to an aspect of one or more examples, there is provided a flyback converter to receive an input voltage and provide an output voltage. The flyback converter may include a transformer having a primary winding and secondary winding, a primary switch coupled to the primary winding, a synchronous rectifier device coupled to the secondary winding, and a secondary side control circuit to turn on the synchronous rectifier device by outputting a control signal at a first amplitude, subsequently modify the control signal to maintain substantially constant voltage across the synchronous rectifier device until a predicted time that precedes a current in the synchronous rectifier device reaching zero, subsequently turn off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero, and subsequently turn on the synchronous rectifier device by outputting the control signal at a second amplitude, before the primary switch is turned on. The second amplitude may be less than the first amplitude.
- The secondary side control circuit may include a synchronous rectifier control circuit that may predict the predicted time that precedes a time at which the current in the synchronous rectifier device reaches substantially zero. The synchronous rectifier control circuit may have a transconductance error amplifier, and the synchronous rectifier control circuit may store a voltage level at an output of the transconductance error amplifier sampled at the predicted time. The second amplitude may substantially equal the stored voltage level at the predicted time.
- The synchronous rectifier control circuit may predict the predicted time that precedes the time at which the current in the synchronous rectifier device reaches substantially zero by integrating a difference between the voltage across the synchronous rectifier device and the output voltage.
- The synchronous rectifier control circuit may predict the predicted time that precedes the time at which the current in the synchronous rectifier device reaches substantially zero by integrating the voltage across the secondary winding.
- The secondary side control circuit may turn on the synchronous rectifier device by outputting the control signal at the first amplitude in response to detecting that the voltage across the synchronous rectifier device is negative, and may reduce the control signal from the first amplitude as the current in the synchronous rectifier device decreases.
- The secondary side control circuit may hold the control signal at a substantially constant level after the predicted time, before turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero.
- The voltage across the synchronous rectifier device may enter oscillation when the synchronous rectifier device is turned off. The secondary side control circuit may turn on the synchronous rectifier device at the last valley of the oscillation of the voltage across the synchronous rectifier device before the primary switch is turned on.
- The secondary side control circuit may include a pulse generator circuit that may detect a period of the oscillation of the voltage across the synchronous rectifier device. The secondary side control circuit may turn on the synchronous rectifier device before the primary switch is turned on for a duration of time based on the detected period of oscillation of the voltage across the synchronous rectifier device.
- The flyback converter may also include a primary switch control circuit that may turn on the primary switch after a dead time delay following the turn off of the synchronous rectifier device.
- According to an aspect of one or more examples, there is provided a method of controlling a flyback converter that includes a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, and a synchronous rectifier device coupled to the secondary winding. The method may include outputting a control signal at a first amplitude to turn on the synchronous rectifier device, subsequently modifying the control signal to maintain substantially constant voltage across the synchronous rectifier device until a predicted time that precedes a current in the synchronous rectifier device reaching substantially zero, subsequently turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero, subsequently turning on the synchronous rectifier device by outputting the control signal at a second amplitude, before the primary switch is turned on. The second amplitude may be less than the first amplitude.
- The method may also include predicting a predicted time that precedes a time at which a current in the synchronous rectifier device reaches substantially zero. The method may also include storing a voltage level of the output of a transconductance error amplifier at the predicted time. The output of the transconductance error amplifier may be based on a difference between the voltage across the synchronous rectifier device and a reference voltage. The second amplitude may substantially equal the stored voltage level at the predicted time.
- Predicting the predicted time may include integrating a difference between the voltage across the synchronous rectifier device and an output voltage across the secondary winding.
- Predicting the predicted time may include integrating a voltage across the secondary winding.
- The outputting of the control signal at the first amplitude to turn on the synchronous rectifier device may occur in response to detecting the voltage across the synchronous rectifier device is negative.
- The method may include, after the outputting of the control signal at the first amplitude to turn on the synchronous rectifier device, reducing the control signal from the first amplitude as the current in the synchronous rectifier device decreases.
- The method may include, at the predicted time, holding the control signal at a substantially constant level, before turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero.
- The voltage across the synchronous rectifier device may enter oscillation when the synchronous rectifier device is turned off, and the subsequent turning off of the synchronous rectifier device may occur at the last valley of the oscillation of the voltage across the synchronous rectifier device before the primary switch is turned on.
- The method may include detecting a period of the oscillation of the voltage across the synchronous rectifier device. The subsequent turning on of the synchronous rectifier device may be for a duration based on the detected period of oscillation of the voltage across the synchronous rectifier device.
- The method may include turning on the primary switch after a dead time delay following the turning off of the synchronous rectifier device.
- According to an aspect of one or more examples, there is provided a method of generating an auxiliary pulse signal for controlling a synchronous rectifier device coupled to a secondary winding of a transformer in a flyback converter. The method may include outputting a control signal at a first amplitude, reducing the control signal from the first amplitude as the current in the synchronous rectifier device decreases, predicting a predicted time that precedes a time at which the current in the synchronous rectifier device reaches substantially zero, storing a voltage level of the output of a transconductance amplifier at the predicted time, wherein the output of the transconductance error amplifier is based on a difference between the voltage across the synchronous rectifier device and a reference voltage. The method may also include generating the auxiliary pulse signal so as to output the control signal to turn on the synchronous rectifier device before the primary switch is turned on, the control signal responsive to the auxiliary pulse signal at an amplitude substantially equal to the stored voltage level of the output of the transconductance error amplifier at the predicted time.
- According to an aspect of one or more examples, there is provided a method of generating an auxiliary pulse signal for controlling a synchronous rectifier device coupled to a secondary winding of a transformer in a flyback converter. The method may include detecting a period of oscillation of a voltage across the synchronous rectifier device, detecting a peak voltage across the synchronous rectifier device, and generating the auxiliary pulse signal having a pulse width determined based on the detected period of oscillation of the voltage across the synchronous the rectifier device, and a difference between the peak voltage across the synchronous rectifier device and an output voltage of the flyback converter.
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FIG. 1 shows an active clamp flyback converter according to the prior art. -
FIG. 2 shows a flyback converter having an auxiliary winding according to the prior art. -
FIG. 3 shows a waveform diagram illustrating the operation of the flyback converters ofFIGS. 1 and 2 . -
FIG. 4 shows a circuit diagram of a flyback converter according to various examples of the present disclosure. -
FIG. 5 shows a waveform diagram illustrating the operation of the flyback converter shown inFIG. 4 . -
FIG. 6 shows a waveform diagram illustration the operation of a pulse generator circuit according to various examples of the present disclosure. -
FIG. 7 shows a circuit diagram of a pulse generator circuit according to various examples of the present disclosure. -
FIG. 8 shows a circuit diagram of a synchronous rectifier control circuit according to various examples of the present disclosure. -
FIG. 9 shows a circuit diagram of a zero current prediction circuit according to various examples of the present disclosure. - Reference will now be made in detail to the following various examples, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The following examples may be embodied in various forms without being limited to the examples set forth herein. Descriptions of well-known parts are omitted for clarity.
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FIG. 4 is a circuit schematic of aflyback converter 400 in accordance with various examples of the present disclosure. Theexample flyback converter 400 receives input voltage VIN from aninput voltage source 101 and delivers galvanically isolated output voltage VO to aload 200. Theflyback converter 400 includes: atransformer 102 having a primary winding PRI and a secondary winding SEC; aprimary switch 103; a primaryswitch control circuit 112; asynchronous rectifier device 104 coupled to the secondary winding SEC; a secondaryside control circuit 199, which may include a synchronousrectifier control circuit 117 and apulse generator circuit 116; and anoutput smoothing capacitor 105. Theconverter 400 also includes effectiveparasitic capacitance 109.FIG. 4 depicts thecapacitance 109 reflected to theprimary switch 103, while it needs to be understood as total parasitic capacitance distributed across all elements of theflyback converter 400 and its physical construction. - The primary
switch control circuit 112 activates theprimary switch 103 repetitively to couple the primary winding PRI to theinput voltage source 101 for receiving electrical energy from theinput voltage source 101 and storing it in thetransformer 102. The secondaryside control circuit 199 drives thesynchronous rectifier device 104. According to one or more examples, the secondaryside control circuit 199 may include thepulse generator circuit 116 that generates an auxiliary pulse signal in accordance with the output voltage VO and the voltage VD across thesynchronous rectifier device 104. The secondaryside control circuit 199 may also include the synchronousrectifier control circuit 117 that controls thesynchronous rectifier device 104 in accordance with the voltage VD across thesynchronous rectifier device 104 and the auxiliary pulse signal received from thepulse generator circuit 116. The synchronousrectifier control circuit 117 may also control thesynchronous rectifier device 104 based on the output voltage VO, as represented by the dotted line inFIG. 4 connecting the output voltage VO to the synchronousrectifier control circuit 117. - The operating principle of the
flyback converter 400 is illustrated byFIG. 5 . Referring toFIGS. 4 and 5 , thewaveform 301 represents the voltage across theprimary switch 103. Thewaveform 311 represents the voltage VD across thesynchronous rectifier device 104, whereas its exploded portion in the vicinity of the common return voltage is shown by thewaveform 311 a. Thewaveform 399 represents the current in thesynchronous rectifier device 104, which substantially equals the current in the secondary winding SEC of thetransformer 102. Thewaveform 302 shows the primary control signal to theprimary switch 103 generated by the primaryswitch control circuit 112, whereas thewaveform 312 represents the control voltage to thesynchronous rectifier device 104 generated by the synchronousrectifier control circuit 117. - As illustrated by the
waveform 311 a, following the turn-off of theprimary switch 103, voltage VD across thesynchronous rectifier device 104 becomes negative. The synchronousrectifier control circuit 117 detects this negative voltage VD and switches thesynchronous rectifier device 104 fully on as illustrated by thewaveform 312. Upon the turn-on of thesynchronous rectifier device 104, the voltage VD across it is determined by the on resistance of thesynchronous rectifier device 104. As the current in secondary winding SEC decreases, as shown bywaveform 399, the corresponding voltage VD across thesynchronous rectifier device 104 decreases proportionally until it reaches a level designated as Plateau in thewaveform 311 a. The synchronousrectifier control circuit 117 maintains this Plateau level of voltage VD across thesynchronous rectifier device 104 by reducing the control voltage to thesynchronous rectifier device 104 as shown bywaveform 312 so as to increase the on resistance of thesynchronous rectifier device 104 as the current through the synchronous rectifier device 104 (shown as waveform 399), i.e. the current through secondary winding SEC, falls towards zero. The synchronousrectifier control circuit 117 further predicts a predicted time that precedes the current in thesynchronous rectifier device 104 reaching substantially zero by, for example, integrating the difference between voltage VD across thesynchronous rectifier device 104 and the output voltage VO. The synchronousrectifier control circuit 117 may alternatively predict a predicted time that precedes the current in thesynchronous rectifier device 104 reaching substantially zero by integrating the voltage across the secondary winding SEC, i.e. VO - VD. When this predicted time, designated on thewaveform 312 as ZCP, is reached, the synchronousrectifier control circuit 117 changes its output to a high impedance, thus no longer driving the control voltage to thesynchronous rectifier device 104 as shown bywaveform 312. When the synchronousrectifier control circuit 117 changes its output to a high impedance, there is no discharge path for the gate of thesynchronous rectifier device 104, so the control voltage to thesynchronous rectifier device 104, shown bywaveform 312, remains at a substantially constant level. This substantially constant voltage level of the gate of thesynchronous rectifier device 104 dictates a substantially constant on resistance of thesynchronous rectifier device 104. Accordingly, the voltage VD across thesynchronous rectifier device 104 falls out of the regulated Plateau level and begins approaching zero, while its magnitude is now dictated by the product of the substantially constant on resistance of thesynchronous rectifier device 104 held from ZCP and the current in thesynchronous rectifier device 104. When the voltage VD across thesynchronous rectifier device 104 reaches substantially zero level, designated as Common in thewaveform 311 a, the synchronousrectifier control circuit 117 turns thesynchronous rectifier device 104 off by driving the control voltage to thesynchronous rectifier device 104 as shown bywaveform 312 to substantially zero voltage. The level of the control voltage to thesynchronous rectifier device 104 as shown bywaveform 312 to thesynchronous rectifier device 104 is sampled at ZCP, and is stored to subsequently set the amplitude of the control signal based on an auxiliary pulse signal, having pulse width tNEG, as illustrated by thewaveform 312. - The auxiliary pulse signal, having pulse width tNEG, may be generated by the
pulse generator circuit 116 at the last peak of oscillation of thewaveform 301, i.e. the last peak of oscillation of the voltage across theprimary switch 103, or the last valley of oscillation of thewaveform 311, i.e. the last valley of oscillation of the VD across thesynchronous rectifier device 104, that precedes the next turn on of theprimary switch 103, and further propagated by the synchronousrectifier control circuit 117 as the control signal to thesynchronous rectifier device 104 at the stored amplitude. By reducing the amplitude of the control signal output by the synchronousrectifier control circuit 117, as compared to the amplitude of the control signal that initially switches thesynchronous rectifier device 104 fully on as illustrated by thewaveform 312, losses in the synchronousrectifier control circuit 117 may be reduced. The auxiliary pulse signal, having pulse width tNEG, may reduce switching losses in thesynchronous rectifier device 104, by activating thesynchronous rectifier device 104 in the last valley of oscillation of the voltage VD across thesynchronous rectifier device 104 that precedes the next turn on of theprimary switch 103. - The principle of operation of the
pulse generator circuit 116 according to various examples is illustrated byFIG. 6 . Thewaveform 311 represents the voltage VD across thesynchronous rectifier device 104, referenced to the output voltage level VO. The pulse width of thewaveform 322 represents the half-cycle of the oscillation of the voltage VD across thesynchronous rectifier device 104, which is measured by thepulse generator circuit 116. Thewaveform 323 is the auxiliary pulse signal having pulse width tNEG generated by thepulse generator circuit 116. - The
parasitic capacitance 109 may be non-linear since it includes the output capacitance of theprimary switch 103, which increases substantially at a lower voltage across it. Therefore, the energy stored in theparasitic capacitance 109 is greater by a factor of ker>1 as compared to one calculated as CV2/2. Thepulse generator circuit 116 according to various examples monitors the voltage VD across thesynchronous rectifier device 104 and the output voltage VO, and may generate a pulse width tNEG of the auxiliary pulse signal based on the following equation: -
- where VD(PK) is a sampled peak voltage at the
synchronous rectifier device 104, and T/2 is the half-cycle of the oscillation of the voltage VD across thesynchronous rectifier device 104 detected by thepulse generator circuit 116. - When generated in accordance with the above equation under the condition of ker(VD(PK)-VO)2/VO 2>>1, the auxiliary pulse signal may result in a reverse magnetic flux in the
transformer 102 that discharges theparasitic capacitance 109 to substantially zero, and may reduce switching power losses. Thepulse generator circuit 116, therefore, may generate the auxiliary pulse signal having a pulse width tNEG that is adaptive to the levels of the voltage VD across thesynchronous rectifier device 104 and the output voltage VO, as well as theparasitic capacitance 109 and inductance of thetransformer 102. - The primary
switch control circuit 112 provides a delay between the trailing edge of the control voltage, generated responsive to auxiliary pulse signal, to thesynchronous rectifier device 104, as shown bywaveform 312, and the leading edge of the primary control signal, as shown bywaveform 302 ofFIG. 5 , designated as Dead Time inFIGS. 5 and 6 . As one skilled in the art would understand, the primaryswitch control circuit 112 may be coupled to receive an indication of the control signal for thesynchronous rectifier device 104 via magnetic, capacitive, or optical devices. The Dead Time delay may be a predetermined delay, and may allow for discharging theparasitic capacitance 109 to substantially zero. According to various examples, the Dead Time delay may be adaptively calculated as a function of the sampled period of oscillation T of the voltage VD across thesynchronous rectifier device 104, as shown inwaveform 322, which sampling may be done by the synchronousrectifier control circuit 117. For example, the Dead Time delay may be programmed to be T/4 from when the voltage VD across thesynchronous rectifier device 104 exceeds the output voltage VO. - A
pulse generator circuit 116 according to various examples is depicted inFIG. 7 . Referring toFIGS. 4 and 7 , thepulse generator circuit 116 repetitively generates an auxiliary pulse signal based on the voltage VD across thesynchronous rectifier device 104, and the output voltage VO. Thepulse generator circuit 116 may include a leading-edge blanking circuit 401, apeak detector 402, asubtractor circuit 405, acomparator 403, and a pulse width modulation (PWM) circuit 406. Thepeak detector 402 samples the peak voltage at the synchronous rectifier device 104 VD(PK) after a blanking delay generated by the leading-edge blanking circuit 401. Thesubtractor 405 further subtracts the output voltage VO from the sampled peak voltage VD(PK). Thecomparator 403 compares the voltage VD across thesynchronous rectifier device 104 with the output voltage VO and outputs a pulse width equal to a half-cycle T/2 of the oscillation of the voltage VD across thesynchronous rectifier device 104 responsive to the voltage VD across thesynchronous rectifier device 104 exceeding the output voltage VO. The PWM circuit 406 generates the auxiliary pulse signal having a pulse width tNEG proportional to: -
- A synchronous
rectifier control circuit 117 according to various examples is shown inFIG. 8 . The synchronousrectifier control circuit 117 depicted inFIG. 8 generates a control signal SR_Ctrl for driving thesynchronous rectifier device 104 by monitoring the voltage VD across thesynchronous rectifier device 104. The synchronousrectifier control circuit 117 may also monitor the output voltage VO, and also propagates the auxiliary pulse signal having pulse width tNEG received from thepulse generator circuit 116 to its output, as the control signal SR_Ctrl, at a controlled amplitude. The synchronousrectifier control circuit 117 includes: afirst comparator 504 having a non-inverting terminal configured to receive a first reference threshold -VTH1 and an inverting terminal configured to receive the voltage VD across thesynchronous rectifier device 104, asecond comparator 505 having an inverting terminal configured to receive a second reference threshold -VTH2 and a non-inverting terminal configured to receive the voltage VD across thesynchronous rectifier device 104, atransconductance error amplifier 501 having a non-inverting terminal configured to receive a reference voltage -VREF, an inverting terminal configured to receive the voltage VD across thesynchronous rectifier device 104, and a tri-state control input HI-Z, a zerocurrent prediction circuit 509, afrequency compensator circuit 502, a voltage buffer 503, alatch circuit 506, an OR gate 507, and anoutput buffer 508. The magnitudes of the thresholds -VTH1, -VTH2 and the reference voltage -VTH2 are selected to fulfil the condition VTH1>VREF>VTH2. - In operation, the
first comparator 504 detects negative voltage VD across thesynchronous rectifier device 104 falling below the first threshold -VTH1 and sets thelatch circuit 506.Transconductance amplifier 501 receives voltage VD across thesynchronous rectifier device 104 at its inverting input, a reference voltage -VREF at its non-inverting input, and outputs an amplified error voltage as a function of the difference between VD and -VREF. According to an example, thefrequency compensator circuit 502 may be an RC network having an impedance Z(s). While the negative voltage drop across thesynchronous rectifier device 104 is significantly greater than -VREF, the output voltage of thetransconductance amplifier 104 takes the highest magnitude, as dictated by the output voltage range of thetransconductance amplifier 104. The output of thelatch circuit 506 then propagates via the gate 507 and theoutput buffer 508 at the highest output magnitude of thetransconductance error amplifier 501, as buffered by voltage buffer 503. The magnitude of the voltage VD across thesynchronous rectifier device 104 begins falling until it reaches substantially the reference level -VREF. When the magnitude of the voltage VD across thesynchronous rectifier device 104 reaches substantially the reference level -VREF, the voltage at the output of thetransconductance error amplifier 501 decreases. The decreasing voltage at the output of thetransconductance error amplifier 501, which is buffered by voltage buffer 503, reduces the magnitude of the control signal SR_Ctrl to maintain a substantially constant voltage VD across thesynchronous rectifier device 104. As the energy stored in thetransformer 102 is gradually depleted, the zerocurrent prediction circuit 509 seeks to predict a predicted time that precedes the time at which the current in thesynchronous rectifier device 104 reaches zero. - When this predicted time is reached, the zero
current prediction circuit 509 outputs a signal to the high-impedance state input of theerror amplifier 501, placing the output oftransconductance error amplifier 501 into a high impedance state. Thefrequency compensator circuit 502 stores the voltage at the output of thetransconductance error amplifier 501 at a substantially constant level, i.e. substantially at the voltage level appearing at the output of thetransconductance error amplifier 501 when the predicted time is reached. Since the voltage VD across thesynchronous rectifier device 104 is no longer regulated, it begins falling. Thesecond comparator 505 detects the voltage VD across the synchronous rectifier device reaching the second threshold -VTH2 and resets thelatch circuit 506, terminating the control signal SR_Ctrl through OR gate 507. - When the synchronous
rectifier control circuit 117 receives the auxiliary pulse signal having a pulse width tNEG, it propagates the auxiliary pulse signal to the control signal SR_Ctrl output via the OR gate 507 and theoutput buffer 508 at the magnitude of the voltage VD across thesynchronous rectifier device 104 held by thefrequency compensator circuit 502 and buffered by the voltage buffer 503. -
FIG. 9 depicts a zerocurrent prediction circuit 509 according to various examples. The zerocurrent prediction circuit 509 depicted inFIG. 9 , by monitoring the output voltage VO and the voltage VD across thesynchronous rectifier device 104, generates a HI-Z command for putting theerror amplifier 501 ofFIG. 8 into a high-impedance output state. The zerocurrent prediction circuit 509 ofFIG. 9 includes: asubtractor 601; anintegrator 602 having a reset input; afirst comparator 603 with a first threshold voltage VTH3; and alatch 605. Theintegrator 602 integrates over time the difference between the voltage VD across thesynchronous rectifier device 104 and the output voltage VO derived by thesubtraction node 601. The output of theintegrator 602 is monitored by thefirst comparator 603 and compared to the first reference voltage VTH3 to predict demagnetization of thetransformer 102. Thefirst comparator 603 sets thelatch 605 when the output of theintegrator 602 reaches the first threshold VTH3. Thelatch 605 can be reset at any arbitrary moment following the auxiliary pulse signal. For clarity, the zerocurrent prediction circuit 509 ofFIG. 9 shows asecond comparator 604 with a second threshold voltage -VTH4. Thesecond comparator 604 detects the voltage VD across thesynchronous rectifier device 104 falling below the second reference voltage -VTH4 and resets thelatch 605, terminating the HI-Z command. - Various examples have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious to literally describe and illustrate every combination and subcombination of these examples. Accordingly, all examples can be combined in any way and/or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the examples described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.
- It will be appreciated by persons skilled in the art that the examples described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings.
Claims (25)
1. A flyback converter to receive an input voltage and provide an output voltage, the flyback converter comprising:
a transformer having a primary winding and secondary winding;
a primary switch coupled to the primary winding;
a synchronous rectifier device coupled to the secondary winding; and
a secondary side control circuit to:
turn on the synchronous rectifier device by outputting a control signal at a first amplitude,
subsequently modify the control signal to maintain a voltage across the synchronous rectifier device substantially constant until a predicted time that precedes a current in the synchronous rectifier device reaching substantially zero,
subsequently turn off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero, and
subsequently turn on the synchronous rectifier device by outputting the control signal at a second amplitude, before the primary switch is turned on;
wherein the second amplitude is less than the first amplitude.
2. The flyback converter of claim 1 , wherein the secondary side control circuit includes a synchronous rectifier control circuit to predict the predicted time that precedes the current in the synchronous rectifier device reaching substantially zero.
3. The flyback converter of claim 1 , wherein the secondary side control circuit includes a synchronous rectifier control circuit having a transconductance error amplifier, wherein the synchronous rectifier control circuit is to store a voltage level at an output of the transconductance error amplifier at the predicted time; and
wherein the second amplitude substantially equals the stored voltage level at the predicted time.
4. The flyback converter of claim 2 , wherein the secondary side control circuit predicts the predicted time by integration of a difference between the voltage across the synchronous rectifier device and the output voltage.
5. The flyback converter of claim 2 , wherein the secondary side control circuit predicts the predicted time is determined by integration of a voltage across the secondary winding.
6. The flyback converter of claim 1 , wherein the secondary side control circuit to turn on the synchronous rectifier device by outputting the control signal at the first amplitude in response to detection that the voltage across the synchronous rectifier device is negative.
7. The flyback converter of claim 1 , wherein the secondary side control circuit to reduce the control signal from the first amplitude as the current in the synchronous rectifier device decreases.
8. The flyback converter of claim 1 , wherein the secondary side control circuit to hold the control signal at a substantially constant level after the predicted time, before turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero.
9. The flyback converter of claim 1 , wherein the voltage across the synchronous rectifier device enters oscillation when the synchronous rectifier device is turned off.
10. The flyback converter of claim 9 , wherein the secondary side control circuit to turn on the synchronous rectifier device at the last valley of the oscillation of the voltage across the synchronous rectifier device before the primary switch is turned on.
11. The flyback converter of claim 9 , wherein the secondary side control circuit includes a pulse generator circuit to detect a period of the oscillation of the voltage across the synchronous rectifier device, and
wherein the secondary side control circuit to turn on the synchronous rectifier device before the primary switch is turned on for a duration of time based on the detected period of oscillation of the voltage across the synchronous rectifier device.
12. The flyback converter of claim 8 , further comprising a primary switch control circuit to turn on the primary switch after a dead time delay following the turn off of the synchronous rectifier device.
13. A method of controlling a flyback converter that includes a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, and a synchronous rectifier device coupled to the secondary winding, the method comprising:
outputting a control signal at a first amplitude to turn on the synchronous rectifier device;
subsequently modifying the control signal to maintain a voltage across the synchronous rectifier device substantially constant until a predicted time that precedes a current in the synchronous rectifier device reaching substantially zero;
subsequently turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero;
subsequently turning on the synchronous rectifier device by outputting the control signal at a second amplitude, before the primary switch is turned on, wherein the second amplitude is less than the first amplitude.
14. The method of claim 13 , further comprising:
predicting the predicted time that precedes the current in the synchronous rectifier device reaching substantially zero.
15. The method of claim 13 , further comprising:
storing a voltage level of the output of a transconductance error amplifier at the predicted time, wherein the output of the transconductance error amplifier is based on a difference between the voltage across the synchronous rectifier device and a reference voltage;
wherein the second amplitude substantially equals the stored voltage level at the predicted time.
16. The method of claim 14 , wherein the predicting the predicted time comprises integrating a difference between the voltage across the synchronous rectifier device and an output voltage across the secondary winding.
17. The method of claim 14 , wherein the predicting the predicted time comprises integrating a voltage across the secondary winding.
18. The method of claim 13 , wherein said outputting the control signal at the first amplitude to turn on the synchronous rectifier device occurs in response to detecting that the voltage across the synchronous rectifier device is negative.
19. The method of claim 13 , comprising:
after the outputting of the control signal at the first amplitude to turn on the synchronous rectifier device, reducing the control signal from the first amplitude as the current in the synchronous rectifier device decreases.
20. The method of claim 13 , comprising, after the predicted time, holding the control signal at a substantially constant level, before turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero.
21. The method of claim 13 , wherein the voltage across the synchronous rectifier device enters oscillation when the synchronous rectifier device is turned off; and
wherein said subsequent turning off of the synchronous rectifier device occurs at the last valley of the oscillation of the voltage across the synchronous rectifier device before the primary switch is turned on.
22. The method of claim 21 , comprising detecting a period of the oscillation of the voltage across the synchronous rectifier device;
wherein said subsequent turning on of the synchronous rectifier device is for a duration based on the detected period of oscillation of the voltage across the synchronous rectifier device.
23. The method of claim 13 , comprising turning on the primary switch after a dead time delay following the turning off of the synchronous rectifier device.
24. A method of generating an auxiliary pulse signal for controlling a synchronous rectifier device coupled to a secondary winding of a transformer in a flyback converter, the method comprising:
outputting a control signal at a first amplitude;
reducing the control signal from the first amplitude as a current in the synchronous rectifier device decreases;
predicting a predicted time that precedes a time at which the current in the synchronous rectifier device reaches substantially zero;
storing a voltage level of the output of an error amplifier at the predicted time, wherein the output of the error amplifier is based on a difference between the voltage across the synchronous rectifier device and a reference voltage; and
generating an auxiliary pulse signal so as to output the control signal to turn on the synchronous rectifier device after the voltage across the synchronous rectifier device reaches substantially zero and before the primary switch is turned on, the control signal responsive to the auxiliary pulse signal and at an amplitude substantially equal to the stored voltage level of the output of the error amplifier at the predicted time.
25. A method of generating an auxiliary pulse signal for controlling a synchronous rectifier device coupled to a secondary winding of a transformer in a flyback converter, the method comprising:
detecting a period of oscillation of a voltage across the synchronous rectifier device;
detecting a peak voltage across the synchronous rectifier device; and
generating the auxiliary pulse signal having a pulse width determined based on the detected period of oscillation of the voltage across the synchronous the rectifier device, and a difference between the peak voltage across the synchronous rectifier device and an output voltage of the flyback converter.
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Citations (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5719755A (en) * | 1995-12-11 | 1998-02-17 | Sanken Electric Co., Ltd. | Dc to dc converter |
US20060013022A1 (en) * | 2002-04-12 | 2006-01-19 | Jitaru Ionel D | High efficiency flyback converter |
US20070121349A1 (en) * | 2005-11-28 | 2007-05-31 | Alexander Mednik | Transformer-isolated flyback converters and methods for regulating output current thereof |
US20090257250A1 (en) * | 2008-04-15 | 2009-10-15 | Green Mark Technology Inc. | Synchronous rectifier dc/dc converters using a controlled-coupling sense winding |
US20100027298A1 (en) * | 2008-07-31 | 2010-02-04 | Texas Instruments Incorporated | System and method for synchronous rectifier drive that enables converters to operate in transition and discontinuous mode |
US20100110732A1 (en) * | 2008-11-03 | 2010-05-06 | Moyer James C | Tail current control of isolated converter and apparatus thereof |
US8358090B1 (en) * | 2010-03-15 | 2013-01-22 | Supertex, Inc. | Dimmer circuit for transformer—isolated LED driver and method therefor |
US20130272036A1 (en) * | 2012-04-12 | 2013-10-17 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods for regulating power conversion systems with output detection and synchronized rectifying mechanisms |
US20140112030A1 (en) * | 2012-10-24 | 2014-04-24 | Infineon Technologies Ag | Method and a controller for determining a demagnetization zero current time for a switched mode power supply |
US20140218976A1 (en) * | 2012-04-12 | 2014-08-07 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods for regulating power conversion systems with output detection and synchronized rectifying mechanisms |
US20150280573A1 (en) * | 2014-04-01 | 2015-10-01 | Infineon Technologies Austria Ag | System and Method for a Switched-Mode Power Supply |
US20150280584A1 (en) * | 2014-04-01 | 2015-10-01 | Infineon Technologies Austria Ag | System and Method for a Switched-Mode Power Supply |
US20160111961A1 (en) * | 2014-10-21 | 2016-04-21 | Power Integrations, Inc. | Output-side controller with switching request at relaxation ring extremum |
US20160141961A1 (en) * | 2014-11-14 | 2016-05-19 | Power Integrations, Inc. | Power converter controller with stability compensation |
US20160182131A1 (en) * | 2014-12-23 | 2016-06-23 | Microchip Technology Incorporated | Communication Method and Apparatus using Modulation of Post-Conduction Oscillation Frequency in Switching Converters |
US20160233779A1 (en) * | 2015-02-06 | 2016-08-11 | Texas Instruments Incorporated | Soft switching flyback converter |
US20170317598A1 (en) * | 2016-04-29 | 2017-11-02 | Semiconductor Components Industries, Llc | Current sense detection for synchronous rectification |
US20170353099A1 (en) * | 2016-06-01 | 2017-12-07 | Silergy Semiconductor Technology (Hangzhou) Ltd | Secondary-side control circuit, control method and flyback converter thereof |
US9899931B1 (en) * | 2016-10-25 | 2018-02-20 | Alpha And Omega Semiconductor Incorporated | Zero voltage switching flyback converter for primary switch turn-off transitions |
US9935559B2 (en) * | 2016-08-25 | 2018-04-03 | Dialog Semiconductors Inc. | Efficient power supply voltage regulation for synchronous rectifier controller |
US20180115252A1 (en) * | 2016-10-25 | 2018-04-26 | Alpha And Omega Semiconductor Incorporated | Forced zero voltage switching flyback converter |
US9991811B1 (en) * | 2016-12-06 | 2018-06-05 | Delta Electronics (Shanghai) Co., Ltd. | Control method and control apparatus for flyback circuit |
US20180294735A1 (en) * | 2017-04-10 | 2018-10-11 | Delta Electronics (Shanghai) Co., Ltd | Control device and control method |
US20190123655A1 (en) * | 2017-10-25 | 2019-04-25 | Fujitsu Limited | Switching power supply device and synchronous rectifier circuit |
US20190149032A1 (en) * | 2017-11-10 | 2019-05-16 | Richtek Technology Corporation | Zvs control circuit for use in a flyback power converter |
US20190222131A1 (en) * | 2018-01-16 | 2019-07-18 | Texas Instruments Incorporated | Methods and apparatus for zero voltage switching using flyback converters |
US20200036293A1 (en) * | 2018-07-30 | 2020-01-30 | Texas Instruments Incorporated | Methods and apparatus for adaptive synchronous rectifier control |
US20200153327A1 (en) * | 2018-11-08 | 2020-05-14 | Richtek Technology Corporation | Flyback power converter and zvs control circuit and control method thereof |
US20200280263A1 (en) * | 2019-02-28 | 2020-09-03 | Richtek Technology Corporation | Flyback power converter and zvs control circuit and control method thereof |
US20210119526A1 (en) * | 2019-10-22 | 2021-04-22 | Semiconductor Components Industries, Llc | Partial zero voltage switching (zvs) for flyback power converter and method therefor |
US11177740B1 (en) * | 2020-09-01 | 2021-11-16 | Asian Power Devices Inc. | Power conversion apparatus with oscillation reduction control, oscillation reduction control module, and method of operating the same |
US20220200466A1 (en) * | 2020-12-17 | 2022-06-23 | Shanghai Bright Power Semiconductor Co., Ltd. | Isolated power supply control circuits, isolated power supply and control method thereof |
US20220200453A1 (en) * | 2020-12-23 | 2022-06-23 | Microchip Technology Incorporated | DC-DC Converter With Improved Line Transient Rejection |
US20220209676A1 (en) * | 2020-12-31 | 2022-06-30 | Chengdu Monolithic Power Systems Co., Ltd. | Isolated switching converter with secondary side modulation and control method thereof |
US20220271676A1 (en) * | 2021-02-25 | 2022-08-25 | Richtek Technology Corporation | Half-bridge flyback power converter and control method thereof |
US20230216421A1 (en) * | 2021-12-30 | 2023-07-06 | Ark Semiconductor Corp. Ltd. | Flyback converter providing accurate synchronous rectification and method of controlling the same |
-
2022
- 2022-02-04 US US17/665,272 patent/US20230155516A1/en active Pending
Patent Citations (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5719755A (en) * | 1995-12-11 | 1998-02-17 | Sanken Electric Co., Ltd. | Dc to dc converter |
US20060013022A1 (en) * | 2002-04-12 | 2006-01-19 | Jitaru Ionel D | High efficiency flyback converter |
US20070121349A1 (en) * | 2005-11-28 | 2007-05-31 | Alexander Mednik | Transformer-isolated flyback converters and methods for regulating output current thereof |
US20090257250A1 (en) * | 2008-04-15 | 2009-10-15 | Green Mark Technology Inc. | Synchronous rectifier dc/dc converters using a controlled-coupling sense winding |
US20100027298A1 (en) * | 2008-07-31 | 2010-02-04 | Texas Instruments Incorporated | System and method for synchronous rectifier drive that enables converters to operate in transition and discontinuous mode |
US20100110732A1 (en) * | 2008-11-03 | 2010-05-06 | Moyer James C | Tail current control of isolated converter and apparatus thereof |
US8358090B1 (en) * | 2010-03-15 | 2013-01-22 | Supertex, Inc. | Dimmer circuit for transformer—isolated LED driver and method therefor |
US20140218976A1 (en) * | 2012-04-12 | 2014-08-07 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods for regulating power conversion systems with output detection and synchronized rectifying mechanisms |
US20130272036A1 (en) * | 2012-04-12 | 2013-10-17 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods for regulating power conversion systems with output detection and synchronized rectifying mechanisms |
US20140112030A1 (en) * | 2012-10-24 | 2014-04-24 | Infineon Technologies Ag | Method and a controller for determining a demagnetization zero current time for a switched mode power supply |
US20150280573A1 (en) * | 2014-04-01 | 2015-10-01 | Infineon Technologies Austria Ag | System and Method for a Switched-Mode Power Supply |
US20150280584A1 (en) * | 2014-04-01 | 2015-10-01 | Infineon Technologies Austria Ag | System and Method for a Switched-Mode Power Supply |
US20160111961A1 (en) * | 2014-10-21 | 2016-04-21 | Power Integrations, Inc. | Output-side controller with switching request at relaxation ring extremum |
US20160141961A1 (en) * | 2014-11-14 | 2016-05-19 | Power Integrations, Inc. | Power converter controller with stability compensation |
US20160182131A1 (en) * | 2014-12-23 | 2016-06-23 | Microchip Technology Incorporated | Communication Method and Apparatus using Modulation of Post-Conduction Oscillation Frequency in Switching Converters |
US20160233779A1 (en) * | 2015-02-06 | 2016-08-11 | Texas Instruments Incorporated | Soft switching flyback converter |
US20170317598A1 (en) * | 2016-04-29 | 2017-11-02 | Semiconductor Components Industries, Llc | Current sense detection for synchronous rectification |
US20170353099A1 (en) * | 2016-06-01 | 2017-12-07 | Silergy Semiconductor Technology (Hangzhou) Ltd | Secondary-side control circuit, control method and flyback converter thereof |
US9935559B2 (en) * | 2016-08-25 | 2018-04-03 | Dialog Semiconductors Inc. | Efficient power supply voltage regulation for synchronous rectifier controller |
US9899931B1 (en) * | 2016-10-25 | 2018-02-20 | Alpha And Omega Semiconductor Incorporated | Zero voltage switching flyback converter for primary switch turn-off transitions |
US20180115252A1 (en) * | 2016-10-25 | 2018-04-26 | Alpha And Omega Semiconductor Incorporated | Forced zero voltage switching flyback converter |
US9991811B1 (en) * | 2016-12-06 | 2018-06-05 | Delta Electronics (Shanghai) Co., Ltd. | Control method and control apparatus for flyback circuit |
US20180294735A1 (en) * | 2017-04-10 | 2018-10-11 | Delta Electronics (Shanghai) Co., Ltd | Control device and control method |
US20190123655A1 (en) * | 2017-10-25 | 2019-04-25 | Fujitsu Limited | Switching power supply device and synchronous rectifier circuit |
US20190149032A1 (en) * | 2017-11-10 | 2019-05-16 | Richtek Technology Corporation | Zvs control circuit for use in a flyback power converter |
US20200153353A1 (en) * | 2018-01-16 | 2020-05-14 | Texas Instruments Incorporated | Methods and apparatus for zero voltage switching using flyback converters |
US20190222131A1 (en) * | 2018-01-16 | 2019-07-18 | Texas Instruments Incorporated | Methods and apparatus for zero voltage switching using flyback converters |
US20200036293A1 (en) * | 2018-07-30 | 2020-01-30 | Texas Instruments Incorporated | Methods and apparatus for adaptive synchronous rectifier control |
US20200153327A1 (en) * | 2018-11-08 | 2020-05-14 | Richtek Technology Corporation | Flyback power converter and zvs control circuit and control method thereof |
US20200280263A1 (en) * | 2019-02-28 | 2020-09-03 | Richtek Technology Corporation | Flyback power converter and zvs control circuit and control method thereof |
US20210119526A1 (en) * | 2019-10-22 | 2021-04-22 | Semiconductor Components Industries, Llc | Partial zero voltage switching (zvs) for flyback power converter and method therefor |
US11177740B1 (en) * | 2020-09-01 | 2021-11-16 | Asian Power Devices Inc. | Power conversion apparatus with oscillation reduction control, oscillation reduction control module, and method of operating the same |
US20220200466A1 (en) * | 2020-12-17 | 2022-06-23 | Shanghai Bright Power Semiconductor Co., Ltd. | Isolated power supply control circuits, isolated power supply and control method thereof |
US20240154537A1 (en) * | 2020-12-17 | 2024-05-09 | Shanghai Bright Power Semiconductor Co., Ltd | Control circuit for an isolated power supply |
US20220200453A1 (en) * | 2020-12-23 | 2022-06-23 | Microchip Technology Incorporated | DC-DC Converter With Improved Line Transient Rejection |
US20220209676A1 (en) * | 2020-12-31 | 2022-06-30 | Chengdu Monolithic Power Systems Co., Ltd. | Isolated switching converter with secondary side modulation and control method thereof |
US20220271676A1 (en) * | 2021-02-25 | 2022-08-25 | Richtek Technology Corporation | Half-bridge flyback power converter and control method thereof |
US20230216421A1 (en) * | 2021-12-30 | 2023-07-06 | Ark Semiconductor Corp. Ltd. | Flyback converter providing accurate synchronous rectification and method of controlling the same |
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