US20230084374A1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- US20230084374A1 US20230084374A1 US17/990,148 US202217990148A US2023084374A1 US 20230084374 A1 US20230084374 A1 US 20230084374A1 US 202217990148 A US202217990148 A US 202217990148A US 2023084374 A1 US2023084374 A1 US 2023084374A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims description 85
- 230000000903 blocking effect Effects 0.000 claims abstract description 138
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 230000000149 penetrating effect Effects 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 121
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 79
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 43
- 238000005530 etching Methods 0.000 claims description 41
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 27
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 19
- 229910052799 carbon Inorganic materials 0.000 claims description 19
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims description 8
- 150000004706 metal oxides Chemical class 0.000 claims description 8
- 238000009832 plasma treatment Methods 0.000 claims description 5
- 238000007669 thermal treatment Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 claims 43
- 239000002356 single layer Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 37
- 239000002184 metal Substances 0.000 description 37
- 239000003795 chemical substances by application Substances 0.000 description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 20
- 229920005591 polysilicon Polymers 0.000 description 19
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 18
- 229910052681 coesite Inorganic materials 0.000 description 18
- 229910052906 cristobalite Inorganic materials 0.000 description 18
- 239000000377 silicon dioxide Substances 0.000 description 18
- 229910052682 stishovite Inorganic materials 0.000 description 18
- 229910052905 tridymite Inorganic materials 0.000 description 18
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 18
- 229910052721 tungsten Inorganic materials 0.000 description 18
- 239000010937 tungsten Substances 0.000 description 18
- 239000004020 conductor Substances 0.000 description 15
- 238000001020 plasma etching Methods 0.000 description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 13
- 150000001875 compounds Chemical class 0.000 description 13
- 239000003989 dielectric material Substances 0.000 description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 12
- 238000000231 atomic layer deposition Methods 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 239000007769 metal material Substances 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 229910052732 germanium Inorganic materials 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 description 6
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 6
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 6
- 229910001928 zirconium oxide Inorganic materials 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Images
Classifications
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- H01L27/11582—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
-
- H01L27/11565—
-
- H01L27/1157—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Definitions
- Exemplary embodiments of the present invention relate to an electronic device, and more particularly, to a semiconductor device, and a method for fabricating a semiconductor device.
- a semiconductor device in which memory cells are integrated in three dimensions is proposed.
- Semiconductor devices require improved reliability.
- a semiconductor device includes: an alternating stack of conductive layers and dielectric layers disposed over a substrate; a channel layer disposed in a through portion, penetrating through the alternating stack; a blocking layer disposed in the through portion, surrounding an outer wall of the channel layer; and a continuous etch stop layer disposed in the through portion, surrounding an outer wall of the blocking layer.
- a method for fabricating a semiconductor device includes: forming an alternating stack of sacrificial layers and dielectric layers over a substrate; forming a first through portion penetrating through the alternating stack; forming an etch stop layer to cover a sidewall of the first through portion; forming a blocking layer disposed in the first through portion over the etch stop layer; forming a second through portion by etching a portion of the alternating stack; removing the sacrificial layers through the second through portion to form an air gap between the dielectric layers; and forming conductive layers in place of the sacrificial layers, wherein the conductive layers are in contact with the etch stop layer while filling the air gaps.
- first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.
- FIGS. 1 A and 1 B illustrate a semiconductor device in accordance with an embodiment of the present invention.
- FIGS. 2 A to 2 H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
- FIGS. 3 A and 3 B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention.
- FIGS. 4 A and 4 B illustrate a semiconductor device according to a modified example of FIG. 1 A .
- FIGS. 5 A and 5 B illustrate a semiconductor device according to a modified example of FIG. 4 A .
- FIGS. 6 A and 6 B illustrate a semiconductor device in accordance with another embodiment of the present invention.
- FIGS. 7 A to 7 H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention.
- FIGS. 8 A and 8 B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention.
- FIGS. 9 A and 9 B illustrate a semiconductor device in accordance with another embodiment of the present invention.
- FIGS. 10 A to 10 H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention.
- FIGS. 11 A and 11 B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention.
- Embodiments of the present invention are directed to a semiconductor device with improved reliability, and a method for fabricating the semiconductor device.
- FIGS. 1 A and 1 B illustrate a semiconductor device 100 in accordance with an embodiment of the present invention.
- FIG. 1 B is a plan view according to a line A 1 -A 2 of FIG. 1 A .
- the semiconductor device 100 may include a stack body 100 S and a pillar structure 100 P that penetrates through the stack body 100 S in a substantially vertical manner.
- the stack body 100 S may include a first layer 101 , a second layer 103 , and a conductive layer 102 , the conductive layer 102 being formed between the first layer 101 and the second layer 103 .
- the first layer 101 may be formed over a substrate or another layer (not shown).
- the conductive layer 102 may be formed over the first layer 101
- the second layer 103 may be formed over the conductive layer 102 .
- the conductive layer 102 may be disposed between the first layer 101 and the second layer 103 .
- the first layer 101 , the conductive layer 102 , and the second layer 103 may be stacked vertically along a first direction D 1 .
- the conductive layer 102 may include a material that is different from the first layer 101 and the second layer 103 , and the first layer 101 and the second layer 103 may be of the same material or of different materials.
- the first layer 101 and the second layer 103 may include a dielectric material.
- the first layer 101 and the second layer 103 may include silicon oxide, silicon nitride, or a combination thereof.
- the first layer 101 and the second layer 103 may have the same thickness.
- the first layer 101 , the conductive layer 102 , and the second layer 103 may have the same thickness.
- the conductive layer 102 may be thicker than the first layer 101 and the third layer 103 .
- the conductive layer 102 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.
- the conductive layer 102 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten (TiN/W).
- the conductive layer 102 may be shaped to surround the sidewall of the pillar structure 100 P.
- the conductive layer 102 may have a planar shape that is parallel to a second direction D 2 .
- the pillar structure 100 P may extend vertically along the first direction D 1 .
- the pillar structure 100 P may be referred to as a vertical pillar structure.
- the pillar structure 100 P may include an etch stop layer 104 , a high dielectric layer 105 , an interface layer 106 , and an active layer 107 .
- the active layer 107 may include a first doped region 108 and a second doped region 109 .
- a vertical channel CH may be formed between the first doped region 108 and the second doped region 109 .
- the first doped region 108 and the second doped region 109 may be referred to as the source and drain regions.
- the etch stop layer 104 may be thinner than the first layer 101 , the conductive layer 102 , and the second layer 103 .
- the etch stop layer 104 may include a material that is different from that of the conductive layer 102 .
- the etch stop layer 104 may include a material that is different from those of the first layer 101 and the second layer 103 .
- the etch stop layer 104 may include a dielectric material.
- the etch stop layer 104 may include a carbon-containing material, and the first layer 101 and the second layer 103 may include carbon-free materials.
- the first layer 101 and the second layer 103 may be carbon-free silicon oxide, and the etch stop layer 104 may be carbon-containing silicon oxide.
- the first layer 101 and the second layer 103 may be SiO 2
- the etch stop layer 104 may be SiCO. SiCO may be more etch-resistant than SiO 2 .
- the high dielectric layer 105 may include a material that is different from that of the etch stop layer 104 .
- the high dielectric layer 105 may include a metal-containing material.
- the high dielectric layer 105 may include a metal oxide.
- the high dielectric layer 105 may have a higher dielectric constant than the etch stop layer 104 .
- the high dielectric layer 105 may include a high-k material.
- the high dielectric layer 105 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof.
- the high dielectric layer 105 may be thicker than the etch stop layer 104 .
- the interface layer 106 may include a low-k material.
- the interface layer 106 may include a material that is different from those of the etch stop layer 104 and the high dielectric layer 105 .
- the interface layer 106 may include silicon oxide and may be free of carbon.
- the active layer 107 may include a semiconductor material.
- the active layer 107 may include one among a polycrystalline semiconductor material, an amorphous semiconductor material, and a monocrystalline semiconductor material.
- the active layer 107 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound.
- the active layer 107 may include polysilicon.
- the first doped region 108 and the second doped region 109 may be formed in the active layer 107 .
- the first doped region 108 and the second doped region 109 may be regions that are doped with a conductive dopant.
- the conductive dopant may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B).
- the first doped region 108 and the second doped region 109 may be doped with dopants of the same conductivity type.
- the semiconductor device 100 may be a transistor, and the conductive layer 102 may be a gate electrode.
- the conductive layer 102 may be formed by replacing the sacrificial layer with a conductive material.
- the etch stop layer 104 may protect the high dielectric layer 105 .
- FIGS. 2 A to 2 H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with an embodiment of the present invention.
- a stacked body 100 S may be prepared.
- the stack body 100 S may include a first layer 101 , a second layer 103 , and a sacrificial layer 102 A, the sacrificial layer 102 A being formed between the first layer 101 and the second layer 103 .
- the first layer 101 may be formed over a substrate or another layer (not shown).
- the sacrificial layer 102 A may be formed over the first layer 101
- the second layer 103 may be formed over the sacrificial layer 102 A.
- the sacrificial layer 102 A may be located between the first layer 101 and the second layer 103 .
- the sacrificial layer 102 A may include a material that is different from those of the first layer 101 and the second layer 103 . Furthermore, the etching selectivity of the sacrificial layer 102 A, with respect to the first layer 101 and the second layer 103 , may be sufficiently large.
- the first layer 101 and the second layer 103 may be of the same material or different materials.
- the first layer 101 and the second layer 103 may include silicon oxide, and the sacrificial layer 102 A may include silicon nitride, a metal material, or polysilicon.
- the first layer 101 and the second layer 103 may include silicon nitride, and the sacrificial layer 102 A may include silicon oxide.
- a first through portion OP 1 may be formed in the stack body 100 S.
- the first through portion OP 1 may be, for example, a hole or a slit that is formed through an anisotropic etching process, such as reactive ion etching (RIE).
- RIE reactive ion etching
- the first through portion OP 1 may be referred to as an opening.
- the first through portion OP 1 may penetrate through the second layer 103 , the sacrificial layer 102 A, and the first layer 101 in a substantially vertical manner.
- the sidewall of the first through portion OP 1 may be formed by etching the surface of the first layer 101 , the sacrificial layer 102 A, and the second layer 103 .
- an etch stop layer 104 may be formed to cover the sidewall of the first through portion OP 1 .
- the etch stop layer 104 may be formed to cover the sidewall of the first through portion OP 1 .
- the etch stop layer 104 may be thinner than the first layer 101 , the sacrificial layer 102 A, and the second layer 103 .
- the etch stop layer 104 may include a material that is different from that of the sacrificial layer 102 A.
- the etching selectivity of the etch stop layer 104 with respect to the sacrificial layer 102 A, may be sufficiently large.
- the etch stop layer 104 may include a material that is different from those of the first layer 101 and the second layer 103 .
- the etch stop layer 104 may include a carbon-containing material, and the first layer 101 and the second layer 103 may include carbon-free materials.
- the first layer 101 and the second layer 103 may be carbon-free silicon oxide, and the etch stop layer 104 may be carbon-containing silicon oxide.
- the first layer 101 and the second layer 103 may include SiO 2
- the etch stop layer 104 may include SiCO.
- SiCO may have a greater etch resistance than SiO 2 .
- a high dielectric layer 105 may be formed over the etch stop layer 104 .
- the high dielectric layer 105 may include a material that is different from that of the etch stop layer 104 .
- the high dielectric layer 105 may include a metal-containing material.
- the high dielectric layer 105 may include a metal oxide.
- the high dielectric layer 105 may have a higher dielectric constant than the etch stop layer 104 .
- the high dielectric layer 105 may include a high-k material.
- the high dielectric layer 105 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof.
- the high dielectric layer 105 may be thicker than the etch stop layer 104 .
- An interface layer 106 may be formed over the high dielectric layer 105 .
- the interface layer 106 may include a material that is different from that of the high dielectric layer 105 .
- the interface layer 106 may be thicker than the high dielectric layer 105 .
- the interface layer 106 may have a smaller dielectric constant than the high dielectric layer 105 .
- the interface layer 106 may include a low-k material.
- the interface layer 106 may include a material that is different from that of the etch stop layer 104 .
- the interface layer 106 may include silicon oxide or silicon oxynitride, and the interface layer 106 may be free of carbon.
- an active layer 107 may be formed over the interface layer 106 .
- the active layer 107 may include a semiconductor material.
- the active layer 107 may include one of a polycrystalline semiconductor material, an amorphous semiconductor material, and a monocrystalline semiconductor material.
- the active layer 107 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound.
- the active layer 107 may include polysilicon.
- the active layer 107 may fill a first through portion OP 1 .
- the active layer 107 may include a first doped region 108 and a second doped region 109 .
- the first through portion OP 1 may be filled with a pillar structure 100 P.
- the pillar structure 100 P may include an etch stop layer 104 , a high dielectric layer 105 , an interface layer 106 , and an active layer 107 .
- the interface layer 106 may be shaped to enclose the active layer 107
- the high dielectric layer 105 may be shaped to enclose the interface layer 106 .
- the etch stop layer 104 may be shaped to surround the high dielectric layer 106 .
- a second through portion OP 2 may be formed in a portion of the stack body 100 S.
- the second through portion OP 2 may be, for example, a hole or a slit that is formed through an anisotropic etching process, such as reactive ion etching (RIE).
- RIE reactive ion etching
- the second through portion OP 2 may be referred to as an opening.
- the first through portion OP 1 may have a hole shape, and the second through portion OP 2 may have a slit shape.
- the second through portion OP 2 may penetrate through the second layer 103 , the sacrificial layer 102 A, and the first layer 101 in a substantially vertical manner.
- the sidewall of the second through portion OP 2 may be formed by etching the surface of the first layer 101 , the sacrificial layer 102 A, and the second layer 103 .
- FIGS. 2 G and 2 H illustrate a series of processes for replacing the sacrificial layer 102 A with the conductive layer 102 .
- the sacrificial layer 102 A may be selectively removed.
- the sacrificial layer 102 A may be selectively etched.
- the silicon oxide may be etched by supplying an etchant with hydrofluoric acid to the second through portion OP 2 .
- the first layer 101 and the second layer 103 may include, for example, silicon nitride or a metal material. The metal material and silicon nitride may have an etch resistance to an etchant with hydrofluoric acid.
- silicon nitride when the sacrificial layer 102 A is silicon nitride, silicon nitride may be etched by supplying an etchant with phosphoric acid to the second through portion OP 2 .
- the first layer 101 and the second layer 103 may be, for example, silicon oxide, and the silicon oxide may have an etch resistance to an etchant with phosphoric acid.
- the etching of the sacrificial layer 102 A may proceed from an end surface of the sacrificial layer 102 A that is exposed through the second through portion OP 2 .
- the end surface of the sacrificial layer 102 A may be recessed in a diametral direction or a width direction through the second through portion OP 2 .
- an air gap AG continuous from the second through portion OP 2 , may be formed between the first layer 101 and the second layer 103 .
- the sacrificial layer 102 A might not remain between the first layer 101 and the second layer 103 .
- all of the sacrificial layer 102 A may be removed, and as a result, the etch stop layer 104 may be exposed.
- the air gap AG may be formed between the second through portion OP 2 and the etch stop layer 104 .
- the etch stop layer 104 may control the end point of the etching process for the sacrificial layer 102 A.
- the etching process of the sacrificial layer 102 A may include a dip-out process.
- the etch stop layer 104 may protect the high dielectric layer 105 while the sacrificial layer 102 A is etched.
- a process to convert the etch stop layer 104 may be performed.
- the converting process may expose the etch stop layer 104 to a plasma treatment or a thermal treatment.
- the etch stop layer 104 may be converted to a carbon-free material through the converting process.
- SiCO may be converted to SiO 2 .
- a conductive layer 102 may be formed.
- the conductive layer 102 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.
- the conductive layer 102 may include titanium nitride, tungsten, or a stack of titanium nitride and tungsten.
- the conductive layer 102 may be formed in the air gap AG.
- the conductive layer 102 may be formed by depositing a conductive material to fill the air gap AG and then by performing an etch-back process on the conductive material.
- the conductive layer 102 may be disposed between the first layer 101 and the second layer 103 .
- the conductive layer 102 may serve as a gate electrode.
- the conductive layer 102 may fully fill the air gap AG, while not overflowing into the second through portion OP 2 .
- the conductive layer 102 may be in direct contact with the etch stop layer 104 .
- the gap-fill characteristic of the conductive layer 102 may be improved.
- No material, other than the conductive layer 102 may be formed in the air gap AG.
- the etch stop layer 104 , the high dielectric layer 105 , and the interface layer 106 might not be formed in the air gap AG. Accordingly, the volume of the conductive layer 102 , filling the air gap AG, may be increased.
- a multi-layered stack may be formed between the active layer 107 and the conductive layer 102 .
- the multi-layered stack may include an etch stop layer 104 , a high dielectric layer 105 , and an interface layer 106 .
- the conductive layer 102 may be a ring type, the hole being formed by surrounding the pillar structure 100 P.
- a transistor with a vertical channel high-k metal gate (HKMG) structure may be formed.
- the vertical channel CH may be formed in a substantially vertical manner in the active layer 107 between the first doped region 108 and the second doped region 109 .
- FIGS. 3 A and 3 B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention.
- the air gap AG may be formed through a series of processes that are illustrated in FIGS. 2 A to 2 G .
- a portion of the etch stop layer 104 , exposed by the air gap AG, may be removed.
- some surfaces 105 S of the high dielectric layer 105 may be exposed, and the air gap AG may be horizontally extended.
- the widened air gap AG may be formed.
- the air gap AG may be horizontally wider than the air gap AG of FIG. 2 G .
- the process for removing a portion of the etch stop layer 104 may include dry etching. According to another embodiment of the present invention, even when the etch stop layer 104 is converted to SiO 2 , a portion of the etch stop layer 104 may be removed through a dry etching process.
- a conductive layer 102 may be formed.
- the conductive layer 102 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.
- the conductive layer 102 may include titanium nitride, tungsten, or a stack of titanium nitride and tungsten.
- the conductive layer 102 may be formed in the air gap AG.
- the conductive layer 102 may be formed by depositing a conductive material to fill the air gap AG and then by performing an etch-back process on the conductive material.
- the conductive layer 102 may be disposed between the first layer 101 and the second layer 103 .
- the conductive layer 102 may serve as a gate electrode.
- the conductive layer 102 may fully fill the air gap AG, while not overflowing into the second through portion OP 2 and.
- the conductive layer 102 may be in direct contact with the high dielectric layer 105 .
- the gap-fill characteristic of the conductive layer 102 may be improved.
- No material, other than the conductive layer 102 may be formed in the air gap AG.
- the etch stop layer 104 , the high dielectric layer 105 , and the interface layer 106 might not be formed in the air gap AG. Accordingly, the volume of the conductive layer 102 , filling the air gap AG, may be increased.
- a multi-layered stack may be formed between the active layer 107 and the conductive layer 102 .
- the multi-layered stack may include a high dielectric layer 105 and an interface layer 106 .
- the conductive layer 102 may be a ring type, the hole being formed by surrounding the pillar structure 100 P.
- a transistor with a vertical channel high-k metal gate (HKMG) structure may be formed.
- the vertical channel CH may be formed in a substantially vertical manner in the active layer 107 between the first doped region 108 and the second doped region 109 .
- the high dielectric layer 105 and the interface layer 106 may remain between the vertical channel CH and the conductive layer 102 .
- the etch stop layer 104 , the high dielectric layer 105 , and the interface layer 106 may remain between the first layer 101 and the second doped region 109 .
- the etch stop layer 104 , the high dielectric layer 105 , and the interface layer 106 may remain between the second layer 103 and the first doped region 108 .
- FIGS. 4 A and 4 B illustrate a semiconductor device according to a modified example of FIG. 1 A .
- FIG. 4 B is a plan view taken along a line A 1 -A 2 of FIG. 4 A .
- the semiconductor device 100 A may be similar to the semiconductor device 100 of FIG. 1 A .
- detailed description on the constituent elements appearing in common will be omitted.
- the semiconductor device 100 A may include a stack body 100 S and a pillar structure 100 PA penetrating through the stack body 100 S.
- the stack body 100 S may include a first layer 101 , a second layer 103 , and a conductive layer 102 provided between the first layer 101 and the second layer 103 .
- the first layer 101 may be formed over a substrate or another layer that is not shown.
- the conductive layer 102 may be formed over the first layer 101
- the second layer 103 may be formed over the conductive layer 102 .
- the conductive layer 102 may be disposed between the first layer 101 and the second layer 103 .
- the first layer 101 , the conductive layer 102 , and the second layer 103 may be stacked vertically in the first direction D 1 .
- the conductive layer 102 may have a shape surrounding the sidewall of the pillar structure 100 PA.
- the conductive layer 102 may have a planar shape that is parallel to the second direction D 2 .
- the pillar structure 100 PA may extend vertically in the first direction D 1 .
- the pillar structure 100 PA may be referred to as a vertical pillar structure.
- the pillar structure 100 PA may include the etch stop layer 104 , the high dielectric layer 105 , the interface layer 106 , and the active layer 107 A.
- the active layer 107 A may include a first doped region 108 and a second doped region 109 .
- a vertical channel CH may be defined between the first doped region 108 and the second doped region 109 .
- the first doped region 108 and the second doped region 109 may be referred to as source and drain regions.
- the etch stop layer 104 , the high dielectric layer 105 , and the interface layer 106 may have a shape whose top and bottom are opened.
- the active layer 107 A may have a shape whose top and bottom are opened.
- the active layer 107 A may be a tube shape or cylinder shape with an inner space.
- the inner space of the active layer 107 A may be filled with a core dielectric layer 107 ′.
- the bottom surfaces of the etch stop layer 104 , the high dielectric layer 105 , the interface layer 106 , and the active layer 107 A may be positioned at the same level.
- the etch stop layer 104 may continue in the first direction D 1 .
- the etch stop layer 104 , the high dielectric layer 105 , and the interface layer 106 may be formed between the vertical channel CH and the conductive layer 102 .
- the etch stop layer 104 , the high dielectric layer 105 , and the interface layer 106 may be formed between the first layer 101 and the second doped region 109 .
- the etch stop layer 104 , the high dielectric layer 105 , and the interface layer 106 may be formed between the second layer 103 and the first doped region 108 .
- the conductive layer 102 may directly contact the etch stop layer 104 .
- FIGS. 5 A and 5 B illustrate a semiconductor device according to a modified example of FIG. 4 A .
- FIG. 5 B is a plan view taken along a line A 1 -A 2 of FIG. 5 A .
- the semiconductor device 100 B may be similar to the semiconductor device 100 A of FIG. 4 A .
- detailed description on the constituent elements appearing in common will be omitted.
- the semiconductor device 100 B may include a stack body 100 S and a pillar structure 100 PB penetrating through the stack body 100 S.
- the pillar structure 100 PB may extend vertically in the first direction D 1 .
- the pillar structure 100 PB may be referred to as a vertical pillar structure.
- the pillar structure 100 PB may include an etch stop layer 104 , a high dielectric layer 105 , an interface layer 106 , and an active layer 107 A.
- the active layer 107 A may include a first doped region 108 and a second doped region 109 .
- a vertical channel CH may be defined between the first doped region 108 and the second doped region 109 .
- the first doped region 108 and the second doped region 109 may be referred to as source and drain regions.
- the high dielectric layer 105 and the interface layer 106 may have a shape whose top and bottom are opened.
- the active layer 107 A may have a shape whose top and bottom are opened. According to another embodiment of the present invention, the active layer 107 A may be a tube shape or cylinder shape with an inner space. The inner space of the active layer 107 A may be filled with a core dielectric layer 107 ′. The bottom surfaces of the high dielectric layer 105 , the interface layer 106 , and the active layer 107 A may be positioned at the same level.
- the etch stop layer 104 may be discontinuous in the first direction D 1 .
- the high dielectric layer 105 and the interface layer 106 may be formed between the vertical channel CH and the conductive layer 102 , and the etch stop layer 104 may not be formed.
- the etch stop layer 104 , the high dielectric layer 105 , and the interface layer 106 may be formed between the first layer 101 and the second doped region 109 .
- the etch stop layer 104 , the high dielectric layer 105 , and the interface layer 106 may be formed between the second layer 103 and the first doped region 108 .
- the conductive layer 102 may directly contact the high dielectric layer 105 .
- FIGS. 6 A and 6 B illustrate a semiconductor device in accordance with another embodiment of the present invention.
- FIG. 6 B is a plan view taken along a line A 1 -A 2 of FIG. 6 A .
- the semiconductor device 100 N may include a stack body 110 and a pillar structure 110 P, the pillar structure 110 P penetrating through the stack body 110 in a substantially vertical manner.
- the stack body 110 may include a first layer 111 , a second layer 113 , and a conductive layer 124 , the conductive layer 124 being formed between the first layer 111 and the second layer 113 .
- the first layer 111 may be formed over a substrate or another layer that is not shown.
- the conductive layer 124 may be formed over the first layer 111
- the second layer 113 may be formed over the conductive layer 124 .
- the conductive layer 124 may be disposed between the first layer 111 and the second layer 113 .
- the first layer 111 , the conductive layer 124 , and the second layer 113 may be stacked vertically in the first direction D 1 .
- the conductive layer 124 may include a material that is different from the first layer 111 and the second layer 113 , and the first layer 111 and the second layer 113 may be of the same material or different materials.
- the first layer 111 and the second layer 113 may include a dielectric material.
- the first layer 111 and the second layer 113 may include silicon oxide, silicon nitride, or a combination thereof.
- the first layer 111 and the second layer 113 may have the same thickness.
- the first layer 111 , the conductive layer 124 , and the second layer 113 may have the same thickness.
- the conductive layer 124 may be thicker than the first layer 111 and the third layer 113 .
- the conductive layer 124 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.
- the conductive layer 124 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten (TiN/W).
- the conductive layer 124 may be shaped to surround a sidewall of the pillar structure 110 P.
- the conductive layer 124 may have a planar shape that is parallel to the second direction D 2 .
- the pillar structure 110 P may extend in a substantially vertical manner in the first direction D 1 .
- the pillar structure 110 P may be referred to as a vertical pillar structure.
- the pillar structure 110 P may include an etch stop layer 115 , a first blocking layer 116 , a second blocking layer 117 , a charge trapping layer 118 , a tunnel dielectric layer 119 , a channel layer 120 , and a core dielectric layer 121 .
- the pillar structure 110 P may fill a first through portion (not marked, refer to 114 of FIG. 7 B ).
- the etch stop layer 115 may be thinner than the first layer 111 , the conductive layer 124 , and the second layer 113 .
- the etch stop layer 115 may include a material that is different from that of the conductive layer 124 .
- the etch stop layer 115 may include a material that is different from those of the first layer 111 and the second layer 113 .
- the etch stop layer 115 may include a dielectric material.
- the etch stop layer 115 may be a carbon-containing material, and the first layer 111 and the second layer 113 may be carbon-free materials.
- the first layer 111 and the second layer 113 may be carbon-free silicon oxide, and the etch stop layer 115 may be carbon-containing silicon oxide.
- the first layer 111 and the second layer 113 may be SiO 2
- the etch stop layer 115 may be SiCO. SiCO may be more etch-resistant than SiO 2 .
- the first blocking layer 116 may include a material that is different from that of the etch stop layer 115 .
- the first blocking layer 116 may be a metal-containing material.
- the first blocking layer 116 may include a metal oxide.
- the first blocking layer 116 may have a greater dielectric constant than the etch stop layer 115 .
- the first blocking layer 116 may include a high-k material.
- the first blocking layer 116 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof.
- the first blocking layer 116 may be thicker than the etch stop layer 115 .
- the second blocking layer 117 may include a low-k material.
- the second blocking layer 117 may include a material that is different from those of the etch stop layer 115 and the first blocking layer 116 .
- the second blocking layer 117 may include silicon oxide and may be free of carbon.
- the second blocking layer 117 may be thicker than the first blocking layer 116 .
- the charge trapping layer 118 may include a charge trapping dielectric material, such as silicon nitride.
- the charge trapping layer 118 may be formed to cover the second blocking layer 117 .
- the tunnel dielectric layer 119 may be formed over the charge trapping layer 118 .
- the tunnel dielectric layer 119 may include silicon oxide.
- the channel layer 120 may be formed over the tunnel dielectric layer 119 .
- the channel layer 120 may include a semiconductor material.
- the channel layer 120 may include any one among a polycrystalline semiconductor material, an amorphous semiconductor material, and a monocrystalline semiconductor material.
- the channel layer 120 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound.
- the channel layer 120 may include polysilicon.
- At least one or more other layers may be further formed over the channel layer 120 .
- the semiconductor device 100 N may be part of a NAND memory cell, and the conductive layer 124 may be a gate electrode or a word line. As will be described later, the conductive layer 124 may be formed by replacing the sacrificial layer with a conductive material through the second through portion 122 . During the process of replacing the sacrificial layer with the conductive layer 124 , the etch stop layer 115 may protect the first blocking layer 116 .
- FIGS. 7 A to 7 H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention.
- a stacked body 110 may be prepared.
- the stack body 110 may include a first layer 111 , a second layer 113 , and a sacrificial layer 112 , the sacrificial layer 112 being formed between the first layer 111 and the second layer 113 .
- the first layer 111 may be formed over a substrate or another layer (not shown).
- the sacrificial layer 112 may be formed over the first layer 111
- the second layer 113 may be formed over the sacrificial layer 112 .
- the sacrificial layer 112 may be disposed between the first layer 111 and the second layer 113 .
- the sacrificial layer 112 may include a material that is different from those of the first layer 111 and the second layer 113 . Furthermore, the etching selectivity of the sacrificial layer 112 , with respect to the first layer 111 and the second layer 113 , may be sufficiently large.
- the first layer 111 and the second layer 113 may be of the same material or of different materials.
- the first layer 111 and the second layer 113 may include silicon oxide, and the sacrificial layer 112 may include silicon nitride, a metal material, or polysilicon.
- the first layer 111 and the second layer 113 may include silicon nitride, and the sacrificial layer 112 may include silicon oxide.
- a first through portion 114 may be formed in the stack body 110 .
- the first through portion 114 may be, for example, a hole or a slit that is formed through an anisotropic etching process, such as reactive ion etching (RIE).
- RIE reactive ion etching
- the first through portion 114 may also be referred to as an opening.
- the first through portion 114 may penetrate through the second layer 113 , the sacrificial layer 112 , and the first layer 111 in a substantially vertical manner.
- a sidewall of the first through portion 114 may be formed by etching the surface of the first layer 111 , the sacrificial layer 112 , and the second layer 113 .
- the etch stop layer 115 may be formed to cover the sidewall of the first through portion 114 .
- the etch stop layer 115 may be formed to cover the sidewall of the first through portion 114 .
- the etch stop layer 115 may be thinner than the first layer 111 , the sacrificial layer 112 , and the second layer 113 .
- the etch stop layer 115 may include a material that is different from that of the sacrificial layer 112 .
- the etching selectivity of the etch stop layer 115 with respect to the sacrificial layer 112 , may be sufficiently large.
- the etch stop layer 115 may include a material that is different from those of the first layer 111 and the second layer 113 .
- the etch stop layer 115 may be a carbon-containing material, and the first layer 111 and the second layer 113 may be carbon-free materials.
- the first layer 111 and the second layer 113 may be carbon-free silicon oxide, and the etch stop layer 115 may be carbon-containing silicon oxide.
- the first layer 111 and the second layer 113 may be SiO 2
- the etch stop layer 115 may be SiCO. While the sacrificial layer 112 is etched subsequently, SiCO may be more etch-resistant than SiO 2 .
- the first blocking layer 116 may be formed over the etch stop layer 115 .
- the first blocking layer 116 may include a material that is different from that of the etch stop layer 115 .
- the first blocking layer 116 may be a metal-containing material.
- the first blocking layer 116 may include a metal oxide.
- the first blocking layer 116 may have a greater dielectric constant than the etch stop layer 115 .
- the first blocking layer 116 may include a high-k material.
- the first blocking layer 116 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof.
- the first blocking layer 116 may be thicker than the etch stop layer 115 .
- the second blocking layer 117 may be formed over the first blocking layer 116 .
- the second blocking layer 117 may include a material that is different from that of the first blocking layer 116 .
- the second blocking layer 117 may be thicker than the first blocking layer 116 .
- the second blocking layer 117 may have a smaller dielectric constant than the first blocking layer 116 .
- the second blocking layer 117 may include a low-k material.
- the second blocking layer 117 may include a material that is different from that of the etch stop layer 115 .
- the second blocking layer 117 may include silicon oxide and may be free of carbon.
- an in-plugged blocking structure including the first blocking layer 116 and the second blocking layer 117 , disposed in the first through portion 114 , may be formed.
- the first blocking layer 116 includes alumina (or aluminum oxide)
- the first blocking layer 116 may be referred to as an in-plugged alumina blocking structure.
- a charge trapping layer 118 may be formed over the second blocking layer 117 .
- the charge trapping layer 118 may include a charge trapping dielectric material, such as silicon nitride.
- the charge trapping layer 118 may be formed through a conformal deposition process, such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).
- CVD Chemical Vapor Deposition
- ALD Atomic Layer Deposition
- the charge trapping layer 118 may be conformally deposited over the second blocking layer 117 .
- a tunnel dielectric layer 119 may be formed over the charge trapping layer 118 .
- the tunnel dielectric layer 119 may include silicon oxide.
- the tunnel dielectric layer 119 may be formed through a conformal deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Tunnel dielectric layer 119 may be conformally deposited over the charge trapping layer 118 .
- CVD chemical vapor deposition
- ALD atomic layer deposition
- the channel layer 120 may be formed over the tunnel dielectric layer 119 .
- the channel layer 120 may include a semiconductor material.
- the channel layer 120 may include one of a polycrystalline semiconductor material, an amorphous semiconductor material, and a monocrystalline semiconductor material.
- the channel layer 120 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound.
- the channel layer 120 may include polysilicon.
- the channel layer 120 may be formed to cover the tunnel dielectric layer 119 in the first through portion 114 .
- the channel layer 120 might not fill the first through portion 114 .
- At least one or more other layers may be further formed over the channel layer 120 .
- the core dielectric layer 121 may fill the first through portion 114 .
- a second through portion 122 may be formed in a portion of the stack body 110 .
- the second through portion 122 may be, for example, a hole or a slit formed through an anisotropic etching process, such as reactive ion etching (RIE).
- RIE reactive ion etching
- the second through portion 122 may be referred to as an opening.
- the first through portion 114 may have a hole shape, and the second through portion 122 may have a slit shape.
- the second through portion 122 may penetrate through the second layer 113 , the sacrificial layer 112 , and the first layer 111 in a substantially vertical manner.
- a sidewall of the second through portion 122 may be formed by etching the surface of the first layer 111 , the sacrificial layer 112 , and the second layer 113 .
- the sacrificial layer 112 may be selectively removed.
- the sacrificial layer 112 may be selectively etched.
- the sacrificial layer 112 is silicon oxide
- the silicon oxide may be etched by supplying an etchant with hydrofluoric acid to the second through portion 122 .
- the first layer 111 and the second layer 113 may be, for example, silicon nitride or a metal material, and the metal material and silicon nitride may have etch resistance to an etchant with hydrofluoric acid.
- the silicon nitride when the sacrificial layer 112 is silicon nitride, the silicon nitride may be etched by supplying an etchant with phosphoric acid to the second through portion 122 .
- the first layer 111 and the second layer 113 may be, for example, silicon oxide, and the silicon oxide may have etch resistance to an etchant with phosphoric acid.
- the etching of the sacrificial layer 112 may proceed from an end surface of the sacrificial layer 112 exposed through the second through portion 122 .
- the end surface of the sacrificial layer 112 may be recessed in a diametral or width direction through the second through portion 122 .
- an air gap 123 may be formed between the first layer 111 and the second layer 113 .
- the sacrificial layer 112 might not remain between the first layer 111 and the second layer 113 .
- all of the sacrificial layers 112 may be removed, and as a result, the etch stop layer 115 may be exposed.
- the air gap 123 may be formed between the second through portion 122 and the etch stop layer 115 .
- the etch stop layer 115 may control the end point of the etching process for the sacrificial layer 112 .
- the etching process of the sacrificial layer 112 may include a dip-out process.
- the etch stop layer 115 may protect the first blocking layer 116 while the sacrificial layer 112 is etched.
- a converting process for the etch stop layer 115 may be performed.
- the converting process may expose the etch stop layer 115 to a plasma treatment or a thermal treatment.
- the etching stop layer 115 may be converted into a carbon-free material through the converting process.
- SiCO may be converted to SiO 2 .
- a conductive layer 124 may be formed.
- the conductive layer 124 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.
- the conductive layer 124 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten.
- the conductive layer 124 may be formed in the air gap 123 .
- the conductive layer 124 may be formed by depositing a conductive material to fill the air gap 123 and then by performing an etch-back process on the conductive material.
- the conductive layer 124 may be disposed between the first layer 111 and the second layer 113 .
- the conductive layer 124 may serve as a gate electrode.
- the conductive layer 124 may fully fill the air gap 123 , while not overflowing into the second through portion 122 .
- the conductive layer 124 may directly contact the etch stop layer 115 .
- the gap-fill characteristic of the conductive layer 124 may be improved.
- No material, other than the conductive layer 124 may be formed in the air gap 123 .
- the etch stop layer 115 , the first blocking layer 116 , and the second blocking layer 117 might not be formed in the air gap 123 . Accordingly, the gap between the conductive layers 124 that are adjacent to each other vertically may be reduced.
- a multi-layered stack may be formed between the channel layer 120 and the conductive layer 124 .
- the multi-layered stack may include the etch stop layer 115 , the first blocking layer 116 , the second blocking layer 117 , the charge trapping layer 118 , and the tunnel dielectric layer 119 .
- FIGS. 8 A and 8 B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention.
- an air gap 123 may be formed through a series of processes illustrated in FIGS. 7 A to 7 G .
- a portion of the etch stop layer 115 , exposed by the air gap 123 may be removed. Accordingly, some surfaces 116 S of the first blocking layer 116 may be exposed, and the air gap 123 may be horizontally extended. In other words, the widened air gap 123 ′ may be formed. The air gap 123 ′ may be horizontally wider than the air gap 123 of FIG. 7 G .
- the process to remove a portion of the etch stop layer 115 may include dry etching. According to another embodiment of the present invention, even when the etch stop layer 115 is converted into SiO 2 , a portion of the etch stop layer 115 may be removed by dry etching.
- a conductive layer 124 may be formed.
- the conductive layer 124 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.
- the conductive layer 124 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten.
- the conductive layer 124 may be formed in the air gap 123 ′.
- the conductive layer 124 may be formed by depositing a conductive material to fill the air gap 123 ′ and then by performing an etch-back process on the conductive material.
- the conductive layer 124 may be disposed between the first layer 111 and the second layer 113 .
- the conductive layer 124 may serve as a gate electrode.
- the conductive layer 124 may fully fill the air gap 123 ′, while not overflowing into the second through portion 122 .
- the conductive layer 124 may be in direct contact with the first blocking layer 116 .
- the gap-fill characteristic of the conductive layer 124 may be improved.
- No material, other than the conductive layer 124 may be formed in the air gap 123 ′.
- the etch stop layer 115 , the first blocking layer 116 , and the second blocking layer 117 might not be formed in the air gap 123 ′. Accordingly, the volume of the conductive layer 124 filling the air gap 123 ′ may be increased.
- FIGS. 9 A and 9 B illustrates a semiconductor device 200 V in accordance with another embodiment of the present invention.
- FIG. 9 B is a plan view taken along a line A 1 -A 2 of FIG. 9 A .
- the semiconductor device 200 V may include a vertical NAND.
- the semiconductor device 200 V may include a three-dimensional (3D) NAND.
- the semiconductor device 200 V may include a lower structure 200 L, a stack body 210 over the lower structure 200 L, and a vertical channel structure 220 that penetrates through the stack body 210 .
- the lower structure 200 L may include a substrate. According to another embodiment of the present invention, the lower structure 200 L may include a peripheral circuit.
- the peripheral circuit unit may include a plurality of control circuits. At least one control circuit of the peripheral circuit portion may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit may include a planar channel transistor, a recess channel transistor, a buried gate transistor, a fin channel transistor (FinFET), and the like.
- the lower structure 200 L and the stack body 210 may be interconnected to each other through a multi-level metal wire (not shown).
- the stack body 210 may include a stack of word lines 212 and dielectric layers 211 , stacked in an alternating manner, positioned over the lower structure 200 L.
- the vertical channel structure 220 including a channel layer 226 , may be formed in the through portion that penetrates through the alternating stack.
- a first blocking layer 222 may be formed in the through portion to surround the outer wall of the channel layer 225 .
- An etch stop layer 221 surrounding the outer wall of the first blocking layer 222 , may be included in the through portion.
- the etch stop layer 221 may be in direct contact with the word lines 212 and the dielectric layers 211 .
- the etch stop layer 221 may be a continuous etch stop layer, extending vertically along the stacking direction of the alternating stack.
- the first blocking layer 222 may extend vertically in the stacking direction of the alternating stack.
- the stack body 210 may be formed by stacking the dielectric layer 211 and the word line 212 in an alternating manner.
- the vertical channel structure 220 may penetrate through the stack body 210 in a substantially vertical manner.
- the word line 212 may include a material that surrounds the vertical channel structure 220 .
- the vertical channel structure 220 may include an etch stop layer 221 which is in contact with the word line 212 , a first blocking layer 222 , a second blocking layer 223 , a charge trapping layer 224 , a tunnel dielectric layer 225 , and a channel layer 226 .
- the inner space of the channel layer 226 may be filled with the core dielectric layer 227 .
- the dielectric layer 211 may be formed over the lower structure 200 L.
- the word line 212 may be disposed between the dielectric layers 211 .
- the word line 212 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.
- the word line 212 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten (TiN/W).
- the word line 212 may be shaped to surround the sidewall of the vertical channel structure 220 .
- the word line 212 may have a planar shape.
- the etch stop layer 221 may include a dielectric material.
- the etch stop layer 221 may be a carbon-containing material, and the dielectric layer 211 may be a carbon-free material.
- the dielectric layer 211 may be a carbon-free silicon oxide, and the etch stop layer 221 may be a carbon-containing silicon oxide.
- the dielectric layer 211 may be SiO 2
- the etch stop layer 221 may be SiCO. SiCO may be more etch-resistant than SiO 2 .
- the etch stop layer 221 may be a continuous etch stop layer that is continuous along the stacking direction of the dielectric layer 211 and the word line 212 .
- the first blocking layer 222 may include a material that is different from that of the etch stop layer 221 .
- the first blocking layer 222 may be a metal-containing material.
- the first blocking layer 222 may include a metal oxide.
- the first blocking layer 222 may have a greater dielectric constant than the etch stop layer 221 .
- the first blocking layer 222 may include a high-k material.
- the first blocking layer 222 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof.
- the first blocking layer 222 may be thicker than the etch stop layer 221 .
- the second blocking layer 223 may include a low-k material.
- the second blocking layer 223 may include a material that is different from those of the etch stop layer 221 and the first blocking layer 222 .
- the second blocking layer 223 may include silicon oxide and may be free of carbon.
- the second blocking layer 223 may be thicker than the first blocking layer 222 .
- the charge trapping layer 224 may include a charge trapping dielectric material, such as silicon nitride.
- the charge trapping layer 224 may be formed to cover the second blocking layer 222 .
- a tunnel dielectric layer 225 may be formed over the charge trapping layer 224 .
- the tunnel dielectric layer 225 may include silicon oxide.
- the channel layer 226 may be formed over the tunnel dielectric layer 225 .
- the channel layer 226 may include a semiconductor material.
- the channel layer 226 may include any one among a polycrystalline semiconductor material, an amorphous semiconductor material, and a monocrystalline semiconductor material.
- the channel layer 226 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound.
- the channel layer 226 may include polysilicon.
- At least one or more other layers may be further formed over the channel layer 226 .
- a blocking-free structure in which only the word line 212 is disposed may be formed between the dielectric layers 211 .
- the resistance of the word line 212 may be reduced by increasing the volume of the word line 212 without decreasing the height of the memory cell stack.
- the etch stop layer 221 may have a thickness that is thinner than that of the first blocking layer 222 , and thus might not cause deterioration in the characteristics of a capacitor between the word line 212 and the charge trapping layer 224 .
- the etch stop layer 221 may have a thickness of approximately 30 ⁇ .
- FIGS. 10 A to 10 H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention.
- an alternating stack 11 M may be formed over the substrate 11 .
- the substrate 11 may be a material that is suitable for semiconductor processing.
- the substrate 11 may include a semiconductor substrate.
- the substrate 11 may be a silicon substrate, a monocrystalline silicon substrate, a polysilicon substrate, an amorphous silicon substrate, a silicon germanium substrate, a monocrystalline silicon germanium substrate, a polycrystalline silicon germanium substrate, a carbon-doped silicon substrate, a combination thereof, or a multi-layer thereof.
- the substrate 11 may include other semiconductor materials, such as germanium.
- the substrate 11 may include a group III/V semiconductor substrate, such as a compound semiconductor substrate, e.g., GaAs.
- the substrate 11 may include a Silicon-On-Insulator (SOI) substrate.
- SOI Silicon-On-Insulator
- the alternating stack 11 M may be a stack body in which the first material layer and the second material layer may be alternately stacked.
- the first material layer may include a first material
- the second material layer may include a second material.
- the first material and the second material may be of different materials.
- the first material layer and the second material layer may include a dielectric layer 12 and a sacrificial layer 13 , respectively.
- the dielectric layer 12 may include a dielectric material
- the sacrificial layer 13 may include a sacrificial material.
- the ‘sacrificial material’ may refer to a substance to be removed in the subsequent process.
- the dielectric layer 12 may include at least one dielectric material among silicon oxide, silicon nitride, silicon oxynitride, a spin-on-dielectric material (SOD), a dielectric metal oxide, a silicate, and a dielectric metal oxynitride.
- SOD spin-on-dielectric material
- the sacrificial layer 13 may include a sacrificial material that may be selectively removed with respect to the dielectric layer 12 .
- the removal of the sacrificial layer 13 may be optional with respect to the dielectric layer 12 .
- the ratio of the removal rate of the sacrificial layer 13 to the removal rate of the dielectric layer 12 may be referred to as a selectivity of the removal process of the sacrificial layer 13 with respect to the dielectric layer 12 .
- the sacrificial layer 13 may include a dielectric material.
- the sacrificial layer 13 may be replaced with a conductive material in a subsequent process. For example, it may be replaced with the gate electrode (or word line) of the vertical NAND device.
- the sacrificial layer 13 may include silicon nitride, amorphous silicon, or polysilicon. According to an embodiment of the present invention, the sacrificial layer 13 may include silicon nitride.
- the dielectric layer 12 may include silicon oxide, and the sacrificial layer 13 may include silicon nitride.
- the alternating number of dielectric layers 12 and sacrificial layers 13 , in the alternating stack 11 M, may be determined according to the number of memory cells. For example, when 48 memory cells are stacked vertically, the dielectric layer 12 and the sacrificial layer 13 may be stacked 48 times, individually. The dielectric layer 12 and the sacrificial layer 13 may be repeatedly stacked in a direction that is perpendicular to the surface of the substrate 11 .
- the dielectric layer 12 may be deposited through a Chemical Vapor Deposition (CVD) process or Atomic Layer Deposition (ALD) process.
- the sacrificial layer 13 may be deposited through a chemical vapor deposition process or an atomic layer deposition process.
- the bottom and top layers of the alternating stack 11 M may be the dielectric layers 12 .
- the dielectric layer 12 and the sacrificial layer 13 may have the same thickness.
- the top dielectric layer 12 may be thicker than the other dielectric layers 12 .
- the top dielectric layer 12 may be referred to as a dielectric cap layer.
- a first through portion 14 may be formed in the alternating stack 11 M.
- a portion of the alternating stack 11 M may be etched using a mask (not shown) to form the first through portion 14 .
- the mask may include a resist pattern, and the resist pattern may be formed by applying a resist material and performing a photolithography process.
- the resist material may include a photoresist.
- the process of etching the alternating stack 11 M to form the first through portion 14 may include an anisotropic etch process.
- the anisotropic etching may include reactive ion etching (RIE).
- RIE reactive ion etching
- the reactive ion etching of the dielectric layers 12 and the reactive ion etching of the sacrificial layers 13 may be performed continuously.
- the first through portion 14 may penetrate through the alternating stack 11 M and extend in a direction that is perpendicular to the surface of the substrate 11 .
- the bottom of the first through portion 14 may expose the surface of the substrate 11 .
- the first through portion 14 may include a vertical hole.
- a plurality of first through portions 14 may be arranged. From the perspective of a top view, the first through portions 14 may be arranged in a zigzag arrangement. Each of the first through portions 14 may have a uniform size.
- the sidewall of the first through portion 14 may have a vertical profile. According to another embodiment of the present invention, the sidewall of the first through portion 14 may have a sloped profile.
- the first through portion 14 may be referred to as a channel hole or a vertical hole.
- the first through portion 14 may penetrate through the dielectric layers 12 and the sacrificial layers 13 in a substantially vertical manner.
- the sidewall of the first through portion 14 may be formed by etching the surface of the dielectric layers 12 and the sacrificial layers 13 .
- an etch stop layer 15 may be formed to cover the sidewall of the first through portion 14 .
- the etch stop layer 15 may be formed to cover the sidewall of the first through portion 14 .
- the etch stop layer 15 may cover the bottom surface of the first through portion 14 .
- the etch stop layer 15 may be thinner than the dielectric layer 12 and the sacrificial layer 13 .
- the etch stop layer 15 may include of a material that is different from the sacrificial layer 13 .
- the etching selectivity of the etch stop layer 15 with respect to the sacrificial layer 13 , may be sufficiently large.
- the etch stop layer 15 may include a material that is different from that of the dielectric layer 12 .
- the etch stop layer 15 may be a carbon-containing material, and the dielectric layer 12 may be a carbon-free material.
- the dielectric layer 12 may be carbon-free silicon oxide, and the etch stop layer 15 may be carbon-containing silicon oxide.
- the dielectric layer 12 may be SiO 2 and the etch stop layer 15 may be SiCO. While the subsequent sacrificial layer 13 is etched, SiCO may be more etch resistant than SiO 2 .
- the etch stop layer 15 may have a thickness of approximately 30 ⁇ .
- a first blocking layer 16 may be formed over the etch stop layer 15 .
- the first blocking layer 16 may include a material that is different from that of the etch stop layer 15 .
- the first blocking layer 16 may be a metal-containing material.
- the first blocking layer 16 may include a metal oxide.
- the first blocking layer 16 may have a greater dielectric constant than the etch stop layer 15 .
- the first blocking layer 16 may include a high-k material.
- the first blocking layer 16 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof.
- the first blocking layer 16 may be thicker than the etch stop layer 15 .
- the first blocking layer 16 may be formed to a thickness of approximately 20 ⁇ to 100 A.
- the second blocking layer 17 may be formed over the first blocking layer 16 .
- the second blocking layer 17 may include a material that is different from that of the first blocking layer 16 .
- the second blocking layer 17 may be thicker than the first blocking layer 16 .
- the second blocking layer 17 may have a smaller dielectric constant than that of the first blocking layer 16 .
- the second blocking layer 17 may include a low-k material.
- the second blocking layer 17 may include a material that is different from that of the etch stop layer 15 .
- the second blocking layer 17 may include silicon oxide and may be free of carbon.
- an in-plugged blocking structure including the first blocking layer 16 and the second blocking layer 17 , disposed in the first through portion 14 , may be formed.
- the first blocking layer 16 includes alumina (or aluminum oxide)
- the first blocking layer 16 may be called an in-plugged alumina blocking structure.
- a charge trapping layer 18 may be formed over the second blocking layer 17 .
- the charge trapping layer 18 may include a charge trapping dielectric material, such as silicon nitride.
- the charge trapping layer 18 may be formed through a conformal deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).
- CVD chemical vapor deposition
- ALD atomic layer deposition
- the charge trapping layer 18 may be conformally deposited over the second blocking layer 17 .
- a tunnel dielectric layer 19 may be formed over the charge trapping layer 18 .
- the tunnel dielectric layer 19 may include silicon oxide.
- the tunnel dielectric layer 19 may be formed through a conformal deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).
- CVD chemical vapor deposition
- ALD atomic layer deposition
- the tunnel dielectric layer 19 may be conformally deposited over the charge trapping layer 18 .
- the first blocking layer 16 , the second blocking layer 17 , the charge trapping layer 18 , and the tunnel dielectric layer 19 may cover the bottom surface of the first through portion 14 .
- a portion of the tunnel dielectric layer 19 may be cut from the bottom surface of the first through portion 14 .
- the charge trapping layer 18 , the second blocking layer 17 , the first blocking layer 16 and the etch stop layer 15 may be sequentially cut from the bottom surface of the first through portion 14 .
- the channel layer 20 may be formed over the tunnel dielectric layer 19 .
- the channel layer 20 may include a semiconductor material.
- the channel layer 20 may include any one among a polycrystalline semiconductor material, an amorphous semiconductor material, or a monocrystalline semiconductor material.
- the channel layer 20 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound.
- the channel layer 20 may include polysilicon.
- the channel layer 20 may be formed to cover the tunnel dielectric layer 19 in the first through portion 14 .
- the channel layer 20 might not fill the first through portion 14 .
- At least one or more other layers including a core dielectric layer 21 may be further formed over the channel layer 20 .
- the core dielectric layer 21 may fill the first through portion 14 .
- a second through portion 22 may be formed in a portion of the alternating stack 11 M.
- the second through portion 22 may be, for example, a hole or a slit that is formed through an anisotropic etching process, such as reactive ion etching (RIE).
- RIE reactive ion etching
- the second through portion 22 may be referred to as an opening.
- the first through portion 14 may have a hole shape, and the second through portion 22 may have a slit shape.
- the second through portion 22 may penetrate through the dielectric layers 12 and the sacrificial layers 13 in a substantially vertical manner.
- the sidewall of the second through portion 22 may be formed by etching the surface of the dielectric layers 12 and the sacrificial layers 13 .
- the sacrificial layers 13 may be selectively removed.
- the sacrificial layer 13 may be selectively etched.
- the sacrificial layer 13 is silicon oxide
- the silicon oxide may be etched by supplying an etchant with hydrofluoric acid to the second through portion 22 .
- the dielectric layers 12 may be, for example, silicon nitride or a metal material, and the metal material and silicon nitride may have etch resistance to the etchant with hydrofluoric acid.
- the silicon nitride when the sacrificial layers 13 are silicon nitride, the silicon nitride may be etched by supplying an etchant with phosphoric acid to the second through portion 22 .
- the dielectric layers 12 may be, for example, silicon oxide, and the silicon oxide may have etch resistance to an etchant with phosphoric acid.
- the etching of the sacrificial layers 13 may proceed from an end surface of the sacrificial layer 13 exposed through the second through portion 22 .
- the end surface of the sacrificial layer 13 may be recessed in the diametral or width direction of the second through portion 22 .
- an air gap 23 continuous from the second through portion 22 may be formed between the dielectric layers 12 .
- the sacrificial layer 13 might not remain between the dielectric layers 12 .
- all of the sacrificial layer 13 may be removed, and as a result, the etch stop layer 15 may be exposed.
- the air gap 23 may be formed between the second through portion 22 and the etch stop layer 15 .
- the etch stop layer 15 may control the etching end point at which the etching of the sacrificial layer 13 ends.
- the process of etching the sacrificial layer 13 may include a dip-out process.
- the etch stop layer 15 may protect the first blocking layer 16 while the sacrificial layer 13 is etched.
- a converting process for the etch stop layer 15 may be performed.
- the converting process may expose the etch stop layer 15 to a plasma treatment or a thermal treatment.
- the etching stop layer 15 may be converted to a carbon-free material by the converting process.
- SiCO may be converted into SiO 2 .
- the converting process may include a thermal treatment or a plasma treatment.
- a conductive layer 24 may be formed.
- the conductive layer 24 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.
- the conductive layer 24 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten.
- the conductive layer 24 may be formed in the air gap 23 .
- the conductive layer 24 may be formed by depositing a conductive material to fill the air gap 23 and then performing an etch-back process on the conductive material.
- the conductive layer 24 may be disposed between the dielectric layers 12 .
- the conductive layer 24 may serve as a gate electrode or a word line.
- the conductive layer 24 may fully fill the air gap 23 , while not overflowing into the second through portion 22 .
- the conductive layer 24 may directly contact the etch stop layer 15 .
- the gap-fill characteristic of the conductive layer 24 may be improved.
- No material, other than the conductive layer 24 may be formed in the air gap 23 .
- the etch stop layer 15 , the first blocking layer 16 , and the second blocking layer 17 might not be formed in the air gap 23 .
- the gap between the conductive layers 24 that are vertically adjacent to each other may be reduced. Since the first blocking layer 16 is not formed inside the air gap 23 , poor step coverage of the first blocking layer 16 may be prevented.
- a multi-layered stack may be formed between the channel layer 20 and the conductive layer 24 .
- the multi-layered stack may include an etch stop layer 15 , a first blocking layer 16 , a second blocking layer 17 , a charge trapping layer 18 , and a tunnel dielectric layer 19 .
- An alternating stack 11 M may be formed over the substrate 11 , and the alternating stack 11 M may be formed by alternately stacking the dielectric layer 12 and the conductive layer 24 .
- a blocking-free structure in which only the conductive layer 24 is disposed between the dielectric layers 12 may be formed.
- the etch stop layer 15 may be disposed between the conductive layer 24 and the first blocking layer 16 .
- the etch stop layer 15 may be disposed between the dielectric layer 12 and the first blocking layer 16 .
- FIGS. 11 A and 11 B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention.
- an air gap 23 may be formed through a series of processes illustrated in FIGS. 10 A to 10 G .
- a portion of the etch stop layer 15 , exposed by the air gap 23 may be removed.
- the surface 16 S of a portion of the first blocking layer 16 may be exposed, and the air gap 23 may horizontally extend.
- a wider air gap 23 ′ may be formed.
- the air gap 23 ′ may be horizontally wider than the air gap 23 of FIG. 10 G .
- the process to remove a portion of the etch stop layer 15 may include a dry etching process or a wet etching process. According to another embodiment of the present invention, even when the etch stop layer 15 is converted into SiO 2 , a portion of the etch stop layer 15 may be removed by a dry etching process or a wet etching process.
- a conductive layer 24 may be formed.
- the conductive layer 24 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.
- the conductive layer 24 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten.
- the conductive layer 24 may be formed in the air gap 23 ′.
- the conductive layer 24 may be formed by depositing a conductive material to fill the air gap 23 ′ and then by performing an etch-back process on the conductive material.
- the conductive layer 24 may be disposed between the dielectric layers 12 .
- the conductive layer 24 may serve as a gate electrode.
- the conductive layer 24 may fully fill the air gap 23 ′, while not overflowing into the second through portion 22 .
- the conductive layer 24 may directly contact the first blocking layer 16 .
- the gap-fill characteristic of the conductive layer 24 may be improved.
- No material, other than the conductive layer 24 may be formed in the air gap 23 ′.
- the etch stop layer 15 , the first blocking layer 16 , and the second blocking layer 17 might not be formed in the air gap 23 ′.
- the volume of the conductive layer 24 filling the air gap 23 ′ may be increased.
- the conductive layer 24 and the first blocking layer 16 may be in direct contact with each other, and the etch stop layer 15 may be disposed between the dielectric layer 12 and the first blocking layer 16 .
- the resistance of word lines may be reduced by forming the word lines in a blocking-free structure.
- both the difficulty of a high aspect ratio etching process and the production cost may be reduced by decreasing a pitch of a dielectric layer and a sacrificial layer according to an increase in the number of stacked layers of the dielectric layer and the sacrificial layer so as to reduce the total height.
- step coverage of a blocking layer may be improved as the number of rows in a memory block increases.
Abstract
A semiconductor device includes: an alternating stack of conductive layers and dielectric layers disposed over a substrate; a channel layer disposed in a through portion, penetrating through the alternating stack; a blocking layer disposed in the through portion, surrounding an outer wall of the channel layer; and a continuous etch stop layer disposed in the through portion, surrounding an outer wall of the blocking layer.
Description
- The present application is a continuation application of U.S. patent application Ser. No. 16/897,009, filed on Jun. 9, 2020, and claims priority to Korean Patent Application No. 10-2019-0167067, filed on Dec. 13, 2019, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.
- Exemplary embodiments of the present invention relate to an electronic device, and more particularly, to a semiconductor device, and a method for fabricating a semiconductor device.
- A semiconductor device in which memory cells are integrated in three dimensions is proposed. Semiconductor devices require improved reliability.
- In accordance with an embodiment of the present invention, a semiconductor device includes: an alternating stack of conductive layers and dielectric layers disposed over a substrate; a channel layer disposed in a through portion, penetrating through the alternating stack; a blocking layer disposed in the through portion, surrounding an outer wall of the channel layer; and a continuous etch stop layer disposed in the through portion, surrounding an outer wall of the blocking layer.
- In accordance with another embodiment of the present invention, a method for fabricating a semiconductor device includes: forming an alternating stack of sacrificial layers and dielectric layers over a substrate; forming a first through portion penetrating through the alternating stack; forming an etch stop layer to cover a sidewall of the first through portion; forming a blocking layer disposed in the first through portion over the etch stop layer; forming a second through portion by etching a portion of the alternating stack; removing the sacrificial layers through the second through portion to form an air gap between the dielectric layers; and forming conductive layers in place of the sacrificial layers, wherein the conductive layers are in contact with the etch stop layer while filling the air gaps.
- Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.
- In the drawing figures, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.
- The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.
-
FIGS. 1A and 1B illustrate a semiconductor device in accordance with an embodiment of the present invention. -
FIGS. 2A to 2H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with an embodiment of the present invention. -
FIGS. 3A and 3B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention. -
FIGS. 4A and 4B illustrate a semiconductor device according to a modified example ofFIG. 1A . -
FIGS. 5A and 5B illustrate a semiconductor device according to a modified example ofFIG. 4A . -
FIGS. 6A and 6B illustrate a semiconductor device in accordance with another embodiment of the present invention. -
FIGS. 7A to 7H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention. -
FIGS. 8A and 8B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention. -
FIGS. 9A and 9B illustrate a semiconductor device in accordance with another embodiment of the present invention. -
FIGS. 10A to 10H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention. -
FIGS. 11A and 11B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention. - Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.
- It will be understood that although the terms “first”, “second”, “third” etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present disclosure.
- Embodiments of the present invention are directed to a semiconductor device with improved reliability, and a method for fabricating the semiconductor device.
-
FIGS. 1A and 1B illustrate asemiconductor device 100 in accordance with an embodiment of the present invention.FIG. 1B is a plan view according to a line A1-A2 ofFIG. 1A . - Referring to
FIGS. 1A and 1B , thesemiconductor device 100 may include astack body 100S and apillar structure 100P that penetrates through thestack body 100S in a substantially vertical manner. - The
stack body 100S may include afirst layer 101, asecond layer 103, and aconductive layer 102, theconductive layer 102 being formed between thefirst layer 101 and thesecond layer 103. For example, thefirst layer 101 may be formed over a substrate or another layer (not shown). Theconductive layer 102 may be formed over thefirst layer 101, and thesecond layer 103 may be formed over theconductive layer 102. Theconductive layer 102 may be disposed between thefirst layer 101 and thesecond layer 103. Thefirst layer 101, theconductive layer 102, and thesecond layer 103 may be stacked vertically along a first direction D1. Theconductive layer 102 may include a material that is different from thefirst layer 101 and thesecond layer 103, and thefirst layer 101 and thesecond layer 103 may be of the same material or of different materials. Thefirst layer 101 and thesecond layer 103 may include a dielectric material. Thefirst layer 101 and thesecond layer 103 may include silicon oxide, silicon nitride, or a combination thereof. Thefirst layer 101 and thesecond layer 103 may have the same thickness. Thefirst layer 101, theconductive layer 102, and thesecond layer 103 may have the same thickness. According to another embodiment of the present invention, theconductive layer 102 may be thicker than thefirst layer 101 and thethird layer 103. Theconductive layer 102 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Theconductive layer 102 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten (TiN/W). Theconductive layer 102 may be shaped to surround the sidewall of thepillar structure 100P. Theconductive layer 102 may have a planar shape that is parallel to a second direction D2. - The
pillar structure 100P may extend vertically along the first direction D1. Thepillar structure 100P may be referred to as a vertical pillar structure. Thepillar structure 100P may include anetch stop layer 104, ahigh dielectric layer 105, aninterface layer 106, and anactive layer 107. Theactive layer 107 may include a firstdoped region 108 and a seconddoped region 109. A vertical channel CH may be formed between the firstdoped region 108 and the seconddoped region 109. The firstdoped region 108 and the seconddoped region 109 may be referred to as the source and drain regions. - The
etch stop layer 104 may be thinner than thefirst layer 101, theconductive layer 102, and thesecond layer 103. Theetch stop layer 104 may include a material that is different from that of theconductive layer 102. Theetch stop layer 104 may include a material that is different from those of thefirst layer 101 and thesecond layer 103. Theetch stop layer 104 may include a dielectric material. In other words, theetch stop layer 104 may include a carbon-containing material, and thefirst layer 101 and thesecond layer 103 may include carbon-free materials. Thefirst layer 101 and thesecond layer 103 may be carbon-free silicon oxide, and theetch stop layer 104 may be carbon-containing silicon oxide. For example, thefirst layer 101 and thesecond layer 103 may be SiO2, and theetch stop layer 104 may be SiCO. SiCO may be more etch-resistant than SiO2. - The
high dielectric layer 105 may include a material that is different from that of theetch stop layer 104. Thehigh dielectric layer 105 may include a metal-containing material. Thehigh dielectric layer 105 may include a metal oxide. Thehigh dielectric layer 105 may have a higher dielectric constant than theetch stop layer 104. Thehigh dielectric layer 105 may include a high-k material. For example, thehigh dielectric layer 105 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof. Thehigh dielectric layer 105 may be thicker than theetch stop layer 104. - The
interface layer 106 may include a low-k material. - The
interface layer 106 may include a material that is different from those of theetch stop layer 104 and thehigh dielectric layer 105. Theinterface layer 106 may include silicon oxide and may be free of carbon. - The
active layer 107 may include a semiconductor material. For example, theactive layer 107 may include one among a polycrystalline semiconductor material, an amorphous semiconductor material, and a monocrystalline semiconductor material. Theactive layer 107 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound. Theactive layer 107 may include polysilicon. The firstdoped region 108 and the seconddoped region 109 may be formed in theactive layer 107. The firstdoped region 108 and the seconddoped region 109 may be regions that are doped with a conductive dopant. For example, the conductive dopant may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The firstdoped region 108 and the seconddoped region 109 may be doped with dopants of the same conductivity type. - Referring to
FIGS. 1A and 1B , thesemiconductor device 100 may be a transistor, and theconductive layer 102 may be a gate electrode. As will be described later, theconductive layer 102 may be formed by replacing the sacrificial layer with a conductive material. During the process of replacing the sacrificial layer with aconductive layer 102, theetch stop layer 104 may protect thehigh dielectric layer 105. -
FIGS. 2A to 2H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with an embodiment of the present invention. - Referring to
FIG. 2A , astacked body 100S may be prepared. Thestack body 100S may include afirst layer 101, asecond layer 103, and asacrificial layer 102A, thesacrificial layer 102A being formed between thefirst layer 101 and thesecond layer 103. - For example, the
first layer 101 may be formed over a substrate or another layer (not shown). Thesacrificial layer 102A may be formed over thefirst layer 101, and thesecond layer 103 may be formed over thesacrificial layer 102A. Thesacrificial layer 102A may be located between thefirst layer 101 and thesecond layer 103. - The
sacrificial layer 102A may include a material that is different from those of thefirst layer 101 and thesecond layer 103. Furthermore, the etching selectivity of thesacrificial layer 102A, with respect to thefirst layer 101 and thesecond layer 103, may be sufficiently large. Thefirst layer 101 and thesecond layer 103 may be of the same material or different materials. - The
first layer 101 and thesecond layer 103 may include silicon oxide, and thesacrificial layer 102A may include silicon nitride, a metal material, or polysilicon. Thefirst layer 101 and thesecond layer 103 may include silicon nitride, and thesacrificial layer 102A may include silicon oxide. - Referring to
FIG. 2B , a first through portion OP1 may be formed in thestack body 100S. The first through portion OP1 may be, for example, a hole or a slit that is formed through an anisotropic etching process, such as reactive ion etching (RIE). The first through portion OP1 may be referred to as an opening. - The first through portion OP1 may penetrate through the
second layer 103, thesacrificial layer 102A, and thefirst layer 101 in a substantially vertical manner. The sidewall of the first through portion OP1 may be formed by etching the surface of thefirst layer 101, thesacrificial layer 102A, and thesecond layer 103. - Referring to
FIG. 2C , anetch stop layer 104 may be formed to cover the sidewall of the first through portion OP1. Theetch stop layer 104 may be formed to cover the sidewall of the first through portion OP1. Theetch stop layer 104 may be thinner than thefirst layer 101, thesacrificial layer 102A, and thesecond layer 103. Theetch stop layer 104 may include a material that is different from that of thesacrificial layer 102A. Furthermore, the etching selectivity of theetch stop layer 104, with respect to thesacrificial layer 102A, may be sufficiently large. Theetch stop layer 104 may include a material that is different from those of thefirst layer 101 and thesecond layer 103. Theetch stop layer 104 may include a carbon-containing material, and thefirst layer 101 and thesecond layer 103 may include carbon-free materials. Thefirst layer 101 and thesecond layer 103 may be carbon-free silicon oxide, and theetch stop layer 104 may be carbon-containing silicon oxide. For example, thefirst layer 101 and thesecond layer 103 may include SiO2, and theetch stop layer 104 may include SiCO. During the subsequent process of etching thesacrificial layer 102A, SiCO may have a greater etch resistance than SiO2. - Referring to
FIG. 2D , ahigh dielectric layer 105 may be formed over theetch stop layer 104. Thehigh dielectric layer 105 may include a material that is different from that of theetch stop layer 104. Thehigh dielectric layer 105 may include a metal-containing material. Thehigh dielectric layer 105 may include a metal oxide. Thehigh dielectric layer 105 may have a higher dielectric constant than theetch stop layer 104. Thehigh dielectric layer 105 may include a high-k material. For example, thehigh dielectric layer 105 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof. Thehigh dielectric layer 105 may be thicker than theetch stop layer 104. - An
interface layer 106 may be formed over thehigh dielectric layer 105. Theinterface layer 106 may include a material that is different from that of thehigh dielectric layer 105. Theinterface layer 106 may be thicker than thehigh dielectric layer 105. Theinterface layer 106 may have a smaller dielectric constant than thehigh dielectric layer 105. Theinterface layer 106 may include a low-k material. Theinterface layer 106 may include a material that is different from that of theetch stop layer 104. Theinterface layer 106 may include silicon oxide or silicon oxynitride, and theinterface layer 106 may be free of carbon. - Referring to
FIG. 2E , anactive layer 107 may be formed over theinterface layer 106. Theactive layer 107 may include a semiconductor material. For example, theactive layer 107 may include one of a polycrystalline semiconductor material, an amorphous semiconductor material, and a monocrystalline semiconductor material. Theactive layer 107 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound. Theactive layer 107 may include polysilicon. Theactive layer 107 may fill a first through portion OP1. Theactive layer 107 may include a firstdoped region 108 and a seconddoped region 109. - The first through portion OP1 may be filled with a
pillar structure 100P. Thepillar structure 100P may include anetch stop layer 104, ahigh dielectric layer 105, aninterface layer 106, and anactive layer 107. Theinterface layer 106 may be shaped to enclose theactive layer 107, and thehigh dielectric layer 105 may be shaped to enclose theinterface layer 106. Theetch stop layer 104 may be shaped to surround thehigh dielectric layer 106. - Referring to
FIG. 2F , a second through portion OP2 may be formed in a portion of thestack body 100S. The second through portion OP2 may be, for example, a hole or a slit that is formed through an anisotropic etching process, such as reactive ion etching (RIE). The second through portion OP2 may be referred to as an opening. The first through portion OP1 may have a hole shape, and the second through portion OP2 may have a slit shape. - The second through portion OP2 may penetrate through the
second layer 103, thesacrificial layer 102A, and thefirst layer 101 in a substantially vertical manner. The sidewall of the second through portion OP2 may be formed by etching the surface of thefirst layer 101, thesacrificial layer 102A, and thesecond layer 103. -
FIGS. 2G and 2H illustrate a series of processes for replacing thesacrificial layer 102A with theconductive layer 102. - Referring to
FIG. 2G , thesacrificial layer 102A may be selectively removed. When an etchant or an etching gas is supplied to the second through portion OP2, thesacrificial layer 102A may be selectively etched. For example, when thesacrificial layer 102A is silicon oxide, the silicon oxide may be etched by supplying an etchant with hydrofluoric acid to the second through portion OP2. Thefirst layer 101 and thesecond layer 103 may include, for example, silicon nitride or a metal material. The metal material and silicon nitride may have an etch resistance to an etchant with hydrofluoric acid. - According to another embodiment of the present invention, when the
sacrificial layer 102A is silicon nitride, silicon nitride may be etched by supplying an etchant with phosphoric acid to the second through portion OP2. Thefirst layer 101 and thesecond layer 103 may be, for example, silicon oxide, and the silicon oxide may have an etch resistance to an etchant with phosphoric acid. - The etching of the
sacrificial layer 102A may proceed from an end surface of thesacrificial layer 102A that is exposed through the second through portion OP2. The end surface of thesacrificial layer 102A may be recessed in a diametral direction or a width direction through the second through portion OP2. - By etching the
sacrificial layer 102A, an air gap AG, continuous from the second through portion OP2, may be formed between thefirst layer 101 and thesecond layer 103. Thesacrificial layer 102A might not remain between thefirst layer 101 and thesecond layer 103. For example, all of thesacrificial layer 102A may be removed, and as a result, theetch stop layer 104 may be exposed. The air gap AG may be formed between the second through portion OP2 and theetch stop layer 104. Theetch stop layer 104 may control the end point of the etching process for thesacrificial layer 102A. The etching process of thesacrificial layer 102A may include a dip-out process. - As described above, the
etch stop layer 104 may protect thehigh dielectric layer 105 while thesacrificial layer 102A is etched. - According to another embodiment of the present invention, after the
sacrificial layer 102A is removed, a process to convert theetch stop layer 104 may be performed. The converting process may expose theetch stop layer 104 to a plasma treatment or a thermal treatment. Theetch stop layer 104 may be converted to a carbon-free material through the converting process. For example, SiCO may be converted to SiO2. - Referring to
FIG. 2H , aconductive layer 102 may be formed. Theconductive layer 102 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Theconductive layer 102 may include titanium nitride, tungsten, or a stack of titanium nitride and tungsten. Theconductive layer 102 may be formed in the air gap AG. Theconductive layer 102 may be formed by depositing a conductive material to fill the air gap AG and then by performing an etch-back process on the conductive material. Theconductive layer 102 may be disposed between thefirst layer 101 and thesecond layer 103. Theconductive layer 102 may serve as a gate electrode. - The
conductive layer 102 may fully fill the air gap AG, while not overflowing into the second through portion OP2. Theconductive layer 102 may be in direct contact with theetch stop layer 104. - As described above, since the air gap AG is filled only with the
conductive layer 102, the gap-fill characteristic of theconductive layer 102 may be improved. No material, other than theconductive layer 102, may be formed in the air gap AG. For example, theetch stop layer 104, thehigh dielectric layer 105, and theinterface layer 106 might not be formed in the air gap AG. Accordingly, the volume of theconductive layer 102, filling the air gap AG, may be increased. - A multi-layered stack may be formed between the
active layer 107 and theconductive layer 102. The multi-layered stack may include anetch stop layer 104, ahigh dielectric layer 105, and aninterface layer 106. Theconductive layer 102 may be a ring type, the hole being formed by surrounding thepillar structure 100P. When theconductive layer 102 includes a metal material, a transistor with a vertical channel high-k metal gate (HKMG) structure may be formed. The vertical channel CH may be formed in a substantially vertical manner in theactive layer 107 between the firstdoped region 108 and the seconddoped region 109. -
FIGS. 3A and 3B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention. - First of all, the air gap AG may be formed through a series of processes that are illustrated in
FIGS. 2A to 2G . - Subsequently, as illustrated in
FIG. 3A , a portion of theetch stop layer 104, exposed by the air gap AG, may be removed. As a result, some surfaces 105S of thehigh dielectric layer 105 may be exposed, and the air gap AG may be horizontally extended. In other words, the widened air gap AG may be formed. The air gap AG may be horizontally wider than the air gap AG ofFIG. 2G . - The process for removing a portion of the
etch stop layer 104 may include dry etching. According to another embodiment of the present invention, even when theetch stop layer 104 is converted to SiO2, a portion of theetch stop layer 104 may be removed through a dry etching process. - Referring to
FIG. 3B , aconductive layer 102 may be formed. Theconductive layer 102 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Theconductive layer 102 may include titanium nitride, tungsten, or a stack of titanium nitride and tungsten. Theconductive layer 102 may be formed in the air gap AG. Theconductive layer 102 may be formed by depositing a conductive material to fill the air gap AG and then by performing an etch-back process on the conductive material. Theconductive layer 102 may be disposed between thefirst layer 101 and thesecond layer 103. Theconductive layer 102 may serve as a gate electrode. - The
conductive layer 102 may fully fill the air gap AG, while not overflowing into the second through portion OP2 and. Theconductive layer 102 may be in direct contact with thehigh dielectric layer 105. - As described above, since the air gap AG is filled only with the
conductive layer 102, the gap-fill characteristic of theconductive layer 102 may be improved. No material, other than theconductive layer 102, may be formed in the air gap AG. For example, theetch stop layer 104, thehigh dielectric layer 105, and theinterface layer 106 might not be formed in the air gap AG. Accordingly, the volume of theconductive layer 102, filling the air gap AG, may be increased. - A multi-layered stack may be formed between the
active layer 107 and theconductive layer 102. The multi-layered stack may include ahigh dielectric layer 105 and aninterface layer 106. Theconductive layer 102 may be a ring type, the hole being formed by surrounding thepillar structure 100P. When theconductive layer 102 includes a metal material, a transistor with a vertical channel high-k metal gate (HKMG) structure may be formed. The vertical channel CH may be formed in a substantially vertical manner in theactive layer 107 between the firstdoped region 108 and the seconddoped region 109. - The
high dielectric layer 105 and theinterface layer 106 may remain between the vertical channel CH and theconductive layer 102. Theetch stop layer 104, thehigh dielectric layer 105, and theinterface layer 106 may remain between thefirst layer 101 and the seconddoped region 109. Theetch stop layer 104, thehigh dielectric layer 105, and theinterface layer 106 may remain between thesecond layer 103 and the firstdoped region 108. -
FIGS. 4A and 4B illustrate a semiconductor device according to a modified example ofFIG. 1A .FIG. 4B is a plan view taken along a line A1-A2 ofFIG. 4A . Thesemiconductor device 100A may be similar to thesemiconductor device 100 ofFIG. 1A . Hereinafter, detailed description on the constituent elements appearing in common will be omitted. - Referring to
FIGS. 4A and 4B , thesemiconductor device 100A may include astack body 100S and a pillar structure 100PA penetrating through thestack body 100S. - The
stack body 100S may include afirst layer 101, asecond layer 103, and aconductive layer 102 provided between thefirst layer 101 and thesecond layer 103. For example, thefirst layer 101 may be formed over a substrate or another layer that is not shown. Theconductive layer 102 may be formed over thefirst layer 101, and thesecond layer 103 may be formed over theconductive layer 102. Theconductive layer 102 may be disposed between thefirst layer 101 and thesecond layer 103. Thefirst layer 101, theconductive layer 102, and thesecond layer 103 may be stacked vertically in the first direction D1. Theconductive layer 102 may have a shape surrounding the sidewall of the pillar structure 100PA. Theconductive layer 102 may have a planar shape that is parallel to the second direction D2. - The pillar structure 100PA may extend vertically in the first direction D1. The pillar structure 100PA may be referred to as a vertical pillar structure. The pillar structure 100PA may include the
etch stop layer 104, thehigh dielectric layer 105, theinterface layer 106, and theactive layer 107A. Theactive layer 107A may include a firstdoped region 108 and a seconddoped region 109. A vertical channel CH may be defined between the firstdoped region 108 and the seconddoped region 109. The firstdoped region 108 and the seconddoped region 109 may be referred to as source and drain regions. Theetch stop layer 104, thehigh dielectric layer 105, and theinterface layer 106 may have a shape whose top and bottom are opened. Theactive layer 107A may have a shape whose top and bottom are opened. According to another embodiment of the present invention, theactive layer 107A may be a tube shape or cylinder shape with an inner space. The inner space of theactive layer 107A may be filled with acore dielectric layer 107′. The bottom surfaces of theetch stop layer 104, thehigh dielectric layer 105, theinterface layer 106, and theactive layer 107A may be positioned at the same level. - The
etch stop layer 104 may continue in the first direction D1. Theetch stop layer 104, thehigh dielectric layer 105, and theinterface layer 106 may be formed between the vertical channel CH and theconductive layer 102. Theetch stop layer 104, thehigh dielectric layer 105, and theinterface layer 106 may be formed between thefirst layer 101 and the seconddoped region 109. Theetch stop layer 104, thehigh dielectric layer 105, and theinterface layer 106 may be formed between thesecond layer 103 and the firstdoped region 108. Theconductive layer 102 may directly contact theetch stop layer 104. -
FIGS. 5A and 5B illustrate a semiconductor device according to a modified example ofFIG. 4A .FIG. 5B is a plan view taken along a line A1-A2 ofFIG. 5A . The semiconductor device 100B may be similar to thesemiconductor device 100A ofFIG. 4A . Hereinafter, detailed description on the constituent elements appearing in common will be omitted. - Referring to
FIGS. 5A and 5B , the semiconductor device 100B may include astack body 100S and a pillar structure 100PB penetrating through thestack body 100S. - The pillar structure 100PB may extend vertically in the first direction D1. The pillar structure 100PB may be referred to as a vertical pillar structure. The pillar structure 100PB may include an
etch stop layer 104, ahigh dielectric layer 105, aninterface layer 106, and anactive layer 107A. Theactive layer 107A may include a firstdoped region 108 and a seconddoped region 109. A vertical channel CH may be defined between the firstdoped region 108 and the seconddoped region 109. The firstdoped region 108 and the seconddoped region 109 may be referred to as source and drain regions. Thehigh dielectric layer 105 and theinterface layer 106 may have a shape whose top and bottom are opened. Theactive layer 107A may have a shape whose top and bottom are opened. According to another embodiment of the present invention, theactive layer 107A may be a tube shape or cylinder shape with an inner space. The inner space of theactive layer 107A may be filled with acore dielectric layer 107′. The bottom surfaces of thehigh dielectric layer 105, theinterface layer 106, and theactive layer 107A may be positioned at the same level. - The
etch stop layer 104 may be discontinuous in the first direction D1. Thehigh dielectric layer 105 and theinterface layer 106 may be formed between the vertical channel CH and theconductive layer 102, and theetch stop layer 104 may not be formed. Theetch stop layer 104, thehigh dielectric layer 105, and theinterface layer 106 may be formed between thefirst layer 101 and the seconddoped region 109. Theetch stop layer 104, thehigh dielectric layer 105, and theinterface layer 106 may be formed between thesecond layer 103 and the firstdoped region 108. Theconductive layer 102 may directly contact thehigh dielectric layer 105. -
FIGS. 6A and 6B illustrate a semiconductor device in accordance with another embodiment of the present invention.FIG. 6B is a plan view taken along a line A1-A2 ofFIG. 6A . - Referring to
FIGS. 6A and 6B , thesemiconductor device 100N may include astack body 110 and apillar structure 110P, thepillar structure 110P penetrating through thestack body 110 in a substantially vertical manner. - The
stack body 110 may include afirst layer 111, asecond layer 113, and aconductive layer 124, theconductive layer 124 being formed between thefirst layer 111 and thesecond layer 113. For example, thefirst layer 111 may be formed over a substrate or another layer that is not shown. Theconductive layer 124 may be formed over thefirst layer 111, and thesecond layer 113 may be formed over theconductive layer 124. Theconductive layer 124 may be disposed between thefirst layer 111 and thesecond layer 113. Thefirst layer 111, theconductive layer 124, and thesecond layer 113 may be stacked vertically in the first direction D1. Theconductive layer 124 may include a material that is different from thefirst layer 111 and thesecond layer 113, and thefirst layer 111 and thesecond layer 113 may be of the same material or different materials. Thefirst layer 111 and thesecond layer 113 may include a dielectric material. Thefirst layer 111 and thesecond layer 113 may include silicon oxide, silicon nitride, or a combination thereof. Thefirst layer 111 and thesecond layer 113 may have the same thickness. Thefirst layer 111, theconductive layer 124, and thesecond layer 113 may have the same thickness. According to another embodiment of the present invention, theconductive layer 124 may be thicker than thefirst layer 111 and thethird layer 113. Theconductive layer 124 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Theconductive layer 124 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten (TiN/W). Theconductive layer 124 may be shaped to surround a sidewall of thepillar structure 110P. Theconductive layer 124 may have a planar shape that is parallel to the second direction D2. - The
pillar structure 110P may extend in a substantially vertical manner in the first direction D1. Thepillar structure 110P may be referred to as a vertical pillar structure. Thepillar structure 110P may include anetch stop layer 115, afirst blocking layer 116, asecond blocking layer 117, acharge trapping layer 118, atunnel dielectric layer 119, achannel layer 120, and acore dielectric layer 121. Thepillar structure 110P may fill a first through portion (not marked, refer to 114 ofFIG. 7B ). - The
etch stop layer 115 may be thinner than thefirst layer 111, theconductive layer 124, and thesecond layer 113. Theetch stop layer 115 may include a material that is different from that of theconductive layer 124. Theetch stop layer 115 may include a material that is different from those of thefirst layer 111 and thesecond layer 113. Theetch stop layer 115 may include a dielectric material. Theetch stop layer 115 may be a carbon-containing material, and thefirst layer 111 and thesecond layer 113 may be carbon-free materials. Thefirst layer 111 and thesecond layer 113 may be carbon-free silicon oxide, and theetch stop layer 115 may be carbon-containing silicon oxide. For example, thefirst layer 111 and thesecond layer 113 may be SiO2, and theetch stop layer 115 may be SiCO. SiCO may be more etch-resistant than SiO2. - The
first blocking layer 116 may include a material that is different from that of theetch stop layer 115. Thefirst blocking layer 116 may be a metal-containing material. Thefirst blocking layer 116 may include a metal oxide. Thefirst blocking layer 116 may have a greater dielectric constant than theetch stop layer 115. Thefirst blocking layer 116 may include a high-k material. For example, thefirst blocking layer 116 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof. Thefirst blocking layer 116 may be thicker than theetch stop layer 115. - The
second blocking layer 117 may include a low-k material. Thesecond blocking layer 117 may include a material that is different from those of theetch stop layer 115 and thefirst blocking layer 116. Thesecond blocking layer 117 may include silicon oxide and may be free of carbon. Thesecond blocking layer 117 may be thicker than thefirst blocking layer 116. - The
charge trapping layer 118 may include a charge trapping dielectric material, such as silicon nitride. Thecharge trapping layer 118 may be formed to cover thesecond blocking layer 117. - The
tunnel dielectric layer 119 may be formed over thecharge trapping layer 118. Thetunnel dielectric layer 119 may include silicon oxide. - The
channel layer 120 may be formed over thetunnel dielectric layer 119. Thechannel layer 120 may include a semiconductor material. For example, thechannel layer 120 may include any one among a polycrystalline semiconductor material, an amorphous semiconductor material, and a monocrystalline semiconductor material. Thechannel layer 120 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound. Thechannel layer 120 may include polysilicon. - At least one or more other layers, including the
core dielectric layer 121, may be further formed over thechannel layer 120. - Referring to
FIGS. 6A and 6B , thesemiconductor device 100N may be part of a NAND memory cell, and theconductive layer 124 may be a gate electrode or a word line. As will be described later, theconductive layer 124 may be formed by replacing the sacrificial layer with a conductive material through the second throughportion 122. During the process of replacing the sacrificial layer with theconductive layer 124, theetch stop layer 115 may protect thefirst blocking layer 116. -
FIGS. 7A to 7H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention. - Referring to
FIG. 7A , astacked body 110 may be prepared. Thestack body 110 may include afirst layer 111, asecond layer 113, and asacrificial layer 112, thesacrificial layer 112 being formed between thefirst layer 111 and thesecond layer 113. - For example, the
first layer 111 may be formed over a substrate or another layer (not shown). Thesacrificial layer 112 may be formed over thefirst layer 111, and thesecond layer 113 may be formed over thesacrificial layer 112. Thesacrificial layer 112 may be disposed between thefirst layer 111 and thesecond layer 113. - The
sacrificial layer 112 may include a material that is different from those of thefirst layer 111 and thesecond layer 113. Furthermore, the etching selectivity of thesacrificial layer 112, with respect to thefirst layer 111 and thesecond layer 113, may be sufficiently large. Thefirst layer 111 and thesecond layer 113 may be of the same material or of different materials. - The
first layer 111 and thesecond layer 113 may include silicon oxide, and thesacrificial layer 112 may include silicon nitride, a metal material, or polysilicon. Thefirst layer 111 and thesecond layer 113 may include silicon nitride, and thesacrificial layer 112 may include silicon oxide. - Referring to
FIG. 7B , a first throughportion 114 may be formed in thestack body 110. The first throughportion 114 may be, for example, a hole or a slit that is formed through an anisotropic etching process, such as reactive ion etching (RIE). The first throughportion 114 may also be referred to as an opening. - The first through
portion 114 may penetrate through thesecond layer 113, thesacrificial layer 112, and thefirst layer 111 in a substantially vertical manner. A sidewall of the first throughportion 114 may be formed by etching the surface of thefirst layer 111, thesacrificial layer 112, and thesecond layer 113. - Referring to
FIG. 7C , theetch stop layer 115 may be formed to cover the sidewall of the first throughportion 114. Theetch stop layer 115 may be formed to cover the sidewall of the first throughportion 114. Theetch stop layer 115 may be thinner than thefirst layer 111, thesacrificial layer 112, and thesecond layer 113. Theetch stop layer 115 may include a material that is different from that of thesacrificial layer 112. Furthermore, the etching selectivity of theetch stop layer 115, with respect to thesacrificial layer 112, may be sufficiently large. Theetch stop layer 115 may include a material that is different from those of thefirst layer 111 and thesecond layer 113. Theetch stop layer 115 may be a carbon-containing material, and thefirst layer 111 and thesecond layer 113 may be carbon-free materials. Thefirst layer 111 and thesecond layer 113 may be carbon-free silicon oxide, and theetch stop layer 115 may be carbon-containing silicon oxide. For example, thefirst layer 111 and thesecond layer 113 may be SiO2, and theetch stop layer 115 may be SiCO. While thesacrificial layer 112 is etched subsequently, SiCO may be more etch-resistant than SiO2. - Referring to
FIG. 7D , thefirst blocking layer 116 may be formed over theetch stop layer 115. Thefirst blocking layer 116 may include a material that is different from that of theetch stop layer 115. Thefirst blocking layer 116 may be a metal-containing material. Thefirst blocking layer 116 may include a metal oxide. Thefirst blocking layer 116 may have a greater dielectric constant than theetch stop layer 115. Thefirst blocking layer 116 may include a high-k material. For example, thefirst blocking layer 116 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof. Thefirst blocking layer 116 may be thicker than theetch stop layer 115. - The
second blocking layer 117 may be formed over thefirst blocking layer 116. Thesecond blocking layer 117 may include a material that is different from that of thefirst blocking layer 116. Thesecond blocking layer 117 may be thicker than thefirst blocking layer 116. Thesecond blocking layer 117 may have a smaller dielectric constant than thefirst blocking layer 116. Thesecond blocking layer 117 may include a low-k material. Thesecond blocking layer 117 may include a material that is different from that of theetch stop layer 115. Thesecond blocking layer 117 may include silicon oxide and may be free of carbon. - As described above, an in-plugged blocking structure, including the
first blocking layer 116 and thesecond blocking layer 117, disposed in the first throughportion 114, may be formed. When thefirst blocking layer 116 includes alumina (or aluminum oxide), thefirst blocking layer 116 may be referred to as an in-plugged alumina blocking structure. - Referring to
FIG. 7E , acharge trapping layer 118 may be formed over thesecond blocking layer 117. Thecharge trapping layer 118 may include a charge trapping dielectric material, such as silicon nitride. Thecharge trapping layer 118 may be formed through a conformal deposition process, such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). Thecharge trapping layer 118 may be conformally deposited over thesecond blocking layer 117. - A
tunnel dielectric layer 119 may be formed over thecharge trapping layer 118. Thetunnel dielectric layer 119 may include silicon oxide. Thetunnel dielectric layer 119 may be formed through a conformal deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).Tunnel dielectric layer 119 may be conformally deposited over thecharge trapping layer 118. - The
channel layer 120 may be formed over thetunnel dielectric layer 119. Thechannel layer 120 may include a semiconductor material. For example, thechannel layer 120 may include one of a polycrystalline semiconductor material, an amorphous semiconductor material, and a monocrystalline semiconductor material. Thechannel layer 120 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound. Thechannel layer 120 may include polysilicon. Thechannel layer 120 may be formed to cover thetunnel dielectric layer 119 in the first throughportion 114. Thechannel layer 120 might not fill the first throughportion 114. - At least one or more other layers, including a
core dielectric layer 121, may be further formed over thechannel layer 120. Thecore dielectric layer 121 may fill the first throughportion 114. - Referring to
FIG. 7F , a second throughportion 122 may be formed in a portion of thestack body 110. The second throughportion 122 may be, for example, a hole or a slit formed through an anisotropic etching process, such as reactive ion etching (RIE). The second throughportion 122 may be referred to as an opening. The first throughportion 114 may have a hole shape, and the second throughportion 122 may have a slit shape. - The second through
portion 122 may penetrate through thesecond layer 113, thesacrificial layer 112, and thefirst layer 111 in a substantially vertical manner. A sidewall of the second throughportion 122 may be formed by etching the surface of thefirst layer 111, thesacrificial layer 112, and thesecond layer 113. - Referring to
FIG. 7G , thesacrificial layer 112 may be selectively removed. When an etchant or an etching gas is supplied to the second throughportion 122, thesacrificial layer 112 may be selectively etched. For example, when thesacrificial layer 112 is silicon oxide, the silicon oxide may be etched by supplying an etchant with hydrofluoric acid to the second throughportion 122. Thefirst layer 111 and thesecond layer 113 may be, for example, silicon nitride or a metal material, and the metal material and silicon nitride may have etch resistance to an etchant with hydrofluoric acid. - According to another embodiment of the present invention, when the
sacrificial layer 112 is silicon nitride, the silicon nitride may be etched by supplying an etchant with phosphoric acid to the second throughportion 122. Thefirst layer 111 and thesecond layer 113 may be, for example, silicon oxide, and the silicon oxide may have etch resistance to an etchant with phosphoric acid. - The etching of the
sacrificial layer 112 may proceed from an end surface of thesacrificial layer 112 exposed through the second throughportion 122. The end surface of thesacrificial layer 112 may be recessed in a diametral or width direction through the second throughportion 122. - By etching the
sacrificial layer 112, anair gap 123, continuous from the second throughportion 122, may be formed between thefirst layer 111 and thesecond layer 113. Thesacrificial layer 112 might not remain between thefirst layer 111 and thesecond layer 113. For example, all of thesacrificial layers 112 may be removed, and as a result, theetch stop layer 115 may be exposed. Theair gap 123 may be formed between the second throughportion 122 and theetch stop layer 115. Theetch stop layer 115 may control the end point of the etching process for thesacrificial layer 112. The etching process of thesacrificial layer 112 may include a dip-out process. - As described above, the
etch stop layer 115 may protect thefirst blocking layer 116 while thesacrificial layer 112 is etched. - According to another embodiment of the present invention, after the
sacrificial layer 112 is removed, a converting process for theetch stop layer 115 may be performed. The converting process may expose theetch stop layer 115 to a plasma treatment or a thermal treatment. Theetching stop layer 115 may be converted into a carbon-free material through the converting process. For example, SiCO may be converted to SiO2. - Referring to
FIG. 7H , aconductive layer 124 may be formed. Theconductive layer 124 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Theconductive layer 124 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten. Theconductive layer 124 may be formed in theair gap 123. Theconductive layer 124 may be formed by depositing a conductive material to fill theair gap 123 and then by performing an etch-back process on the conductive material. Theconductive layer 124 may be disposed between thefirst layer 111 and thesecond layer 113. Theconductive layer 124 may serve as a gate electrode. - The
conductive layer 124 may fully fill theair gap 123, while not overflowing into the second throughportion 122. Theconductive layer 124 may directly contact theetch stop layer 115. - As described above, since the
air gap 123 is filled only with theconductive layer 124, the gap-fill characteristic of theconductive layer 124 may be improved. No material, other than theconductive layer 124, may be formed in theair gap 123. For example, theetch stop layer 115, thefirst blocking layer 116, and thesecond blocking layer 117 might not be formed in theair gap 123. Accordingly, the gap between theconductive layers 124 that are adjacent to each other vertically may be reduced. - A multi-layered stack may be formed between the
channel layer 120 and theconductive layer 124. The multi-layered stack may include theetch stop layer 115, thefirst blocking layer 116, thesecond blocking layer 117, thecharge trapping layer 118, and thetunnel dielectric layer 119. -
FIGS. 8A and 8B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention. - First, an
air gap 123 may be formed through a series of processes illustrated inFIGS. 7A to 7G . - Subsequently, as shown in
FIG. 8A , a portion of theetch stop layer 115, exposed by theair gap 123, may be removed. Accordingly, some surfaces 116S of thefirst blocking layer 116 may be exposed, and theair gap 123 may be horizontally extended. In other words, the widenedair gap 123′ may be formed. Theair gap 123′ may be horizontally wider than theair gap 123 ofFIG. 7G . - The process to remove a portion of the
etch stop layer 115 may include dry etching. According to another embodiment of the present invention, even when theetch stop layer 115 is converted into SiO2, a portion of theetch stop layer 115 may be removed by dry etching. - Referring to
FIG. 8B , aconductive layer 124 may be formed. Theconductive layer 124 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Theconductive layer 124 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten. Theconductive layer 124 may be formed in theair gap 123′. Theconductive layer 124 may be formed by depositing a conductive material to fill theair gap 123′ and then by performing an etch-back process on the conductive material. Theconductive layer 124 may be disposed between thefirst layer 111 and thesecond layer 113. Theconductive layer 124 may serve as a gate electrode. - The
conductive layer 124 may fully fill theair gap 123′, while not overflowing into the second throughportion 122. Theconductive layer 124 may be in direct contact with thefirst blocking layer 116. - As described above, since the
air gap 123′ is filled only with theconductive layer 124, the gap-fill characteristic of theconductive layer 124 may be improved. No material, other than theconductive layer 124, may be formed in theair gap 123′. For example, theetch stop layer 115, thefirst blocking layer 116, and thesecond blocking layer 117 might not be formed in theair gap 123′. Accordingly, the volume of theconductive layer 124 filling theair gap 123′ may be increased. -
FIGS. 9A and 9B illustrates asemiconductor device 200V in accordance with another embodiment of the present invention.FIG. 9B is a plan view taken along a line A1-A2 ofFIG. 9A . - Referring to
FIGS. 9A and 9B , thesemiconductor device 200V may include a vertical NAND. Thesemiconductor device 200V may include a three-dimensional (3D) NAND. Thesemiconductor device 200V may include alower structure 200L, astack body 210 over thelower structure 200L, and avertical channel structure 220 that penetrates through thestack body 210. - The
lower structure 200L may include a substrate. According to another embodiment of the present invention, thelower structure 200L may include a peripheral circuit. The peripheral circuit unit may include a plurality of control circuits. At least one control circuit of the peripheral circuit portion may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit may include a planar channel transistor, a recess channel transistor, a buried gate transistor, a fin channel transistor (FinFET), and the like. Thelower structure 200L and thestack body 210 may be interconnected to each other through a multi-level metal wire (not shown). - The
stack body 210 may include a stack ofword lines 212 anddielectric layers 211, stacked in an alternating manner, positioned over thelower structure 200L. Thevertical channel structure 220, including achannel layer 226, may be formed in the through portion that penetrates through the alternating stack. Afirst blocking layer 222 may be formed in the through portion to surround the outer wall of thechannel layer 225. Anetch stop layer 221, surrounding the outer wall of thefirst blocking layer 222, may be included in the through portion. Theetch stop layer 221 may be in direct contact with the word lines 212 and the dielectric layers 211. Theetch stop layer 221 may be a continuous etch stop layer, extending vertically along the stacking direction of the alternating stack. Thefirst blocking layer 222 may extend vertically in the stacking direction of the alternating stack. - The
stack body 210 may be formed by stacking thedielectric layer 211 and theword line 212 in an alternating manner. Thevertical channel structure 220 may penetrate through thestack body 210 in a substantially vertical manner. - The
word line 212 may include a material that surrounds thevertical channel structure 220. - The
vertical channel structure 220 may include anetch stop layer 221 which is in contact with theword line 212, afirst blocking layer 222, asecond blocking layer 223, acharge trapping layer 224, atunnel dielectric layer 225, and achannel layer 226. The inner space of thechannel layer 226 may be filled with thecore dielectric layer 227. - The
dielectric layer 211 may be formed over thelower structure 200L. Theword line 212 may be disposed between the dielectric layers 211. Theword line 212 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Theword line 212 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten (TiN/W). Theword line 212 may be shaped to surround the sidewall of thevertical channel structure 220. Theword line 212 may have a planar shape. - The
etch stop layer 221 may include a dielectric material. Theetch stop layer 221 may be a carbon-containing material, and thedielectric layer 211 may be a carbon-free material. Thedielectric layer 211 may be a carbon-free silicon oxide, and theetch stop layer 221 may be a carbon-containing silicon oxide. For example, thedielectric layer 211 may be SiO2, and theetch stop layer 221 may be SiCO. SiCO may be more etch-resistant than SiO2. Theetch stop layer 221 may be a continuous etch stop layer that is continuous along the stacking direction of thedielectric layer 211 and theword line 212. - The
first blocking layer 222 may include a material that is different from that of theetch stop layer 221. Thefirst blocking layer 222 may be a metal-containing material. Thefirst blocking layer 222 may include a metal oxide. Thefirst blocking layer 222 may have a greater dielectric constant than theetch stop layer 221. Thefirst blocking layer 222 may include a high-k material. For example, thefirst blocking layer 222 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof. Thefirst blocking layer 222 may be thicker than theetch stop layer 221. - The
second blocking layer 223 may include a low-k material. Thesecond blocking layer 223 may include a material that is different from those of theetch stop layer 221 and thefirst blocking layer 222. Thesecond blocking layer 223 may include silicon oxide and may be free of carbon. Thesecond blocking layer 223 may be thicker than thefirst blocking layer 222. - The
charge trapping layer 224 may include a charge trapping dielectric material, such as silicon nitride. Thecharge trapping layer 224 may be formed to cover thesecond blocking layer 222. - A
tunnel dielectric layer 225 may be formed over thecharge trapping layer 224. Thetunnel dielectric layer 225 may include silicon oxide. - The
channel layer 226 may be formed over thetunnel dielectric layer 225. Thechannel layer 226 may include a semiconductor material. For example, thechannel layer 226 may include any one among a polycrystalline semiconductor material, an amorphous semiconductor material, and a monocrystalline semiconductor material. Thechannel layer 226 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound. Thechannel layer 226 may include polysilicon. - At least one or more other layers, including a
core dielectric layer 227, may be further formed over thechannel layer 226. - Referring to
FIGS. 9A and 9B , a blocking-free structure in which only theword line 212 is disposed may be formed between the dielectric layers 211. As a result, the resistance of theword line 212 may be reduced by increasing the volume of theword line 212 without decreasing the height of the memory cell stack. - The
etch stop layer 221 may have a thickness that is thinner than that of thefirst blocking layer 222, and thus might not cause deterioration in the characteristics of a capacitor between theword line 212 and thecharge trapping layer 224. Theetch stop layer 221 may have a thickness of approximately 30 Å. -
FIGS. 10A to 10H are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention. - Referring to
FIG. 10A , an alternatingstack 11M may be formed over thesubstrate 11. Thesubstrate 11 may be a material that is suitable for semiconductor processing. Thesubstrate 11 may include a semiconductor substrate. For example, thesubstrate 11 may be a silicon substrate, a monocrystalline silicon substrate, a polysilicon substrate, an amorphous silicon substrate, a silicon germanium substrate, a monocrystalline silicon germanium substrate, a polycrystalline silicon germanium substrate, a carbon-doped silicon substrate, a combination thereof, or a multi-layer thereof. Thesubstrate 11 may include other semiconductor materials, such as germanium. Thesubstrate 11 may include a group III/V semiconductor substrate, such as a compound semiconductor substrate, e.g., GaAs. Thesubstrate 11 may include a Silicon-On-Insulator (SOI) substrate. - The alternating
stack 11M may be a stack body in which the first material layer and the second material layer may be alternately stacked. The first material layer may include a first material, and the second material layer may include a second material. The first material and the second material may be of different materials. The first material layer and the second material layer may include adielectric layer 12 and asacrificial layer 13, respectively. Thedielectric layer 12 may include a dielectric material, and thesacrificial layer 13 may include a sacrificial material. Herein, the ‘sacrificial material’ may refer to a substance to be removed in the subsequent process. Thedielectric layer 12 may include at least one dielectric material among silicon oxide, silicon nitride, silicon oxynitride, a spin-on-dielectric material (SOD), a dielectric metal oxide, a silicate, and a dielectric metal oxynitride. - The
sacrificial layer 13 may include a sacrificial material that may be selectively removed with respect to thedielectric layer 12. Herein, the removal of thesacrificial layer 13 may be optional with respect to thedielectric layer 12. The ratio of the removal rate of thesacrificial layer 13 to the removal rate of thedielectric layer 12 may be referred to as a selectivity of the removal process of thesacrificial layer 13 with respect to thedielectric layer 12. - The
sacrificial layer 13 may include a dielectric material. Thesacrificial layer 13 may be replaced with a conductive material in a subsequent process. For example, it may be replaced with the gate electrode (or word line) of the vertical NAND device. Thesacrificial layer 13 may include silicon nitride, amorphous silicon, or polysilicon. According to an embodiment of the present invention, thesacrificial layer 13 may include silicon nitride. - According to the embodiment of the present invention, the
dielectric layer 12 may include silicon oxide, and thesacrificial layer 13 may include silicon nitride. - The alternating number of
dielectric layers 12 andsacrificial layers 13, in the alternatingstack 11M, may be determined according to the number of memory cells. For example, when 48 memory cells are stacked vertically, thedielectric layer 12 and thesacrificial layer 13 may be stacked 48 times, individually. Thedielectric layer 12 and thesacrificial layer 13 may be repeatedly stacked in a direction that is perpendicular to the surface of thesubstrate 11. - The
dielectric layer 12 may be deposited through a Chemical Vapor Deposition (CVD) process or Atomic Layer Deposition (ALD) process. Thesacrificial layer 13 may be deposited through a chemical vapor deposition process or an atomic layer deposition process. - The bottom and top layers of the alternating
stack 11M may be the dielectric layers 12. Thedielectric layer 12 and thesacrificial layer 13 may have the same thickness. Thetop dielectric layer 12 may be thicker than the other dielectric layers 12. Thetop dielectric layer 12 may be referred to as a dielectric cap layer. - Referring to
FIG. 10B , a first throughportion 14 may be formed in the alternatingstack 11M. A portion of the alternatingstack 11M may be etched using a mask (not shown) to form the first throughportion 14. The mask may include a resist pattern, and the resist pattern may be formed by applying a resist material and performing a photolithography process. The resist material may include a photoresist. The process of etching the alternatingstack 11M to form the first throughportion 14 may include an anisotropic etch process. For example, the anisotropic etching may include reactive ion etching (RIE). The reactive ion etching of thedielectric layers 12 and the reactive ion etching of thesacrificial layers 13 may be performed continuously. - The first through
portion 14 may penetrate through the alternatingstack 11M and extend in a direction that is perpendicular to the surface of thesubstrate 11. The bottom of the first throughportion 14 may expose the surface of thesubstrate 11. The first throughportion 14 may include a vertical hole. A plurality of first throughportions 14 may be arranged. From the perspective of a top view, the first throughportions 14 may be arranged in a zigzag arrangement. Each of the first throughportions 14 may have a uniform size. - The sidewall of the first through
portion 14 may have a vertical profile. According to another embodiment of the present invention, the sidewall of the first throughportion 14 may have a sloped profile. The first throughportion 14 may be referred to as a channel hole or a vertical hole. - The first through
portion 14 may penetrate through thedielectric layers 12 and thesacrificial layers 13 in a substantially vertical manner. The sidewall of the first throughportion 14 may be formed by etching the surface of thedielectric layers 12 and the sacrificial layers 13. - Referring to
FIG. 10C , anetch stop layer 15 may be formed to cover the sidewall of the first throughportion 14. Theetch stop layer 15 may be formed to cover the sidewall of the first throughportion 14. Although not shown, theetch stop layer 15 may cover the bottom surface of the first throughportion 14. Theetch stop layer 15 may be thinner than thedielectric layer 12 and thesacrificial layer 13. Theetch stop layer 15 may include of a material that is different from thesacrificial layer 13. Furthermore, the etching selectivity of theetch stop layer 15, with respect to thesacrificial layer 13, may be sufficiently large. Theetch stop layer 15 may include a material that is different from that of thedielectric layer 12. Theetch stop layer 15 may be a carbon-containing material, and thedielectric layer 12 may be a carbon-free material. Thedielectric layer 12 may be carbon-free silicon oxide, and theetch stop layer 15 may be carbon-containing silicon oxide. For example, thedielectric layer 12 may be SiO2 and theetch stop layer 15 may be SiCO. While the subsequentsacrificial layer 13 is etched, SiCO may be more etch resistant than SiO2. - The
etch stop layer 15 may have a thickness of approximately 30 Å. - Referring to
FIG. 10D , afirst blocking layer 16 may be formed over theetch stop layer 15. Thefirst blocking layer 16 may include a material that is different from that of theetch stop layer 15. Thefirst blocking layer 16 may be a metal-containing material. Thefirst blocking layer 16 may include a metal oxide. Thefirst blocking layer 16 may have a greater dielectric constant than theetch stop layer 15. Thefirst blocking layer 16 may include a high-k material. For example, thefirst blocking layer 16 may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof. Thefirst blocking layer 16 may be thicker than theetch stop layer 15. Thefirst blocking layer 16 may be formed to a thickness of approximately 20 Å to 100 A. - The
second blocking layer 17 may be formed over thefirst blocking layer 16. Thesecond blocking layer 17 may include a material that is different from that of thefirst blocking layer 16. Thesecond blocking layer 17 may be thicker than thefirst blocking layer 16. Thesecond blocking layer 17 may have a smaller dielectric constant than that of thefirst blocking layer 16. Thesecond blocking layer 17 may include a low-k material. Thesecond blocking layer 17 may include a material that is different from that of theetch stop layer 15. Thesecond blocking layer 17 may include silicon oxide and may be free of carbon. - As described above, an in-plugged blocking structure, including the
first blocking layer 16 and thesecond blocking layer 17, disposed in the first throughportion 14, may be formed. When thefirst blocking layer 16 includes alumina (or aluminum oxide), thefirst blocking layer 16 may be called an in-plugged alumina blocking structure. - Referring to
FIG. 10E , acharge trapping layer 18 may be formed over thesecond blocking layer 17. Thecharge trapping layer 18 may include a charge trapping dielectric material, such as silicon nitride. Thecharge trapping layer 18 may be formed through a conformal deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Thecharge trapping layer 18 may be conformally deposited over thesecond blocking layer 17. - A
tunnel dielectric layer 19 may be formed over thecharge trapping layer 18. Thetunnel dielectric layer 19 may include silicon oxide. Thetunnel dielectric layer 19 may be formed through a conformal deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Thetunnel dielectric layer 19 may be conformally deposited over thecharge trapping layer 18. - According to another embodiment of the present invention, although not illustrated, the
first blocking layer 16, thesecond blocking layer 17, thecharge trapping layer 18, and thetunnel dielectric layer 19 may cover the bottom surface of the first throughportion 14. After thetunnel dielectric layer 19 is formed, a portion of thetunnel dielectric layer 19 may be cut from the bottom surface of the first throughportion 14. After thetunnel dielectric layer 19 is cut, thecharge trapping layer 18, thesecond blocking layer 17, thefirst blocking layer 16 and theetch stop layer 15 may be sequentially cut from the bottom surface of the first throughportion 14. - The
channel layer 20 may be formed over thetunnel dielectric layer 19. Thechannel layer 20 may include a semiconductor material. For example, thechannel layer 20 may include any one among a polycrystalline semiconductor material, an amorphous semiconductor material, or a monocrystalline semiconductor material. Thechannel layer 20 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), a group III-V compound, or a group II-VI compound. Thechannel layer 20 may include polysilicon. Thechannel layer 20 may be formed to cover thetunnel dielectric layer 19 in the first throughportion 14. Thechannel layer 20 might not fill the first throughportion 14. - At least one or more other layers including a
core dielectric layer 21 may be further formed over thechannel layer 20. Thecore dielectric layer 21 may fill the first throughportion 14. - Referring to
FIG. 10F , a second throughportion 22 may be formed in a portion of the alternatingstack 11M. The second throughportion 22 may be, for example, a hole or a slit that is formed through an anisotropic etching process, such as reactive ion etching (RIE). The second throughportion 22 may be referred to as an opening. The first throughportion 14 may have a hole shape, and the second throughportion 22 may have a slit shape. - The second through
portion 22 may penetrate through thedielectric layers 12 and thesacrificial layers 13 in a substantially vertical manner. The sidewall of the second throughportion 22 may be formed by etching the surface of thedielectric layers 12 and the sacrificial layers 13. - Referring to
FIG. 10G , thesacrificial layers 13 may be selectively removed. When an etchant or an etching gas is supplied to the second throughportion 22, thesacrificial layer 13 may be selectively etched. For example, when thesacrificial layer 13 is silicon oxide, the silicon oxide may be etched by supplying an etchant with hydrofluoric acid to the second throughportion 22. The dielectric layers 12 may be, for example, silicon nitride or a metal material, and the metal material and silicon nitride may have etch resistance to the etchant with hydrofluoric acid. - According to another embodiment of the present invention, when the
sacrificial layers 13 are silicon nitride, the silicon nitride may be etched by supplying an etchant with phosphoric acid to the second throughportion 22. The dielectric layers 12 may be, for example, silicon oxide, and the silicon oxide may have etch resistance to an etchant with phosphoric acid. - The etching of the
sacrificial layers 13 may proceed from an end surface of thesacrificial layer 13 exposed through the second throughportion 22. The end surface of thesacrificial layer 13 may be recessed in the diametral or width direction of the second throughportion 22. - By etching the
sacrificial layer 13, anair gap 23 continuous from the second throughportion 22 may be formed between the dielectric layers 12. Thesacrificial layer 13 might not remain between the dielectric layers 12. For example, all of thesacrificial layer 13 may be removed, and as a result, theetch stop layer 15 may be exposed. Theair gap 23 may be formed between the second throughportion 22 and theetch stop layer 15. Theetch stop layer 15 may control the etching end point at which the etching of thesacrificial layer 13 ends. The process of etching thesacrificial layer 13 may include a dip-out process. - As described above, the
etch stop layer 15 may protect thefirst blocking layer 16 while thesacrificial layer 13 is etched. - According to another embodiment of the present invention, after the
sacrificial layer 13 is removed, a converting process for theetch stop layer 15 may be performed. The converting process may expose theetch stop layer 15 to a plasma treatment or a thermal treatment. Theetching stop layer 15 may be converted to a carbon-free material by the converting process. For example, SiCO may be converted into SiO2. The converting process may include a thermal treatment or a plasma treatment. - Referring to
FIG. 10H , aconductive layer 24 may be formed. Theconductive layer 24 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Theconductive layer 24 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten. Theconductive layer 24 may be formed in theair gap 23. Theconductive layer 24 may be formed by depositing a conductive material to fill theair gap 23 and then performing an etch-back process on the conductive material. Theconductive layer 24 may be disposed between the dielectric layers 12. Theconductive layer 24 may serve as a gate electrode or a word line. - The
conductive layer 24 may fully fill theair gap 23, while not overflowing into the second throughportion 22. Theconductive layer 24 may directly contact theetch stop layer 15. - As described above, since the
air gap 23 is filled only with theconductive layer 24, the gap-fill characteristic of theconductive layer 24 may be improved. No material, other than theconductive layer 24, may be formed in theair gap 23. For example, theetch stop layer 15, thefirst blocking layer 16, and thesecond blocking layer 17 might not be formed in theair gap 23. As a result, the gap between theconductive layers 24 that are vertically adjacent to each other may be reduced. Since thefirst blocking layer 16 is not formed inside theair gap 23, poor step coverage of thefirst blocking layer 16 may be prevented. - A multi-layered stack may be formed between the
channel layer 20 and theconductive layer 24. The multi-layered stack may include anetch stop layer 15, afirst blocking layer 16, asecond blocking layer 17, acharge trapping layer 18, and atunnel dielectric layer 19. - An alternating
stack 11M may be formed over thesubstrate 11, and the alternatingstack 11M may be formed by alternately stacking thedielectric layer 12 and theconductive layer 24. A blocking-free structure in which only theconductive layer 24 is disposed between thedielectric layers 12 may be formed. Theetch stop layer 15 may be disposed between theconductive layer 24 and thefirst blocking layer 16. Theetch stop layer 15 may be disposed between thedielectric layer 12 and thefirst blocking layer 16. -
FIGS. 11A and 11B are cross-sectional views, illustrating an example of a method for fabricating a semiconductor device, in accordance with another embodiment of the present invention. - First, an
air gap 23 may be formed through a series of processes illustrated inFIGS. 10A to 10G . - Subsequently, as shown in
FIG. 11A , a portion of theetch stop layer 15, exposed by theair gap 23, may be removed. As a result, the surface 16S of a portion of thefirst blocking layer 16 may be exposed, and theair gap 23 may horizontally extend. In short, awider air gap 23′ may be formed. Theair gap 23′ may be horizontally wider than theair gap 23 ofFIG. 10G . - The process to remove a portion of the
etch stop layer 15 may include a dry etching process or a wet etching process. According to another embodiment of the present invention, even when theetch stop layer 15 is converted into SiO2, a portion of theetch stop layer 15 may be removed by a dry etching process or a wet etching process. - Referring to
FIG. 11B , aconductive layer 24 may be formed. Theconductive layer 24 may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Theconductive layer 24 may include titanium nitride, tungsten or a stack of titanium nitride and tungsten. Theconductive layer 24 may be formed in theair gap 23′. Theconductive layer 24 may be formed by depositing a conductive material to fill theair gap 23′ and then by performing an etch-back process on the conductive material. Theconductive layer 24 may be disposed between the dielectric layers 12. Theconductive layer 24 may serve as a gate electrode. - The
conductive layer 24 may fully fill theair gap 23′, while not overflowing into the second throughportion 22. Theconductive layer 24 may directly contact thefirst blocking layer 16. - As described above, since the
air gap 23′ is filled only with theconductive layer 24, the gap-fill characteristic of theconductive layer 24 may be improved. No material, other than theconductive layer 24, may be formed in theair gap 23′. For example, theetch stop layer 15, thefirst blocking layer 16, and thesecond blocking layer 17 might not be formed in theair gap 23′. As a result, the volume of theconductive layer 24 filling theair gap 23′ may be increased. - The
conductive layer 24 and thefirst blocking layer 16 may be in direct contact with each other, and theetch stop layer 15 may be disposed between thedielectric layer 12 and thefirst blocking layer 16. - According to the embodiments of the present invention, the resistance of word lines may be reduced by forming the word lines in a blocking-free structure.
- According to the embodiments of the present invention, both the difficulty of a high aspect ratio etching process and the production cost may be reduced by decreasing a pitch of a dielectric layer and a sacrificial layer according to an increase in the number of stacked layers of the dielectric layer and the sacrificial layer so as to reduce the total height.
- According to the embodiments of the present invention, step coverage of a blocking layer may be improved as the number of rows in a memory block increases.
- According to the embodiments of the present invention, it is possible to protect a blocking layer from being attacked by a wet-etch chemical, when a sacrificial layer is removed.
- While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims (14)
1. A method for fabricating a semiconductor device, comprising:
forming an alternating stack of sacrificial layers and dielectric layers over a substrate;
forming a first through portion, penetrating through the alternating stack;
forming an etch stop layer to cover a sidewall of the first through portion;
forming a blocking layer disposed in the first through portion over the etch stop layer;
forming a second through portion by etching a portion of the alternating stack;
removing the sacrificial layers through the second through portion to form air gaps between the dielectric layers; and
forming conductive layers in the air gaps,
wherein the conductive layers are in contact with the etch stop layer while filling the air gaps.
2. The method of claim 1 , wherein the etch stop layer fully covers the sidewall of the first through portion, extending substantially vertically in a direction in which the alternating stack is stacked.
3. The method of claim 1 , wherein the etch stop layer includes a material having an etching selectivity with respect to the sacrificial layers.
4. The method of claim 1 , wherein the etch stop layer includes SiCO, and the sacrificial layers include silicon nitride.
5. The method of claim 1 , wherein the blocking layer includes aluminum oxide, and the etch stop layer includes SiCO.
6. The method of claim 1 , further comprising:
converting the etch stop layer, exposed by the air gap, before the forming of the conductive layers.
7. The method of claim 6 , wherein the converting of the etch stop layer, exposed by the air gap, includes a plasma treatment or a thermal treatment.
8. The method of claim 1 , wherein the etch stop layer is formed of a single layer of a carbon-containing material.
9. The method of claim 1 , wherein the forming the blocking layer disposed in the first through portion over the etch stop layer comprises:
a first blocking layer over the etch stop layer; and
a second blocking layer over the first blocking layer.
10. The method of claim 9 , wherein the first blocking layer includes a metal oxide, and the second blocking layer includes a silicon oxide.
11. The method of claim 9 , wherein the first blocking layer includes aluminum oxide, and the etch stop layer includes SiCO.
12. The method of claim 9 , wherein the etch stop layer is thinner than the first blocking layer.
13. The method of claim 1 , further comprising:
forming a charge trapping layer over the blocking layer;
forming a tunnel dielectric layer over the charge trapping layer; and
forming a channel layer over tunnel dielectric layer.
14. The method of claim 1 , wherein the removing the sacrificial layers through the second through portion to form the air gaps between the dielectric layers comprises:
removing the sacrificial layers to expose the etch stop layer.
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9236396B1 (en) * | 2014-11-12 | 2016-01-12 | Sandisk Technologies Inc. | Three dimensional NAND device and method of making thereof |
US20160315095A1 (en) * | 2015-04-27 | 2016-10-27 | Sandisk Technologies Inc. | Blocking oxide in memory opening integration scheme for three-dimensional memory structure |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8253183B2 (en) * | 2001-06-28 | 2012-08-28 | Samsung Electronics Co., Ltd. | Charge trapping nonvolatile memory devices with a high-K blocking insulation layer |
KR100795363B1 (en) * | 2006-11-24 | 2008-01-17 | 삼성전자주식회사 | Conductive wiring for a semiconductor device and method of forming the same, and flash memory device having the conductive wiring and method of manufacturing the same |
US10128261B2 (en) * | 2010-06-30 | 2018-11-13 | Sandisk Technologies Llc | Cobalt-containing conductive layers for control gate electrodes in a memory structure |
KR101787041B1 (en) * | 2010-11-17 | 2017-10-18 | 삼성전자주식회사 | Methods for forming semiconductor devices having etch stopping layers, and methods for fabricating semiconductor devices |
CN102693946B (en) * | 2012-06-11 | 2017-04-05 | 上海华虹宏力半导体制造有限公司 | Method, semi-conductor device manufacturing method and memory manufacturing |
US20160020119A1 (en) * | 2014-07-16 | 2016-01-21 | Macronix International Co., Ltd. | Method of Controlling Recess Depth and Bottom ECD in Over-Etching |
US9355727B1 (en) * | 2014-12-09 | 2016-05-31 | Sandisk Technologies Inc. | Three-dimensional memory structure having a back gate electrode |
US9443866B1 (en) * | 2015-03-24 | 2016-09-13 | Sandisk Technologies Llc | Mid-tunneling dielectric band gap modification for enhanced data retention in a three-dimensional semiconductor device |
US9997533B2 (en) * | 2015-10-06 | 2018-06-12 | Toshiba Memory Corporation | Semiconductor device and method for manufacturing same |
US9812463B2 (en) * | 2016-03-25 | 2017-11-07 | Sandisk Technologies Llc | Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof |
KR20180061473A (en) * | 2016-11-28 | 2018-06-08 | 삼성전자주식회사 | Semiconductor devices and method for fabricating the same |
US10224340B2 (en) * | 2017-06-19 | 2019-03-05 | Sandisk Technologies Llc | Three-dimensional memory device having discrete direct source strap contacts and method of making thereof |
US10438964B2 (en) * | 2017-06-26 | 2019-10-08 | Sandisk Technologies Llc | Three-dimensional memory device having direct source contact and metal oxide blocking dielectric and method of making thereof |
JP2019054149A (en) * | 2017-09-15 | 2019-04-04 | 東芝メモリ株式会社 | Semiconductor storage device and method for manufacturing the same |
CN109727919B (en) * | 2017-10-30 | 2020-12-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
-
2019
- 2019-12-13 KR KR1020190167067A patent/KR20210075689A/en active Search and Examination
-
2020
- 2020-06-09 US US16/897,009 patent/US11538826B2/en active Active
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-
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9236396B1 (en) * | 2014-11-12 | 2016-01-12 | Sandisk Technologies Inc. | Three dimensional NAND device and method of making thereof |
US20160315095A1 (en) * | 2015-04-27 | 2016-10-27 | Sandisk Technologies Inc. | Blocking oxide in memory opening integration scheme for three-dimensional memory structure |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230056408A1 (en) * | 2021-08-20 | 2023-02-23 | Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of fabricating the same |
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US20210183884A1 (en) | 2021-06-17 |
KR20210075689A (en) | 2021-06-23 |
US11538826B2 (en) | 2022-12-27 |
CN112992911A (en) | 2021-06-18 |
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