US20230061940A1 - Fiber to chip coupler and method of making the same - Google Patents
Fiber to chip coupler and method of making the same Download PDFInfo
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- US20230061940A1 US20230061940A1 US17/446,244 US202117446244A US2023061940A1 US 20230061940 A1 US20230061940 A1 US 20230061940A1 US 202117446244 A US202117446244 A US 202117446244A US 2023061940 A1 US2023061940 A1 US 2023061940A1
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- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000835 fiber Substances 0.000 title description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 208
- 229920005591 polysilicon Polymers 0.000 claims abstract description 208
- 239000000758 substrate Substances 0.000 claims abstract description 101
- 230000003287 optical effect Effects 0.000 claims abstract description 94
- 239000013307 optical fiber Substances 0.000 claims abstract description 44
- 230000008878 coupling Effects 0.000 claims abstract description 30
- 238000010168 coupling process Methods 0.000 claims abstract description 30
- 238000005859 coupling reaction Methods 0.000 claims abstract description 30
- 238000004891 communication Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 57
- 125000006850 spacer group Chemical group 0.000 claims description 55
- 238000005530 etching Methods 0.000 claims description 52
- 238000000059 patterning Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 10
- 239000007943 implant Substances 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 455
- 239000000463 material Substances 0.000 description 55
- 230000008569 process Effects 0.000 description 36
- 229910052710 silicon Inorganic materials 0.000 description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 25
- 239000010703 silicon Substances 0.000 description 25
- 230000015572 biosynthetic process Effects 0.000 description 17
- 238000005253 cladding Methods 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 230000005693 optoelectronics Effects 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 238000010521 absorption reaction Methods 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 7
- 230000006872 improvement Effects 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000002243 precursor Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- -1 quartz Chemical compound 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/26—Optical coupling means
- G02B6/34—Optical coupling means utilising prism or grating
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/02—Optical fibres with cladding with or without a coating
- G02B6/02057—Optical fibres with cladding with or without a coating comprising gratings
- G02B6/02076—Refractive index modulation gratings, e.g. Bragg gratings
- G02B6/02123—Refractive index modulation gratings, e.g. Bragg gratings characterised by the method of manufacture of the grating
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/26—Optical coupling means
- G02B6/28—Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals
- G02B6/293—Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
- G02B6/29304—Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means operating by diffraction, e.g. grating
- G02B6/29316—Light guides comprising a diffractive element, e.g. grating in or on the light guide such that diffracted light is confined in the light guide
- G02B6/29317—Light guides of the optical fibre type
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/26—Optical coupling means
- G02B6/30—Optical coupling means for use between fibre and thin-film device
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12166—Manufacturing methods
- G02B2006/12176—Etching
Definitions
- Optical gratings are usable for directing optical signals between a chip and an optical fiber.
- Optical gratings are usable for directing optical signals from the chip to the optical fiber as well as directing optical signals from the optical fiber to the chip.
- the ability of the optical grating to effectively couple the chip to the optical fiber is based on alignment between the optical signal and the optical grating.
- a cavity is formed in the layers of the chip between the optical fiber and the optical grating in order to reduce signal loss for the optical signal passing through the layers of the chip.
- the signal loss is due to absorption, reflection, refraction, etc.
- a risk of over-etching, which damages a waveguide in the chip, is possible.
- charge accumulates in the substrate during the etching process.
- FIG. 1 is a cross sectional view of a fiber to chip coupling system in accordance with some embodiments.
- FIG. 2 is a flowchart of a method of making a chip in accordance with some embodiments.
- FIGS. 3 A- 3 E are cross sectional views of a chip during various stages of manufacture in accordance with some embodiments.
- FIGS. 4 A- 4 G are cross sectional views of a chip in accordance with some embodiments.
- FIGS. 5 A- 5 E are cross sectional views of a chip in accordance with some embodiments.
- FIG. 6 is a perspective view of a grating in accordance with some embodiments.
- FIG. 7 is a cross sectional view of a grating in accordance with some embodiments.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- an optical signal is used to convey a signal between different electrical components.
- the optical signal is carried by an optical fiber between the electrical components.
- a grating coupler is used to receive the optical signal and couple the signal into the waveguide to be transferred to an optoelectronic component for converting the optical signal into an electrical signal.
- a cavity is defined in the chip above the grating coupler in order to maximize a strength and consistency of the optical signal that reaches the grating coupler.
- the cavity is formed by an etching process, such as reactive ion etching (RIE).
- RIE reactive ion etching
- charge accumulations in the substrate during the etching process accumulates in the substrate during the etching process.
- Charge accumulation is especially problematic in silicon-on-insulator (SOI) substrates, where the charge accumulates within the insulating layers, such as silicon oxide. Charge accumulation weakens the substrate and increases a risk of the substrate breaking.
- SOI silicon-on-insulator
- the current disclosure includes a polysilicon layer over at least a portion of the waveguide layer.
- the polysilicon layer functions as an etch stop layer to reduce the risk of over-etching damaging the waveguide layer.
- the current disclosure also includes a polysilicon layer on a backside of the substrate, opposite from the cavity, in order to help to reduce charge accumulation.
- the backside polysilicon layer helps to conduct charge from insulating materials into the ambient environment or to a ground. As a result, a risk of the substrate breaking due to charge accumulation is reduced.
- FIG. 1 is a cross sectional view of a fiber to chip coupling system 100 in accordance with some embodiments.
- System 100 includes an optical fiber 110 configured to emit an optical signal 115 .
- System 100 further includes a chip 120 .
- Chip 120 includes a substrate 122 .
- a waveguide layer 124 is over the substrate 122 .
- An inter-layer dielectric (ILD) 126 is over the waveguide layer 124 .
- An etch stop layer 128 is over the ILD 126 .
- An interconnect structure 130 is over the etch stop layer 128 .
- ILD inter-metal dielectric
- the interconnect structure 130 includes multiple inter-metal dielectric (IMD) layers and conductive layers in order to electrically connect different components of the chip 120 .
- IMD inter-metal dielectric
- a cavity 136 extends through the interconnect structure 130 , the etch stop layer 128 and a portion of the ILD 126 .
- a grating 140 extends from the waveguide layer 124 and is configured to receive the optical signal 115 passing through the cavity 136 , any remaining portion of the interconnect structure 130 , the etch stop layer 128 and the ILD 126 .
- the grating 140 is configured to direct the optical signal 115 into the waveguide layer 124 to components within the chip 120 .
- the system 100 further includes a polysilicon layer 150 on a surface of the substrate 122 opposite to the cavity 136 . The polysilicon layer 150 helps to release charge that accumulates in the substrate 122 during the etching to form the cavity 136 .
- the system 100 includes a polysilicon layer 160 over the grating 140 .
- the polysilicon layer 160 acts as an etch stop layer during formation of the cavity 136 and helps to reduce the risk of damage to the grating 140 or the waveguide layer 124 due to over-etching.
- additional layers such as cladding and reflective layers, would be included in the system 100 .
- the optical fiber 110 is a single mode optical fiber having a width wf ranging from about 8 microns ( ⁇ m) to about 12 ⁇ m. In some embodiments, the optical fiber 110 is a multimode optical fiber having a width wf ranging from about 45 ⁇ m to about 70 ⁇ m. The width wf is based on a size of a core of the optical fiber 110 including any additional cladding or cover layers. If the width wf is too large, then the size of the optical fiber 110 is unnecessarily increased. If the width wf is too small, then there is a risk of loss of optical signal from the core or interference of the optical signal from external light sources.
- the optical fiber 110 is configured to convey the optical signal 115 from an external device to chip 120 .
- the optical fiber 110 is aligned with the cavity 136 in order for the optical signal 115 to efficiently couple to the grating 140 .
- the optical signal 115 has a wavelength.
- the wavelength of the optical signal 115 ranges from about 1260 nanometers (nm) to about 1360 nm.
- the wavelength of the optical signal 115 ranges from about 770 nm to about 910 nm.
- the wavelength of the optical signal 115 is based on a light source used to generate the optical signal.
- the light source is a laser or a laser diode.
- the light source of the optical fiber is a light emitting diode (LED).
- the optical signal 115 will diverge upon exiting the optical fiber 110 .
- the chip 120 includes at least one optoelectronic component, such as a laser driver, digital control circuit, photodetectors, waveguides, small form-factor pluggable (SFP) transceiver, High-speed phase modulator (HSPM), calibration circuit, distributed Mach-Zehnder Interferometer (MZI), grating couplers, light sources, (i.e., laser), etc.
- the optoelectronic component is configured to receive the optical signal 115 from the waveguide layer 124 and convert the optical signal 115 into an electrical signal. While the description of FIG.
- the system 100 is also usable to transfer an optical signal from the chip 120 to the optical fiber 110 . That is, the optoelectronic component generates the optical signal, which is then transferred to the optical fiber 110 through the waveguide layer 124 and the grating 140 , in some embodiments.
- substrate 122 includes an elementary semiconductor including silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof.
- the alloy semiconductor substrate has a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature.
- the alloy SiGe is formed over a silicon substrate.
- substrate 122 is a strained SiGe substrate.
- the semiconductor substrate has a semiconductor on insulator structure, such as a silicon on insulator (SOI) structure.
- SOI silicon on insulator
- the semiconductor substrate includes a doped epi layer or a buried layer.
- the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure.
- the waveguide layer 124 is configured to direct the optical signal 115 from the grating 140 to an optoelectronic component of the chip 120 .
- the waveguide layer 124 includes an optical transparent material.
- the waveguide layer 124 includes silicon.
- the waveguide layer 124 includes plastic.
- the waveguide layer 124 includes a same material as the grating 140 .
- the waveguide layer 124 includes a different material from the grating 140 .
- the waveguide layer 124 is integral with the grating 140 .
- the waveguide layer 124 is a slab waveguide, a planar waveguide or a light pipe.
- the grating 140 redirects the incident optical signal 115 into an angle of acceptance of the waveguide layer 124 .
- the angle of acceptance of the waveguide layer 124 is based on the wavelength of the optical signal, the frequency of the optical signal and dimensions of the waveguide layer 124 .
- the ILD 126 includes a dielectric material. Contacts are formed through the ILD 126 to electrically connect the optoelectronic component to the interconnect structure 130 and to other components within the chip or to external devices.
- the ILD 126 is deposited on the substrate 122 using chemical vapor deposition, physical vapor deposition, or another suitable deposition process.
- the ILD 126 has a thickness ranging from about 500 nm to about 3000 nm. If the thickness is too great, an aspect ratio for forming the contacts through the ILD 126 makes reliable manufacturing difficult and absorption of the optical signal 115 reduces the strength of the optical signal to an unacceptable level, in some instances. If the thickness is too small, the ILD 126 fails to provide sufficient electrical insulating between conductors, such as conductive layer 134 , and other components in the chip 120 . In some embodiments, the ILD 126 includes dielectric materials, such as Si, Si 3 N 4 , SiO 2 (e.g., quartz, and glass), Al2O3, and H2O, according to various embodiments of the present disclosure.
- dielectric materials such as Si, Si 3 N 4 , SiO 2 (e.g., quartz, and glass), Al2O3, and H2O, according to various embodiments of the present disclosure.
- the etch stop layer 128 is over the ILD 126 and has a different etch chemistry from the ILD 126 and the IMD layer 132 .
- the etch stop layer 128 is deposited using chemical vapor deposition or another suitable deposition process.
- the etch stop layer 128 includes SiC Si 3 N 4 , or another suitable material.
- the etch stop layer 128 has a thickness in a range of about 250 nm to about 350 nm. If the thickness of the etch stop layer 128 is too great, then material is wasted and absorption of the optical signal 115 reduces the strength of the optical signal to an unacceptable level, in some instances. If the thickness of the etch stop layer 128 is too small, then a risk of etching through the etch stop layer 128 during the formation of the cavity 136 or formation of electrical connections between the ILD 126 and the conductive layer 134 increases, in some instances.
- the interconnect structure 130 is configured to electrically connect the optoelectronic component to other components within the chip 120 or to external devices, for example, through chip bonding.
- the interconnect structure includes multiple IMD layers and multiple conductive layer.
- the IMD layers includes a dielectric material.
- the IMD layers provide electrical insulation between the conductive layers and other conductive elements within the chip 120 , such as the contacts in the ILD 126 .
- the IMD layers are deposited using chemical vapor deposition, physical vapor deposition, or another suitable deposition process.
- the IMD layers have a thickness ranging from about 1,000 angstroms to about 30,000 angstroms. If the thickness is too great, an aspect ratio for forming the electrical connections through the IMD layers makes reliable manufacturing difficult, in some instances. If the thickness is too small, the IMD layers fail to provide sufficient electrical insulating between conductors, and other components in the chip 120 .
- the IMD layers include dielectric materials, such as Si, Si 3 N 4 , SiO 2 (e.g., quartz, and glass), Al2O3, and H2O, according to various embodiments of the present disclosure.
- the IMD layers include a low-k dielectric material.
- the IMD layers include a same material as the ILD 126 .
- the IMD layers include a different material from the ILD 126 .
- the conductive layers are configured to convey electrical signals to various components in the chip 120 , for example the optoelectronic component.
- the conductive layers include a seed layer.
- the conductive layers include copper, aluminum, tungsten, alloys thereof or another suitable material.
- the cavity 136 reduces an amount of material that the optical signal 115 passes through before being directed into the waveguide layer 124 by the grating 140 .
- the cavity 136 extends through the interconnect structure 130 , the etch stop layer 128 and through a portion of the ILD 126 . In some embodiments, the cavity 136 extends through a portion of the interconnect structure 130 . In some embodiments, the cavity 136 extends through less than all of the etch stop layer 128 .
- the sidewalls of the cavity 136 are substantially vertical. In some embodiments, the sidewalls of the cavity 136 are tapered. In some embodiments, a width wc of the cavity ranges from about 2.5-times to about 3.5-times more than the width wf of the optical fiber 110 .
- the width wc ranges from about 25 ⁇ m to about 35 ⁇ m. This width wc helps to account for misalignment between the optical fiber 110 and the cavity 136 . The width wc also helps to permit the entire optical signal 115 to pass through the cavity 136 even though the optical signal 115 will diverge upon exiting from the optical fiber. If the width wc is too small, then misalignment or divergence of the optical signal 115 will increase the risk of loss of a portion of the optical signal 115 , in some instances. If the width we is too great, then routing possibilities in the interconnect structure 130 are reduced or an overall size of the chip 120 is increased, in some instances.
- the grating 140 is configured to couple the optical signal 115 from the optical fiber 110 into the waveguide layer 124 .
- the grating 140 directs the optical signal 115 based on an incident angle of the optical signal 115 and dimensions of features of the grating 140 .
- the grating 140 includes a variable grating section.
- the variable grating section includes grating features having different geometric dimensions.
- the variable grating section includes grating features having a variation in width, depth, pitch or combinations thereof.
- the grating 140 includes a uniform grating section.
- the uniform grating section includes grating features having consistent geometric dimensions.
- the grating 140 includes an optical transparent material.
- the grating 140 includes silicon.
- the grating 140 includes plastic.
- the grating 140 is integral with the waveguide layer 124 .
- the polysilicon layer 150 helps to release charge that accumulates during the formation of the cavity 136 .
- the polysilicon layer 150 is undoped.
- the polysilicon layer 150 contains dopants.
- the polysilicon layer 150 is connected to a ground or reference voltage in order to assist with releasing the accumulated charge.
- a thickness of the polysilicon layer 150 ranges from about 1300 angstroms ( ⁇ ) to about 1600 ⁇ . If the thickness of the polysilicon layer 150 is too small, then a resistance to releasing the accumulated charge increases to an unacceptable level, in some instances. If the thickness of the polysilicon layer 150 is too great, then material is wasted without a noticeable increase in performance and an overall size of the chip 120 needlessly increases, in some instances.
- the polysilicon layer 160 acts as an etch stop layer during the formation of the cavity 136 in order to help reduce the risk of over-etching damage to the grating 140 or to the waveguide layer 124 .
- the polysilicon layer 160 is undoped.
- the polysilicon layer 160 contains dopants.
- a thickness of the polysilicon layer 160 ranges from about 1300 angstroms (A) to about 1600 A. If the thickness of the polysilicon layer 160 is too small, then risk of over-etching increases, in some instances. If the thickness of the polysilicon layer 160 is too great, then material is wasted without a noticeable increase in performance and an overall size of the chip 150 needlessly increases, in some instances.
- the thickness of the polysilicon layer 150 is equal to the thickness of the polysilicon layer 160 . In some embodiments, the thickness of the polysilicon layer 150 is different from the thickness of the polysilicon layer 160 . In some embodiments, the polysilicon layer 160 is removed during the formation of the cavity. For examples, in some embodiments, following use as an etch stop layer, a subsequent etching process, e.g., a wet etching, is used to remove the polysilicon layer 160 .
- a subsequent etching process e.g., a wet etching
- FIG. 2 is a flowchart of a method 200 of making a chip in accordance with some embodiments.
- Method 200 includes optional operation 202 in which a SOI substrate is formed or an oxide layer is deposited on a substrate.
- the oxide layer is formed by oxidizing a silicon substrate using high temperature oxidation (HTO).
- HTO high temperature oxidation
- the oxide layer is deposited by chemical vapor deposition.
- operation 202 is omitted.
- operation 202 is omitted because the SOI substrate is provided by an outside vendor.
- a polysilicon layer is deposited on the substrate.
- the polysilicon layer is deposited on the oxide layer.
- a thickness of the polysilicon layer ranges from about 1300 A to about 1600 A. If the thickness of the polysilicon layer is too small, then a resistance to releasing the accumulated charge increases to an unacceptable level, in some instances. If the thickness of the polysilicon layer is too great, then material is wasted without a noticeable increase in performance, in some instances.
- the polysilicon layer is deposited using low pressure chemical vapor deposition. In some embodiments, the polysilicon is deposited using a silane gas precursor.
- the precursor gas is has a concentration ranging from about 15 volume percent to about 40 volume percent with respect to the total volume of the CVD precursor gas with the remaining volume percent portion nitrogen gas. If the concentration of the precursor gas is too low, then the formation process duration is increased, in some instances. If the concentration of the precursor gas is too high, then material is wasted without a noticeable increase in performance, in some instances.
- the deposition process is carried out at a pressure of about 100 milliTorr to about 1 Torr. If the pressure is too low, then the formation process duration is increased, in some instances. If the pressure is too high, then material is wasted without a noticeable increase in performance, in some instances. In some embodiments, the deposition process is carried out at a temperature ranging from about 250° C. to about 650° C. If the temperature is too low, then the formation process duration is increased, in some instances. If the temperature is too high, then a risk of reemission of the deposited material increases, in some instances.
- an oxide layer is formed on the polysilicon layer.
- the polysilicon layer is partially oxidized in order to form the oxide layer.
- the polysilicon layer is oxidized using HTO at a temperature ranging from about 700° C. to about 820° C. If the temperature is too low, then the formation process duration is increased, in some instances. If the temperature is too high, then a risk of consuming too much of the polysilicon layer to permit releasing of accumulated charge increases, in some instances.
- the oxide layer is deposited on the polysilicon layer. In some embodiments, the oxide layer is deposited using chemical vapor deposition. In some embodiments, operation 206 is omitted. In some embodiments, operation 206 is omitted if an oxide space is later formed, see operation 242 below.
- FIG. 3 A is a cross sectional view of a chip 300 A following operation 206 in accordance with some embodiments.
- the chip 300 A includes a substrate 302 .
- a top oxide layer 304 a is over a top surface of the substrate 302 and a bottom oxide layer 304 b is on a bottom surface of the substrate 302 .
- a thickness of the top oxide layer 304 a ranges from about 400 A to about 600 A. If the thickness of the top oxide layer 304 a is too high, material is wasted without a noticeable increase in performance and a size of the chip 300 A is needlessly increased, in some instances.
- a thickness of the bottom oxide layer 304 b ranges from about 1.5 microns ( ⁇ m) to about 2.5 ⁇ m. If the thickness of the bottom oxide layer 304 b is too high, material is wasted without a noticeable increase in performance and a size of the chip 300 A is needlessly increased, in some instances. If the thickness of the bottom oxide layer 304 b is too small, then the bottom oxide layer 304 b fails to provide sufficient insulation between a polysilicon layer 306 and the substrate 302 .
- the polysilicon layer 306 surrounds the substrate 302 , top oxide layer 304 a and bottom oxide layer 304 b . While FIG. 3 A shows an upper portion of the polysilicon layer 306 is thicker than a lower portion of the polysilicon layer 306 , polysilicon layer 306 is conformally deposited. Conformal deposition means that a thickness of the polysilicon layer 306 is substantially uniform on all surfaces. In some embodiments, a thickness of the polysilicon layer 306 ranges from about 1300 A to about 1600 A. If the thickness of the polysilicon layer 306 is too small, then a resistance to releasing the accumulated charge increases to an unacceptable level, in some instances. If the thickness of the polysilicon layer 306 is too great, then material is wasted without a noticeable increase in performance and an overall size of the chip 300 A needlessly increases, in some instances.
- An oxide layer 308 surrounds the polysilicon layer 306 .
- the oxide layer 308 is conformally formed.
- a thickness of the oxide layer 308 ranges from about 50 A to about 70 A. If the thickness of the oxide layer 308 is too small, then protection of the polysilicon layer 306 during subsequent processing is insufficient, in some instances. If the thickness of the oxide layer 308 is too great, then a risk of consuming too much of the polysilicon layer to permit releasing of accumulated charge increases, in some instances
- the oxide layer and the polysilicon layer are patterned to define a recess.
- the patterning is performed using a photoresist and photolithography.
- the recess is defined using an etching process.
- the etching process is a dry etching process.
- the etching process is a wet etching process.
- the etching process oxidizes a sidewall of the polysilicon layer during formation of the recess.
- an additional oxidation process such as HTO, is performed following the etching process.
- a temperature of the oxidation process ranges from about 700° C.
- the temperature is too low, then the oxidation process duration is increased, in some instances. If the temperature is too high, then a risk of consuming too much of the polysilicon layer to permit releasing of accumulated charge increases, in some instances.
- FIG. 3 B is a cross sectional view of a chip 300 B following operation 208 in accordance with some embodiments.
- the chip 300 B includes a recess 310 which a portion of the polysilicon layer 306 and the oxide layer 308 were removed.
- the chip 300 B further includes an oxide spacer 312 on a sidewall of the polysilicon layer 306 .
- a width of the oxide spacer 312 ranges from about 30 A to about 50 A. If the thickness of the oxide spacer 312 is too small, then protection of the polysilicon layer 306 during subsequent processing is insufficient, in some instances.
- oxide spacer 312 If the thickness of the oxide spacer 312 is too great, then a risk of consuming too much of the polysilicon layer to permit releasing of accumulated charge increases, in some instances. Formation of oxide spacer 312 will increase the thickness of other oxide layers in the chip 300 B, in some instances.
- a transistor structure is formed in the substrate.
- the transistor structure includes a planar transistor.
- the transistor structure includes a fin field effect transistor (FinFET).
- the transistor structure includes a gate all around (GAA) transistor structure.
- the transistor structure is formed by removing a portion of the substrate and growing a germanium feature in the substrate.
- source/drain (S/D) features for formed in the substrate.
- the S/D features are formed by ion implantation.
- the S/D features are formed by recessing the substrate and growing strained S/D features in the recesses.
- forming the transistor structure includes forming a lightly doped drain (LDD) region.
- the LDD region is formed by ion implantation.
- a contact etch stop layer is deposited over the substrate and the transistor structure.
- the CESL includes silicon nitride, silicon carbide or another suitable material.
- the CESL is deposited using chemical vapor deposition.
- a thickness of the CESL ranges from about 800 A to about 1,000 A. If the thickness of the CESL is too small, then a risk of inadvertently etching through the CESL increases, in some instances. If the thickness of the CESL is too great, material is wasted without a noticeable increase in performance and a size of the chip is increased needlessly, in some instances.
- the CESL is deposited to form a conformal layer. Following operation 212 , the method 200 proceeds to either operation 220 or to operation 240 .
- the CESL is patterned to define a CESL block and a CESL spacer.
- the CESL block is over a portion of the transistor structure.
- the CESL spacer covers a sidewall of the oxide spacer formed in operation 208 .
- the CESL spacer is omitted.
- the CESL spacer is omitted if the thickness of the oxide spacer is sufficient to avoid being etched through during subsequent processing of the chip.
- FIG. 3 C is a cross sectional view of a chip 300 C following the operation 220 in accordance with some embodiments.
- the chip 300 C includes a transistor structure 320 .
- a CESL block 330 is over a portion of the transistor structure 320 .
- a CESL spacer 332 covers a sidewall of the oxide spacer 312 .
- the transistor structure 320 includes a channel region 322 , a first S/D region 324 on a first side of the channel region 322 , a second S/D region 326 on a second side of the channel region 322 opposite the first side.
- the transistor structure 320 further includes an LDD region 328 overlapping with the channel region 322 .
- the channel region 322 includes doped silicon. In some embodiments, the channel region 322 includes germanium. In some embodiments, a distance D 1 from a top of the channel region 322 to a bottom of the channel region 322 ranges from about 225 nanometers (nm) to about 275 nm. If the distance D 1 is too small, there is an increased resistance within the channel region 322 that prevents efficient signal transfer between the first S/D region 324 and the second S/D region 326 , in some instances. If the distance D 1 is too large, a risk of shorting the channel region to the polysilicon layer 306 on the bottom surface of the substrate 302 increases, in some instances.
- the channel region 322 is separated from the bottom surface of the substrate 302 by a distance D 2 ranging from about 90 nm to about 120 nm. If the distance D 2 is too small, a risk of shorting the channel region to the polysilicon layer 306 on the bottom surface of the substrate 302 increases, in some instances. If the distance D 1 is too large, there is an increased resistance within the channel region 322 that prevents efficient signal transfer between the first S/D region 324 and the second S/D region 326 , in some instances. In some embodiments, the channel region 322 extends a distance D 3 below the top surface of the substrate 302 ranging from about 150 nm to about 180 nm.
- the distance D 3 is too small, there is an increased resistance within the channel region 322 that prevents efficient signal transfer between the first S/D region 324 and the second S/D region 326 , in some instances. If the distance D 3 is too large, a risk of shorting the channel region to the polysilicon layer 306 on the bottom surface of the substrate 302 increases, in some instances.
- the first S/D region 324 and the second S/D region 326 include higher dopant concentrations in the substrate 302 .
- the first S/D region 324 and the second S/D region 326 are strained S/D structures.
- the first S/D region 324 has a first dopant type; and the second S/D region 326 has a second dopant type opposite the first dopant type.
- the first S/D region 324 and the second S/D region 326 have a same dopant type.
- the LDD region 328 overlaps with the channel region 322 and helps with switching speed of the transistor structure 320 .
- the LDD region 328 has a same dopant type as the second S/D region 326 .
- the CESL block 330 overlaps the channel region 322 . In some embodiments, the CESL block 330 partially overlaps at least one of the first S/D region 324 or the second S/D region 326 .
- the CESL block 330 overhangs the channel region by an overhang width wo of at least about 10 nm. If the overhang width wo is too small, then the CESL block 330 fails to provide sufficient protection for the channel region 322 during subsequent processing, in some instances. In some embodiments, the overhang width wo is the same on both sides of the channel region 322 . In some embodiments, the overhang width wo is different on the first side of the channel region 322 than on the second side of the channel region 322 .
- a thickness of the CESL block 330 ranges from about 800 A to about 1,000 A. If the thickness of the CESL block 330 is too small, then a risk of inadvertently etching through the CESL block 330 increases, in some instances. If the thickness of the CESL block 330 is too great, material is wasted without a noticeable increase in performance and a size of the chip is increased needlessly, in some instances.
- the CESL spacer 332 covers the sidewall of the oxide spacer 312 .
- a width ws of the CESL spacer 332 ranges from about 800 A to about 1,000 A. If the width ws of the CESL spacer 332 is too small, then a risk of inadvertently etching through the CESL spacer 332 increases, in some instances. If the thickness of the CESL spacer 332 is too great, material is wasted without a noticeable increase in performance and a size of the chip is increased needlessly, in some instances.
- the width ws of the CESL spacer 332 is equal to the thickness of the CESL block 330 . In some embodiments, the width ws of the CESL spacer 322 is different from the thickness of the CESL block 330 .
- a thickness tox 1 of the top oxide layer 304 a between the substrate 302 and the polysilicon layer 306 ranges from about 400 A to about 600 A. If the thickness tox 1 is too small, a risk of electrical coupling between the substrate 302 and the polysilicon layer 306 increases, in some instances. If the thickness tox 1 is too large, then material is wasted without noticeable improvement in performance, in some instances.
- a thickness tox 2 of the top oxide layer 304 in the recess 310 ranges from about 80 A to about 90 A. If the thickness tox 2 is too small, a risk of electrical coupling between the substrate 302 and subsequently formed layers increases, in some instances. If the thickness tox 2 is too large, then aspect ratios for contacts to be connected to the first S/D region 324 or the second S/D region 326 increases making manufacturing more difficult, in some instances.
- a waveguide layer and a grating are formed on the substrate.
- the waveguide layer and the grating are independently formed using silicon, plastic or another suitable material.
- the waveguide layer and the grating for integral and a single layer is deposited and then patterned to define the grating as part of the waveguide layer.
- the silicon is deposited using chemical vapor deposition.
- the plastic is deposited using spin on coating, chemical vapor deposition, or another suitable technique.
- the grating is patterned using photolithography and etching.
- the grating includes a variable grating region.
- the grating includes a uniform grating region.
- the grating includes a combination of a variable grating region and a uniform grating region.
- an interconnect structure is formed over the substrate.
- the interconnect structure extends over the transistor structure and the grating.
- the interconnect structure is formed by alternately depositing dielectric layers and etch stop layers.
- the dielectric layers have a different etch selectivity from the etch stop layers.
- the dielectric layers include oxide, silicon nitride, or another low-k dielectric material.
- the etch stop layers include silicon nitride, silicon oxide, silicon carbide or another suitable material.
- the dielectric layers and the etch stop layers are deposited using chemical vapor deposition.
- Conductive elements are formed in the dielectric layers and the etch stop layers in order to electrically connect different components of the chip or to electrically connect a component of the chip to an external device. Openings for the conductive elements are formed in the dielectric layers and the etch stop layers using a series of photolithography and etching processes.
- the conductive elements include copper, aluminum, tungsten or another suitable conductive material.
- the conductive elements are formed by plating, physical vapor deposition or another suitable process.
- a cavity is formed in the interconnect structure.
- the cavity is aligned with the grating in order to permit light to pass through the cavity to be incident on the grating.
- the cavity is formed using a series of photolithography and etching processes.
- the cavity is formed using a dry etching process where the etchant is selected based on a material being etched.
- the cavity extends through an entirety of the interconnect structure.
- the cavity extends through less than the entire interconnect structure.
- the sidewalls of the cavity are perpendicular to the top surface of the substrate. In some embodiments, the sidewalls of the cavity are tapered.
- the width ranges from about 25 ⁇ m to about 35 ⁇ m. This width helps to account for misalignment between the optical fiber and the cavity. The width also helps to permit the entire optical signal to pass through the cavity even though the optical signal will diverge upon exiting from the optical fiber. If the width is too small, then misalignment or divergence of the optical signal will increase the risk of loss of a portion of the optical signal, in some instances. If the width is too great, then routing possibilities in the interconnect structure are reduced or an overall size of the chip is increased, in some instances.
- the method 200 proceeds from operation 212 to operation 240 .
- the CESL is patterned to define the CESL block.
- the operation 240 is similar to the operation 220 , except that the operation 240 does not form the CESL spacer.
- an oxide layer is deposited over the CESL block and then patterned to define oxide spacers on sidewalls of the CESL block.
- the oxide layer is deposited using chemical vapor deposition.
- the oxide layer is patterned using photolithography and etching processes.
- a width of the oxide spacer ranges from about 50 A to about 200 A. If the width of the oxide spacer is too small, a risk of electrically connection between later formed polysilicon spacer and a channel region of the transistor structure increases, in some embodiments. If the width of the oxide spacer is too great, material is wasted without a noticeable increase in performance, in some embodiments. Patterning the oxide layer exposes a top surface of the CESL block. In some embodiments, operation 242 is omitted if an overhang width of the CESL block beyond an edge of the channel region of the transistor structure is sufficient to reduce the risk of electrical coupling between the polysilicon spacer and the channel region.
- a polysilicon layer is deposited over the CESL block.
- a thickness of the polysilicon layer ranges from about 50 A to about 200 A. If the thickness of the polysilicon layer is too small, then the polysilicon layer will not sufficient protect from over-etching, in some instances. If the thickness of the polysilicon layer is too great, then material is wasted without a noticeable increase in performance, in some instances.
- the polysilicon layer is deposited using the same process as in operation 204 .
- FIG. 3 D is a cross sectional view of a chip 300 D following operation 244 in accordance with some embodiments.
- the chip 300 D does not include the oxide layer 308 (optional operation 206 was not performed) and does not include CESL spacer 332 .
- the chip 300 D includes oxide spacers 340 along sidewalls of the CESL block 330 .
- a width of the oxide spacers 340 ranges from about 50 A to about 200 A. If the width of the oxide spacers is too small, a risk of electrically connection between later formed polysilicon spacer and a channel region of the transistor structure increases, in some embodiments.
- the chip 300 D further includes a polysilicon layer 350 over the CESL block 330 and over the top oxide layer 304 a in the recess 310 .
- a thickness of the polysilicon layer 350 ranges from about 50 A to about 200 A. If the thickness of the polysilicon layer is too small, then the polysilicon layer will not sufficient protect from over-etching, in some instances. If the thickness of the polysilicon layer is too great, then material is wasted without a noticeable increase in performance, in some instances.
- the polysilicon layer is patterned to define polysilicon spacers.
- the polysilicon layer is patterned using photolithography and etching processes.
- a width of the polysilicon spacers ranges from about 50 A to about 200 A. If the width of the polysilicon spacers are too small, then the polysilicon spacers will not sufficient protect from over-etching, in some instances. If the width of the polysilicon spacers is too great, then material is wasted without a noticeable increase in performance, in some instances.
- FIG. 3 E is a cross section a chip 300 E following operation 246 in accordance with some embodiments.
- the chip 300 E includes polysilicon spacers 352 on an opposite side of the oxide spacers 340 from the CESL block 330 .
- a width of the polysilicon spacers 352 ranges from about 50 A to about 200 A. If the width of the polysilicon spacers 352 are too small, then the polysilicon spacers will not sufficient protect from over-etching, in some instances. If the width of the polysilicon spacers 352 is too great, then material is wasted without a noticeable increase in performance, in some instances.
- a thickness tox 1 ′ of the top oxide layer 304 a between the substrate 302 and the polysilicon layer 306 ranges from about 800 A to about 1,000 A. If the thickness tox 1 ′ is too small, a risk of electrical coupling between the substrate 302 and the polysilicon layer 306 increases, in some instances. If the thickness tox 1 ′ is too large, then material is wasted without noticeable improvement in performance, in some instances.
- a thickness tox 2 ′ of the top oxide layer 304 in the recess 310 ranges from about 120 A to about 150 A. If the thickness tox 2 ′ is too small, a risk of electrical coupling between the substrate 302 and subsequently formed layers increases, in some instances. If the thickness tox 2 ′ is too large, then aspect ratios for contacts to be connected to the first S/D region 324 or the second S/D region 326 increases making manufacturing more difficult, in some instances.
- FIG. 4 A is a cross sectional view of a chip 400 A in accordance with some embodiments.
- the chip 400 A includes a substrate 402 .
- the substrate 402 is similar to the substrate 122 ( FIG. 1 ) or the substrate 302 ( FIGS. 3 A- 3 E ).
- a top oxide layer 404 a is over a top surface of the substrate 402 .
- the top oxide layer 404 a is similar to the top oxide layer 304 a ( FIGS. 3 A- 3 E ).
- a bottom oxide layer 404 b is on a bottom surface of the substrate 402 opposite the top surface.
- the bottom oxide layer 404 b is similar to the bottom oxide layer 304 b ( FIGS. 3 A- 3 E ).
- a polysilicon layer 406 is on an opposite side of the bottom oxide layer 404 b from the substrate 402 .
- the polysilicon layer 406 is similar to the polysilicon layer 150 ( FIG. 1 ) or the polysilicon layer 306 ( FIGS. 3 A- 3 E ).
- a silicon layer 408 is over the top oxide layer 404 a .
- An implant region 410 is in the silicon layer 408 .
- An oxide layer 412 is over the silicon layer 408 .
- a CESL layer 414 is over the oxide layer 412 .
- the CESL layer 414 is similar to the CESL layer 128 ( FIG. 1 ).
- An ILD 416 is over the CESL layer 414 .
- the ILD 416 is similar to the ILD 126 ( FIG. 1 ).
- a waveguide layer 420 is defined in the silicon layer 408 .
- the waveguide layer 420 is similar to the waveguide layer 124 ( FIG. 1 ).
- a grating 422 is integral with the waveguide layer 420 and is configured to receive an optical signal and couple the optical signal into the waveguide layer 420 .
- the grating 422 is similar to the grating 140 ( FIG. 1 ).
- a polysilicon layer 430 is over the waveguide layer 420 .
- the polysilicon layer 430 is similar to the polysilicon layer 160 ( FIG. 1 ).
- An interconnect structure 440 is over the ILD 416 .
- the interconnect structure 440 includes a first interconnect section 450 having conductive features having a first dimension.
- the interconnect structure 440 further includes a second interconnect section 455 having conductive features having a second dimension greater than the first dimension.
- the second interconnect section 455 is over the first interconnect section 450 .
- interconnect structure 440 is similar to the interconnect structure 130 ( FIG. 1 ).
- a contact pad 460 is electrically connected to the implant region 410 by conductive features in the interconnect structure 440 .
- a passivation layer 470 is over the interconnect structure 440 .
- the chip 400 A includes a cavity 436 A for optically coupling an optical fiber with the grating 422 .
- the cavity 436 A extends through a portion of the interconnect structure 440 .
- the cavity 436 A extends through all of the second interconnect section 455 and through an upper portion of the first interconnect section 450 .
- a portion of a bottommost IMD layer of the interconnect structure 440 remains as a bottom surface of the cavity 436 A.
- a remaining portion of the bottommost IMD layer ranges from about 10% to about 90% of the bottommost IMD layer. The amount of the remaining portion of the IMD layer is a result of manufacturing variation during an etching process used to define the cavity 436 A.
- the silicon layer 408 is usable to form transistor structures, e.g., transistor structure 320 ( FIGS. 3 C- 3 E ).
- the silicon layer 408 is also usable to contain the waveguide layer 420 .
- cladding or reflective layers are between the silicon layer 408 and the waveguide layer 420 in order to avoiding reducing the strength of the optical signal traveling through the waveguide layer 420 due to light leaking to the silicon layer 408 .
- the cladding or reflective layers also help to prevent light from entering the waveguide layer 420 from the silicon layer 408 , which would introduce noise into the optical signal within the waveguide layer 420 .
- a thickness of the silicon layer 408 ranges from about 2,500 A to about 3,000 A.
- the thickness of the silicon layer 408 is too small, then an ability to form transistor structures is reduced, in some instances. If the thickness of the silicon layer 408 is too large, material is wasted without a noticeably increase in performance resulting in increasing the size of the chip 400 A needlessly.
- the implant region 410 is part of a component within the chip 400 A. In some embodiments, the implant region 410 is part of an optoelectronic component. In some embodiments, the implant region 410 is part of a transistor structure, e.g., transistor structure 320 ( FIGS. 3 C- 3 E ). The implant region 410 is not particularly limiting and is used merely to indicate that the interconnect structure 440 provides electrical connection to elements within the chip 400 A.
- the oxide layer 412 helps to protect the silicon layer 408 during subsequent processing.
- the oxide layer 412 is formed by oxidizing the silicon layer 408 , e.g., using HTO.
- a thickness of the oxide layer 412 ranges from about 50 A to about 200 A. If the thickness of the oxide layer 412 is too small, a risk of damage to the silicon layer 408 during subsequent processing increases, in some embodiments. If the thickness of the oxide layer 412 is too great, material is wasted without a noticeable increase in performance, in some embodiments.
- the contact pad 460 provides a location for electrically connecting external devices to the interconnect structure 440 .
- the contact pad 460 includes aluminum, copper, tungsten or another suitable conductive material.
- the contact pad 460 is part of a fan-out connection.
- the passivation layer 470 is configured to protect the interconnect structure 440 .
- the passivation layer 470 includes silicon nitride, silicon oxide, silicon oxynitride, or another suitable dielectric material.
- a thickness of the passivation layer 470 ranges from about 5,000 A to about 6,000 A. If the thickness of the passivation layer 470 is too small, a risk of damage to the interconnect structure 440 increases, in some instances. If the thickness of the passivation layer 470 is too great, material is wasted without a noticeable increase in performance and the size of the chip 400 A is needlessly increased, in some instances.
- the polysilicon layer 430 acts as an etch stop layer over the waveguide layer 420 and the grating 422 .
- the polysilicon layer 430 helps to reduce the risk of over-etching during formation of the cavity 436 A. As mentioned above, over-etching that damages the waveguide layer 420 or the grating 422 increases the risk of the chip 400 A being unable to effectively transfer an optical signal from an optical fiber to a component within the chip 400 A.
- a thickness of the polysilicon layer 430 ranges from about 1,400 A to about 1,600 A. If the thickness of the polysilicon layer 430 is too small, then a risk of over-etching damage to the waveguide layer 420 or the grating 422 increases, in some instances.
- the polysilicon layer 430 has a same thickness as the polysilicon layer 406 . In some embodiments, the polysilicon layer 430 has a different thickness from the polysilicon layer 406 .
- FIG. 4 B is a cross sectional view of a chip 400 B in accordance with some embodiments.
- the chip 400 B is similar to the chip 400 A ( FIG. 4 A ).
- the chip 400 B includes cavity 436 B which extends through an entirety of the interconnect structure 440 .
- the cavity 436 B extends into the ILD 416 .
- a portion of the ILD 416 remains as a bottom surface of the cavity 436 B.
- a remaining portion of the ILD 416 ranges from about 10% to about 90% of the ILD 416 .
- the amount of the remaining portion of the ILD 416 is a result of manufacturing variation during an etching process used to define the cavity 436 B.
- the cavity 436 B extends through the entirety of the ILD 416 and exposes the CESL 414 .
- FIG. 4 C is a cross sectional view of a chip 400 C in accordance with some embodiments.
- the chip 400 B is similar to the chip 400 A ( FIG. 4 A ).
- the chip 400 C includes cavity 436 C which extends through an entirety of the interconnect structure 440 , an entirety of the ILD 416 and an entirety of the CESL 414 .
- the cavity 436 C extends into the oxide layer 412 .
- a portion of the oxide layer 412 remains as a bottom surface of the cavity 436 C.
- a remaining portion of the oxide layer 412 ranges from about 10% to about 90% of the oxide layer 412 .
- the amount of the remaining portion of the oxide layer 412 is a result of manufacturing variation during an etching process used to define the cavity 436 C.
- FIG. 4 D is a cross sectional view of a chip 400 D in accordance with some embodiments.
- the chip 400 D is similar to the chip 400 A ( FIG. 4 A ).
- the chip 400 D includes cavity 436 D which extends through an entirety of the interconnect structure 440 , an entirety of the ILD 416 , an entirety of the CESL 414 , and an entirety of the oxide layer 412 .
- the cavity 436 D extends into the polysilicon layer 430 .
- a portion of the polysilicon layer 430 remains as a bottom surface of the cavity 436 D.
- a remaining portion of the polysilicon layer 430 ranges from about 10% to about 90% of the polysilicon layer 430 .
- the amount of the remaining portion of the polysilicon layer 430 is a result of manufacturing variation during an etching process used to define the cavity 436 D.
- FIG. 4 E is a cross sectional view of a chip 400 E in accordance with some embodiments.
- the chip 400 E is similar to the chip 400 A ( FIG. 4 A ).
- the chip 400 E includes cavity 436 E which extends through an entirety of the interconnect structure 440 , an entirety of the ILD 416 , an entirety of the CESL 414 , an entirety of the oxide layer 412 , and an entirety of the polysilicon layer 430 .
- the cavity 436 E exposes the waveguide layer 420 and the grating 422 .
- a portion of the polysilicon layer 430 remains under the oxide layer 412 outside of the cavity 436 E.
- FIG. 4 F is a cross sectional view of a chip 400 F in accordance with some embodiments.
- the chip 400 F is similar to the chip 400 E ( FIG. 4 E ). In comparison with the chip 400 E, the chip 400 F does not include the portion of the polysilicon layer 430 under the oxide layer 412 outside of the cavity 436 F.
- a wet etching is used to remove the portion of the polysilicon layer 430 outside of the cavity 436 F to define an overhang by the oxide layer 412 . Removing this portion of the polysilicon layer 430 increases an amount of the waveguide layer 420 and the grating 422 exposed. Thus, an amount of the waveguide layer 420 and the grating 422 able to receive the optical signal without absorption from other materials is increases. As a result, efficiency of optical coupling between the optical fiber and the waveguide layer 420 is increased.
- FIG. 4 G is a cross sectional view of a chip 400 G in accordance with some embodiments.
- the chip 400 G is similar to the chip 400 E ( FIG. 4 E ).
- the chip 400 G includes a segmented polysilicon layer 430 ′′.
- the polysilicon layer 430 is etched to define openings to form the segmented polysilicon layer 430 ′′. Removing these portions of the polysilicon layer 430 increases an amount of the waveguide layer 420 and the grating 422 exposed. Thus, an amount of the waveguide layer 420 and the grating 422 able to receive the optical signal without absorption from other materials is increases.
- the segmented polysilicon layer 430 ′′ occupies about 20% to about 30% of the cavity width wc of the cavity 436 G. If the amount of the cavity width wc occupied by the segmented polysilicon layer 430 ′′ is too small, then a risk of over-etching increases because the etching tool is less likely to detect the presence of the segmented polysilicon layer 430 ′′ and terminate the etching process, in some instances.
- segmented polysilicon layer 430 ′′ is usable with any of the embodiments in FIGS. 4 A- 4 F .
- the examples of chips 400 A- 400 G result from different etching depths for the cavities 436 A- 436 G.
- different chips on a same wafer will have cavities from the different examples in FIGS. 4 A- 4 G .
- chips on the wafer closer to an edge of the wafer are more likely to have cavities which extend farther into the chip than chips near a center of the wafer.
- FIG. 5 A is a cross sectional view of a chip 500 A in accordance with some embodiments.
- the chip 500 A is similar to the chip 400 B ( FIG. 4 B ). Reference numbers for similar elements are increased by 100 with respect to the reference numbers in FIG. 4 B .
- the chip 500 A includes a polysilicon layer 530 ′ which has a width wp less than a width of the cavity 536 A. In some embodiments, the width wp ranges from about 20% to about 30% of the width wc. If the width wp is too small, then a risk of over-etching increases because the etching tool is less likely to detect the presence of the polysilicon layer 530 ′ and terminate the etching process, in some instances.
- the width wp is too great, then an amount of light from the optical signal that is absorbed or dispersed by the polysilicon layer 530 ′ increases and coupling efficiency is reduced, in some instances.
- the depth of the cavity 536 A is similar to the depth of the cavity 436 B ( FIG. 4 B )
- a depth of a cavity similar to the depth of cavity 436 A ( FIG. 4 A ) is also possible, in some embodiments.
- the cavity 536 A extends through the entirety of the ILD 516 and exposes the CESL 514 .
- FIG. 5 B is a cross sectional view of a chip 500 B in accordance with some embodiments.
- the chip 500 B is similar to the chip 500 A ( FIG. 5 A ).
- the chip 500 B includes cavity 536 B which extends through an entirety of the interconnect structure 540 , an entirety of the ILD 516 and an entirety of the CESL 514 .
- the cavity 536 B extends into the oxide layer 512 .
- a portion of the oxide layer 512 remains as a bottom surface of the cavity 536 B.
- a remaining portion of the oxide layer 512 ranges from about 10% to about 90% of the oxide layer 412 .
- the amount of the remaining portion of the oxide layer 512 is a result of manufacturing variation during an etching process used to define the cavity 536 B.
- FIG. 5 C is a cross sectional view of a chip 500 C in accordance with some embodiments.
- the chip 500 C is similar to the chip 500 A ( FIG. 5 A ).
- the chip 500 C includes cavity 536 C which extends through an entirety of the interconnect structure 540 , an entirety of the ILD 516 , an entirety of the CESL 514 , and an entirety of the oxide layer 512 above the polysilicon layer 530 ′.
- the cavity 536 C extends into the polysilicon layer 530 ′.
- a portion of the polysilicon layer 530 ′ remains as a bottom surface of the cavity 536 C.
- a remaining portion of the polysilicon layer 530 ′ ranges from about 10% to about 90% of the polysilicon layer 430 .
- the amount of the remaining portion of the polysilicon layer 530 ′ is a result of manufacturing variation during an etching process used to define the cavity 536 C.
- FIG. 5 D is a cross sectional view of a chip 500 D in accordance with some embodiments.
- the chip 500 D is similar to the chip 500 C ( FIG. 5 C ).
- the chip 500 D includes cavity 536 D which extends through an entirety of the interconnect structure 540 , an entirety of the ILD 516 , an entirety of the CESL 514 , an entirety of the oxide layer 512 to expose portions of the waveguide layer 520 and the grating 522 that extend beyond an edge of the polysilicon layer 530 ′.
- a portion of the polysilicon layer 530 ′ remains over the waveguide layer 520 and the grating 522 .
- FIG. 5 E is a cross sectional view of a chip 500 E in accordance with some embodiments.
- the chip 500 E is similar to the chip 500 D ( FIG. 5 D ).
- the chip 500 E includes a segmented polysilicon layer 530 ′′.
- the polysilicon layer 530 ′ is etched to define openings to form the segmented polysilicon layer 530 ′′. Removing these portions of the polysilicon layer 530 ′ increases an amount of the waveguide layer 520 and the grating 522 exposed. Thus, an amount of the waveguide layer 520 and the grating 522 able to receive the optical signal without absorption from other materials is increases.
- the segmented polysilicon layer 530 ′′ occupies about 20% to about 30% of the cavity width wc of the cavity 536 E. If the amount of the cavity width wc occupied by the segmented polysilicon layer 530 ′′ is too small, then a risk of over-etching increases because the etching tool is less likely to detect the presence of the segmented polysilicon layer 530 ′′ and terminate the etching process, in some instances.
- segmented polysilicon layer 530 ′′ is only shown with respect to a cavity that extends all the way to the segmented polysilicon layer 530 ′′, one of ordinary skill in the art would recognize that the segmented polysilicon layer 430 ′′ is usable with any of the embodiments in FIGS. 5 A- 5 C .
- the examples of chips 500 A- 500 E result from different etching depths for the cavities 536 A- 536 E.
- different chips on a same wafer will have cavities from the different examples in FIGS. 5 A- 5 E .
- chips on the wafer closer to an edge of the wafer are more likely to have cavities which extend farther into the chip than chips near a center of the wafer.
- FIG. 6 is a perspective view of a grating 600 in accordance with some embodiments.
- Grating 600 is usable as grating 140 ( FIG. 1 ) in some embodiments.
- the gratings 140 , 422 and 522 ( FIGS. 1 , 4 A- 4 G and 5 A- 5 E ) are cross sectional views of the grating 600 taken along line A-A, in some embodiments.
- Grating 700 ( FIG. 7 ) is a cross sectional view of the grating 600 taken along line B-B.
- FIG. 7 is a cross sectional view of a grating 700 in accordance with some embodiments.
- the grating includes a substrate 780 .
- Substrate 780 is similar to substrate 122 ( FIG. 1 ).
- a first reflection layer 790 is over the substrate 780 .
- a first oxide layer 782 is over the first reflection layer 790 .
- a waveguide layer 724 is over the first oxide layer 782 .
- the waveguide layer 724 is similar to the waveguide layer 124 .
- a cladding layer 770 is over the waveguide layer.
- a second reflection layer 792 is over the cladding layer.
- the first reflection layer 790 reflects light from an optical signal back toward a top surface of the grating 700 in order to prevent the light from being lost into the substrate 780 .
- the first reflection layer 790 includes aluminum, copper, nickel, alloys thereof, or another suitable material.
- a thickness of the first reflection layer 790 ranges from about 0.1 ⁇ m to about 10 ⁇ m. If the thickness of the first reflection layer 790 is too small, a risk of light from the optical signal escaping the grating 700 increases, in some instances. If the thickness of the first reflection layer 790 is too great, material is wasted without a noticeable improvement in performance, in some instances.
- the first oxide layer 782 supports the waveguide layer 724 and has a different refractive index from the waveguide layer 724 .
- the difference in refractive index helps to reflect light from the optical signal back into the waveguide layer 724 during propagation of the optical signal along the waveguide layer 724 .
- the first oxide layer 782 has a thickness ranging from about 500 nm to about 3,000 nm. If the thickness of the first oxide layer 782 is too small, then a risk of light penetrating through the first oxide layer 782 increases, in some instances. If the thickness of the first oxide layer 782 is too great, then material is wasted without a noticeable improvement in performance in some instances.
- the first oxide layer 782 contains a material other than silicon oxide, such as silicon nitride, aluminum oxide, hafnium oxide or another suitable material.
- the cladding layer 770 helps to reflect light from the optical signal back into the waveguide layer 724 similar to the first oxide layer 782 .
- a thickness of the cladding layer ranges from about 0.6 ⁇ m to about 3 ⁇ m. If the thickness of the cladding layer 770 is too small, then a risk of light penetrating through the cladding layer 770 increases, in some instances. If the thickness of the cladding layer 770 is too great, then material is wasted without a noticeable improvement in performance in some instances.
- the cladding layer 770 contains silicon oxide, silicon nitride, aluminum oxide, hafnium oxide or another suitable material. In some embodiments, the cladding layer 770 contains a same material as the first oxide layer 782 . In some embodiments, the cladding layer 770 contains a different material from the first oxide layer 782 .
- the second reflection layer 792 reflects light from the optical signal back toward a bottom surface of the grating 700 in order to prevent the light from being lost out of the grating 700 .
- the second reflection layer 792 includes aluminum, copper, nickel, alloys thereof, or another suitable material.
- the second reflection layer 792 contains a same material as the first reflection layer 790 .
- the second reflection layer 792 contains a different material from the first reflection layer 790 .
- a thickness of the second reflection layer 792 ranges from about 0.1 ⁇ m to about 10 ⁇ m. If the thickness of the second reflection layer 792 is too small, a risk of light from the optical signal escaping the grating 700 increases, in some instances.
- the thickness of the second reflection layer 792 is different from the thickness of the first reflection layer 790 . In some embodiments, the thickness of the second reflection layer 792 is equal to the thickness of the first reflection layer 790 . In some embodiments, the second reflection layer 792 is only over portions of the waveguide layer 724 that does not include a grating in order to maximize the transmission of the optical signal, e.g., the optical signal 115 ( FIG. 1 ), to the grating for transmission along the waveguide layer 724 .
- the coupling system includes an optical fiber configured to carry an optical signal.
- the coupling system further includes a chip in optical communication with the optical fiber.
- the chip includes a substrate.
- the chip further includes a grating on a first side of the substrate, wherein the grating is configured to receive the optical signal.
- the chip further includes an interconnect structure over the grating on the first side of the substrate, wherein the interconnect structure defines a cavity aligned with the grating.
- the chip further includes a first polysilicon layer on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate.
- the chip further includes a second polysilicon layer over the grating, wherein the second polysilicon layer is between the interconnect structure and the grating. In some embodiments, the second polysilicon layer directly contacts the grating. In some embodiments, a width of the second polysilicon layer is greater than a width of the cavity. In some embodiments, a width of the second polysilicon layer is less than a width of the cavity. In some embodiments, the width of the second polysilicon layer is about 20% to about 30% of the width of the cavity. In some embodiments, the second polysilicon layer is a segmented polysilicon layer. In some embodiments, the chip includes an oxide layer over the grating, and the oxide layer is between the grating and the interconnect structure.
- the cavity extends beneath the oxide layer to define a recess in a bottommost surface of the oxide layer. In some embodiments, the cavity exposes at least a portion of the grating. In some embodiments, the cavity fails to expose any of the grating.
- the chip includes a substrate.
- the chip further includes a waveguide layer on a first side of the substrate.
- the chip further includes a grating optically connected to the waveguide layer.
- the chip further includes an interconnect structure on the first side of the substrate, wherein the waveguide layer is between the interconnect structure and the substrate, and the interconnect structure defines a cavity aligned with the grating.
- the chip further includes a first polysilicon layer over the grating on the first side of the substrate.
- the chip further includes a second polysilicon layer on a second side of the substrate, wherein a maximum thickness of the first polysilicon layer is equal to a maximum thickness of the second polysilicon layer.
- a width of the first polysilicon layer is greater than a width of the cavity. In some embodiments, a width of the first polysilicon layer is less than a width of the cavity. In some embodiments, the first polysilicon layer is a segmented polysilicon layer. In some embodiments, the cavity exposes the first polysilicon layer. In some embodiments, the chip further includes a dielectric layer over the first polysilicon layer, wherein the dielectric layer is between a bottommost surface of the cavity and the first polysilicon layer.
- An aspect of this description relates to a method of making a chip.
- the method includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate.
- the method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess.
- the method further includes implanting dopants into the substrate to define an implant region.
- the method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region.
- CESL contact etch stop layer
- the method further includes patterning the CESL to define a CESL block.
- the method further includes forming a waveguide and a grating in the substrate.
- the method further includes forming an interconnect structure over the waveguide, the grating and the CESL block.
- the method further includes etching the interconnect structure to define a cavity aligned with the grating.
- patterning the CESL further includes defining a CESL spacer parallel to a sidewall of the first polysilicon layer closest to the recess.
- the method further includes depositing an oxide layer over the CESL block; patterning the oxide layer to define an oxide spacer along a sidewall of the CESL block; depositing a second polysilicon layer over the CESL block and the oxide spacer; and patterning the second polysilicon layer to define a polysilicon spacer along a sidewall of the oxide spacer.
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Abstract
Description
- Optical gratings are usable for directing optical signals between a chip and an optical fiber. Optical gratings are usable for directing optical signals from the chip to the optical fiber as well as directing optical signals from the optical fiber to the chip. The ability of the optical grating to effectively couple the chip to the optical fiber is based on alignment between the optical signal and the optical grating.
- A cavity is formed in the layers of the chip between the optical fiber and the optical grating in order to reduce signal loss for the optical signal passing through the layers of the chip. The signal loss is due to absorption, reflection, refraction, etc. During formation of the cavity, a risk of over-etching, which damages a waveguide in the chip, is possible. In addition, charge accumulates in the substrate during the etching process.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 is a cross sectional view of a fiber to chip coupling system in accordance with some embodiments. -
FIG. 2 is a flowchart of a method of making a chip in accordance with some embodiments. -
FIGS. 3A-3E are cross sectional views of a chip during various stages of manufacture in accordance with some embodiments. -
FIGS. 4A-4G are cross sectional views of a chip in accordance with some embodiments. -
FIGS. 5A-5E are cross sectional views of a chip in accordance with some embodiments. -
FIG. 6 is a perspective view of a grating in accordance with some embodiments. -
FIG. 7 is a cross sectional view of a grating in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In optoelectrical devices, an optical signal is used to convey a signal between different electrical components. The optical signal is carried by an optical fiber between the electrical components. In order to couple the optical signal into a chip, a grating coupler is used to receive the optical signal and couple the signal into the waveguide to be transferred to an optoelectronic component for converting the optical signal into an electrical signal.
- As the optical signal passes through various layers of the chip, the optical signal is subject to absorption, reflection, refraction and other dispersive phenomena that reduces the strength and consistency of the optical signal. A cavity is defined in the chip above the grating coupler in order to maximize a strength and consistency of the optical signal that reaches the grating coupler. The cavity is formed by an etching process, such as reactive ion etching (RIE). During the etching process, there is a risk of over-etching resulting in damage to the waveguide layer within the chip. Damage to the waveguide layer increases a risk that the optical signal is unable to reach the optoelectronic components or that the strength of the optical signal is reduced based on refraction or reflection at the damaged locations of the waveguide layer.
- In addition, charge accumulates in the substrate during the etching process. Charge accumulation is especially problematic in silicon-on-insulator (SOI) substrates, where the charge accumulates within the insulating layers, such as silicon oxide. Charge accumulation weakens the substrate and increases a risk of the substrate breaking.
- The current disclosure includes a polysilicon layer over at least a portion of the waveguide layer. The polysilicon layer functions as an etch stop layer to reduce the risk of over-etching damaging the waveguide layer. The current disclosure also includes a polysilicon layer on a backside of the substrate, opposite from the cavity, in order to help to reduce charge accumulation. The backside polysilicon layer helps to conduct charge from insulating materials into the ambient environment or to a ground. As a result, a risk of the substrate breaking due to charge accumulation is reduced.
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FIG. 1 is a cross sectional view of a fiber tochip coupling system 100 in accordance with some embodiments.System 100 includes anoptical fiber 110 configured to emit anoptical signal 115.System 100 further includes achip 120.Chip 120 includes asubstrate 122. Awaveguide layer 124 is over thesubstrate 122. An inter-layer dielectric (ILD) 126 is over thewaveguide layer 124. Anetch stop layer 128 is over the ILD 126. Aninterconnect structure 130 is over theetch stop layer 128. One of ordinary skill in the art would recognize that theinterconnect structure 130 includes multiple inter-metal dielectric (IMD) layers and conductive layers in order to electrically connect different components of thechip 120. Acavity 136 extends through theinterconnect structure 130, theetch stop layer 128 and a portion of the ILD 126. Agrating 140 extends from thewaveguide layer 124 and is configured to receive theoptical signal 115 passing through thecavity 136, any remaining portion of theinterconnect structure 130, theetch stop layer 128 and the ILD 126. Thegrating 140 is configured to direct theoptical signal 115 into thewaveguide layer 124 to components within thechip 120. Thesystem 100 further includes apolysilicon layer 150 on a surface of thesubstrate 122 opposite to thecavity 136. Thepolysilicon layer 150 helps to release charge that accumulates in thesubstrate 122 during the etching to form thecavity 136. In some embodiments, thesystem 100 includes apolysilicon layer 160 over thegrating 140. Thepolysilicon layer 160 acts as an etch stop layer during formation of thecavity 136 and helps to reduce the risk of damage to thegrating 140 or thewaveguide layer 124 due to over-etching. One of ordinary skill in the art would recognize that additional layers, such as cladding and reflective layers, would be included in thesystem 100. - The
optical fiber 110 is a single mode optical fiber having a width wf ranging from about 8 microns (μm) to about 12 μm. In some embodiments, theoptical fiber 110 is a multimode optical fiber having a width wf ranging from about 45 μm to about 70 μm. The width wf is based on a size of a core of theoptical fiber 110 including any additional cladding or cover layers. If the width wf is too large, then the size of theoptical fiber 110 is unnecessarily increased. If the width wf is too small, then there is a risk of loss of optical signal from the core or interference of the optical signal from external light sources. Theoptical fiber 110 is configured to convey theoptical signal 115 from an external device to chip 120. Theoptical fiber 110 is aligned with thecavity 136 in order for theoptical signal 115 to efficiently couple to thegrating 140. - The
optical signal 115 has a wavelength. In some embodiments where theoptical fiber 110 is a single mode fiber, the wavelength of theoptical signal 115 ranges from about 1260 nanometers (nm) to about 1360 nm. In some embodiments where theoptical fiber 110 is a multimode optical fiber, the wavelength of theoptical signal 115 ranges from about 770 nm to about 910 nm. The wavelength of theoptical signal 115 is based on a light source used to generate the optical signal. In some embodiments where theoptical fiber 110 is a single mode optical fiber, the light source is a laser or a laser diode. In some embodiments where theoptical fiber 110 is a multimode optical fiber, the light source of the optical fiber is a light emitting diode (LED). Theoptical signal 115 will diverge upon exiting theoptical fiber 110. - The
chip 120 includes at least one optoelectronic component, such as a laser driver, digital control circuit, photodetectors, waveguides, small form-factor pluggable (SFP) transceiver, High-speed phase modulator (HSPM), calibration circuit, distributed Mach-Zehnder Interferometer (MZI), grating couplers, light sources, (i.e., laser), etc. The optoelectronic component is configured to receive theoptical signal 115 from thewaveguide layer 124 and convert theoptical signal 115 into an electrical signal. While the description ofFIG. 1 is written as thechip 120 receiving theoptical signal 115 from theoptical fiber 110, one of ordinary skill in the art would understand that thesystem 100 is also usable to transfer an optical signal from thechip 120 to theoptical fiber 110. That is, the optoelectronic component generates the optical signal, which is then transferred to theoptical fiber 110 through thewaveguide layer 124 and the grating 140, in some embodiments. - In some embodiments,
substrate 122 includes an elementary semiconductor including silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate has a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. In some embodiments, the alloy SiGe is formed over a silicon substrate. In some embodiments,substrate 122 is a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor on insulator structure, such as a silicon on insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epi layer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure. - The
waveguide layer 124 is configured to direct theoptical signal 115 from the grating 140 to an optoelectronic component of thechip 120. Thewaveguide layer 124 includes an optical transparent material. In some embodiments, thewaveguide layer 124 includes silicon. In some embodiments, thewaveguide layer 124 includes plastic. In some embodiments, thewaveguide layer 124 includes a same material as thegrating 140. In some embodiments, thewaveguide layer 124 includes a different material from thegrating 140. In some embodiments, thewaveguide layer 124 is integral with thegrating 140. In some embodiments, thewaveguide layer 124 is a slab waveguide, a planar waveguide or a light pipe. In order for the grating 140 to effectively couple theoptical signal 115 into thewaveguide layer 124, the grating 140 redirects the incidentoptical signal 115 into an angle of acceptance of thewaveguide layer 124. The angle of acceptance of thewaveguide layer 124 is based on the wavelength of the optical signal, the frequency of the optical signal and dimensions of thewaveguide layer 124. TheILD 126 includes a dielectric material. Contacts are formed through theILD 126 to electrically connect the optoelectronic component to theinterconnect structure 130 and to other components within the chip or to external devices. TheILD 126 is deposited on thesubstrate 122 using chemical vapor deposition, physical vapor deposition, or another suitable deposition process. In some embodiments, theILD 126 has a thickness ranging from about 500 nm to about 3000 nm. If the thickness is too great, an aspect ratio for forming the contacts through theILD 126 makes reliable manufacturing difficult and absorption of theoptical signal 115 reduces the strength of the optical signal to an unacceptable level, in some instances. If the thickness is too small, theILD 126 fails to provide sufficient electrical insulating between conductors, such as conductive layer 134, and other components in thechip 120. In some embodiments, theILD 126 includes dielectric materials, such as Si, Si3N4, SiO2 (e.g., quartz, and glass), Al2O3, and H2O, according to various embodiments of the present disclosure. Theetch stop layer 128 is over theILD 126 and has a different etch chemistry from theILD 126 and the IMD layer 132. In some embodiments, theetch stop layer 128 is deposited using chemical vapor deposition or another suitable deposition process. In some embodiments, theetch stop layer 128 includes SiC Si3N4, or another suitable material. In some other embodiments, theetch stop layer 128 has a thickness in a range of about 250 nm to about 350 nm. If the thickness of theetch stop layer 128 is too great, then material is wasted and absorption of theoptical signal 115 reduces the strength of the optical signal to an unacceptable level, in some instances. If the thickness of theetch stop layer 128 is too small, then a risk of etching through theetch stop layer 128 during the formation of thecavity 136 or formation of electrical connections between theILD 126 and the conductive layer 134 increases, in some instances. - The
interconnect structure 130 is configured to electrically connect the optoelectronic component to other components within thechip 120 or to external devices, for example, through chip bonding. The interconnect structure includes multiple IMD layers and multiple conductive layer. - The IMD layers includes a dielectric material. The IMD layers provide electrical insulation between the conductive layers and other conductive elements within the
chip 120, such as the contacts in theILD 126. The IMD layers are deposited using chemical vapor deposition, physical vapor deposition, or another suitable deposition process. In some embodiments, the IMD layers have a thickness ranging from about 1,000 angstroms to about 30,000 angstroms. If the thickness is too great, an aspect ratio for forming the electrical connections through the IMD layers makes reliable manufacturing difficult, in some instances. If the thickness is too small, the IMD layers fail to provide sufficient electrical insulating between conductors, and other components in thechip 120. In some embodiments, the IMD layers include dielectric materials, such as Si, Si3N4, SiO2 (e.g., quartz, and glass), Al2O3, and H2O, according to various embodiments of the present disclosure. In some embodiments, the IMD layers include a low-k dielectric material. In some embodiments, the IMD layers include a same material as theILD 126. In some embodiments, the IMD layers include a different material from theILD 126. - The conductive layers are configured to convey electrical signals to various components in the
chip 120, for example the optoelectronic component. In some embodiments the conductive layers include a seed layer. In some embodiments, the conductive layers include copper, aluminum, tungsten, alloys thereof or another suitable material. - The
cavity 136 reduces an amount of material that theoptical signal 115 passes through before being directed into thewaveguide layer 124 by thegrating 140. Thecavity 136 extends through theinterconnect structure 130, theetch stop layer 128 and through a portion of theILD 126. In some embodiments, thecavity 136 extends through a portion of theinterconnect structure 130. In some embodiments, thecavity 136 extends through less than all of theetch stop layer 128. The sidewalls of thecavity 136 are substantially vertical. In some embodiments, the sidewalls of thecavity 136 are tapered. In some embodiments, a width wc of the cavity ranges from about 2.5-times to about 3.5-times more than the width wf of theoptical fiber 110. In some embodiments, the width wc ranges from about 25 μm to about 35 μm. This width wc helps to account for misalignment between theoptical fiber 110 and thecavity 136. The width wc also helps to permit the entireoptical signal 115 to pass through thecavity 136 even though theoptical signal 115 will diverge upon exiting from the optical fiber. If the width wc is too small, then misalignment or divergence of theoptical signal 115 will increase the risk of loss of a portion of theoptical signal 115, in some instances. If the width we is too great, then routing possibilities in theinterconnect structure 130 are reduced or an overall size of thechip 120 is increased, in some instances. - The grating 140 is configured to couple the
optical signal 115 from theoptical fiber 110 into thewaveguide layer 124. The grating 140 directs theoptical signal 115 based on an incident angle of theoptical signal 115 and dimensions of features of thegrating 140. In some embodiments, thegrating 140 includes a variable grating section. The variable grating section includes grating features having different geometric dimensions. In some embodiments, the variable grating section includes grating features having a variation in width, depth, pitch or combinations thereof. In some embodiments, thegrating 140 includes a uniform grating section. The uniform grating section includes grating features having consistent geometric dimensions. The grating 140 includes an optical transparent material. In some embodiments, thegrating 140 includes silicon. In some embodiments, thegrating 140 includes plastic. In some embodiments, thegrating 140 is integral with thewaveguide layer 124. - The
polysilicon layer 150 helps to release charge that accumulates during the formation of thecavity 136. In some embodiments, thepolysilicon layer 150 is undoped. In some embodiments, thepolysilicon layer 150 contains dopants. In some embodiments, thepolysilicon layer 150 is connected to a ground or reference voltage in order to assist with releasing the accumulated charge. In some embodiments, a thickness of thepolysilicon layer 150 ranges from about 1300 angstroms (Å) to about 1600 Å. If the thickness of thepolysilicon layer 150 is too small, then a resistance to releasing the accumulated charge increases to an unacceptable level, in some instances. If the thickness of thepolysilicon layer 150 is too great, then material is wasted without a noticeable increase in performance and an overall size of thechip 120 needlessly increases, in some instances. - The
polysilicon layer 160 acts as an etch stop layer during the formation of thecavity 136 in order to help reduce the risk of over-etching damage to the grating 140 or to thewaveguide layer 124. In some embodiments, thepolysilicon layer 160 is undoped. In some embodiments, thepolysilicon layer 160 contains dopants. In some embodiments, a thickness of thepolysilicon layer 160 ranges from about 1300 angstroms (A) to about 1600 A. If the thickness of thepolysilicon layer 160 is too small, then risk of over-etching increases, in some instances. If the thickness of thepolysilicon layer 160 is too great, then material is wasted without a noticeable increase in performance and an overall size of thechip 150 needlessly increases, in some instances. In some embodiments, the thickness of thepolysilicon layer 150 is equal to the thickness of thepolysilicon layer 160. In some embodiments, the thickness of thepolysilicon layer 150 is different from the thickness of thepolysilicon layer 160. In some embodiments, thepolysilicon layer 160 is removed during the formation of the cavity. For examples, in some embodiments, following use as an etch stop layer, a subsequent etching process, e.g., a wet etching, is used to remove thepolysilicon layer 160. -
FIG. 2 is a flowchart of amethod 200 of making a chip in accordance with some embodiments.Method 200 includesoptional operation 202 in which a SOI substrate is formed or an oxide layer is deposited on a substrate. In some embodiments, the oxide layer is formed by oxidizing a silicon substrate using high temperature oxidation (HTO). In some embodiments, the oxide layer is deposited by chemical vapor deposition. In some embodiments,operation 202 is omitted. In some embodiments,operation 202 is omitted because the SOI substrate is provided by an outside vendor. - In
operation 204, a polysilicon layer is deposited on the substrate. In embodiments which includeoperation 202, the polysilicon layer is deposited on the oxide layer. In some embodiments, a thickness of the polysilicon layer ranges from about 1300 A to about 1600 A. If the thickness of the polysilicon layer is too small, then a resistance to releasing the accumulated charge increases to an unacceptable level, in some instances. If the thickness of the polysilicon layer is too great, then material is wasted without a noticeable increase in performance, in some instances. In some embodiments, the polysilicon layer is deposited using low pressure chemical vapor deposition. In some embodiments, the polysilicon is deposited using a silane gas precursor. In some embodiments, the precursor gas is has a concentration ranging from about 15 volume percent to about 40 volume percent with respect to the total volume of the CVD precursor gas with the remaining volume percent portion nitrogen gas. If the concentration of the precursor gas is too low, then the formation process duration is increased, in some instances. If the concentration of the precursor gas is too high, then material is wasted without a noticeable increase in performance, in some instances. In some embodiments, the deposition process is carried out at a pressure of about 100 milliTorr to about 1 Torr. If the pressure is too low, then the formation process duration is increased, in some instances. If the pressure is too high, then material is wasted without a noticeable increase in performance, in some instances. In some embodiments, the deposition process is carried out at a temperature ranging from about 250° C. to about 650° C. If the temperature is too low, then the formation process duration is increased, in some instances. If the temperature is too high, then a risk of reemission of the deposited material increases, in some instances. - In
optional operation 206, an oxide layer is formed on the polysilicon layer. In some embodiments, the polysilicon layer is partially oxidized in order to form the oxide layer. In some embodiments, the polysilicon layer is oxidized using HTO at a temperature ranging from about 700° C. to about 820° C. If the temperature is too low, then the formation process duration is increased, in some instances. If the temperature is too high, then a risk of consuming too much of the polysilicon layer to permit releasing of accumulated charge increases, in some instances. In some embodiments, the oxide layer is deposited on the polysilicon layer. In some embodiments, the oxide layer is deposited using chemical vapor deposition. In some embodiments,operation 206 is omitted. In some embodiments,operation 206 is omitted if an oxide space is later formed, seeoperation 242 below. -
FIG. 3A is a cross sectional view of achip 300 A following operation 206 in accordance with some embodiments. Thechip 300A includes asubstrate 302. Atop oxide layer 304 a is over a top surface of thesubstrate 302 and abottom oxide layer 304 b is on a bottom surface of thesubstrate 302. In some embodiments, a thickness of thetop oxide layer 304 a ranges from about 400 A to about 600 A. If the thickness of thetop oxide layer 304 a is too high, material is wasted without a noticeable increase in performance and a size of thechip 300A is needlessly increased, in some instances. If the thickness of thetop oxide layer 304 a is too small, then thetop oxide layer 304 a fails to provide sufficient insulation between apolysilicon layer 306 and thesubstrate 302. In some embodiments, a thickness of thebottom oxide layer 304 b ranges from about 1.5 microns (μm) to about 2.5 μm. If the thickness of thebottom oxide layer 304 b is too high, material is wasted without a noticeable increase in performance and a size of thechip 300A is needlessly increased, in some instances. If the thickness of thebottom oxide layer 304 b is too small, then thebottom oxide layer 304 b fails to provide sufficient insulation between apolysilicon layer 306 and thesubstrate 302. - The
polysilicon layer 306 surrounds thesubstrate 302,top oxide layer 304 a andbottom oxide layer 304 b. WhileFIG. 3A shows an upper portion of thepolysilicon layer 306 is thicker than a lower portion of thepolysilicon layer 306,polysilicon layer 306 is conformally deposited. Conformal deposition means that a thickness of thepolysilicon layer 306 is substantially uniform on all surfaces. In some embodiments, a thickness of thepolysilicon layer 306 ranges from about 1300 A to about 1600 A. If the thickness of thepolysilicon layer 306 is too small, then a resistance to releasing the accumulated charge increases to an unacceptable level, in some instances. If the thickness of thepolysilicon layer 306 is too great, then material is wasted without a noticeable increase in performance and an overall size of thechip 300A needlessly increases, in some instances. - An
oxide layer 308 surrounds thepolysilicon layer 306. Theoxide layer 308 is conformally formed. In some embodiments, a thickness of theoxide layer 308 ranges from about 50 A to about 70 A. If the thickness of theoxide layer 308 is too small, then protection of thepolysilicon layer 306 during subsequent processing is insufficient, in some instances. If the thickness of theoxide layer 308 is too great, then a risk of consuming too much of the polysilicon layer to permit releasing of accumulated charge increases, in some instances - Returning to
method 200, inoperation 208, the oxide layer and the polysilicon layer are patterned to define a recess. In some embodiments, the patterning is performed using a photoresist and photolithography. In some embodiments, the recess is defined using an etching process. In some embodiments, the etching process is a dry etching process. In some embodiments, the etching process is a wet etching process. In some embodiments, the etching process oxidizes a sidewall of the polysilicon layer during formation of the recess. In some embodiments, an additional oxidation process, such as HTO, is performed following the etching process. In some embodiments, a temperature of the oxidation process ranges from about 700° C. to about 820° C. If the temperature is too low, then the oxidation process duration is increased, in some instances. If the temperature is too high, then a risk of consuming too much of the polysilicon layer to permit releasing of accumulated charge increases, in some instances. -
FIG. 3B is a cross sectional view of achip 300 B following operation 208 in accordance with some embodiments. In comparison with thechip 300A, thechip 300B includes arecess 310 which a portion of thepolysilicon layer 306 and theoxide layer 308 were removed. Thechip 300B further includes anoxide spacer 312 on a sidewall of thepolysilicon layer 306. In some embodiments, a width of theoxide spacer 312 ranges from about 30 A to about 50 A. If the thickness of theoxide spacer 312 is too small, then protection of thepolysilicon layer 306 during subsequent processing is insufficient, in some instances. If the thickness of theoxide spacer 312 is too great, then a risk of consuming too much of the polysilicon layer to permit releasing of accumulated charge increases, in some instances. Formation ofoxide spacer 312 will increase the thickness of other oxide layers in thechip 300B, in some instances. - Returning to
method 200, in operation 210 a transistor structure is formed in the substrate. In some embodiments, the transistor structure includes a planar transistor. In some embodiments, the transistor structure includes a fin field effect transistor (FinFET). In some embodiments, the transistor structure includes a gate all around (GAA) transistor structure. In some embodiments, the transistor structure is formed by removing a portion of the substrate and growing a germanium feature in the substrate. In some embodiments, source/drain (S/D) features for formed in the substrate. In some embodiments, the S/D features are formed by ion implantation. In some embodiments, the S/D features are formed by recessing the substrate and growing strained S/D features in the recesses. In some embodiments, forming the transistor structure includes forming a lightly doped drain (LDD) region. In some embodiments, the LDD region is formed by ion implantation. - In
operation 212, a contact etch stop layer (CESL) is deposited over the substrate and the transistor structure. In some embodiments, the CESL includes silicon nitride, silicon carbide or another suitable material. In some embodiments, the CESL is deposited using chemical vapor deposition. In some embodiments, a thickness of the CESL ranges from about 800 A to about 1,000 A. If the thickness of the CESL is too small, then a risk of inadvertently etching through the CESL increases, in some instances. If the thickness of the CESL is too great, material is wasted without a noticeable increase in performance and a size of the chip is increased needlessly, in some instances. In some embodiments, the CESL is deposited to form a conformal layer. Followingoperation 212, themethod 200 proceeds to eitheroperation 220 or tooperation 240. - In
operation 220, the CESL is patterned to define a CESL block and a CESL spacer. The CESL block is over a portion of the transistor structure. The CESL spacer covers a sidewall of the oxide spacer formed inoperation 208. In some embodiments, the CESL spacer is omitted. The CESL spacer is omitted if the thickness of the oxide spacer is sufficient to avoid being etched through during subsequent processing of the chip. -
FIG. 3C is a cross sectional view of achip 300C following theoperation 220 in accordance with some embodiments. In comparison with thechip 300B, thechip 300C includes atransistor structure 320. ACESL block 330 is over a portion of thetransistor structure 320. ACESL spacer 332 covers a sidewall of theoxide spacer 312. - The
transistor structure 320 includes achannel region 322, a first S/D region 324 on a first side of thechannel region 322, a second S/D region 326 on a second side of thechannel region 322 opposite the first side. Thetransistor structure 320 further includes anLDD region 328 overlapping with thechannel region 322. - In some embodiments, the
channel region 322 includes doped silicon. In some embodiments, thechannel region 322 includes germanium. In some embodiments, a distance D1 from a top of thechannel region 322 to a bottom of thechannel region 322 ranges from about 225 nanometers (nm) to about 275 nm. If the distance D1 is too small, there is an increased resistance within thechannel region 322 that prevents efficient signal transfer between the first S/D region 324 and the second S/D region 326, in some instances. If the distance D1 is too large, a risk of shorting the channel region to thepolysilicon layer 306 on the bottom surface of thesubstrate 302 increases, in some instances. In some embodiments, thechannel region 322 is separated from the bottom surface of thesubstrate 302 by a distance D2 ranging from about 90 nm to about 120 nm. If the distance D2 is too small, a risk of shorting the channel region to thepolysilicon layer 306 on the bottom surface of thesubstrate 302 increases, in some instances. If the distance D1 is too large, there is an increased resistance within thechannel region 322 that prevents efficient signal transfer between the first S/D region 324 and the second S/D region 326, in some instances. In some embodiments, thechannel region 322 extends a distance D3 below the top surface of thesubstrate 302 ranging from about 150 nm to about 180 nm. If the distance D3 is too small, there is an increased resistance within thechannel region 322 that prevents efficient signal transfer between the first S/D region 324 and the second S/D region 326, in some instances. If the distance D3 is too large, a risk of shorting the channel region to thepolysilicon layer 306 on the bottom surface of thesubstrate 302 increases, in some instances. - The first S/
D region 324 and the second S/D region 326 include higher dopant concentrations in thesubstrate 302. In some embodiments, the first S/D region 324 and the second S/D region 326 are strained S/D structures. In some embodiments, the first S/D region 324 has a first dopant type; and the second S/D region 326 has a second dopant type opposite the first dopant type. In some embodiments, the first S/D region 324 and the second S/D region 326 have a same dopant type. TheLDD region 328 overlaps with thechannel region 322 and helps with switching speed of thetransistor structure 320. In some embodiments, theLDD region 328 has a same dopant type as the second S/D region 326. - The
CESL block 330 overlaps thechannel region 322. In some embodiments, the CESL block 330 partially overlaps at least one of the first S/D region 324 or the second S/D region 326. The CESL block 330 overhangs the channel region by an overhang width wo of at least about 10 nm. If the overhang width wo is too small, then theCESL block 330 fails to provide sufficient protection for thechannel region 322 during subsequent processing, in some instances. In some embodiments, the overhang width wo is the same on both sides of thechannel region 322. In some embodiments, the overhang width wo is different on the first side of thechannel region 322 than on the second side of thechannel region 322. In some embodiments, a thickness of the CESL block 330 ranges from about 800 A to about 1,000 A. If the thickness of theCESL block 330 is too small, then a risk of inadvertently etching through the CESL block 330 increases, in some instances. If the thickness of theCESL block 330 is too great, material is wasted without a noticeable increase in performance and a size of the chip is increased needlessly, in some instances. - The
CESL spacer 332 covers the sidewall of theoxide spacer 312. In some embodiments, a width ws of theCESL spacer 332 ranges from about 800 A to about 1,000 A. If the width ws of theCESL spacer 332 is too small, then a risk of inadvertently etching through theCESL spacer 332 increases, in some instances. If the thickness of theCESL spacer 332 is too great, material is wasted without a noticeable increase in performance and a size of the chip is increased needlessly, in some instances. In some embodiments, the width ws of theCESL spacer 332 is equal to the thickness of theCESL block 330. In some embodiments, the width ws of theCESL spacer 322 is different from the thickness of theCESL block 330. - In some embodiments, a thickness tox1 of the
top oxide layer 304 a between thesubstrate 302 and thepolysilicon layer 306 ranges from about 400 A to about 600 A. If the thickness tox1 is too small, a risk of electrical coupling between thesubstrate 302 and thepolysilicon layer 306 increases, in some instances. If the thickness tox1 is too large, then material is wasted without noticeable improvement in performance, in some instances. In some embodiments, a thickness tox2 of the top oxide layer 304 in therecess 310 ranges from about 80 A to about 90 A. If the thickness tox2 is too small, a risk of electrical coupling between thesubstrate 302 and subsequently formed layers increases, in some instances. If the thickness tox2 is too large, then aspect ratios for contacts to be connected to the first S/D region 324 or the second S/D region 326 increases making manufacturing more difficult, in some instances. - Returning to
method 200, in operation 230 a waveguide layer and a grating are formed on the substrate. In some embodiments, the waveguide layer and the grating are independently formed using silicon, plastic or another suitable material. In some embodiments, the waveguide layer and the grating for integral and a single layer is deposited and then patterned to define the grating as part of the waveguide layer. In some embodiments, the silicon is deposited using chemical vapor deposition. In some embodiments, the plastic is deposited using spin on coating, chemical vapor deposition, or another suitable technique. In some embodiments, the grating is patterned using photolithography and etching. In some embodiments, the grating includes a variable grating region. In some embodiments, the grating includes a uniform grating region. In some embodiments, the grating includes a combination of a variable grating region and a uniform grating region. - In
operation 232, an interconnect structure is formed over the substrate. The interconnect structure extends over the transistor structure and the grating. The interconnect structure is formed by alternately depositing dielectric layers and etch stop layers. The dielectric layers have a different etch selectivity from the etch stop layers. In some embodiments, the dielectric layers include oxide, silicon nitride, or another low-k dielectric material. In some embodiments, the etch stop layers include silicon nitride, silicon oxide, silicon carbide or another suitable material. In some embodiments, the dielectric layers and the etch stop layers are deposited using chemical vapor deposition. - Conductive elements are formed in the dielectric layers and the etch stop layers in order to electrically connect different components of the chip or to electrically connect a component of the chip to an external device. Openings for the conductive elements are formed in the dielectric layers and the etch stop layers using a series of photolithography and etching processes. In some embodiments, the conductive elements include copper, aluminum, tungsten or another suitable conductive material. In some embodiments, the conductive elements are formed by plating, physical vapor deposition or another suitable process.
- In
operation 234, a cavity is formed in the interconnect structure. The cavity is aligned with the grating in order to permit light to pass through the cavity to be incident on the grating. The cavity is formed using a series of photolithography and etching processes. In some embodiments, the cavity is formed using a dry etching process where the etchant is selected based on a material being etched. In some embodiments, the cavity extends through an entirety of the interconnect structure. In some embodiments, the cavity extends through less than the entire interconnect structure. In some embodiments, the sidewalls of the cavity are perpendicular to the top surface of the substrate. In some embodiments, the sidewalls of the cavity are tapered. In some embodiments, the width ranges from about 25 μm to about 35 μm. This width helps to account for misalignment between the optical fiber and the cavity. The width also helps to permit the entire optical signal to pass through the cavity even though the optical signal will diverge upon exiting from the optical fiber. If the width is too small, then misalignment or divergence of the optical signal will increase the risk of loss of a portion of the optical signal, in some instances. If the width is too great, then routing possibilities in the interconnect structure are reduced or an overall size of the chip is increased, in some instances. - In some embodiments, the
method 200 proceeds fromoperation 212 tooperation 240. Inoperation 240, the CESL is patterned to define the CESL block. Theoperation 240 is similar to theoperation 220, except that theoperation 240 does not form the CESL spacer. - In
optional operation 242, an oxide layer is deposited over the CESL block and then patterned to define oxide spacers on sidewalls of the CESL block. In some embodiments, the oxide layer is deposited using chemical vapor deposition. In some embodiments, the oxide layer is patterned using photolithography and etching processes. In some embodiments, a width of the oxide spacer ranges from about 50 A to about 200 A. If the width of the oxide spacer is too small, a risk of electrically connection between later formed polysilicon spacer and a channel region of the transistor structure increases, in some embodiments. If the width of the oxide spacer is too great, material is wasted without a noticeable increase in performance, in some embodiments. Patterning the oxide layer exposes a top surface of the CESL block. In some embodiments,operation 242 is omitted if an overhang width of the CESL block beyond an edge of the channel region of the transistor structure is sufficient to reduce the risk of electrical coupling between the polysilicon spacer and the channel region. - In
operation 244, a polysilicon layer is deposited over the CESL block. In some embodiments, a thickness of the polysilicon layer ranges from about 50 A to about 200 A. If the thickness of the polysilicon layer is too small, then the polysilicon layer will not sufficient protect from over-etching, in some instances. If the thickness of the polysilicon layer is too great, then material is wasted without a noticeable increase in performance, in some instances. In some embodiments, the polysilicon layer is deposited using the same process as inoperation 204. -
FIG. 3D is a cross sectional view of achip 300 D following operation 244 in accordance with some embodiments. In comparison with thechip 300C, thechip 300D does not include the oxide layer 308 (optional operation 206 was not performed) and does not includeCESL spacer 332. Thechip 300D includesoxide spacers 340 along sidewalls of theCESL block 330. In some embodiments, a width of theoxide spacers 340 ranges from about 50 A to about 200 A. If the width of the oxide spacers is too small, a risk of electrically connection between later formed polysilicon spacer and a channel region of the transistor structure increases, in some embodiments. If the width of the oxide spacers is too great, material is wasted without a noticeable increase in performance, in some embodiments. Thechip 300D further includes apolysilicon layer 350 over theCESL block 330 and over thetop oxide layer 304 a in therecess 310. In some embodiments, a thickness of thepolysilicon layer 350 ranges from about 50 A to about 200 A. If the thickness of the polysilicon layer is too small, then the polysilicon layer will not sufficient protect from over-etching, in some instances. If the thickness of the polysilicon layer is too great, then material is wasted without a noticeable increase in performance, in some instances. - Returning to
method 200, inoperation 246, the polysilicon layer is patterned to define polysilicon spacers. The polysilicon layer is patterned using photolithography and etching processes. In some embodiments, a width of the polysilicon spacers ranges from about 50 A to about 200 A. If the width of the polysilicon spacers are too small, then the polysilicon spacers will not sufficient protect from over-etching, in some instances. If the width of the polysilicon spacers is too great, then material is wasted without a noticeable increase in performance, in some instances. -
FIG. 3E is a cross section achip 300 E following operation 246 in accordance with some embodiments. In comparison with thechip 300D, thechip 300E includespolysilicon spacers 352 on an opposite side of theoxide spacers 340 from theCESL block 330. In some embodiments, a width of thepolysilicon spacers 352 ranges from about 50 A to about 200 A. If the width of thepolysilicon spacers 352 are too small, then the polysilicon spacers will not sufficient protect from over-etching, in some instances. If the width of thepolysilicon spacers 352 is too great, then material is wasted without a noticeable increase in performance, in some instances. - In some embodiments, a thickness tox1′ of the
top oxide layer 304 a between thesubstrate 302 and thepolysilicon layer 306 ranges from about 800 A to about 1,000 A. If the thickness tox1′ is too small, a risk of electrical coupling between thesubstrate 302 and thepolysilicon layer 306 increases, in some instances. If the thickness tox1′ is too large, then material is wasted without noticeable improvement in performance, in some instances. In some embodiments, a thickness tox2′ of the top oxide layer 304 in therecess 310 ranges from about 120 A to about 150 A. If the thickness tox2′ is too small, a risk of electrical coupling between thesubstrate 302 and subsequently formed layers increases, in some instances. If the thickness tox2′ is too large, then aspect ratios for contacts to be connected to the first S/D region 324 or the second S/D region 326 increases making manufacturing more difficult, in some instances. -
FIG. 4A is a cross sectional view of achip 400A in accordance with some embodiments. Thechip 400A includes asubstrate 402. In some embodiments, thesubstrate 402 is similar to the substrate 122 (FIG. 1 ) or the substrate 302 (FIGS. 3A-3E ). Atop oxide layer 404 a is over a top surface of thesubstrate 402. In some embodiments, thetop oxide layer 404 a is similar to thetop oxide layer 304 a (FIGS. 3A-3E ). Abottom oxide layer 404 b is on a bottom surface of thesubstrate 402 opposite the top surface. In some embodiments, thebottom oxide layer 404 b is similar to thebottom oxide layer 304 b (FIGS. 3A-3E ). Apolysilicon layer 406 is on an opposite side of thebottom oxide layer 404 b from thesubstrate 402. In some embodiments, thepolysilicon layer 406 is similar to the polysilicon layer 150 (FIG. 1 ) or the polysilicon layer 306 (FIGS. 3A-3E ). Asilicon layer 408 is over thetop oxide layer 404 a. Animplant region 410 is in thesilicon layer 408. Anoxide layer 412 is over thesilicon layer 408. ACESL layer 414 is over theoxide layer 412. In some embodiments, theCESL layer 414 is similar to the CESL layer 128 (FIG. 1 ). AnILD 416 is over theCESL layer 414. In some embodiments, theILD 416 is similar to the ILD 126 (FIG. 1 ). Awaveguide layer 420 is defined in thesilicon layer 408. In some embodiments, thewaveguide layer 420 is similar to the waveguide layer 124 (FIG. 1 ). A grating 422 is integral with thewaveguide layer 420 and is configured to receive an optical signal and couple the optical signal into thewaveguide layer 420. In some embodiments, thegrating 422 is similar to the grating 140 (FIG. 1 ). Apolysilicon layer 430 is over thewaveguide layer 420. In some embodiments, thepolysilicon layer 430 is similar to the polysilicon layer 160 (FIG. 1 ). - An
interconnect structure 440 is over theILD 416. Theinterconnect structure 440 includes afirst interconnect section 450 having conductive features having a first dimension. Theinterconnect structure 440 further includes asecond interconnect section 455 having conductive features having a second dimension greater than the first dimension. Thesecond interconnect section 455 is over thefirst interconnect section 450. In some embodiments,interconnect structure 440 is similar to the interconnect structure 130 (FIG. 1 ). Acontact pad 460 is electrically connected to theimplant region 410 by conductive features in theinterconnect structure 440. Apassivation layer 470 is over theinterconnect structure 440. Thechip 400A includes acavity 436A for optically coupling an optical fiber with thegrating 422. - The
cavity 436A extends through a portion of theinterconnect structure 440. Thecavity 436A extends through all of thesecond interconnect section 455 and through an upper portion of thefirst interconnect section 450. In some embodiments, a portion of a bottommost IMD layer of theinterconnect structure 440 remains as a bottom surface of thecavity 436A. In some embodiments, a remaining portion of the bottommost IMD layer ranges from about 10% to about 90% of the bottommost IMD layer. The amount of the remaining portion of the IMD layer is a result of manufacturing variation during an etching process used to define thecavity 436A. - The
silicon layer 408 is usable to form transistor structures, e.g., transistor structure 320 (FIGS. 3C-3E ). Thesilicon layer 408 is also usable to contain thewaveguide layer 420. In some embodiments, cladding or reflective layers are between thesilicon layer 408 and thewaveguide layer 420 in order to avoiding reducing the strength of the optical signal traveling through thewaveguide layer 420 due to light leaking to thesilicon layer 408. The cladding or reflective layers also help to prevent light from entering thewaveguide layer 420 from thesilicon layer 408, which would introduce noise into the optical signal within thewaveguide layer 420. In some embodiments, a thickness of thesilicon layer 408 ranges from about 2,500 A to about 3,000 A. If the thickness of thesilicon layer 408 is too small, then an ability to form transistor structures is reduced, in some instances. If the thickness of thesilicon layer 408 is too large, material is wasted without a noticeably increase in performance resulting in increasing the size of thechip 400A needlessly. - The
implant region 410 is part of a component within thechip 400A. In some embodiments, theimplant region 410 is part of an optoelectronic component. In some embodiments, theimplant region 410 is part of a transistor structure, e.g., transistor structure 320 (FIGS. 3C-3E ). Theimplant region 410 is not particularly limiting and is used merely to indicate that theinterconnect structure 440 provides electrical connection to elements within thechip 400A. - The
oxide layer 412 helps to protect thesilicon layer 408 during subsequent processing. In some embodiments, theoxide layer 412 is formed by oxidizing thesilicon layer 408, e.g., using HTO. In some embodiments, a thickness of theoxide layer 412 ranges from about 50 A to about 200 A. If the thickness of theoxide layer 412 is too small, a risk of damage to thesilicon layer 408 during subsequent processing increases, in some embodiments. If the thickness of theoxide layer 412 is too great, material is wasted without a noticeable increase in performance, in some embodiments. - The
contact pad 460 provides a location for electrically connecting external devices to theinterconnect structure 440. In some embodiments, thecontact pad 460 includes aluminum, copper, tungsten or another suitable conductive material. In some embodiments, thecontact pad 460 is part of a fan-out connection. - The
passivation layer 470 is configured to protect theinterconnect structure 440. In some embodiments, thepassivation layer 470 includes silicon nitride, silicon oxide, silicon oxynitride, or another suitable dielectric material. In some embodiments, a thickness of thepassivation layer 470 ranges from about 5,000 A to about 6,000 A. If the thickness of thepassivation layer 470 is too small, a risk of damage to theinterconnect structure 440 increases, in some instances. If the thickness of thepassivation layer 470 is too great, material is wasted without a noticeable increase in performance and the size of thechip 400A is needlessly increased, in some instances. - The
polysilicon layer 430 acts as an etch stop layer over thewaveguide layer 420 and thegrating 422. Thepolysilicon layer 430 helps to reduce the risk of over-etching during formation of thecavity 436A. As mentioned above, over-etching that damages thewaveguide layer 420 or the grating 422 increases the risk of thechip 400A being unable to effectively transfer an optical signal from an optical fiber to a component within thechip 400A. In some embodiments, a thickness of thepolysilicon layer 430 ranges from about 1,400 A to about 1,600 A. If the thickness of thepolysilicon layer 430 is too small, then a risk of over-etching damage to thewaveguide layer 420 or the grating 422 increases, in some instances. If the thickness of thepolysilicon layer 430 is too large, material is wasted without a noticeable improvement in performance which needlessly increases the size of thechip 400A, in some instances. In some embodiments, thepolysilicon layer 430 has a same thickness as thepolysilicon layer 406. In some embodiments, thepolysilicon layer 430 has a different thickness from thepolysilicon layer 406. -
FIG. 4B is a cross sectional view of achip 400B in accordance with some embodiments. Thechip 400B is similar to thechip 400A (FIG. 4A ). In comparison with thechip 400A, thechip 400B includescavity 436B which extends through an entirety of theinterconnect structure 440. Thecavity 436B extends into theILD 416. In some embodiments, a portion of theILD 416 remains as a bottom surface of thecavity 436B. In some embodiments, a remaining portion of theILD 416 ranges from about 10% to about 90% of theILD 416. The amount of the remaining portion of theILD 416 is a result of manufacturing variation during an etching process used to define thecavity 436B. In some embodiments, thecavity 436B extends through the entirety of theILD 416 and exposes theCESL 414. -
FIG. 4C is a cross sectional view of achip 400C in accordance with some embodiments. Thechip 400B is similar to thechip 400A (FIG. 4A ). In comparison with thechip 400A, thechip 400C includescavity 436C which extends through an entirety of theinterconnect structure 440, an entirety of theILD 416 and an entirety of theCESL 414. Thecavity 436C extends into theoxide layer 412. In some embodiments, a portion of theoxide layer 412 remains as a bottom surface of thecavity 436C. In some embodiments, a remaining portion of theoxide layer 412 ranges from about 10% to about 90% of theoxide layer 412. The amount of the remaining portion of theoxide layer 412 is a result of manufacturing variation during an etching process used to define thecavity 436C. -
FIG. 4D is a cross sectional view of achip 400D in accordance with some embodiments. Thechip 400D is similar to thechip 400A (FIG. 4A ). In comparison with thechip 400A, thechip 400D includescavity 436D which extends through an entirety of theinterconnect structure 440, an entirety of theILD 416, an entirety of theCESL 414, and an entirety of theoxide layer 412. Thecavity 436D extends into thepolysilicon layer 430. In some embodiments, a portion of thepolysilicon layer 430 remains as a bottom surface of thecavity 436D. In some embodiments, a remaining portion of thepolysilicon layer 430 ranges from about 10% to about 90% of thepolysilicon layer 430. The amount of the remaining portion of thepolysilicon layer 430 is a result of manufacturing variation during an etching process used to define thecavity 436D. -
FIG. 4E is a cross sectional view of achip 400E in accordance with some embodiments. Thechip 400E is similar to thechip 400A (FIG. 4A ). In comparison with thechip 400A, thechip 400E includescavity 436E which extends through an entirety of theinterconnect structure 440, an entirety of theILD 416, an entirety of theCESL 414, an entirety of theoxide layer 412, and an entirety of thepolysilicon layer 430. Thecavity 436E exposes thewaveguide layer 420 and thegrating 422. A portion of thepolysilicon layer 430 remains under theoxide layer 412 outside of thecavity 436E. -
FIG. 4F is a cross sectional view of achip 400F in accordance with some embodiments. Thechip 400F is similar to thechip 400E (FIG. 4E ). In comparison with thechip 400E, thechip 400F does not include the portion of thepolysilicon layer 430 under theoxide layer 412 outside of thecavity 436F. In some embodiments, a wet etching is used to remove the portion of thepolysilicon layer 430 outside of thecavity 436F to define an overhang by theoxide layer 412. Removing this portion of thepolysilicon layer 430 increases an amount of thewaveguide layer 420 and the grating 422 exposed. Thus, an amount of thewaveguide layer 420 and the grating 422 able to receive the optical signal without absorption from other materials is increases. As a result, efficiency of optical coupling between the optical fiber and thewaveguide layer 420 is increased. -
FIG. 4G is a cross sectional view of achip 400G in accordance with some embodiments. Thechip 400G is similar to thechip 400E (FIG. 4E ). In comparison with thechip 400E, thechip 400G includes a segmentedpolysilicon layer 430″. During the formation of thechip 400G, thepolysilicon layer 430 is etched to define openings to form the segmentedpolysilicon layer 430″. Removing these portions of thepolysilicon layer 430 increases an amount of thewaveguide layer 420 and the grating 422 exposed. Thus, an amount of thewaveguide layer 420 and the grating 422 able to receive the optical signal without absorption from other materials is increases. As a result, efficiency of optical coupling between the optical fiber and thewaveguide layer 420 is increased. In some embodiments, the segmentedpolysilicon layer 430″, as a whole, occupies about 20% to about 30% of the cavity width wc of thecavity 436G. If the amount of the cavity width wc occupied by the segmentedpolysilicon layer 430″ is too small, then a risk of over-etching increases because the etching tool is less likely to detect the presence of the segmentedpolysilicon layer 430″ and terminate the etching process, in some instances. If the amount of the cavity width wc occupied by the segmentedpolysilicon layer 430″ is too great, then an amount of light from the optical signal that is absorbed or dispersed by the segmentedpolysilicon layer 430″ increases and coupling efficiency is reduced, in some instances. While the segmentedpolysilicon layer 430″ is only shown with respect to a cavity that extends all the way to the segmentedpolysilicon layer 430″, one of ordinary skill in the art would recognize that thesegmented polysilicon layer 430″ is usable with any of the embodiments inFIGS. 4A-4F . - The examples of
chips 400A-400G (FIGS. 4A-4G ) result from different etching depths for thecavities 436A-436G. In some embodiments, due to manufacturing variation, different chips on a same wafer will have cavities from the different examples inFIGS. 4A-4G . For example, in some embodiments, chips on the wafer closer to an edge of the wafer are more likely to have cavities which extend farther into the chip than chips near a center of the wafer. -
FIG. 5A is a cross sectional view of achip 500A in accordance with some embodiments. Thechip 500A is similar to thechip 400B (FIG. 4B ). Reference numbers for similar elements are increased by 100 with respect to the reference numbers inFIG. 4B . In comparison with thechip 400B, thechip 500A includes apolysilicon layer 530′ which has a width wp less than a width of thecavity 536A. In some embodiments, the width wp ranges from about 20% to about 30% of the width wc. If the width wp is too small, then a risk of over-etching increases because the etching tool is less likely to detect the presence of thepolysilicon layer 530′ and terminate the etching process, in some instances. If the width wp is too great, then an amount of light from the optical signal that is absorbed or dispersed by thepolysilicon layer 530′ increases and coupling efficiency is reduced, in some instances. While the depth of thecavity 536A is similar to the depth of thecavity 436B (FIG. 4B ), one of ordinary skill in the art would recognize that a depth of a cavity similar to the depth ofcavity 436A (FIG. 4A ) is also possible, in some embodiments. In some embodiments, thecavity 536A extends through the entirety of theILD 516 and exposes theCESL 514. -
FIG. 5B is a cross sectional view of achip 500B in accordance with some embodiments. Thechip 500B is similar to thechip 500A (FIG. 5A ). In comparison with thechip 500A, thechip 500B includescavity 536B which extends through an entirety of theinterconnect structure 540, an entirety of theILD 516 and an entirety of theCESL 514. Thecavity 536B extends into theoxide layer 512. In some embodiments, a portion of theoxide layer 512 remains as a bottom surface of thecavity 536B. In some embodiments, a remaining portion of theoxide layer 512 ranges from about 10% to about 90% of theoxide layer 412. The amount of the remaining portion of theoxide layer 512 is a result of manufacturing variation during an etching process used to define thecavity 536B. -
FIG. 5C is a cross sectional view of achip 500C in accordance with some embodiments. Thechip 500C is similar to thechip 500A (FIG. 5A ). In comparison with thechip 500A, thechip 500C includescavity 536C which extends through an entirety of theinterconnect structure 540, an entirety of theILD 516, an entirety of theCESL 514, and an entirety of theoxide layer 512 above thepolysilicon layer 530′. Thecavity 536C extends into thepolysilicon layer 530′. In some embodiments, a portion of thepolysilicon layer 530′ remains as a bottom surface of thecavity 536C. In some embodiments, a remaining portion of thepolysilicon layer 530′ ranges from about 10% to about 90% of thepolysilicon layer 430. The amount of the remaining portion of thepolysilicon layer 530′ is a result of manufacturing variation during an etching process used to define thecavity 536C. -
FIG. 5D is a cross sectional view of achip 500D in accordance with some embodiments. Thechip 500D is similar to thechip 500C (FIG. 5C ). In comparison with thechip 500C, thechip 500D includescavity 536D which extends through an entirety of theinterconnect structure 540, an entirety of theILD 516, an entirety of theCESL 514, an entirety of theoxide layer 512 to expose portions of thewaveguide layer 520 and the grating 522 that extend beyond an edge of thepolysilicon layer 530′. A portion of thepolysilicon layer 530′ remains over thewaveguide layer 520 and thegrating 522. -
FIG. 5E is a cross sectional view of achip 500E in accordance with some embodiments. Thechip 500E is similar to thechip 500D (FIG. 5D ). In comparison with thechip 500D, thechip 500E includes a segmentedpolysilicon layer 530″. During the formation of thechip 500E, thepolysilicon layer 530′ is etched to define openings to form the segmentedpolysilicon layer 530″. Removing these portions of thepolysilicon layer 530′ increases an amount of thewaveguide layer 520 and the grating 522 exposed. Thus, an amount of thewaveguide layer 520 and the grating 522 able to receive the optical signal without absorption from other materials is increases. As a result, efficiency of optical coupling between the optical fiber and thewaveguide layer 520 is increased. In some embodiments, the segmentedpolysilicon layer 530″, as a whole, occupies about 20% to about 30% of the cavity width wc of thecavity 536E. If the amount of the cavity width wc occupied by the segmentedpolysilicon layer 530″ is too small, then a risk of over-etching increases because the etching tool is less likely to detect the presence of the segmentedpolysilicon layer 530″ and terminate the etching process, in some instances. If the amount of the cavity width wc occupied by the segmentedpolysilicon layer 530″ is too great, then an amount of light from the optical signal that is absorbed or dispersed by the segmentedpolysilicon layer 530″ increases and coupling efficiency is reduced, in some instances. While the segmentedpolysilicon layer 530″ is only shown with respect to a cavity that extends all the way to the segmentedpolysilicon layer 530″, one of ordinary skill in the art would recognize that thesegmented polysilicon layer 430″ is usable with any of the embodiments inFIGS. 5A-5C . - The examples of
chips 500A-500E (FIGS. 5A-5E ) result from different etching depths for thecavities 536A-536E. In some embodiments, due to manufacturing variation, different chips on a same wafer will have cavities from the different examples inFIGS. 5A-5E . For example, in some embodiments, chips on the wafer closer to an edge of the wafer are more likely to have cavities which extend farther into the chip than chips near a center of the wafer. -
FIG. 6 is a perspective view of a grating 600 in accordance with some embodiments. Grating 600 is usable as grating 140 (FIG. 1 ) in some embodiments. Thegratings FIGS. 1, 4A-4G and 5A-5E ) are cross sectional views of the grating 600 taken along line A-A, in some embodiments. Grating 700 (FIG. 7 ) is a cross sectional view of the grating 600 taken along line B-B. -
FIG. 7 is a cross sectional view of a grating 700 in accordance with some embodiments. The grating includes asubstrate 780.Substrate 780 is similar to substrate 122 (FIG. 1 ). Afirst reflection layer 790 is over thesubstrate 780. Afirst oxide layer 782 is over thefirst reflection layer 790. Awaveguide layer 724 is over thefirst oxide layer 782. Thewaveguide layer 724 is similar to thewaveguide layer 124. Acladding layer 770 is over the waveguide layer. Asecond reflection layer 792 is over the cladding layer. - The
first reflection layer 790 reflects light from an optical signal back toward a top surface of the grating 700 in order to prevent the light from being lost into thesubstrate 780. In some embodiments, thefirst reflection layer 790 includes aluminum, copper, nickel, alloys thereof, or another suitable material. In some embodiments, a thickness of thefirst reflection layer 790 ranges from about 0.1 μm to about 10 μm. If the thickness of thefirst reflection layer 790 is too small, a risk of light from the optical signal escaping the grating 700 increases, in some instances. If the thickness of thefirst reflection layer 790 is too great, material is wasted without a noticeable improvement in performance, in some instances. - The
first oxide layer 782 supports thewaveguide layer 724 and has a different refractive index from thewaveguide layer 724. The difference in refractive index helps to reflect light from the optical signal back into thewaveguide layer 724 during propagation of the optical signal along thewaveguide layer 724. In some embodiments, thefirst oxide layer 782 has a thickness ranging from about 500 nm to about 3,000 nm. If the thickness of thefirst oxide layer 782 is too small, then a risk of light penetrating through thefirst oxide layer 782 increases, in some instances. If the thickness of thefirst oxide layer 782 is too great, then material is wasted without a noticeable improvement in performance in some instances. In some embodiments, thefirst oxide layer 782 contains a material other than silicon oxide, such as silicon nitride, aluminum oxide, hafnium oxide or another suitable material. - The
cladding layer 770 helps to reflect light from the optical signal back into thewaveguide layer 724 similar to thefirst oxide layer 782. In some embodiments, a thickness of the cladding layer ranges from about 0.6 μm to about 3 μm. If the thickness of thecladding layer 770 is too small, then a risk of light penetrating through thecladding layer 770 increases, in some instances. If the thickness of thecladding layer 770 is too great, then material is wasted without a noticeable improvement in performance in some instances. In some embodiments, thecladding layer 770 contains silicon oxide, silicon nitride, aluminum oxide, hafnium oxide or another suitable material. In some embodiments, thecladding layer 770 contains a same material as thefirst oxide layer 782. In some embodiments, thecladding layer 770 contains a different material from thefirst oxide layer 782. - The
second reflection layer 792 reflects light from the optical signal back toward a bottom surface of the grating 700 in order to prevent the light from being lost out of thegrating 700. In some embodiments, thesecond reflection layer 792 includes aluminum, copper, nickel, alloys thereof, or another suitable material. In some embodiments, thesecond reflection layer 792 contains a same material as thefirst reflection layer 790. In some embodiments, thesecond reflection layer 792 contains a different material from thefirst reflection layer 790. In some embodiments, a thickness of thesecond reflection layer 792 ranges from about 0.1 μm to about 10 μm. If the thickness of thesecond reflection layer 792 is too small, a risk of light from the optical signal escaping the grating 700 increases, in some instances. If the thickness of thesecond reflection layer 792 is too great, material is wasted without a noticeable improvement in performance, in some instances. In some embodiments, the thickness of thesecond reflection layer 792 is different from the thickness of thefirst reflection layer 790. In some embodiments, the thickness of thesecond reflection layer 792 is equal to the thickness of thefirst reflection layer 790. In some embodiments, thesecond reflection layer 792 is only over portions of thewaveguide layer 724 that does not include a grating in order to maximize the transmission of the optical signal, e.g., the optical signal 115 (FIG. 1 ), to the grating for transmission along thewaveguide layer 724. - An aspect of this description relates to a coupling system. The coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a chip in optical communication with the optical fiber. The chip includes a substrate. The chip further includes a grating on a first side of the substrate, wherein the grating is configured to receive the optical signal. The chip further includes an interconnect structure over the grating on the first side of the substrate, wherein the interconnect structure defines a cavity aligned with the grating. The chip further includes a first polysilicon layer on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. In some embodiments, the chip further includes a second polysilicon layer over the grating, wherein the second polysilicon layer is between the interconnect structure and the grating. In some embodiments, the second polysilicon layer directly contacts the grating. In some embodiments, a width of the second polysilicon layer is greater than a width of the cavity. In some embodiments, a width of the second polysilicon layer is less than a width of the cavity. In some embodiments, the width of the second polysilicon layer is about 20% to about 30% of the width of the cavity. In some embodiments, the second polysilicon layer is a segmented polysilicon layer. In some embodiments, the chip includes an oxide layer over the grating, and the oxide layer is between the grating and the interconnect structure. In some embodiments, the cavity extends beneath the oxide layer to define a recess in a bottommost surface of the oxide layer. In some embodiments, the cavity exposes at least a portion of the grating. In some embodiments, the cavity fails to expose any of the grating.
- An aspect of this description relates to a chip. The chip includes a substrate. The chip further includes a waveguide layer on a first side of the substrate. The chip further includes a grating optically connected to the waveguide layer. The chip further includes an interconnect structure on the first side of the substrate, wherein the waveguide layer is between the interconnect structure and the substrate, and the interconnect structure defines a cavity aligned with the grating. The chip further includes a first polysilicon layer over the grating on the first side of the substrate. The chip further includes a second polysilicon layer on a second side of the substrate, wherein a maximum thickness of the first polysilicon layer is equal to a maximum thickness of the second polysilicon layer. In some embodiments, a width of the first polysilicon layer is greater than a width of the cavity. In some embodiments, a width of the first polysilicon layer is less than a width of the cavity. In some embodiments, the first polysilicon layer is a segmented polysilicon layer. In some embodiments, the cavity exposes the first polysilicon layer. In some embodiments, the chip further includes a dielectric layer over the first polysilicon layer, wherein the dielectric layer is between a bottommost surface of the cavity and the first polysilicon layer.
- An aspect of this description relates to a method of making a chip. The method includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate. The method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess. The method further includes implanting dopants into the substrate to define an implant region. The method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region. The method further includes patterning the CESL to define a CESL block. The method further includes forming a waveguide and a grating in the substrate. The method further includes forming an interconnect structure over the waveguide, the grating and the CESL block. The method further includes etching the interconnect structure to define a cavity aligned with the grating. In some embodiments, patterning the CESL further includes defining a CESL spacer parallel to a sidewall of the first polysilicon layer closest to the recess. In some embodiments, the method further includes depositing an oxide layer over the CESL block; patterning the oxide layer to define an oxide spacer along a sidewall of the CESL block; depositing a second polysilicon layer over the CESL block and the oxide spacer; and patterning the second polysilicon layer to define a polysilicon spacer along a sidewall of the oxide spacer.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
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US17/446,244 US11892681B2 (en) | 2021-08-27 | 2021-08-27 | Fiber to chip coupler and method of making the same |
TW111117922A TW202310435A (en) | 2021-08-27 | 2022-05-12 | Coupling system |
CN202210524495.2A CN115508952A (en) | 2021-08-27 | 2022-05-13 | Coupling system, wafer and method for manufacturing wafer |
US18/448,032 US20230384526A1 (en) | 2021-08-27 | 2023-08-10 | Fiber to chip coupler and method of making the same |
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US20160091664A1 (en) * | 2014-09-30 | 2016-03-31 | International Business Machines Corporation | Polarization-independent grating coupler for silicon on insulator |
US20170115456A1 (en) * | 2014-07-08 | 2017-04-27 | Fujitsu Limited | Grating coupler and optical waveguide device |
US20220269006A1 (en) * | 2021-02-22 | 2022-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Optical device for coupling light |
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US20170115456A1 (en) * | 2014-07-08 | 2017-04-27 | Fujitsu Limited | Grating coupler and optical waveguide device |
US20160091664A1 (en) * | 2014-09-30 | 2016-03-31 | International Business Machines Corporation | Polarization-independent grating coupler for silicon on insulator |
US20220269006A1 (en) * | 2021-02-22 | 2022-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Optical device for coupling light |
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