US20230037116A1 - Barrier layer on a piezoelectric-device pad - Google Patents
Barrier layer on a piezoelectric-device pad Download PDFInfo
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- US20230037116A1 US20230037116A1 US17/577,715 US202217577715A US2023037116A1 US 20230037116 A1 US20230037116 A1 US 20230037116A1 US 202217577715 A US202217577715 A US 202217577715A US 2023037116 A1 US2023037116 A1 US 2023037116A1
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- layer
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- piezoelectric
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- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
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- H—ELECTRICITY
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- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
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- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/26—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N30/01—Manufacture or treatment
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N30/01—Manufacture or treatment
- H10N30/03—Assembling devices that include piezoelectric or electrostrictive parts
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N30/20—Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
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- H10N30/20—Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
- H10N30/204—Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators using bending displacement, e.g. unimorph, bimorph or multimorph cantilever or membrane benders
- H10N30/2047—Membrane type
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Definitions
- Piezoelectric actuators and other suitable piezoelectric devices may create physical movement in response to an electrical signal.
- the physical movement may be used to control various kinds of mechanical and optical systems.
- the physical movement may be used to control movement of a moveable membrane to create a speaker.
- FIG. 1 illustrates a cross-sectional view of some embodiments of an integrated circuit (IC) chip in which a barrier layer caps a pad of a piezoelectric device.
- IC integrated circuit
- FIG. 2 illustrates an expanded cross-sectional view of some embodiments of the IC chip of FIG. 1 in which the piezoelectric device surrounds a membrane.
- FIG. 3 illustrates a top layout view of some embodiments of the IC chip of FIG. 2 .
- FIGS. 4 A and 4 B illustrate top layout views of some alternative embodiments of the IC chip of FIG. 3 .
- FIGS. 5 A- 5 G illustrate cross-sectional views of some alternative embodiments of the IC chip of FIG. 2 .
- FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B illustrate a series of views of some embodiments of a method for forming an IC chip in which a barrier layer caps a pad of a piezoelectric device.
- FIG. 21 illustrates a block diagram of some embodiments of the method of FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B.
- FIG. 22 illustrates a cross-sectional view of some first alternative embodiments of the method of FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B.
- FIGS. 23 - 25 illustrate a series of cross-sectional views of some second alternative embodiments of the method of FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B.
- FIGS. 26 and 27 illustrate a series of cross-sectional views of some third alternative embodiments of the method of FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- a piezoelectric actuator or some other suitable piezoelectric device may comprise a bottom electrode, a piezoelectric layer overlying the bottom electrode, and a top electrode overlying the piezoelectric layer.
- a top-electrode pad overlies and is electrically coupled to the top electrode by a top-electrode via extending from the top-electrode pad to the top electrode.
- a bottom-electrode pad overlies and is electrically coupled to the bottom electrode by a bottom-electrode via extending from the bottom-electrode pad to the bottom electrode.
- a challenge with the piezoelectric device is that hydrogen-ion containing processes may be employed after forming the piezoelectric layer. Further, the top-electrode and bottom-electrode vias may provide diffusion paths for hydrogen ions from the hydrogen-ion containing processes to diffuse to the piezoelectric layer. Hydrogen ions that diffuse to the piezoelectric layer may accumulate in the piezoelectric layer and induce delamination and breakdown of the piezoelectric layer, whereby the piezoelectric device may fail.
- a pad barrier layer caps a pad of a piezoelectric device.
- the pad barrier layer is configured to block hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer. Absent the pad barrier layer, hydrogen ions from hydrogen-ion containing processes performed after forming the pad may diffuse to the piezoelectric layer along a via extending from the pad to the piezoelectric device. By blocking diffusion of hydrogen ions and/or other errant materials to the piezoelectric device, the pad barrier layer may prevent delamination and breakdown of the piezoelectric layer. Hence, the pad barrier layer may prevent failure of the piezoelectric device.
- a cross-sectional view 100 of some embodiments of an IC chip is provided in which a pad barrier layer 102 caps a pad 104 of a piezoelectric device 106 .
- the piezoelectric device 106 overlies a substrate 108 and is separated from the substrate 108 by a substrate dielectric layer 110 . Further, the piezoelectric device 106 comprises a bottom electrode 112 , a piezoelectric layer 114 overlying the bottom electrode 112 , and a top electrode 116 overlying the piezoelectric layer 114 .
- the piezoelectric device 106 is an actuator, but other suitable types of piezoelectric device are amenable.
- the piezoelectric device 106 may also be referred to as a metal-piezoelectric-metal (MPM) structure and/or, a piezoelectric structure.
- MPM metal-piezoelectric-metal
- a device barrier layer 118 and a device dielectric layer 120 overlie the piezoelectric device 106 and are stacked between the piezoelectric device 106 and the pad 104 .
- the device barrier layer 118 separates the device dielectric layer 120 from the piezoelectric device 106 and is configured to block hydrogen ions and/or other suitable errant materials from diffusing to the piezoelectric layer 114 from over the device barrier layer 118 .
- the device barrier layer 118 may be regarded as a hydrogen-barrier layer.
- the pad 104 overlies the device barrier layer 118 and comprises a first end 104 fe and a second end 104 se .
- the first end 104 fe overlies the top electrode 116
- a via 122 extends from the first end 104 fe , through the device barrier layer 118 and the device dielectric layer 120 , to the top electrode 116 .
- the via 122 extends to the bottom electrode 112 instead of the top electrode 116 .
- the second end 104 se is distal from the first end 104 fe and is laterally offset from the piezoelectric device 106 .
- the pad barrier layer 102 caps the pad 104
- a passivation layer 124 caps the pad barrier layer 102 and the device dielectric layer 120 .
- a pad opening 126 extends through the pad barrier layer 102 and the passivation layer 124 to expose the second end 104 se of the pad 104 .
- the pad barrier layer 102 is configured to block hydrogen ions and/or other suitable errant materials from diffusing to the piezoelectric device 106 from over the pad 104 .
- the pad barrier layer 102 may be regarded as a hydrogen-barrier layer. Absent the pad barrier layer 102 , hydrogen ions from hydrogen-containing semiconductor manufacturing processes performed after forming the pad 104 may diffuse to the piezoelectric layer 114 along the via 122 .
- Hydrogen ions that diffuse to the piezoelectric layer 114 may accumulate in the piezoelectric layer 114 and induce delamination and breakdown of the piezoelectric layer 114 , whereby the piezoelectric device 106 may fail. Therefore, by blocking diffusion of hydrogen ions to the piezoelectric layer 114 , the pad barrier layer 102 and the device barrier layer 118 may prevent delamination and breakdown of the piezoelectric layer 114 . Hence, the pad barrier layer 102 and the device barrier layer 118 may prevent failure of the piezoelectric device 106 .
- the pad opening 126 extends through the pad barrier layer 102 , hydrogen ions and/or other errant materials may extend through the pad barrier layer 102 .
- the pad opening 126 is at the second end 104 se of the pad 104 , laterally offset from the piezoelectric device 106 , the diffusion path from the pad opening 126 to the piezoelectric layer 114 may be long. Hence, the likelihood of hydrogen ions and/or other errant materials diffusing to the piezoelectric layer 114 from the pad opening 126 may be low.
- a thickness T pb of the pad barrier layer 102 is about 200-600 angstroms, about 200-400 angstroms, about 400-600 angstroms, or some other suitable value. If the thickness T pb is too small (e.g., less than about 200 angstroms), the pad barrier layer 102 may be unable to block diffusion of hydrogen ions and/or other errant materials through the pad barrier layer 102 . If the thickness T pb is too large (e.g., more than about 600 angstroms), material may be wasted and high topographical variation at the pad barrier layer 102 may present processing challenges that reduce manufacturing yields.
- the pad barrier layer 102 is crystalline and/or has a density greater than about 2 grams per cubic centimeter (g/cm 3 ), 2.6 g/cm 3 , 5 g/cm 3 , or some other suitable value. It has been appreciated that such a density may block diffusion of hydrogen ions and/or other errant materials through the pad barrier layer 102 .
- the pad barrier layer 102 is a metal oxide or some other suitable material.
- the metal oxide may, for example, be or comprise aluminum oxide (e.g., Al 2 O 3 ), titanium oxide (e.g., TiO 2 ), iron oxide (e.g., Fe 2 O 3 ), zirconium oxide (e.g., ZrO 2 ), zinc oxide (e.g., ZnO), copper oxide (e.g., CuO), tantalum oxide (e.g., Ta 2 O 5 ), some other suitable type of metal oxide, or any combination of the foregoing.
- the pad barrier layer 102 is dielectric.
- the pad barrier layer 102 is deposited by a process that does not depend on hydrogen ions and/or other errant materials.
- the pad barrier layer 102 may be deposited by physical vapor deposition (PVD) or some other suitable type of deposition.
- the device barrier layer 118 is a same material as the pad barrier layer 102 . In other embodiments, the device barrier layer 118 is a different material than the pad barrier layer 102 . In some embodiments, the device barrier layer 118 is crystalline and/or has a density greater than about 2 g/cm 3 , 2.6 g/cm 3 , 5 g/cm 3 , or some other suitable value. In some embodiments, the density is the same as that of the pad barrier layer 102 . In some embodiments, the device barrier layer 118 is dielectric.
- the substrate 108 is a bulk substrate of silicon or some other suitable type of semiconductor material. In other embodiments, the substrate 108 is a semiconductor-on-insulator (SOI) substrate or some other suitable type of semiconductor substrate. To the extent that the substrate 108 is an SOI substrate, the semiconductor material of the SOI substrate may be silicon or some other suitable type of semiconductor material.
- SOI semiconductor-on-insulator
- the substrate dielectric layer 110 is or comprises silicon oxide and/or some other suitable dielectric(s).
- the device dielectric layer 120 is or comprises silicon oxide and/or some other suitable dielectric(s).
- the substrate dielectric layer 110 and the device dielectric layer 120 are or comprise a same material. In other embodiments, the substrate dielectric layer 110 and the device dielectric layer are or comprise different materials.
- the passivation layer 124 is or comprise silicon nitride and/or some other suitable dielectric(s).
- a rate of diffusion of hydrogen ions through and/or in the pad barrier layer 102 is less than: 1) a rate of diffusion of hydrogen ions through and/or in the substrate dielectric layer 110 ; 2) a rate of diffusion of hydrogen ions through and/or in the device dielectric layer 120 ; 3) a rate of diffusion of hydrogen ions through and/or in the pad 104 ; 4) a rate of diffusion of hydrogen ions through and/or in the passivation layer 124 ; or 5) any combination of the foregoing.
- a rate of diffusion of hydrogen ions through and/or in the device barrier layer 118 is less than: 1) a rate of diffusion of hydrogen ions through and/or in the substrate dielectric layer 110 ; 2) a rate of diffusion of hydrogen ions through and/or in the device dielectric layer 120 ; 3) a rate of diffusion of hydrogen ions through and/or in the pad 104 ; 4) a rate of diffusion of hydrogen ions through and/or in the passivation layer 124 ; or 5) any combination of the foregoing.
- the rates of the pad barrier layer 102 and/or the device barrier layer 118 may, for example, be zero or close to zero.
- the piezoelectric layer 114 is or comprises lead zirconate titanate (e.g., PZT) and/or some other suitable piezoelectric material(s).
- the bottom electrode 112 is or comprises titanium oxide, platinum, some other suitable metal(s) or conductive material(s), or any combination of the foregoing.
- the top electrode 116 is or comprises titanium oxide, platinum, some other suitable metal(s) or conductive material(s), or any combination of the foregoing.
- the bottom and top electrodes 112 , 116 are or comprise a same material. In other embodiments, the bottom and top electrodes 112 , 116 are or comprise different materials.
- the pad 104 is or comprises copper, aluminum copper, aluminum, some other suitable metal(s) or conductive material(s), or any combination of the foregoing.
- the device barrier layer 118 is configured to block material of the pad 104 from diffusing from the pad 104 to the piezoelectric device 106 . Such material may, for example, be or comprise copper and/or some other suitable material.
- a bump structure, a wire bond structure, or some other suitable type of conductive structure is formed in the pad opening 126 to electrically couple the pad 104 and hence the piezoelectric device 106 to another IC chip, a printed circuit board (PCB), an interposer structure, or some other suitable structure.
- PCB printed circuit board
- an expanded cross-sectional view 200 of some embodiments of the IC chip of FIG. 1 is provided in which the piezoelectric device 106 surrounds a membrane 202 .
- the piezoelectric device 106 Upon application of a voltage from the top electrode 116 to the bottom electrode 112 , the piezoelectric device 106 vibrates, thereby causing the membrane 202 to move within a sound opening 204 .
- the membrane 202 and the piezoelectric device 106 collectively form a piezoelectric speaker or some other suitable structure.
- a pair of pads 104 and a pair of vias 122 electrically couple to the piezoelectric device 106 .
- the pair of pads 104 comprises a top-electrode pad 104 t and a bottom-electrode pad 104 b
- the pair of vias 122 comprises a top-electrode via 122 t and a bottom-electrode via 122 b
- the top-electrode pad 104 t and the top-electrode via 122 t correspond to the pad 104 and the via 122 illustrated and described with regard to FIG. 1 .
- the bottom-electrode pad 104 b and the bottom-electrode via 122 b are on an opposite side of the sound opening 204 as the top-electrode pad 104 t and the top-electrode via 122 t . Further, the bottom-electrode via 122 b extends from the bottom-electrode pad 104 b to the bottom electrode 112 .
- the pad barrier layer 102 caps both of the pads 104 and comprises a top-electrode barrier segment 102 t and a bottom-electrode barrier segment 102 b .
- the top-electrode barrier segment 102 t caps the top-electrode pad 104 t
- the bottom-electrode barrier segment 102 b caps the bottom-electrode pad 104 b.
- the pad barrier layer 102 prevents hydrogen ions and/or other errant particles from diffusing to the piezoelectric device 106 from over the top-electrode pad 104 t and the bottom-electrode pad 104 b . Absent the pad barrier layer 102 , hydrogen ions from hydrogen-containing semiconductor manufacturing processes performed after forming the top-electrode pad 104 t and the bottom-electrode pad 104 b may diffuse to the piezoelectric layer 114 along the top-electrode via 122 t and/or along the bottom-electrode via 122 b . This may induce delamination and breakdown of the piezoelectric layer 114 , whereby the piezoelectric device 106 may fail. Therefore, by blocking diffusion of hydrogen ions to the piezoelectric layer 114 , the pad barrier layer 102 may prevent failure of the piezoelectric device 106 .
- a pair of pad openings 126 respectively expose the pads 104 respectively at locations laterally offset from the piezoelectric device 106 , whereby diffusion paths from the pad openings 126 to the piezoelectric layer 114 may be long. Because the diffusion paths may be long, the likelihood of hydrogen ions and/or other errant materials diffusing to the piezoelectric layer 114 from the pad openings 126 may be low.
- the substrate 108 is an SOI substrate and comprises a lower semiconductor layer 108 l , an insulator layer 108 i overlying the lower semiconductor layer 108 l , and an upper semiconductor layer 108 u overlying the insulator layer 108 i .
- the insulator layer 108 i is or comprises silicon oxide and/or some other suitable dielectric(s).
- the lower semiconductor layer 108 l and the upper semiconductor layers 108 u are or comprise silicon and/or some other suitable semiconductor(s).
- the membrane 202 corresponds to a portion of the upper semiconductor layer 108 u and is connected to a remainder of the upper semiconductor layer 108 u outside the cross-sectional view 200 of FIG. 2 . Further, as described above, the membrane 202 moves in the sound opening 204 in response to vibrations from the piezoelectric device 106 .
- the piezoelectric device 106 may also be regarded as a piezoelectric actuator or some other suitable type of piezoelectric device, and the piezoelectric device 106 and the membrane 202 may collectively form a piezoelectric speaker.
- the sound opening 204 extends through the substrate 108 , the substrate dielectric layer 110 , the device dielectric layer 120 , and the passivation layer 124 . Further, the substrate 108 , the substrate dielectric layer 110 , the device dielectric layer 120 , and passivation layer 124 form a common sidewall in the sound opening 204 . In alternative embodiments, the device dielectric layer 120 and/or the passivation layer 124 do not form the common sidewall, and/or the device barrier layer 118 further forms the common sidewall.
- a top layout view 300 of some embodiments of the IC chip of FIG. 2 is provided.
- the cross-sectional view 200 of FIG. 2 may, for example, be taken along line A, and the portions of the IC chip illustrated in the cross-sectional view 200 of FIG. 2 may, for example, correspond to solid portions of line A.
- the membrane 202 has a circular top geometry, and the sound opening 204 has six slit-shaped segments.
- the slit-shaped segments extend through the membrane 202 (see the cross-sectional view 200 of FIG. 2 ) and are evenly spaced circumferentially around the membrane 202 respectively at 0 degrees, 60 degrees, 120 degrees, 180 degrees, 240 degrees, and 300 degrees.
- the slit-shaped segments may be unevenly spaced circumferentially around the membrane 202 .
- the sound opening 204 has more or less slit-shaped segments.
- the sound opening 204 may have 8, 12, or some other suitable number of slit-shaped segments.
- the piezoelectric device 106 (constituents of which are shown in phantom) has a ring-shaped top geometry that extends in a closed path around the membrane 202 . In alternative embodiments, the piezoelectric device 106 has some other suitable top geometry. Further, the top-electrode pad 104 t and the bottom-electrode pad 104 b (both shown in phantom) extend respectively from the top-electrode via 122 t and the bottom-electrode via 122 b respectively to locations laterally offset from the piezoelectric device 106 .
- top-electrode and bottom-electrode barrier segments 102 t , 102 b (collectively the barrier segments 102 t , 102 b ) of the pad barrier layer 102 are individual to and respectively overlap with the top-electrode pad 104 t and the bottom-electrode pad 104 b . Further, the barrier segments 102 t , 102 b have top geometrical shapes that respectively match top geometrical shapes of the top-electrode pad 104 t and the bottom-electrode pad 104 b .
- the barrier segments 102 t , 102 b may have L-shaped top geometrical shapes or other suitable top geometrical shapes.
- the barrier segments 102 t , 102 b have top geometrical shapes different than those of the top-electrode pad 104 t and the bottom-electrode pad 104 b.
- the sound opening 204 is illustrated with six slit-shaped segments circumferentially spaced around the membrane 202 , more or less slit-shaped segments are amenable.
- top layout views 400 A, 400 B of some alternative embodiments of the IC chip of FIG. 3 are provided in which the number of slit-shaped segments is varied.
- the sound opening 204 has eight slit-shaped segments.
- the sound opening 204 has twelve slit-shaped segments.
- cross-sectional views 500 A- 500 G of some alternative embodiments of the IC chip of FIG. 2 are provided.
- the passivation layer 124 is on sidewalls of the membrane 202 and a top surface of the membrane 202 . Further, the passivation layer 124 lines a common sidewall formed by the upper semiconductor layer 108 u , the substrate dielectric layer 110 , and the device dielectric layer 120 . This may change the rigidity of the membrane 202 , whereby the membrane 202 may vibrate differently during use of the piezoelectric speaker collectively formed by the membrane 202 and the piezoelectric device 106 .
- the passivation layer 124 and the pad barrier layer 102 are both on sidewalls of the membrane 202 and a top surface of the membrane 202 . Further, the passivation layer 124 and the pad barrier layer 102 both line a common sidewall formed by the upper semiconductor layer 108 u , the substrate dielectric layer 110 , and the device dielectric layer 120 . This may change the rigidity of the membrane 202 , whereby the membrane 202 may vibrate differently during use of the piezoelectric speaker collectively formed by the membrane 202 and the piezoelectric device 106 .
- the top-electrode and bottom-electrode barrier segments 102 t , 102 b of the pad barrier layer 102 are connected outside the cross-sectional view 500 B of FIG. 5 B .
- the top electrode 116 and the piezoelectric layer 114 form common sidewalls and share a common width less than that of the bottom electrode 112 .
- the bottom and top electrodes 112 , 116 and the piezoelectric layer 114 form common sidewalls and share a common width.
- a getter layer 502 separates the piezoelectric device 106 from the substrate dielectric layer 110 and has a greater width than the common width.
- the getter layer 502 is configured to absorb hydrogen ions and/or other errant materials, whereby the getter layer 502 may prevent hydrogen ions and/or other errant materials from diffusing to and accumulating in the piezoelectric layer 114 .
- hydrogen ions that accumulate in the piezoelectric layer 114 may induce delamination and breakdown of the piezoelectric layer 114 , whereby the piezoelectric device 106 may fail. Accordingly, by absorbing hydrogen ions, the getter layer 502 may prevent device failure.
- the substrate dielectric layer 110 comprises hydrogen ions, which are absorbed by the getter layer 502 to prevent the hydrogen ions from diffusing to the piezoelectric layer 114 .
- the substrate dielectric layer 110 may comprise hydrogen ions in embodiments in which the substrate dielectric layer 110 is tetraethyl orthosilicate (TEOS) silicon oxide (e.g., TEOS-SiO 2 ), silane silicon oxide (e.g., SiH 4 —SiO 2 ), some other suitable oxide or dielectric, or any combination of the foregoing.
- the getter layer 502 is or comprises titanium, barium, cerium, lanthanum, aluminum, magnesium, thorium, or some other suitable conductive getter material for hydrogen ions and/or other errant materials.
- the bottom electrode 112 and the getter layer 502 share a first common width and form first common sidewalls. Further, the piezoelectric layer 114 and the top electrode 116 share a second common width less than the first common width and form second common sidewalls laterally offset from the first common sidewalls.
- the getter layer 502 described with regard to FIG. 5 D separates the top electrode 116 from the device barrier layer 118 instead of separating the bottom electrode 112 from the substrate dielectric layer 110 . Further, the getter layer 502 forms common sidewalls with the top electrode 116 and the piezoelectric layer 114 and shares a common width with the top electrode 116 and the piezoelectric layer 114 .
- a top-electrode getter layer 502 t is atop the top electrode 116
- a bottom-electrode getter layer 502 b is on an underside of the bottom electrode 112 .
- the bottom-electrode getter layer 502 b and the bottom-electrode getter layer 502 b are respectively as their counterparts are described with regard to FIGS. 5 E and 5 F .
- FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B a series of views of some embodiments of a method for forming an IC chip in which a barrier layer caps a pad of a piezoelectric device is provided.
- Figures labeled with a suffix of “A” or with no suffix correspond to cross-sectional views
- figures labeled with a suffix of “B” correspond to top layout views for like numbered figured with a suffix of “A”.
- FIGS. 2 and 3 The cross-sectional views of figures labeled with a suffix “A” may, for example, be taken along line A or B (whichever is present) in the top layout views of corresponding figures labeled with a suffix of “B”.
- the method is illustrated forming an IC chip according to the embodiments of FIGS. 2 and 3 . However, the method may alternatively be employed to form an IC chip according to other suitable embodiments.
- a substrate dielectric layer 110 is deposited over a substrate 108 .
- the substrate 108 is an SOI substrate and comprises a lower semiconductor layer 108 l , an insulator layer 108 i overlying the lower semiconductor layer 108 l , and an upper semiconductor layer 108 u overlying the insulator layer 108 i .
- the substrate 108 is a bulk semiconductor substrate or some other suitable type of semiconductor substrate.
- the substrate dielectric layer 110 and the insulator layer 108 i are a same material. In other embodiments, the substrate dielectric layer 110 and the insulator layer 108 i are different materials.
- a device film 602 is deposited over the substrate dielectric layer 110 and comprises a bottom-electrode layer 1121 , a piezoelectric layer 114 overlying the bottom-electrode layer 1121 , and a top-electrode layer 1161 overlying the piezoelectric layer 114 .
- the bottom-electrode layer 1121 and the top-electrode layer 1161 are a same material. In other embodiments, the bottom-electrode layer 1121 and the top-electrode layer 1161 are different materials.
- the device film 602 (see, e.g., FIG. 6 ) is patterned to form a piezoelectric device 106 having a ring-shaped top geometry (see, e.g., FIG. 7 B ) and extending in a closed path around a central area 702 .
- the piezoelectric device 106 may have some other suitable top geometry extending in a closed path around the central area 702 .
- the piezoelectric device 106 comprises a bottom electrode 112 , a patterned portion of the piezoelectric layer 114 (hereafter referred to more simply as the piezoelectric layer 114 ) overlying the bottom electrode 112 , and a top electrode 116 overlying the piezoelectric layer 114 .
- the bottom electrode 112 corresponds to a patterned portion of the bottom-electrode layer 1121 (see, e.g., FIG. 6 ), whereas the top electrode 116 corresponds to a patterned portion of the top-electrode layer 1161 .
- the piezoelectric layer 114 has a lesser width than the bottom electrode 112 , and further has sidewalls laterally offset from sidewalls of the bottom electrode 112 .
- the top electrode 116 has a lesser width than the piezoelectric layer 114 , and further has sidewalls laterally offset from sidewalls of the piezoelectric layer 114 .
- a process for performing the patterning does not employ hydrogen ions and/or other errant materials that may diffuse to and induce failure of the piezoelectric layer 114 .
- Hydrogen ions that diffuse to the piezoelectric layer 114 may accumulate in the piezoelectric layer 114 and induce delamination and breakdown of the piezoelectric layer 114 , whereby the piezoelectric device 106 may fail.
- a process for performing the patterning comprises: 1) performing a first photolithography/etching process into the top-electrode layer 1161 using a first mask to form the top electrode 116 ; 2) performing a second photolithography/etching process into the piezoelectric layer 114 using a second mask; and 3) performing a third photolithography/etching process into the bottom-electrode layer 1121 using a third mask to form the bottom electrode 112 .
- some other suitable process is performed for the patterning.
- the top-electrode layer 1161 and the piezoelectric layer 114 may be patterned together using a common photolithography/etching process and a common mask, whereas the bottom-electrode layer 1121 may be patterned using a different photolithography/etching process and a different mask.
- the top-electrode layer 1161 , the piezoelectric layer 114 , and the bottom-electrode layer 1121 may be patterned together using a common photolithography/etching process and a common mask.
- the two alternative examples use fewer masks and hence reduce manufacturing costs.
- a device barrier layer 118 is deposited covering the piezoelectric device 106 and the substrate dielectric layer 110 .
- the device barrier layer 118 is configured to block hydrogen and/or other suitable errant materials from diffusing to the piezoelectric layer 114 from over the device barrier layer 118 .
- the pad barrier layer 102 may prevent failure of the piezoelectric device 106 .
- the device barrier layer 118 is a metal oxide or some other suitable material.
- the metal oxide may, for example, be or comprise aluminum oxide (e.g., Al 2 O 3 ), titanium oxide (e.g., TiO 2 ), iron oxide (e.g., Fe 2 O 3 ), zirconium oxide (e.g., ZrO 2 ), zinc oxide (e.g., ZnO), copper oxide (e.g., CuO), tantalum oxide (e.g., Ta 2 O 5 ), some other suitable type of metal oxide, or any combination of the foregoing.
- aluminum oxide e.g., Al 2 O 3
- titanium oxide e.g., TiO 2
- iron oxide e.g., Fe 2 O 3
- zirconium oxide e.g., ZrO 2
- zinc oxide e.g., ZnO
- copper oxide e.g., CuO
- tantalum oxide e.g., Ta 2 O 5
- some other suitable type of metal oxide or any
- the device barrier layer 118 is deposited by a process that does not expose the piezoelectric layer 114 to hydrogen ions and/or other suitable errant materials.
- the device barrier layer 118 may be deposited by physical vapor deposition (PVD), atomic layer deposition (ALD), or some other suitable deposition process(es).
- the device barrier layer 118 is patterned to remove a central portion of the device barrier layer 118 surrounded by the piezoelectric device 106 . Further, the patterning removes a peripheral portion of the device barrier layer 118 surrounding the piezoelectric device 106 . At completion of the patterning, the piezoelectric device 106 remains covered (e.g., completely covered) by the device barrier layer 118 .
- the patterning may, for example, be performed by a photolithography/etching process or by some other suitable process.
- a device dielectric layer 120 is deposited covering the device barrier layer 118 .
- the device dielectric layer 120 may, for example, be or comprise TEOS oxide and/or some other suitable dielectric(s).
- the device dielectric layer 120 is deposited by a deposition process that exposes the device barrier layer 118 to hydrogen ions and/or other errant materials.
- the device barrier layer 118 blocks the errant material (e.g., the hydrogen ions) from accumulating in the piezoelectric layer 114 . As described above, this may, for example, prevent failure of the piezoelectric device 106 .
- the device dielectric layer 120 and the device barrier layer 118 are patterned to form a pair of via openings 1102 .
- the via openings 1102 are individual to and respectively expose the top electrode 116 and the bottom electrode 112 .
- the patterning is performed by a process that does employ hydrogen ions and/or other errant materials that may diffuse to and induce failure of the piezoelectric layer 114 .
- the patterning is performed by a photolithography/etching process or by some other suitable patterning process.
- a pair of pads 104 and a pair of vias 122 are formed.
- the pads 104 have first ends individual to and respectively overlying the via openings 1102 (see, e.g., FIG. 11 ). Further, the pads 104 have second ends distal from the first ends and laterally offset from the first ends.
- the vias 122 are individual to and respectively fill the via openings 1102 . Further, the vias 122 extend respectively from the pads 104 respectively to the top electrode 116 and the bottom electrode 112 .
- the pads 104 and the vias 122 are part of a common layer. In other embodiments, the pads 104 are part of a first layer, whereas the vias 122 are part of a second layer that is different than the first layer.
- the pads 104 and the vias 122 are formed by a process that does not employ hydrogen ions and/or other errant materials that may diffuse to and induce failure of the piezoelectric layer 114 .
- a process for forming the pads 104 and the vias 122 comprises: 1) depositing a conductive layer covering the device dielectric layer 120 and filling the via openings 1102 ; and 2) performing a photolithography/etching process to pattern the conductive layer into the pads 104 .
- some other suitable process is performed for forming the pads 104 and the vias 122 .
- a pad barrier layer 102 is deposited covering the pads 104 and the device dielectric layer 120 .
- the pad barrier layer 102 is configured to block hydrogen ions and/or other suitable errant materials from diffusing to the piezoelectric device 106 from over the pad 104 .
- hydrogen ions from hydrogen-containing semiconductor manufacturing processes performed after forming the pad 104 may diffuse to the piezoelectric layer 114 along the vias 122 .
- hydrogen ions that diffuse to the piezoelectric layer 114 may accumulate in the piezoelectric layer 114 and induce delamination and breakdown of the piezoelectric layer 114 , whereby the piezoelectric device 106 may fail. Therefore, by blocking diffusion of hydrogen ions to the piezoelectric layer 114 , the device barrier layer 118 may prevent delamination and breakdown of the piezoelectric layer 114 . This, in turn, may prevent failure of the piezoelectric device 106 .
- the pad barrier layer 102 is deposited by a process that does not expose the pads 104 to hydrogen ions and/or other suitable errant materials.
- the pad barrier layer 102 may be deposited by PVD, ALD, or some other suitable deposition process(es).
- a thickness T pb of the pad barrier layer 102 is about 200-600 angstroms, about 200-400 angstroms, about 400-600 angstroms, or some other suitable value. If the thickness T pb is too small (e.g., less than about 200 angstroms), the pad barrier layer 102 may be unable to block diffusion of hydrogen ions and/or other errant materials through the pad barrier layer 102 . If the thickness T pb is too large (e.g., more than about 600 angstroms), material may be wasted and high topographical variation at the pad barrier layer 102 may present processing challenges that reduce manufacturing yields.
- the pad barrier layer 102 is crystalline and/or has a density greater than about 2 g/cm 3 , 2.6 g/cm 3 , 5 g/cm 3 , or some other suitable value. It has been appreciated that such a density may block diffusion of hydrogen ions and/or other errant materials through the pad barrier layer 102 .
- the pad barrier layer 102 is a metal oxide or some other suitable material.
- the metal oxide may, for example, be or comprise aluminum oxide (e.g., Al 2 O 3 ), titanium oxide (e.g., TiO 2 ), iron oxide (e.g., Fe 2 O 3 ), zirconium oxide (e.g., ZrO 2 ), zinc oxide (e.g., ZnO), copper oxide (e.g., CuO), tantalum oxide (e.g., Ta 2 O 5 ), some other suitable type of metal oxide, or any combination of the foregoing.
- aluminum oxide e.g., Al 2 O 3
- titanium oxide e.g., TiO 2
- iron oxide e.g., Fe 2 O 3
- zirconium oxide e.g., ZrO 2
- zinc oxide e.g., ZnO
- copper oxide e.g., CuO
- tantalum oxide e.g., Ta 2 O 5
- some other suitable type of metal oxide or any combination of the foregoing.
- the pad barrier layer 102 is a same material as the device barrier layer 118 . In other embodiments, the pad barrier layer 102 is a different material than the device barrier layer 118 . In some embodiments, the device barrier layer 118 is crystalline and/or has a density greater than about 2 g/cm 3 , 2.6 g/cm 3 , 5 g/cm 3 , or some other suitable value. In some embodiments, the density is the same as that of the pad barrier layer 102 .
- the pad barrier layer 102 is patterned to segment the pad barrier layer 102 .
- a bottom-electrode barrier segment 102 b overlies and is localized to the pad 104 at the bottom electrode 112
- a top-electrode barrier segment 102 t overlies and is localized to the pad 104 at the top electrode 116 .
- the pads 104 remain covered (e.g., completely covered) by the pad barrier layer 102 .
- the patterning may, for example, be performed by a photolithography/etching process or by some other suitable process.
- the device and substrate dielectric layers 120 , 110 and the upper semiconductor layer 108 u are patterned to form a plurality of slits 1502 at the central area 702 surrounded by the piezoelectric device 106 .
- the slits 1502 overlie the insulator layer 108 i , and extend through the device and substrate dielectric layers 120 , 110 and the upper semiconductor layer 108 u to the insulator layer 108 i .
- the slits 1502 are circumferentially spaced around, and extend laterally into, a circular region of the upper semiconductor layer 108 u .
- the circular region is surrounded by the piezoelectric device (e.g., when viewed top down) and is hereafter referred to as a membrane 202 .
- a process for forming the slits 1502 comprises: 1) forming a photoresist mask over the pad barrier layer 102 and the device dielectric layer 120 ; 2) performing a dry etch into the device and substrate dielectric layers 120 , 110 and the upper semiconductor layer 108 u with the mask in place; and 3) performing plasma ashing to remove the photoresist mask.
- some other suitable process is performed to form the slits 1502 .
- the dry etching and/or the plasma ashing expose the expose the IC chip being formed to hydrogen ions and/or other errant materials.
- the pad barrier layer 102 and the device barrier layer 118 block the errant material (e.g., the hydrogen ions) from diffusing to and accumulating in the piezoelectric layer 114 . As described above, this may, for example, prevent failure of the piezoelectric device 106 .
- the errant material e.g., the hydrogen ions
- a passivation layer 124 is deposited covering the pad barrier layer 102 , the device dielectric layer 120 , and the membrane 202 , and further lining the slits 1502 .
- the depositing exposes the IC chip being formed to hydrogen ions and/or other errant materials.
- the pad barrier layer 102 and the device barrier layer 118 block the errant material (e.g., the hydrogen ions) from diffusing to and accumulating in the piezoelectric layer 114 .
- the passivation layer 124 and the pad barrier layer 102 are patterned to form pad openings 126 at ends of the pads 104 distal from the vias 122 . Further, the patterning clears the passivation layer 124 from the membrane 202 and the slits 1502 . In alternative embodiments, the passivation layer 124 persists at the membrane 202 and the slits 1502 (e.g., to form the IC chip according to the embodiments of FIG. 5 A ).
- a process for performing the patterning comprises: 1) forming a photoresist mask over the passivation layer 124 ; 2) performing a dry etch into the passivation layer 124 and the pad barrier layer 102 with the mask in place; and 3) performing plasma ashing to remove the photoresist mask.
- some other suitable process is performed to form the pad openings 126 .
- the dry etching and/or the plasma ashing expose the IC chip being formed to hydrogen ions and/or other errant materials. Because the pad openings 126 extend through the pad barrier layer 102 , hydrogen ions and/or other errant materials may extend through the pad barrier layer 102 . However, because the pad openings 126 are at ends of the pads 104 distal from the vias 122 , the diffusion path from the pad openings 126 to the piezoelectric layer 114 may be long. Hence, the likelihood of hydrogen ions and/or other errant materials diffusing to the piezoelectric layer 114 is low.
- a sacrificial layer 1802 is deposited covering the IC chip being formed and filling the pad openings 126 (see, e.g., FIGS. 17 A and 17 B ) and the slits 1502 (see, e.g., FIGS. 17 A and 17 B ).
- the sacrificial layer 1802 is silicon oxide and/or some other suitable dielectric(s).
- the IC chip of FIG. 18 is flipped vertically and the substrate 108 is patterned to form a sound opening 204 overlying and exposing the membrane 202 .
- the patterning may, for example, be performed by a photolithography/etching process or by some other suitable process.
- the IC chip is flipped vertically. Further, the sacrificial layer 1802 is removed. The removal may, for example, be performed by an etch using an etchant having a high selectivity for the sacrificial layer 1802 relative to underlying structure (e.g., the passivation layer 124 and the membrane 202 ).
- the sound opening 204 incorporates the slits 1502 (see, e.g., FIGS. 17 A and 17 B ) and hence extends through the membrane 202 . Further, the membrane 202 is released and may move in the sound opening 204 . In response to application of a voltage across the piezoelectric layer 114 , from the top electrode 116 to the bottom electrode 112 , the piezoelectric device 106 may vibrate. The vibrations may move to the membrane 202 and cause the membrane 202 to vibrate, which generates sound waves in the sound opening 204 . Accordingly, the piezoelectric device 106 and the membrane 202 coordinate to form a piezoelectric speaker.
- FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B are described with reference to a method, it will be appreciated that the structures shown in these figures are not limited to the method but rather may stand alone separate of the method. While FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B are described with reference to a method, it will be appreciated that the structures shown in these figures are not limited to the method but rather may stand alone separate of the method. While FIGS.
- FIG. 21 a block diagram 2100 of some embodiments of the method of FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B is provided.
- a device film is formed overlying a substrate, wherein the device film comprises a bottom-electrode layer, a piezoelectric layer over the bottom-electrode layer, and a top-electrode layer over the piezoelectric layer. See, for example, FIG. 6 .
- the device film is patterned to form a piezoelectric device extending in a closed path around a central area. See, for example, FIGS. 7 A and 7 B .
- a device barrier layer is formed covering the piezoelectric device, wherein the device barrier layer is configured to block diffusion of hydrogen ions and/or other errant materials. See, for example, FIGS. 8 , 9 A, and 9 B .
- a device dielectric layer is deposited covering the device barrier layer and the piezoelectric device, wherein the device dielectric layer blocks hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer while depositing the device dielectric layer. See, for example, FIG. 10 .
- a pair of pads is formed, wherein the pads have first ends respectively overlying and connected to a top electrode of the piezoelectric device and a bottom electrode of the piezoelectric device respectively by vias, and wherein the pads have second ends distal from the first ends and laterally offset from the piezoelectric device. See, for example, FIGS. 11 , 12 A , and 12 B.
- a pad barrier layer is formed covering the pads, wherein the pad barrier layer is configured to block diffusion of hydrogen ions and/or other errant materials. See, for example, FIGS. 13 , 14 A, and 14 B .
- the substrate is patterned to form a plurality of slits at the central area, wherein the slits are circumferentially spaced around a membrane of the substrate at the central area, and wherein the pad barrier layer blocks hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer while forming the slits. See, for example, FIGS. 15 A and 15 B .
- a passivation layer is deposited covering the pad barrier layer, wherein the pad barrier layer blocks hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer while depositing the passivation layer. See, for example, FIG. 16 .
- the pad barrier layer and the passivation layer are patterned to form pad openings respectively exposing the second ends of the pads, wherein hydrogen ions and/or other errant materials used while forming the pad openings are unlikely to diffuse to the piezoelectric layer through the pad openings because the second ends are distal from the vias. See, for example, FIGS. 17 A and 17 B .
- a sound opening is formed extending through the substrate to the membrane on an opposite side of the substrate as the piezoelectric device, wherein the forming of the sound opening releases the membrane to allow the membrane to move. See, for example, FIGS. 18 , 19 , 20 A, and 20 B .
- FIG. 21 While the block diagram 2100 of FIG. 21 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.
- a cross-sectional view 2200 of some first alternative embodiments of the method of FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B is provided in which the passivation layer 124 persists on the membrane 202 at completion of the method.
- the acts described with regard to FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, and 16 are performed.
- the patterning described with regard to FIGS. 17 A and 17 B is performed, except that the patterning does not clear the passivation layer 124 from the membrane 202 and the slits 1502 . Rather, the patterning forms openings 2202 extending through the passivation layer 124 respectively at the slits 1502 to expose the insulator layer 108 i .
- the acts described with regard to FIGS. 18 , 19 , 20 A, and 20 B are performed.
- the resulting IC chip may, for example, be as illustrated at FIG. 5 A .
- FIGS. 23 - 25 a series of cross-sectional views 2300 - 2500 of some second alternative embodiments of the method of FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B is provided in which the pad barrier layer 102 and the passivation layer 124 are on the membrane 202 at completion of the method.
- the acts described with regard to FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, and 12 B are performed. Further, the acts described with regard to FIGS. 15 A and 15 B are thereafter performed. Notably, the acts described with regard to FIGS. 13 , 14 A, and 14 B are not performed. Hence, the pad barrier layer 102 is not formed before the patterning to form the slits 1502 .
- the acts described with regard to FIGS. 13 and 16 are sequentially formed to respectively deposit the pad barrier layer 102 and the passivation layer 124 .
- the pad barrier layer 102 and the passivation layer 124 are deposited after the patterning to form the slits 1502 .
- the patterning described with regard to FIGS. 17 A and 17 B is performed, except that the patterning does not clear the pad barrier layer 102 and the passivation layer 124 from the membrane 202 and the slits 1502 . Rather, the patterning forms openings 2502 extending through the passivation layer 124 and the pad barrier layer 102 respectively at the slits 1502 to expose the insulator layer 108 i . Thereafter, the acts described with regard to FIGS. 18 , 19 , 20 A, and 20 B are performed. The resulting IC chip may, for example, be as illustrated at FIG. 5 B .
- a series of cross-sectional views 2600 and 2700 of some third alternative embodiments of the method of FIGS. 6 , 7 A, 7 B, 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 , 14 A, 14 B, 15 A, 15 B, 16 , 17 A, 17 B, 18 , 19 , 20 A , and 20 B is provided in which a getter layer 502 is on a bottom of the bottom electrode 112 .
- a getter layer 502 is deposited between the depositing of the substrate dielectric layer 110 and the depositing of the device film 602 .
- the getter layer 502 is configured to absorb hydrogen ions and/or other errant materials, whereby the getter layer 502 may prevent hydrogen ions and/or other errant materials from accumulating in the piezoelectric layer 114 .
- the getter layer 502 is conductive and may, for example, be or comprise titanium, barium, cerium, lanthanum, aluminum, magnesium, thorium, or some other suitable conductive getter material for hydrogen ions and/or other errant materials.
- the acts described with regard to FIGS. 7 A and 7 B are performed, with a few exceptions.
- the bottom-electrode layer 1121 (see, e.g., FIG. 26 ), the piezoelectric layer 114 , and the top-electrode layer 1161 (see, e.g., FIG. 26 ) are patterned with a common pattern.
- the getter layer 502 is patterned with a pattern different than the common pattern.
- the common pattern is the same as that illustrated for the piezoelectric layer 114 in FIGS. 7 A and 7 B and/or the different pattern is the same as that illustrated for the bottom-electrode layer 1121 in FIGS.
- the resulting IC chip may, for example, be as illustrated at FIG. 5 D .
- the present disclosure provides an IC chip including: a substrate; a piezoelectric device overlying the substrate; a pad overlying the piezoelectric device; a via extending from the pad to the piezoelectric device; and a barrier layer overlying the pad; wherein the barrier layer is configured to block hydrogen ions from diffusing through the barrier layer, from over the barrier layer to the piezoelectric device.
- the barrier layer includes aluminum oxide, titanium oxide, iron oxide, zirconium oxide, zinc oxide, copper oxide, or tantalum oxide.
- the barrier layer has a density in excess of about 2 grams per cubic centimeter.
- the IC chip further includes a dielectric layer between the pad and the piezoelectric device, wherein the via extends through the dielectric layer, and wherein a rate of diffusion of hydrogen ions through the dielectric layer is more than a rate of diffusion of hydrogen ions through the barrier layer.
- the IC chip further includes a second barrier layer between the pad and the piezoelectric device, wherein the via extends through the second barrier layer, and wherein the second barrier layer is configured to block hydrogen ions from diffusing through the second barrier layer, from over the second barrier layer to the piezoelectric device.
- the IC chip further includes: a second pad including a first end overlying the piezoelectric device; and a second via extending from the second pad to the piezoelectric device, wherein the barrier layer overlies and is level with the second pad.
- the IC chip further includes a getter layer on an underside of the piezoelectric device and configured to getter hydrogen ions.
- the present disclosure provides another IC chip including: a substrate; a piezoelectric structure over the substrate, wherein the piezoelectric structure includes a bottom electrode, a piezoelectric layer overlying the bottom electrode, and a top electrode overlying the piezoelectric layer; a first hydrogen-barrier layer overlying the piezoelectric structure; a pad having a first end and a second end, wherein the first end overlies the first hydrogen-barrier layer and the piezoelectric structure and is electrically coupled to the top or bottom electrode, and wherein the second end is level with the piezoelectric structure; and a second hydrogen-barrier layer overlying the pad and the piezoelectric structure.
- the second hydrogen-barrier layer is a metal oxide.
- the first hydrogen-barrier layer extends along individual sidewalls respectively of the bottom electrode, the top electrode, and the piezoelectric layer.
- the first and second hydrogen-barrier layers share a common density.
- the substrate includes a moveable membrane at an opening extending through the substrate, wherein the piezoelectric structure extends in a closed path around the moveable membrane.
- the second hydrogen-barrier layer is on a sidewall of the moveable membrane.
- the IC chip further includes a passivation layer overlying the second hydrogen-barrier layer, wherein the passivation layer is on a sidewall of the moveable membrane, and wherein the second hydrogen-barrier layer is spaced from the moveable membrane.
- the pad is elongated continuously from the first end of the pad to the second end of the pad, wherein the second end is distal from the first end and is laterally offset from the piezoelectric structure.
- the IC chip further includes a passivation layer overlying the second hydrogen-barrier layer, wherein the passivation layer and the second hydrogen-barrier layer form a common sidewall at the second end of the pad, and wherein the second end is distal from and laterally offset from the first end and the piezoelectric structure.
- the present disclosure provides a method including: forming a piezoelectric structure over a substrate and including a first electrode, a piezoelectric layer overlying the first electrode, and a second electrode overlying the piezoelectric layer; depositing a dielectric layer covering the piezoelectric structure; forming a pad and a via, wherein the pad overlies the dielectric layer, and wherein the via extends through the dielectric layer, from the pad to the to the piezoelectric structure; depositing a barrier layer covering the pad and the piezoelectric structure; and performing a semiconductor manufacturing process after the depositing of the barrier layer, wherein the semiconductor manufacturing process exposes the barrier layer to ions, and wherein the barrier layer blocks the ions from passing through the barrier layer.
- the depositing of the barrier layer is performed without a source of hydrogen, and wherein the ions are hydrogen ions.
- the piezoelectric structure extends laterally in a closed path around a central area, wherein the semiconductor manufacturing process includes patterning the substrate to form a plurality of slits at the central area.
- the semiconductor manufacturing process includes: depositing a passivation layer covering the barrier layer; and patterning the passivation layer and the barrier layer to form a pad opening exposing an end of the pad laterally offset from the piezoelectric structure.
Abstract
Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a pad barrier layer caps a pad of a piezoelectric device. The pad barrier layer is configured to block hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer. Absent the pad barrier layer, hydrogen ions from hydrogen-ion containing processes performed after forming the pad may diffuse to the piezoelectric layer along a via extending from the pad to the piezoelectric device. By blocking diffusion of hydrogen ions and/or other errant materials to the piezoelectric device, the pad barrier layer may prevent delamination and breakdown of the piezoelectric layer. Hence, the pad barrier layer may prevent failure of the piezoelectric device.
Description
- This application claims the benefit of U.S. Provisional Application No. 63/228,275, filed on Aug. 2, 2021, the contents of which are incorporated by reference in their entirety.
- Piezoelectric actuators and other suitable piezoelectric devices may create physical movement in response to an electrical signal. The physical movement may be used to control various kinds of mechanical and optical systems. For example, the physical movement may be used to control movement of a moveable membrane to create a speaker.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 illustrates a cross-sectional view of some embodiments of an integrated circuit (IC) chip in which a barrier layer caps a pad of a piezoelectric device. -
FIG. 2 illustrates an expanded cross-sectional view of some embodiments of the IC chip ofFIG. 1 in which the piezoelectric device surrounds a membrane. -
FIG. 3 illustrates a top layout view of some embodiments of the IC chip ofFIG. 2 . -
FIGS. 4A and 4B illustrate top layout views of some alternative embodiments of the IC chip ofFIG. 3 . -
FIGS. 5A-5G illustrate cross-sectional views of some alternative embodiments of the IC chip ofFIG. 2 . -
FIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B illustrate a series of views of some embodiments of a method for forming an IC chip in which a barrier layer caps a pad of a piezoelectric device. -
FIG. 21 illustrates a block diagram of some embodiments of the method ofFIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B. -
FIG. 22 illustrates a cross-sectional view of some first alternative embodiments of the method ofFIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B. -
FIGS. 23-25 illustrate a series of cross-sectional views of some second alternative embodiments of the method ofFIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B. -
FIGS. 26 and 27 illustrate a series of cross-sectional views of some third alternative embodiments of the method ofFIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B. - The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- A piezoelectric actuator or some other suitable piezoelectric device may comprise a bottom electrode, a piezoelectric layer overlying the bottom electrode, and a top electrode overlying the piezoelectric layer. A top-electrode pad overlies and is electrically coupled to the top electrode by a top-electrode via extending from the top-electrode pad to the top electrode. A bottom-electrode pad overlies and is electrically coupled to the bottom electrode by a bottom-electrode via extending from the bottom-electrode pad to the bottom electrode.
- A challenge with the piezoelectric device is that hydrogen-ion containing processes may be employed after forming the piezoelectric layer. Further, the top-electrode and bottom-electrode vias may provide diffusion paths for hydrogen ions from the hydrogen-ion containing processes to diffuse to the piezoelectric layer. Hydrogen ions that diffuse to the piezoelectric layer may accumulate in the piezoelectric layer and induce delamination and breakdown of the piezoelectric layer, whereby the piezoelectric device may fail.
- Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a pad barrier layer caps a pad of a piezoelectric device. The pad barrier layer is configured to block hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer. Absent the pad barrier layer, hydrogen ions from hydrogen-ion containing processes performed after forming the pad may diffuse to the piezoelectric layer along a via extending from the pad to the piezoelectric device. By blocking diffusion of hydrogen ions and/or other errant materials to the piezoelectric device, the pad barrier layer may prevent delamination and breakdown of the piezoelectric layer. Hence, the pad barrier layer may prevent failure of the piezoelectric device.
- With reference to
FIG. 1 , across-sectional view 100 of some embodiments of an IC chip is provided in which apad barrier layer 102 caps apad 104 of apiezoelectric device 106. Thepiezoelectric device 106 overlies asubstrate 108 and is separated from thesubstrate 108 by a substratedielectric layer 110. Further, thepiezoelectric device 106 comprises abottom electrode 112, apiezoelectric layer 114 overlying thebottom electrode 112, and atop electrode 116 overlying thepiezoelectric layer 114. In some embodiments, thepiezoelectric device 106 is an actuator, but other suitable types of piezoelectric device are amenable. In some embodiments, thepiezoelectric device 106 may also be referred to as a metal-piezoelectric-metal (MPM) structure and/or, a piezoelectric structure. - A
device barrier layer 118 and a devicedielectric layer 120 overlie thepiezoelectric device 106 and are stacked between thepiezoelectric device 106 and thepad 104. Thedevice barrier layer 118 separates the devicedielectric layer 120 from thepiezoelectric device 106 and is configured to block hydrogen ions and/or other suitable errant materials from diffusing to thepiezoelectric layer 114 from over thedevice barrier layer 118. In some embodiments, thedevice barrier layer 118 may be regarded as a hydrogen-barrier layer. - The
pad 104 overlies thedevice barrier layer 118 and comprises afirst end 104 fe and asecond end 104 se. Thefirst end 104 fe overlies thetop electrode 116, and avia 122 extends from thefirst end 104 fe, through thedevice barrier layer 118 and the devicedielectric layer 120, to thetop electrode 116. In alternative embodiments, thevia 122 extends to thebottom electrode 112 instead of thetop electrode 116. Thesecond end 104 se is distal from thefirst end 104 fe and is laterally offset from thepiezoelectric device 106. - The
pad barrier layer 102 caps thepad 104, and apassivation layer 124 caps thepad barrier layer 102 and the devicedielectric layer 120. Further, a pad opening 126 extends through thepad barrier layer 102 and thepassivation layer 124 to expose thesecond end 104 se of thepad 104. Similar to thedevice barrier layer 118, thepad barrier layer 102 is configured to block hydrogen ions and/or other suitable errant materials from diffusing to thepiezoelectric device 106 from over thepad 104. In some embodiments, thepad barrier layer 102 may be regarded as a hydrogen-barrier layer. Absent thepad barrier layer 102, hydrogen ions from hydrogen-containing semiconductor manufacturing processes performed after forming thepad 104 may diffuse to thepiezoelectric layer 114 along thevia 122. - Hydrogen ions that diffuse to the
piezoelectric layer 114 may accumulate in thepiezoelectric layer 114 and induce delamination and breakdown of thepiezoelectric layer 114, whereby thepiezoelectric device 106 may fail. Therefore, by blocking diffusion of hydrogen ions to thepiezoelectric layer 114, thepad barrier layer 102 and thedevice barrier layer 118 may prevent delamination and breakdown of thepiezoelectric layer 114. Hence, thepad barrier layer 102 and thedevice barrier layer 118 may prevent failure of thepiezoelectric device 106. - Because the pad opening 126 extends through the
pad barrier layer 102, hydrogen ions and/or other errant materials may extend through thepad barrier layer 102. However, because the pad opening 126 is at thesecond end 104 se of thepad 104, laterally offset from thepiezoelectric device 106, the diffusion path from the pad opening 126 to thepiezoelectric layer 114 may be long. Hence, the likelihood of hydrogen ions and/or other errant materials diffusing to thepiezoelectric layer 114 from thepad opening 126 may be low. - In some embodiments, a thickness Tpb of the
pad barrier layer 102 is about 200-600 angstroms, about 200-400 angstroms, about 400-600 angstroms, or some other suitable value. If the thickness Tpb is too small (e.g., less than about 200 angstroms), thepad barrier layer 102 may be unable to block diffusion of hydrogen ions and/or other errant materials through thepad barrier layer 102. If the thickness Tpb is too large (e.g., more than about 600 angstroms), material may be wasted and high topographical variation at thepad barrier layer 102 may present processing challenges that reduce manufacturing yields. - In some embodiments, the
pad barrier layer 102 is crystalline and/or has a density greater than about 2 grams per cubic centimeter (g/cm3), 2.6 g/cm3, 5 g/cm3, or some other suitable value. It has been appreciated that such a density may block diffusion of hydrogen ions and/or other errant materials through thepad barrier layer 102. - In some embodiments, the
pad barrier layer 102 is a metal oxide or some other suitable material. The metal oxide may, for example, be or comprise aluminum oxide (e.g., Al2O3), titanium oxide (e.g., TiO2), iron oxide (e.g., Fe2O3), zirconium oxide (e.g., ZrO2), zinc oxide (e.g., ZnO), copper oxide (e.g., CuO), tantalum oxide (e.g., Ta2O5), some other suitable type of metal oxide, or any combination of the foregoing. In some embodiments, thepad barrier layer 102 is dielectric. In some embodiments, during formation of the IC chip, thepad barrier layer 102 is deposited by a process that does not depend on hydrogen ions and/or other errant materials. For example, thepad barrier layer 102 may be deposited by physical vapor deposition (PVD) or some other suitable type of deposition. - In some embodiments, the
device barrier layer 118 is a same material as thepad barrier layer 102. In other embodiments, thedevice barrier layer 118 is a different material than thepad barrier layer 102. In some embodiments, thedevice barrier layer 118 is crystalline and/or has a density greater than about 2 g/cm3, 2.6 g/cm3, 5 g/cm3, or some other suitable value. In some embodiments, the density is the same as that of thepad barrier layer 102. In some embodiments, thedevice barrier layer 118 is dielectric. - In some embodiments, the
substrate 108 is a bulk substrate of silicon or some other suitable type of semiconductor material. In other embodiments, thesubstrate 108 is a semiconductor-on-insulator (SOI) substrate or some other suitable type of semiconductor substrate. To the extent that thesubstrate 108 is an SOI substrate, the semiconductor material of the SOI substrate may be silicon or some other suitable type of semiconductor material. - In some embodiments, the
substrate dielectric layer 110 is or comprises silicon oxide and/or some other suitable dielectric(s). In some embodiments, thedevice dielectric layer 120 is or comprises silicon oxide and/or some other suitable dielectric(s). In some embodiments, thesubstrate dielectric layer 110 and thedevice dielectric layer 120 are or comprise a same material. In other embodiments, thesubstrate dielectric layer 110 and the device dielectric layer are or comprise different materials. In some embodiments, thepassivation layer 124 is or comprise silicon nitride and/or some other suitable dielectric(s). - In some embodiments, a rate of diffusion of hydrogen ions through and/or in the
pad barrier layer 102 is less than: 1) a rate of diffusion of hydrogen ions through and/or in thesubstrate dielectric layer 110; 2) a rate of diffusion of hydrogen ions through and/or in thedevice dielectric layer 120; 3) a rate of diffusion of hydrogen ions through and/or in thepad 104; 4) a rate of diffusion of hydrogen ions through and/or in thepassivation layer 124; or 5) any combination of the foregoing. Similarly, in some embodiments, a rate of diffusion of hydrogen ions through and/or in thedevice barrier layer 118 is less than: 1) a rate of diffusion of hydrogen ions through and/or in thesubstrate dielectric layer 110; 2) a rate of diffusion of hydrogen ions through and/or in thedevice dielectric layer 120; 3) a rate of diffusion of hydrogen ions through and/or in thepad 104; 4) a rate of diffusion of hydrogen ions through and/or in thepassivation layer 124; or 5) any combination of the foregoing. The rates of thepad barrier layer 102 and/or thedevice barrier layer 118 may, for example, be zero or close to zero. - In some embodiments, the
piezoelectric layer 114 is or comprises lead zirconate titanate (e.g., PZT) and/or some other suitable piezoelectric material(s). In some embodiments, thebottom electrode 112 is or comprises titanium oxide, platinum, some other suitable metal(s) or conductive material(s), or any combination of the foregoing. In some embodiments, thetop electrode 116 is or comprises titanium oxide, platinum, some other suitable metal(s) or conductive material(s), or any combination of the foregoing. In some embodiments, the bottom andtop electrodes top electrodes - In some embodiments, the
pad 104 is or comprises copper, aluminum copper, aluminum, some other suitable metal(s) or conductive material(s), or any combination of the foregoing. In some embodiments, thedevice barrier layer 118 is configured to block material of thepad 104 from diffusing from thepad 104 to thepiezoelectric device 106. Such material may, for example, be or comprise copper and/or some other suitable material. - In some embodiments, while not shown, a bump structure, a wire bond structure, or some other suitable type of conductive structure is formed in the
pad opening 126 to electrically couple thepad 104 and hence thepiezoelectric device 106 to another IC chip, a printed circuit board (PCB), an interposer structure, or some other suitable structure. - With reference to
FIG. 2 , an expandedcross-sectional view 200 of some embodiments of the IC chip ofFIG. 1 is provided in which thepiezoelectric device 106 surrounds amembrane 202. Upon application of a voltage from thetop electrode 116 to thebottom electrode 112, thepiezoelectric device 106 vibrates, thereby causing themembrane 202 to move within asound opening 204. As such, themembrane 202 and thepiezoelectric device 106 collectively form a piezoelectric speaker or some other suitable structure. - A pair of
pads 104 and a pair ofvias 122 electrically couple to thepiezoelectric device 106. The pair ofpads 104 comprises a top-electrode pad 104 t and a bottom-electrode pad 104 b, and the pair ofvias 122 comprises a top-electrode via 122 t and a bottom-electrode via 122 b. The top-electrode pad 104 t and the top-electrode via 122 t correspond to thepad 104 and the via 122 illustrated and described with regard toFIG. 1 . The bottom-electrode pad 104 b and the bottom-electrode via 122 b are on an opposite side of thesound opening 204 as the top-electrode pad 104 t and the top-electrode via 122 t. Further, the bottom-electrode via 122 b extends from the bottom-electrode pad 104 b to thebottom electrode 112. - The
pad barrier layer 102 caps both of thepads 104 and comprises a top-electrode barrier segment 102 t and a bottom-electrode barrier segment 102 b. The top-electrode barrier segment 102 t caps the top-electrode pad 104 t, whereas the bottom-electrode barrier segment 102 b caps the bottom-electrode pad 104 b. - By capping the
pads 104, thepad barrier layer 102 prevents hydrogen ions and/or other errant particles from diffusing to thepiezoelectric device 106 from over the top-electrode pad 104 t and the bottom-electrode pad 104 b. Absent thepad barrier layer 102, hydrogen ions from hydrogen-containing semiconductor manufacturing processes performed after forming the top-electrode pad 104 t and the bottom-electrode pad 104 b may diffuse to thepiezoelectric layer 114 along the top-electrode via 122 t and/or along the bottom-electrode via 122 b. This may induce delamination and breakdown of thepiezoelectric layer 114, whereby thepiezoelectric device 106 may fail. Therefore, by blocking diffusion of hydrogen ions to thepiezoelectric layer 114, thepad barrier layer 102 may prevent failure of thepiezoelectric device 106. - A pair of
pad openings 126 respectively expose thepads 104 respectively at locations laterally offset from thepiezoelectric device 106, whereby diffusion paths from thepad openings 126 to thepiezoelectric layer 114 may be long. Because the diffusion paths may be long, the likelihood of hydrogen ions and/or other errant materials diffusing to thepiezoelectric layer 114 from thepad openings 126 may be low. - The
substrate 108 is an SOI substrate and comprises a lower semiconductor layer 108 l, aninsulator layer 108 i overlying the lower semiconductor layer 108 l, and anupper semiconductor layer 108 u overlying theinsulator layer 108 i. In some embodiments, theinsulator layer 108 i is or comprises silicon oxide and/or some other suitable dielectric(s). In some embodiments, the lower semiconductor layer 108 l and the upper semiconductor layers 108 u are or comprise silicon and/or some other suitable semiconductor(s). - The
membrane 202 corresponds to a portion of theupper semiconductor layer 108 u and is connected to a remainder of theupper semiconductor layer 108 u outside thecross-sectional view 200 ofFIG. 2 . Further, as described above, themembrane 202 moves in thesound opening 204 in response to vibrations from thepiezoelectric device 106. As such, thepiezoelectric device 106 may also be regarded as a piezoelectric actuator or some other suitable type of piezoelectric device, and thepiezoelectric device 106 and themembrane 202 may collectively form a piezoelectric speaker. - The
sound opening 204 extends through thesubstrate 108, thesubstrate dielectric layer 110, thedevice dielectric layer 120, and thepassivation layer 124. Further, thesubstrate 108, thesubstrate dielectric layer 110, thedevice dielectric layer 120, andpassivation layer 124 form a common sidewall in thesound opening 204. In alternative embodiments, thedevice dielectric layer 120 and/or thepassivation layer 124 do not form the common sidewall, and/or thedevice barrier layer 118 further forms the common sidewall. - With reference to
FIG. 3 , atop layout view 300 of some embodiments of the IC chip ofFIG. 2 is provided. Thecross-sectional view 200 ofFIG. 2 may, for example, be taken along line A, and the portions of the IC chip illustrated in thecross-sectional view 200 ofFIG. 2 may, for example, correspond to solid portions of line A. - The
membrane 202 has a circular top geometry, and thesound opening 204 has six slit-shaped segments. The slit-shaped segments extend through the membrane 202 (see thecross-sectional view 200 ofFIG. 2 ) and are evenly spaced circumferentially around themembrane 202 respectively at 0 degrees, 60 degrees, 120 degrees, 180 degrees, 240 degrees, and 300 degrees. In other embodiments, the slit-shaped segments may be unevenly spaced circumferentially around themembrane 202. Further, in other embodiments, thesound opening 204 has more or less slit-shaped segments. For example, thesound opening 204 may have 8, 12, or some other suitable number of slit-shaped segments. - The piezoelectric device 106 (constituents of which are shown in phantom) has a ring-shaped top geometry that extends in a closed path around the
membrane 202. In alternative embodiments, thepiezoelectric device 106 has some other suitable top geometry. Further, the top-electrode pad 104 t and the bottom-electrode pad 104 b (both shown in phantom) extend respectively from the top-electrode via 122 t and the bottom-electrode via 122 b respectively to locations laterally offset from thepiezoelectric device 106. - The top-electrode and bottom-
electrode barrier segments barrier segments pad barrier layer 102 are individual to and respectively overlap with the top-electrode pad 104 t and the bottom-electrode pad 104 b. Further, thebarrier segments electrode pad 104 t and the bottom-electrode pad 104 b. For example, thebarrier segments electrode pad 104 t and the bottom-electrode pad 104 b, may have L-shaped top geometrical shapes or other suitable top geometrical shapes. In alternative embodiments, thebarrier segments electrode pad 104 t and the bottom-electrode pad 104 b. - While the
sound opening 204 is illustrated with six slit-shaped segments circumferentially spaced around themembrane 202, more or less slit-shaped segments are amenable. For example, with reference toFIGS. 4A and 4B , top layout views 400A, 400B of some alternative embodiments of the IC chip ofFIG. 3 are provided in which the number of slit-shaped segments is varied. InFIG. 4A , thesound opening 204 has eight slit-shaped segments. InFIG. 4B , thesound opening 204 has twelve slit-shaped segments. - With reference to
FIGS. 5A-5G ,cross-sectional views 500A-500G of some alternative embodiments of the IC chip ofFIG. 2 are provided. - In
FIG. 5A , thepassivation layer 124 is on sidewalls of themembrane 202 and a top surface of themembrane 202. Further, thepassivation layer 124 lines a common sidewall formed by theupper semiconductor layer 108 u, thesubstrate dielectric layer 110, and thedevice dielectric layer 120. This may change the rigidity of themembrane 202, whereby themembrane 202 may vibrate differently during use of the piezoelectric speaker collectively formed by themembrane 202 and thepiezoelectric device 106. - In
FIG. 5B , thepassivation layer 124 and thepad barrier layer 102 are both on sidewalls of themembrane 202 and a top surface of themembrane 202. Further, thepassivation layer 124 and thepad barrier layer 102 both line a common sidewall formed by theupper semiconductor layer 108 u, thesubstrate dielectric layer 110, and thedevice dielectric layer 120. This may change the rigidity of themembrane 202, whereby themembrane 202 may vibrate differently during use of the piezoelectric speaker collectively formed by themembrane 202 and thepiezoelectric device 106. In some embodiments, the top-electrode and bottom-electrode barrier segments pad barrier layer 102 are connected outside thecross-sectional view 500B ofFIG. 5B . - In
FIG. 5C , thetop electrode 116 and thepiezoelectric layer 114 form common sidewalls and share a common width less than that of thebottom electrode 112. - In
FIG. 5D , the bottom andtop electrodes piezoelectric layer 114 form common sidewalls and share a common width. Further, agetter layer 502 separates thepiezoelectric device 106 from thesubstrate dielectric layer 110 and has a greater width than the common width. Thegetter layer 502 is configured to absorb hydrogen ions and/or other errant materials, whereby thegetter layer 502 may prevent hydrogen ions and/or other errant materials from diffusing to and accumulating in thepiezoelectric layer 114. As described above, hydrogen ions that accumulate in thepiezoelectric layer 114 may induce delamination and breakdown of thepiezoelectric layer 114, whereby thepiezoelectric device 106 may fail. Accordingly, by absorbing hydrogen ions, thegetter layer 502 may prevent device failure. - In some embodiments, the
substrate dielectric layer 110 comprises hydrogen ions, which are absorbed by thegetter layer 502 to prevent the hydrogen ions from diffusing to thepiezoelectric layer 114. For example, thesubstrate dielectric layer 110 may comprise hydrogen ions in embodiments in which thesubstrate dielectric layer 110 is tetraethyl orthosilicate (TEOS) silicon oxide (e.g., TEOS-SiO2), silane silicon oxide (e.g., SiH4—SiO2), some other suitable oxide or dielectric, or any combination of the foregoing. In some embodiments, thegetter layer 502 is or comprises titanium, barium, cerium, lanthanum, aluminum, magnesium, thorium, or some other suitable conductive getter material for hydrogen ions and/or other errant materials. - In
FIG. 5E , thebottom electrode 112 and thegetter layer 502 share a first common width and form first common sidewalls. Further, thepiezoelectric layer 114 and thetop electrode 116 share a second common width less than the first common width and form second common sidewalls laterally offset from the first common sidewalls. - In
FIG. 5F , thegetter layer 502 described with regard toFIG. 5D separates thetop electrode 116 from thedevice barrier layer 118 instead of separating thebottom electrode 112 from thesubstrate dielectric layer 110. Further, thegetter layer 502 forms common sidewalls with thetop electrode 116 and thepiezoelectric layer 114 and shares a common width with thetop electrode 116 and thepiezoelectric layer 114. - In
FIG. 5G , a top-electrode getter layer 502 t is atop thetop electrode 116, whereas a bottom-electrode getter layer 502 b is on an underside of thebottom electrode 112. The bottom-electrode getter layer 502 b and the bottom-electrode getter layer 502 b are respectively as their counterparts are described with regard toFIGS. 5E and 5F . - With reference to
FIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B, a series of views of some embodiments of a method for forming an IC chip in which a barrier layer caps a pad of a piezoelectric device is provided. Figures labeled with a suffix of “A” or with no suffix correspond to cross-sectional views, and figures labeled with a suffix of “B” correspond to top layout views for like numbered figured with a suffix of “A”. The cross-sectional views of figures labeled with a suffix “A” may, for example, be taken along line A or B (whichever is present) in the top layout views of corresponding figures labeled with a suffix of “B”. The method is illustrated forming an IC chip according to the embodiments ofFIGS. 2 and 3 . However, the method may alternatively be employed to form an IC chip according to other suitable embodiments. - As illustrated by a
cross-sectional view 600 ofFIG. 6 , asubstrate dielectric layer 110 is deposited over asubstrate 108. Thesubstrate 108 is an SOI substrate and comprises a lower semiconductor layer 108 l, aninsulator layer 108 i overlying the lower semiconductor layer 108 l, and anupper semiconductor layer 108 u overlying theinsulator layer 108 i. In alternative embodiments, thesubstrate 108 is a bulk semiconductor substrate or some other suitable type of semiconductor substrate. In some embodiments, thesubstrate dielectric layer 110 and theinsulator layer 108 i are a same material. In other embodiments, thesubstrate dielectric layer 110 and theinsulator layer 108 i are different materials. - Also illustrated by the
cross-sectional view 600 ofFIG. 6 , adevice film 602 is deposited over thesubstrate dielectric layer 110 and comprises a bottom-electrode layer 1121, apiezoelectric layer 114 overlying the bottom-electrode layer 1121, and a top-electrode layer 1161 overlying thepiezoelectric layer 114. In some embodiments, the bottom-electrode layer 1121 and the top-electrode layer 1161 are a same material. In other embodiments, the bottom-electrode layer 1121 and the top-electrode layer 1161 are different materials. - As illustrated by a
cross-sectional view 700A ofFIG. 7A , and atop layout view 700B ofFIG. 7B , the device film 602 (see, e.g.,FIG. 6 ) is patterned to form apiezoelectric device 106 having a ring-shaped top geometry (see, e.g.,FIG. 7B ) and extending in a closed path around acentral area 702. In alternative embodiments, thepiezoelectric device 106 may have some other suitable top geometry extending in a closed path around thecentral area 702. Thepiezoelectric device 106 comprises abottom electrode 112, a patterned portion of the piezoelectric layer 114 (hereafter referred to more simply as the piezoelectric layer 114) overlying thebottom electrode 112, and atop electrode 116 overlying thepiezoelectric layer 114. - The
bottom electrode 112 corresponds to a patterned portion of the bottom-electrode layer 1121 (see, e.g.,FIG. 6 ), whereas thetop electrode 116 corresponds to a patterned portion of the top-electrode layer 1161. Thepiezoelectric layer 114 has a lesser width than thebottom electrode 112, and further has sidewalls laterally offset from sidewalls of thebottom electrode 112. Thetop electrode 116 has a lesser width than thepiezoelectric layer 114, and further has sidewalls laterally offset from sidewalls of thepiezoelectric layer 114. - In some embodiments, a process for performing the patterning does not employ hydrogen ions and/or other errant materials that may diffuse to and induce failure of the
piezoelectric layer 114. Hydrogen ions that diffuse to thepiezoelectric layer 114 may accumulate in thepiezoelectric layer 114 and induce delamination and breakdown of thepiezoelectric layer 114, whereby thepiezoelectric device 106 may fail. - In some embodiments, a process for performing the patterning comprises: 1) performing a first photolithography/etching process into the top-
electrode layer 1161 using a first mask to form thetop electrode 116; 2) performing a second photolithography/etching process into thepiezoelectric layer 114 using a second mask; and 3) performing a third photolithography/etching process into the bottom-electrode layer 1121 using a third mask to form thebottom electrode 112. In alternative embodiments, some other suitable process is performed for the patterning. For example, the top-electrode layer 1161 and thepiezoelectric layer 114 may be patterned together using a common photolithography/etching process and a common mask, whereas the bottom-electrode layer 1121 may be patterned using a different photolithography/etching process and a different mask. As example, the top-electrode layer 1161, thepiezoelectric layer 114, and the bottom-electrode layer 1121 may be patterned together using a common photolithography/etching process and a common mask. The two alternative examples use fewer masks and hence reduce manufacturing costs. - As illustrated by a
cross-sectional view 800 ofFIG. 8 , adevice barrier layer 118 is deposited covering thepiezoelectric device 106 and thesubstrate dielectric layer 110. Thedevice barrier layer 118 is configured to block hydrogen and/or other suitable errant materials from diffusing to thepiezoelectric layer 114 from over thedevice barrier layer 118. By blocking diffusion of errant materials (e.g., hydrogen ions) to thepiezoelectric layer 114, thepad barrier layer 102 may prevent failure of thepiezoelectric device 106. - In some embodiments, the
device barrier layer 118 is a metal oxide or some other suitable material. The metal oxide may, for example, be or comprise aluminum oxide (e.g., Al2O3), titanium oxide (e.g., TiO2), iron oxide (e.g., Fe2O3), zirconium oxide (e.g., ZrO2), zinc oxide (e.g., ZnO), copper oxide (e.g., CuO), tantalum oxide (e.g., Ta2O5), some other suitable type of metal oxide, or any combination of the foregoing. - The
device barrier layer 118 is deposited by a process that does not expose thepiezoelectric layer 114 to hydrogen ions and/or other suitable errant materials. For example, thedevice barrier layer 118 may be deposited by physical vapor deposition (PVD), atomic layer deposition (ALD), or some other suitable deposition process(es). - As illustrated by a
cross-sectional view 900A ofFIG. 9A , and atop layout view 900B ofFIG. 9B , thedevice barrier layer 118 is patterned to remove a central portion of thedevice barrier layer 118 surrounded by thepiezoelectric device 106. Further, the patterning removes a peripheral portion of thedevice barrier layer 118 surrounding thepiezoelectric device 106. At completion of the patterning, thepiezoelectric device 106 remains covered (e.g., completely covered) by thedevice barrier layer 118. The patterning may, for example, be performed by a photolithography/etching process or by some other suitable process. - As illustrated by a
cross-sectional view 1000 ofFIG. 10 , adevice dielectric layer 120 is deposited covering thedevice barrier layer 118. Thedevice dielectric layer 120 may, for example, be or comprise TEOS oxide and/or some other suitable dielectric(s). In some embodiments, thedevice dielectric layer 120 is deposited by a deposition process that exposes thedevice barrier layer 118 to hydrogen ions and/or other errant materials. In such embodiments, thedevice barrier layer 118 blocks the errant material (e.g., the hydrogen ions) from accumulating in thepiezoelectric layer 114. As described above, this may, for example, prevent failure of thepiezoelectric device 106. - As illustrated by the
cross-sectional view 1100 ofFIG. 11 , thedevice dielectric layer 120 and thedevice barrier layer 118 are patterned to form a pair of viaopenings 1102. The viaopenings 1102 are individual to and respectively expose thetop electrode 116 and thebottom electrode 112. In some embodiments, the patterning is performed by a process that does employ hydrogen ions and/or other errant materials that may diffuse to and induce failure of thepiezoelectric layer 114. In some embodiments, the patterning is performed by a photolithography/etching process or by some other suitable patterning process. - As illustrated by a
cross-sectional view 1200A ofFIG. 12A , and atop layout view 1200B ofFIG. 12B , a pair ofpads 104 and a pair ofvias 122 are formed. Thepads 104 have first ends individual to and respectively overlying the via openings 1102 (see, e.g.,FIG. 11 ). Further, thepads 104 have second ends distal from the first ends and laterally offset from the first ends. Thevias 122 are individual to and respectively fill the viaopenings 1102. Further, thevias 122 extend respectively from thepads 104 respectively to thetop electrode 116 and thebottom electrode 112. In some embodiments, thepads 104 and thevias 122 are part of a common layer. In other embodiments, thepads 104 are part of a first layer, whereas thevias 122 are part of a second layer that is different than the first layer. - In some embodiments, the
pads 104 and thevias 122 are formed by a process that does not employ hydrogen ions and/or other errant materials that may diffuse to and induce failure of thepiezoelectric layer 114. In some embodiments, a process for forming thepads 104 and thevias 122 comprises: 1) depositing a conductive layer covering thedevice dielectric layer 120 and filling the viaopenings 1102; and 2) performing a photolithography/etching process to pattern the conductive layer into thepads 104. In alternative embodiments, some other suitable process is performed for forming thepads 104 and thevias 122. - As illustrated by a
cross-sectional view 1300 ofFIG. 13 , apad barrier layer 102 is deposited covering thepads 104 and thedevice dielectric layer 120. Thepad barrier layer 102 is configured to block hydrogen ions and/or other suitable errant materials from diffusing to thepiezoelectric device 106 from over thepad 104. - Absent the
pad barrier layer 102, hydrogen ions from hydrogen-containing semiconductor manufacturing processes performed after forming thepad 104 may diffuse to thepiezoelectric layer 114 along thevias 122. As described above, hydrogen ions that diffuse to thepiezoelectric layer 114 may accumulate in thepiezoelectric layer 114 and induce delamination and breakdown of thepiezoelectric layer 114, whereby thepiezoelectric device 106 may fail. Therefore, by blocking diffusion of hydrogen ions to thepiezoelectric layer 114, thedevice barrier layer 118 may prevent delamination and breakdown of thepiezoelectric layer 114. This, in turn, may prevent failure of thepiezoelectric device 106. - The
pad barrier layer 102 is deposited by a process that does not expose thepads 104 to hydrogen ions and/or other suitable errant materials. For example, thepad barrier layer 102 may be deposited by PVD, ALD, or some other suitable deposition process(es). - In some embodiments, a thickness Tpb of the
pad barrier layer 102 is about 200-600 angstroms, about 200-400 angstroms, about 400-600 angstroms, or some other suitable value. If the thickness Tpb is too small (e.g., less than about 200 angstroms), thepad barrier layer 102 may be unable to block diffusion of hydrogen ions and/or other errant materials through thepad barrier layer 102. If the thickness Tpb is too large (e.g., more than about 600 angstroms), material may be wasted and high topographical variation at thepad barrier layer 102 may present processing challenges that reduce manufacturing yields. - In some embodiments, the
pad barrier layer 102 is crystalline and/or has a density greater than about 2 g/cm3, 2.6 g/cm3, 5 g/cm3, or some other suitable value. It has been appreciated that such a density may block diffusion of hydrogen ions and/or other errant materials through thepad barrier layer 102. In some embodiments, thepad barrier layer 102 is a metal oxide or some other suitable material. The metal oxide may, for example, be or comprise aluminum oxide (e.g., Al2O3), titanium oxide (e.g., TiO2), iron oxide (e.g., Fe2O3), zirconium oxide (e.g., ZrO2), zinc oxide (e.g., ZnO), copper oxide (e.g., CuO), tantalum oxide (e.g., Ta2O5), some other suitable type of metal oxide, or any combination of the foregoing. - In some embodiments, the
pad barrier layer 102 is a same material as thedevice barrier layer 118. In other embodiments, thepad barrier layer 102 is a different material than thedevice barrier layer 118. In some embodiments, thedevice barrier layer 118 is crystalline and/or has a density greater than about 2 g/cm3, 2.6 g/cm3, 5 g/cm3, or some other suitable value. In some embodiments, the density is the same as that of thepad barrier layer 102. - As illustrated by a
cross-sectional view 1400A ofFIG. 14A , and atop layout view 1400B ofFIG. 14B , thepad barrier layer 102 is patterned to segment thepad barrier layer 102. A bottom-electrode barrier segment 102 b overlies and is localized to thepad 104 at thebottom electrode 112, and a top-electrode barrier segment 102 t overlies and is localized to thepad 104 at thetop electrode 116. At completion of the patterning, thepads 104 remain covered (e.g., completely covered) by thepad barrier layer 102. The patterning may, for example, be performed by a photolithography/etching process or by some other suitable process. - As illustrated by a
cross-sectional view 1500A ofFIG. 15A , and atop layout view 1500B ofFIG. 15B , the device and substratedielectric layers upper semiconductor layer 108 u are patterned to form a plurality ofslits 1502 at thecentral area 702 surrounded by thepiezoelectric device 106. Theslits 1502 overlie theinsulator layer 108 i, and extend through the device and substratedielectric layers upper semiconductor layer 108 u to theinsulator layer 108 i. Further, theslits 1502 are circumferentially spaced around, and extend laterally into, a circular region of theupper semiconductor layer 108 u. The circular region is surrounded by the piezoelectric device (e.g., when viewed top down) and is hereafter referred to as amembrane 202. - In some embodiments, a process for forming the
slits 1502 comprises: 1) forming a photoresist mask over thepad barrier layer 102 and thedevice dielectric layer 120; 2) performing a dry etch into the device and substratedielectric layers upper semiconductor layer 108 u with the mask in place; and 3) performing plasma ashing to remove the photoresist mask. In alternative embodiments, some other suitable process is performed to form theslits 1502. In some embodiments, the dry etching and/or the plasma ashing expose the expose the IC chip being formed to hydrogen ions and/or other errant materials. In such embodiments, thepad barrier layer 102 and thedevice barrier layer 118 block the errant material (e.g., the hydrogen ions) from diffusing to and accumulating in thepiezoelectric layer 114. As described above, this may, for example, prevent failure of thepiezoelectric device 106. - As illustrated by a
cross-sectional view 1600 ofFIG. 16 , apassivation layer 124 is deposited covering thepad barrier layer 102, thedevice dielectric layer 120, and themembrane 202, and further lining theslits 1502. In some embodiments, the depositing exposes the IC chip being formed to hydrogen ions and/or other errant materials. In such embodiments, thepad barrier layer 102 and thedevice barrier layer 118 block the errant material (e.g., the hydrogen ions) from diffusing to and accumulating in thepiezoelectric layer 114. - As illustrated by a
cross-sectional view 1700A ofFIG. 17A , and atop layout view 1700B ofFIG. 17B , thepassivation layer 124 and thepad barrier layer 102 are patterned to formpad openings 126 at ends of thepads 104 distal from thevias 122. Further, the patterning clears thepassivation layer 124 from themembrane 202 and theslits 1502. In alternative embodiments, thepassivation layer 124 persists at themembrane 202 and the slits 1502 (e.g., to form the IC chip according to the embodiments ofFIG. 5A ). - In some embodiments, a process for performing the patterning comprises: 1) forming a photoresist mask over the
passivation layer 124; 2) performing a dry etch into thepassivation layer 124 and thepad barrier layer 102 with the mask in place; and 3) performing plasma ashing to remove the photoresist mask. In alternative embodiments, some other suitable process is performed to form thepad openings 126. - In some embodiments, the dry etching and/or the plasma ashing expose the IC chip being formed to hydrogen ions and/or other errant materials. Because the
pad openings 126 extend through thepad barrier layer 102, hydrogen ions and/or other errant materials may extend through thepad barrier layer 102. However, because thepad openings 126 are at ends of thepads 104 distal from thevias 122, the diffusion path from thepad openings 126 to thepiezoelectric layer 114 may be long. Hence, the likelihood of hydrogen ions and/or other errant materials diffusing to thepiezoelectric layer 114 is low. - As illustrated by a
cross-sectional view 1800 ofFIG. 18 , asacrificial layer 1802 is deposited covering the IC chip being formed and filling the pad openings 126 (see, e.g.,FIGS. 17A and 17B ) and the slits 1502 (see, e.g.,FIGS. 17A and 17B ). In some embodiments, thesacrificial layer 1802 is silicon oxide and/or some other suitable dielectric(s). - As illustrated by a
cross-sectional view 1900 ofFIG. 19 , the IC chip ofFIG. 18 is flipped vertically and thesubstrate 108 is patterned to form asound opening 204 overlying and exposing themembrane 202. The patterning may, for example, be performed by a photolithography/etching process or by some other suitable process. - As illustrated by a
cross-sectional view 2000A ofFIG. 20A , and atop layout view 2000B ofFIG. 20B , the IC chip is flipped vertically. Further, thesacrificial layer 1802 is removed. The removal may, for example, be performed by an etch using an etchant having a high selectivity for thesacrificial layer 1802 relative to underlying structure (e.g., thepassivation layer 124 and the membrane 202). - By removing the
sacrificial layer 1802, thesound opening 204 incorporates the slits 1502 (see, e.g.,FIGS. 17A and 17B ) and hence extends through themembrane 202. Further, themembrane 202 is released and may move in thesound opening 204. In response to application of a voltage across thepiezoelectric layer 114, from thetop electrode 116 to thebottom electrode 112, thepiezoelectric device 106 may vibrate. The vibrations may move to themembrane 202 and cause themembrane 202 to vibrate, which generates sound waves in thesound opening 204. Accordingly, thepiezoelectric device 106 and themembrane 202 coordinate to form a piezoelectric speaker. - While
FIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B are described with reference to a method, it will be appreciated that the structures shown in these figures are not limited to the method but rather may stand alone separate of the method. WhileFIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. - With reference to
FIG. 21 , a block diagram 2100 of some embodiments of the method ofFIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B is provided. - At 2102, a device film is formed overlying a substrate, wherein the device film comprises a bottom-electrode layer, a piezoelectric layer over the bottom-electrode layer, and a top-electrode layer over the piezoelectric layer. See, for example,
FIG. 6 . - At 2104, the device film is patterned to form a piezoelectric device extending in a closed path around a central area. See, for example,
FIGS. 7A and 7B . - At 2106, a device barrier layer is formed covering the piezoelectric device, wherein the device barrier layer is configured to block diffusion of hydrogen ions and/or other errant materials. See, for example,
FIGS. 8, 9A, and 9B . - At 2108, a device dielectric layer is deposited covering the device barrier layer and the piezoelectric device, wherein the device dielectric layer blocks hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer while depositing the device dielectric layer. See, for example,
FIG. 10 . - At 2110, a pair of pads is formed, wherein the pads have first ends respectively overlying and connected to a top electrode of the piezoelectric device and a bottom electrode of the piezoelectric device respectively by vias, and wherein the pads have second ends distal from the first ends and laterally offset from the piezoelectric device. See, for example,
FIGS. 11, 12A , and 12B. - At 2112, a pad barrier layer is formed covering the pads, wherein the pad barrier layer is configured to block diffusion of hydrogen ions and/or other errant materials. See, for example,
FIGS. 13, 14A, and 14B . - At 2114, the substrate is patterned to form a plurality of slits at the central area, wherein the slits are circumferentially spaced around a membrane of the substrate at the central area, and wherein the pad barrier layer blocks hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer while forming the slits. See, for example,
FIGS. 15A and 15B . - At 2116, a passivation layer is deposited covering the pad barrier layer, wherein the pad barrier layer blocks hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer while depositing the passivation layer. See, for example,
FIG. 16 . - At 2118, the pad barrier layer and the passivation layer are patterned to form pad openings respectively exposing the second ends of the pads, wherein hydrogen ions and/or other errant materials used while forming the pad openings are unlikely to diffuse to the piezoelectric layer through the pad openings because the second ends are distal from the vias. See, for example,
FIGS. 17A and 17B . - At 2120, a sound opening is formed extending through the substrate to the membrane on an opposite side of the substrate as the piezoelectric device, wherein the forming of the sound opening releases the membrane to allow the membrane to move. See, for example,
FIGS. 18, 19, 20A, and 20B . - While the block diagram 2100 of
FIG. 21 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. - With reference to
FIG. 22 , across-sectional view 2200 of some first alternative embodiments of the method ofFIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B is provided in which thepassivation layer 124 persists on themembrane 202 at completion of the method. - As illustrated by the
cross-sectional view 2200 ofFIG. 22 , the acts described with regard toFIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, and 16 are performed. Thereafter, the patterning described with regard toFIGS. 17A and 17B is performed, except that the patterning does not clear thepassivation layer 124 from themembrane 202 and theslits 1502. Rather, the patterning formsopenings 2202 extending through thepassivation layer 124 respectively at theslits 1502 to expose theinsulator layer 108 i. Thereafter, the acts described with regard toFIGS. 18, 19, 20A, and 20B are performed. The resulting IC chip may, for example, be as illustrated atFIG. 5A . - With reference to
FIGS. 23-25 , a series of cross-sectional views 2300-2500 of some second alternative embodiments of the method ofFIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B is provided in which thepad barrier layer 102 and thepassivation layer 124 are on themembrane 202 at completion of the method. - As illustrated by the
cross-sectional view 2300 ofFIG. 23 , the acts described with regard toFIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, and 12B are performed. Further, the acts described with regard toFIGS. 15A and 15B are thereafter performed. Notably, the acts described with regard toFIGS. 13, 14A, and 14B are not performed. Hence, thepad barrier layer 102 is not formed before the patterning to form theslits 1502. - As illustrated by the
cross-sectional view 2400 ofFIG. 24 , the acts described with regard toFIGS. 13 and 16 are sequentially formed to respectively deposit thepad barrier layer 102 and thepassivation layer 124. Hence, thepad barrier layer 102 and thepassivation layer 124 are deposited after the patterning to form theslits 1502. - As illustrated by the
cross-sectional view 2500 ofFIG. 25 , the patterning described with regard toFIGS. 17A and 17B is performed, except that the patterning does not clear thepad barrier layer 102 and thepassivation layer 124 from themembrane 202 and theslits 1502. Rather, the patterning formsopenings 2502 extending through thepassivation layer 124 and thepad barrier layer 102 respectively at theslits 1502 to expose theinsulator layer 108 i. Thereafter, the acts described with regard toFIGS. 18, 19, 20A, and 20B are performed. The resulting IC chip may, for example, be as illustrated atFIG. 5B . - With reference to
FIGS. 26 and 27 , a series ofcross-sectional views FIGS. 6, 7A, 7B, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A , and 20B is provided in which agetter layer 502 is on a bottom of thebottom electrode 112. - As illustrated by the
cross-sectional view 2600 ofFIG. 26 , the acts described with regard toFIG. 6 are performed, except that agetter layer 502 is deposited between the depositing of thesubstrate dielectric layer 110 and the depositing of thedevice film 602. Thegetter layer 502 is configured to absorb hydrogen ions and/or other errant materials, whereby thegetter layer 502 may prevent hydrogen ions and/or other errant materials from accumulating in thepiezoelectric layer 114. Further, thegetter layer 502 is conductive and may, for example, be or comprise titanium, barium, cerium, lanthanum, aluminum, magnesium, thorium, or some other suitable conductive getter material for hydrogen ions and/or other errant materials. - As illustrated by the
cross-sectional view 2700 ofFIG. 27 , the acts described with regard toFIGS. 7A and 7B are performed, with a few exceptions. The bottom-electrode layer 1121 (see, e.g.,FIG. 26 ), thepiezoelectric layer 114, and the top-electrode layer 1161 (see, e.g.,FIG. 26 ) are patterned with a common pattern. Further, thegetter layer 502 is patterned with a pattern different than the common pattern. In some embodiments, the common pattern is the same as that illustrated for thepiezoelectric layer 114 inFIGS. 7A and 7B and/or the different pattern is the same as that illustrated for the bottom-electrode layer 1121 inFIGS. 7A and 7B . Thereafter, the acts described with regard toFIGS. 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14A, 14B, 15A, 15B, 16, 17A, 17B, 18, 19, 20A, and 20B are performed. The resulting IC chip may, for example, be as illustrated atFIG. 5D . - In some embodiments, the present disclosure provides an IC chip including: a substrate; a piezoelectric device overlying the substrate; a pad overlying the piezoelectric device; a via extending from the pad to the piezoelectric device; and a barrier layer overlying the pad; wherein the barrier layer is configured to block hydrogen ions from diffusing through the barrier layer, from over the barrier layer to the piezoelectric device. In some embodiments, the barrier layer includes aluminum oxide, titanium oxide, iron oxide, zirconium oxide, zinc oxide, copper oxide, or tantalum oxide. In some embodiments, the barrier layer has a density in excess of about 2 grams per cubic centimeter. In some embodiments, the IC chip further includes a dielectric layer between the pad and the piezoelectric device, wherein the via extends through the dielectric layer, and wherein a rate of diffusion of hydrogen ions through the dielectric layer is more than a rate of diffusion of hydrogen ions through the barrier layer. In some embodiments, the IC chip further includes a second barrier layer between the pad and the piezoelectric device, wherein the via extends through the second barrier layer, and wherein the second barrier layer is configured to block hydrogen ions from diffusing through the second barrier layer, from over the second barrier layer to the piezoelectric device. In some embodiments, the IC chip further includes: a second pad including a first end overlying the piezoelectric device; and a second via extending from the second pad to the piezoelectric device, wherein the barrier layer overlies and is level with the second pad. In some embodiments, the IC chip further includes a getter layer on an underside of the piezoelectric device and configured to getter hydrogen ions.
- In some embodiments, the present disclosure provides another IC chip including: a substrate; a piezoelectric structure over the substrate, wherein the piezoelectric structure includes a bottom electrode, a piezoelectric layer overlying the bottom electrode, and a top electrode overlying the piezoelectric layer; a first hydrogen-barrier layer overlying the piezoelectric structure; a pad having a first end and a second end, wherein the first end overlies the first hydrogen-barrier layer and the piezoelectric structure and is electrically coupled to the top or bottom electrode, and wherein the second end is level with the piezoelectric structure; and a second hydrogen-barrier layer overlying the pad and the piezoelectric structure. In some embodiments, the second hydrogen-barrier layer is a metal oxide. In some embodiments, the first hydrogen-barrier layer extends along individual sidewalls respectively of the bottom electrode, the top electrode, and the piezoelectric layer. In some embodiments, the first and second hydrogen-barrier layers share a common density. In some embodiments, the substrate includes a moveable membrane at an opening extending through the substrate, wherein the piezoelectric structure extends in a closed path around the moveable membrane. In some embodiments, the second hydrogen-barrier layer is on a sidewall of the moveable membrane. In some embodiments, the IC chip further includes a passivation layer overlying the second hydrogen-barrier layer, wherein the passivation layer is on a sidewall of the moveable membrane, and wherein the second hydrogen-barrier layer is spaced from the moveable membrane. In some embodiments, the pad is elongated continuously from the first end of the pad to the second end of the pad, wherein the second end is distal from the first end and is laterally offset from the piezoelectric structure. In some embodiments, the IC chip further includes a passivation layer overlying the second hydrogen-barrier layer, wherein the passivation layer and the second hydrogen-barrier layer form a common sidewall at the second end of the pad, and wherein the second end is distal from and laterally offset from the first end and the piezoelectric structure.
- In some embodiments, the present disclosure provides a method including: forming a piezoelectric structure over a substrate and including a first electrode, a piezoelectric layer overlying the first electrode, and a second electrode overlying the piezoelectric layer; depositing a dielectric layer covering the piezoelectric structure; forming a pad and a via, wherein the pad overlies the dielectric layer, and wherein the via extends through the dielectric layer, from the pad to the to the piezoelectric structure; depositing a barrier layer covering the pad and the piezoelectric structure; and performing a semiconductor manufacturing process after the depositing of the barrier layer, wherein the semiconductor manufacturing process exposes the barrier layer to ions, and wherein the barrier layer blocks the ions from passing through the barrier layer. In some embodiments, the depositing of the barrier layer is performed without a source of hydrogen, and wherein the ions are hydrogen ions. In some embodiments, the piezoelectric structure extends laterally in a closed path around a central area, wherein the semiconductor manufacturing process includes patterning the substrate to form a plurality of slits at the central area. In some embodiments, the semiconductor manufacturing process includes: depositing a passivation layer covering the barrier layer; and patterning the passivation layer and the barrier layer to form a pad opening exposing an end of the pad laterally offset from the piezoelectric structure.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. An integrated circuit (IC) chip comprising:
a substrate;
a piezoelectric device overlying the substrate;
a pad overlying the piezoelectric device;
a via extending from the pad to the piezoelectric device; and
a barrier layer overlying the pad;
wherein the barrier layer is configured to block hydrogen ions from diffusing through the barrier layer, from over the barrier layer to the piezoelectric device.
2. The IC chip according to claim 1 , wherein the barrier layer comprises aluminum oxide, titanium oxide, iron oxide, zirconium oxide, zinc oxide, copper oxide, or tantalum oxide.
3. The IC chip according to claim 1 , wherein the barrier layer has a density in excess of about 2 grams per cubic centimeter.
4. The IC chip according to claim 1 , further comprising:
a dielectric layer between the pad and the piezoelectric device, wherein the via extends through the dielectric layer, and wherein a rate of diffusion of hydrogen ions through the dielectric layer is more than a rate of diffusion of hydrogen ions through the barrier layer.
5. The IC chip according to claim 1 , further comprising:
a second barrier layer between the pad and the piezoelectric device, wherein the via extends through the second barrier layer, and wherein the second barrier layer is configured to block hydrogen ions from diffusing through the second barrier layer, from over the second barrier layer to the piezoelectric device.
6. The IC chip according to claim 1 , further comprising:
a second pad comprising a first end overlying the piezoelectric device; and
a second via extending from the second pad to the piezoelectric device, wherein the barrier layer overlies and is level with the second pad.
7. The IC chip according to claim 1 , further comprising:
a getter layer on an underside of the piezoelectric device and configured to getter hydrogen ions.
8. An integrated circuit (IC) chip comprising:
a substrate;
a piezoelectric structure over the substrate, wherein the piezoelectric structure comprises a bottom electrode, a piezoelectric layer overlying the bottom electrode, and a top electrode overlying the piezoelectric layer;
a first hydrogen-barrier layer overlying the piezoelectric structure;
a pad having a first end and a second end, wherein the first end overlies the first hydrogen-barrier layer and the piezoelectric structure and is electrically coupled to the top or bottom electrode, and wherein the second end is level with the piezoelectric structure; and
a second hydrogen-barrier layer overlying the pad and the piezoelectric structure.
9. The IC chip according to claim 8 , wherein the second hydrogen-barrier layer is a metal oxide.
10. The IC chip according to claim 8 , wherein the first hydrogen-barrier layer extends along individual sidewalls respectively of the bottom electrode, the top electrode, and the piezoelectric layer.
11. The IC chip according to claim 8 , wherein the first and second hydrogen-barrier layers share a common density.
12. The IC chip according to claim 8 , wherein the substrate comprises a moveable membrane at an opening extending through the substrate, and wherein the piezoelectric structure extends in a closed path around the moveable membrane.
13. The IC chip according to claim 12 , wherein the second hydrogen-barrier layer is on a sidewall of the moveable membrane.
14. The IC chip according to claim 12 , further comprising:
a passivation layer overlying the second hydrogen-barrier layer, wherein the passivation layer is on a sidewall of the moveable membrane, and wherein the second hydrogen-barrier layer is spaced from the moveable membrane.
15. The IC chip according to claim 8 , wherein the pad is elongated continuously from the first end of the pad to the second end of the pad, and wherein the second end is distal from the first end and is laterally offset from the piezoelectric structure.
16. The IC chip according to claim 8 , further comprising:
a passivation layer overlying the second hydrogen-barrier layer, wherein the passivation layer and the second hydrogen-barrier layer form a common sidewall at the second end of the pad, and wherein the second end is distal from and laterally offset from the first end and the piezoelectric structure.
17. A method comprising:
forming a piezoelectric structure over a substrate and comprising a first electrode, a piezoelectric layer overlying the first electrode, and a second electrode overlying the piezoelectric layer;
depositing a dielectric layer covering the piezoelectric structure;
forming a pad and a via, wherein the pad overlies the dielectric layer, and wherein the via extends through the dielectric layer, from the pad to the piezoelectric structure;
depositing a barrier layer covering the pad and the piezoelectric structure; and
performing a semiconductor manufacturing process after the depositing of the barrier layer, wherein the semiconductor manufacturing process exposes the barrier layer to ions, and wherein the barrier layer blocks the ions from passing through the barrier layer.
18. The method according to claim 17 , wherein the depositing of the barrier layer is performed without a source of hydrogen, and wherein the ions are hydrogen ions.
19. The method according to claim 17 , wherein the piezoelectric structure extends laterally in a closed path around a central area, and wherein the semiconductor manufacturing process comprises patterning the substrate to form a plurality of slits at the central area.
20. The method according to claim 17 , wherein the semiconductor manufacturing process comprises:
depositing a passivation layer covering the barrier layer; and
patterning the passivation layer and the barrier layer to form a pad opening exposing an end of the pad laterally offset from the piezoelectric structure.
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US17/577,715 US20230037116A1 (en) | 2021-08-02 | 2022-01-18 | Barrier layer on a piezoelectric-device pad |
DE102022101983.7A DE102022101983A1 (en) | 2021-08-02 | 2022-01-28 | BARRIER LAYER ON A PIEZOELECTRIC DEVICE PAD |
KR1020220031586A KR20230019765A (en) | 2021-08-02 | 2022-03-14 | Barrier layer on a piezoelectric-device pad |
TW111109792A TWI801168B (en) | 2021-08-02 | 2022-03-17 | Integrated circuit chip and method for forming the same |
CN202210430608.2A CN115701768A (en) | 2021-08-02 | 2022-04-22 | Integrated circuit chip and forming method thereof |
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US202163228275P | 2021-08-02 | 2021-08-02 | |
US17/577,715 US20230037116A1 (en) | 2021-08-02 | 2022-01-18 | Barrier layer on a piezoelectric-device pad |
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KR (1) | KR20230019765A (en) |
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Citations (2)
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US6347147B1 (en) * | 1998-12-07 | 2002-02-12 | The United States Of America As Represented By The Sceretary Of The Navy | High noise suppression microphone |
US20210043721A1 (en) * | 2019-08-05 | 2021-02-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Titanium layer as getter layer for hydrogen in a mim device |
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US9029963B2 (en) * | 2012-09-25 | 2015-05-12 | Sand 9, Inc. | MEMS microphone |
US10115883B2 (en) * | 2014-09-04 | 2018-10-30 | Rohm Co., Ltd. | Device using a piezoelectric element and method for manufacturing the same |
US10861929B2 (en) * | 2018-06-27 | 2020-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electronic device including a capacitor |
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2022
- 2022-01-18 US US17/577,715 patent/US20230037116A1/en active Pending
- 2022-01-28 DE DE102022101983.7A patent/DE102022101983A1/en active Pending
- 2022-03-14 KR KR1020220031586A patent/KR20230019765A/en unknown
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US6347147B1 (en) * | 1998-12-07 | 2002-02-12 | The United States Of America As Represented By The Sceretary Of The Navy | High noise suppression microphone |
US20210043721A1 (en) * | 2019-08-05 | 2021-02-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Titanium layer as getter layer for hydrogen in a mim device |
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TWI801168B (en) | 2023-05-01 |
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