US20230013358A1 - Semiconductor device and method of fabricating the same - Google Patents
Semiconductor device and method of fabricating the same Download PDFInfo
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- US20230013358A1 US20230013358A1 US17/951,058 US202217951058A US2023013358A1 US 20230013358 A1 US20230013358 A1 US 20230013358A1 US 202217951058 A US202217951058 A US 202217951058A US 2023013358 A1 US2023013358 A1 US 2023013358A1
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/2003—Nitride compounds
Definitions
- the present invention relates to the field of semiconductor devices, and more particularly to high electron mobility transistors and fabricating method thereof.
- group III-V semiconductor compounds may be used to form various integrated circuit (IC) devices, such as high power field-effect transistors (FETs), high frequency transistors, or high electron mobility transistors (HEMTs).
- FETs high power field-effect transistors
- HEMTs high electron mobility transistors
- a HEMT is a field effect transistor having a two dimensional electron gas (2-DEG) layer close to a junction between two materials with different band gaps (i.e., a heterojunction) .
- the 2-DEG layer is used as the transistor channel instead of a doped region, as is generally the case for metal oxide semiconductor field effect transistors (MOSFETs) .
- MOSFETs metal oxide semiconductor field effect transistors
- HEMTs have a number of attractive properties such as high electron mobility and the ability to transmit signals at high frequencies.
- VBR breakdown voltage
- a semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer.
- the semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer.
- the gate electrode is disposed on the semiconductor barrier layer.
- the first electrode is disposed at one side of the gate electrode.
- the first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer.
- the dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.
- a method of fabricating a semiconductor device includes the following steps: providing a substrate; forming a semiconductor channel layer on the substrate; forming a semiconductor barrier layer on the semiconductor channel layer; performing an etching process to expose a portion of the semiconductor channel layer; forming a dielectric layer covering the semiconductor barrier layer and the exposed semiconductor channel layer; and forming a first electrode after forming the dielectric layer, where the first electrode comprises a body portion and a vertical extension portion, the body portion is electrically connected to the semiconductor barrier layer, and a bottom surface of the vertical extension portion is lower than a top surface of the semiconductor channel layer.
- FIG. 1 is a schematic cross-sectional diagram of a semiconductor device according to one embodiment of the present disclosure.
- FIG. 2 is a schematic cross-sectional diagram of a semiconductor device with a vertical extension portion according to a modified embodiment of the present disclosure
- FIG. 3 is a schematic cross-sectional diagram of a semiconductor device with a vertical extension portion according to a modified embodiment of the present disclosure.
- FIG. 4 is a schematic cross-sectional diagram of a semiconductor device with a conformal dielectric layer according to a modified embodiment of the present disclosure.
- FIG. 5 is a schematic cross-sectional diagram of a structure after a recess is formed in a semiconductor buffer layer according to one embodiment of the present disclosure.
- FIG. 6 is a schematic cross-sectional diagram of a structure after forming a dielectric layer according to one embodiment of the present disclosure.
- FIG. 7 is a schematic cross-sectional diagram of the structure after etching part of the dielectric layer according to one embodiment of the present disclosure.
- FIG. 8 is a schematic cross-sectional diagram of a structure after forming a conductive electrode according to one embodiment of the present disclosure.
- FIG. 9 is a schematic cross-sectional diagram of the structure after exposing the gate capping layer according to one embodiment of the present disclosure.
- FIG. 10 is a diagram showing the relationship between the electric field and the position in the semiconductor devices according to embodiments and comparative embodiments of the present disclosure.
- FIG. 11 is a diagram showing the relationship between the electric field and the position in the semiconductor devices of the embodiments and comparative embodiments of the present disclosure.
- FIG. 12 shows electrical performance regarding IDS-VDS and breakdown voltage (VBR) of a semiconductor device according to one embodiment of the present disclosure.
- first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer and/or section from another region, layer and/or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the teachings of the embodiments.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- the present invention is directed to a high electron mobility transistor (HEMT) and method for fabricating the same, where HEMTs may be used as power switching transistors for voltage converter applications.
- group III-V HEMTs feature low on-state resistances and low switching losses due to wide bandgap properties.
- a “group III-V semiconductor” is referred to as a compound semiconductor that includes at least one group III element and at least one group V element, where group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and group V element may be nitrogen (N) , phosphorous (P), arsenic (As), or antimony (Sb).
- the group III-V semiconductor may refer to, but not limited to, gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), and the like, or a combination thereof.
- GaN gallium nitride
- InP indium phosphide
- AlAs aluminum arsenide
- GaAs gallium arsenide
- AlGaN aluminum gallium nitride
- InAlGaN indium aluminum gallium nitride
- InGaN indium gallium nitride
- a “III-nitride semiconductor” is referred to as a compound semiconductor that includes nitrogen and at least one group III element, such as, but not limited to, GaN, aluminum nitride (AlN), indium nitride (InN), AlGaN, InGaN, InAlGaN, and the like, or a combination thereof, but is not limited thereto.
- group III element such as, but not limited to, GaN, aluminum nitride (AlN), indium nitride (InN), AlGaN, InGaN, InAlGaN, and the like, or a combination thereof, but is not limited thereto.
- FIG. 1 is a schematic cross-sectional diagram of a semiconductor device according to one embodiment of the present disclosure.
- a semiconductor device 100 - 1 includes at least a substrate 102 , a semiconductor channel layer 106 , a semiconductor barrier layer 108 , a gate electrode 112 , and a dielectric layer 116 .
- the semiconductor channel layer 106 is disposed on the substrate 102
- the semiconductor barrier layer 108 is disposed on the semiconductor channel layer 106
- the gate electrode 112 is disposed on the semiconductor barrier layer 108 .
- the first electrode 120 is disposed at one side of the gate electrode 112 , where the first electrode 120 may include a body portion 122 , a vertical extension portion 126 , and an optional horizontal extension portion 124 .
- the body portion 122 may be electrically connected to the vertical extension portion 126 and the horizontal extension portion 124 , and the body portion 122 may be electrically connected to the semiconductor barrier layer 106 .
- a bottom surface 126 B of the vertical extension portion 126 is lower than a top surface 106 T of the semiconductor channel layer 106 .
- the dielectric layer 116 may be disposed between the vertical extension portion 126 and the semiconductor channel layer 106 .
- the semiconductor device 100 - 1 may further include a buffer layer 104 , a gate capping layer 110 and a second electrode 130 .
- the semiconductor buffer layer 104 may be disposed between the substrate 102 and the semiconductor channel layer 106 , which may be used to reduce leakage current between the substrate 102 and the semiconductor channel layer 106 , or to reduce stress accumulation or lattice mismatch between the substrate 102 and the semiconductor channel layer 106 .
- the gate capping layer 110 may be disposed between the semiconductor barrier layer 108 and the gate electrode 112 .
- the first electrode 120 and the second electrode 130 may be disposed at both sides of the gate electrode 112 , respectively.
- a two-dimensional electron gas (2-DEG) may be generated at the junction of the semiconductor channel layer 106 and the semiconductor barrier layer 108 .
- the substrate 102 may be a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, but not limited thereto.
- the stacked layers on the substrate 102 may be formed by performing any suitable processes, such as molecular-beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), or other suitable methods, to thereby form the buffer layer 104 , the semiconductor channel layer 106 , the semiconductor barrier layer 108 , and the gate capping layer 110 disposed on the substrate 102 .
- MBE molecular-beam epitaxy
- MOCVD metal organic chemical vapor deposition
- HVPE hydride vapor phase epitaxy
- ALD atomic layer deposition
- the buffer layer 104 may include a plurality of sub-semiconductor layers (i.e., multiple layers) and the overall resistance of the buffer layer 104 may be higher than the resistance of other layers on the substrate 102 . Specifically, the ratio of some elements, such as metal element, of the buffer layer 104 may be changed gradually along a direction from the substrate 102 to the semiconductor channel layer 106 .
- the buffer layer 104 may be graded aluminum gallium nitride (AlxGa(1-x)N) where there is a continuous or stepwise decrease in the x ratio from 0.9 to 0.15 along the direction from the substrate 102 to the semiconductor channel layer 106 .
- the buffer layer 104 may have a superlattice structure.
- the semiconductor channel layer 106 may include one or more layers of group III-V semiconductor composed of GaN, AlGaN, InGaN, or InAlGaN, but not limited thereto.
- the semiconductor channel layer 106 may also be one or more layers of doped group III-V semiconductor, such as p-type III-V semiconductor.
- the dopants of which may be C, Fe, Mg or Zn, but not limited thereto.
- the thickness of the semiconductor channel layer 106 may range from 50 nm to 350 nm, such as 200 nm, but not limited thereto.
- the semiconductor barrier layer 108 may include one or more layers of group III-V semiconductor with the composition different from that of the group III-V semiconductor of the semiconductor channel layer 106 .
- the semiconductor barrier layer 108 may include AlN, AlyGa(1-y)N (0 ⁇ y ⁇ 1), or a combination thereof.
- the semiconductor channel layer 106 may be an undoped GaN layer, and the semiconductor barrier layer 108 may be an inherent n-type AlGaN layer.
- a thin layer with high electron mobility also called a two-dimensional electron gas, may be accumulated near the heterojunction between the semiconductor channel layer 106 and the semiconductor barrier layer 108 due to the piezoelectric effect.
- the dielectric layer 116 may be disposed along the surface of the semiconductor barrier layer 108 and between the vertical extension portion 126 of the first electrode 120 and the semiconductor channel layer 106 , or further between the horizontal extension portion 124 of the first electrode 120 and the semiconductor barrier layer 108 .
- the thicknesses of the dielectric layers 116 disposed in different regions may be the same or different.
- the dielectric layer 116 between the vertical extension portion 126 and the semiconductor channel layer 106 may have a thickness T 3
- the dielectric layer 116 between the horizontal extension portion 124 and the semiconductor barrier layer 108 may have a thickness T 4 .
- the thickness T 3 and the thickness T 4 may be each slightly thinner than the thickness T 1 of semiconductor barrier layer 108 , and the thickness T 3 and the thickness T 4 may be the same or different.
- the dielectric layer 116 may directly contact the semiconductor channel layer 106 and the vertical extension portion 126 of the first electrode 122 .
- the dielectric layer 116 may cover the sidewall and the bottom surface 126 B of the vertical extension portion 126 , and the thickness T 3 of the dielectric layer 116 may be less than the vertical length Lv of the vertical extension portion 126 .
- the composition of the dielectric layer 116 may include dielectric material, such as a high dielectric constant (high-k) material with a dielectric constant greater than 4.
- the material of the high-k dielectric may be selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST), or a combination thereof.
- the gate capping layer 110 may include one or more layers of group III-V semiconductor with the composition different from that of the group III-V semiconductor of the semiconductor barrier layer 108 , such as p-type III-V semiconductor.
- group III-V semiconductor the dopants of which may be C, Fe, Mg or Zn, but not limited thereto.
- the gate capping layer 110 may be a p-type GaN layer.
- the body portion 122 of the first electrode 120 may be in direct contact with and electrically connected to the semiconductor barrier layer 106 .
- the bottom surface 122 B of the body portion 122 may be level with or deeper than the top surface 106 T of the semiconductor channel layer 106 .
- the vertical extension portion 126 of the first electrode 120 may extend downward from the bottom surface 122 B of the body portion 122 , so that the bottom surface 126 B of the vertical extension portion 126 may be lower than the top surface 104 T of the semiconductor buffer layer 104 .
- the vertical length Lv of the vertical extension portion 126 may be 0.5 ⁇ m to 3 ⁇ m, but not limited thereto.
- the dielectric layer 116 is disposed between the vertical extension portion 126 and the underlying layers (i.e., the semiconductor channel layer 106 and the semiconductor buffer layer 104 ), it is possible to prevent current from flowing from the vertical extension portion 126 into the semiconductor channel layer 106 or the semiconductor buffer layer 104 .
- the horizontal extension portion 124 of the first electrode 120 may extend from one side of the body portion 122 toward the gate electrode 112 .
- the horizontal length Lh of the horizontal extension portion 124 may be 0.5 ⁇ m to 3 ⁇ m, but not limited thereto.
- the dielectric layer 116 is disposed between the horizontal extension portion 124 and the semiconductor barrier layer 108 , it is possible to prevent current from flowing from the horizontal extension portion 124 into the semiconductor barrier layer 108 .
- the first electrode 120 , the second electrode 130 , and the gate electrode 112 may be single-layer or multi-layer structures, and their compositions can include low-resistance semiconductors, metals, or alloys, such as Al, Cu, W, Au, Pt, Ti, and polysilicon, but not limited thereto.
- the first electrode 120 and the second electrode 130 may form ohmic contact with the underlying semiconductor channel layer 106 .
- the first electrode 120 when operating the semiconductor device 100 - 1 , the first electrode 120 may be, for example, a drain electrode electrically connected to an external high voltage (e.g., 10V-200V), while the second electrode 130 may be, for example, a source electrode electrically connected to an external voltage of lower voltage (e.g., 0V), but is not limited thereto.
- the first electrode 120 may be, for example, a source electrode
- the second electrode 130 may be, for example, a drain electrode.
- the semiconductor device 100 - 1 may further include an interlayer dielectric layer covering the first electrode 120 , the second electrode 130 , and the gate electrode 112 .
- contact holes may be provided in the interlayer dielectric layer for accommodating contact plugs respectively. The contact plugs may be electrically connected to the first electrode 120 , the second electrode 130 , and the gate electrode 112 , respectively.
- the present invention may further include other modifications about semiconductor devices.
- the description below is mainly focused on differences among these embodiments.
- the present invention may repeat reference numerals and/or letters in the various modifications and variations. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- FIG. 2 is a schematic cross-sectional diagram of a semiconductor device with a vertical extension portion according to a modified embodiment of the present disclosure.
- the structure of the semiconductor device 100 - 2 is similar to that of the semiconductor device 100 - 1 shown in the embodiment of FIG. 1 , with the main difference in that the first electrode 120 does not include a horizontal extension portion.
- FIG. 3 is a schematic cross-sectional diagram of a semiconductor device with a vertical extension portion according to a modified embodiment of the present disclosure.
- the structure of the semiconductor device 100 - 3 is similar to that of the semiconductor device 100 - 1 shown in the embodiment of FIG. 1 . the main difference between these two embodiments is that the second electrode 130 of the semiconductor device 100 - 3 includes a body portion 132 and a vertical extension portion 136 .
- the body portion 132 may be electrically connected to the semiconductor barrier layer 106 .
- the vertical extension portion 136 may extend downward from the bottom surface of the body portion 132 , so that the bottom surface 136 B of the vertical extension portion 136 may be lower than the top surface 104 T of the semiconductor buffer layer 104 .
- the vertical length Lv of the vertical extension portion 126 may be 0.5 ⁇ m to 3 ⁇ m, but not limited thereto.
- the dielectric layer 116 is disposed between the vertical extension portion 136 and the underlying layers (i.e., the semiconductor channel layer 106 and the semiconductor buffer layer 104 ), it is possible to prevent current from flowing from the vertical extension portion 126 into the semiconductor channel layer 106 or the semiconductor buffer layer 104 .
- one of the first electrode 120 and the second electrode 130 may be a source electrode
- the other one of the first electrode 120 and the second electrode 130 may be a drain electrode, so either the source electrode or the drain electrode may have vertical extension portions 126 , 136 .
- FIG. 4 is a schematic cross-sectional diagram of a semiconductor device with a conformal dielectric layer according to a modified embodiment of the present disclosure.
- the structure of the semiconductor device 100 - 4 is similar to that of the semiconductor device 100 - 1 shown in the embodiment of FIG. 1 , the main difference is that the body portion 132 , the horizontal extension portion 124 and the vertical extension portion 126 of the first electrode 120 conformally cover the dielectric layer 116 and the semiconductor barrier layer 106 .
- FIG. 5 is a schematic cross-sectional diagram of a structure after a recess is formed in a semiconductor buffer layer according to one embodiment of the present disclosure.
- a semiconductor buffer layer 104 , a semiconductor channel layer 106 , a semiconductor barrier layer 108 , and a gate capping layer 110 may be sequentially formed on a substrate 102 to obtain a semiconductor structure 100 - 5 .
- a patterned mask 140 may be formed, and the semiconductor barrier layer 108 , the semiconductor channel layer 106 , and the semiconductor buffer layer 104 exposed from the patterned mask 140 may be etched to form a recess 142 .
- the recess 142 may expose the sidewall 108 S of the semiconductor barrier layer 108 , the sidewall 106 S of the semiconductor channel layer 106 , and the vertical surface 105 S and the horizontal surface 105 T of the semiconductor buffer layer 104 . Subsequently, the patterned mask 140 may be further removed.
- FIG. 6 is a schematic cross-sectional diagram of a structure after forming a dielectric layer according to one embodiment of the present disclosure.
- a dielectric layer 144 may be deposited to conformally cover the gate capping layer 110 , the sidewall 108 S of the semiconductor barrier layer 108 , the sidewall 106 S of the semiconductor channel layer 106 , and the vertical surface 105 S and the horizontal surface 105 T of the semiconductor buffer layer 104 .
- the dielectric layer 144 may be further etched to thereby form the dielectric layer 116 disclosed in the above embodiment.
- FIG. 7 is a schematic cross-sectional diagram of the structure after etching part of the dielectric layer according to one embodiment of the present disclosure.
- a patterned mask 150 may be formed, and the dielectric layer 144 and the semiconductor barrier layer 108 exposed from the patterned mask 150 may be etched to thereby form dielectric layers 144 A, 144 B separated from one another as well as recesses 152 at both sides of the gate capping layer 110 .
- the bottom surface of the recess 152 may be level with or lower than the top surface of the semiconductor channel layer 106 .
- FIG. 8 is a schematic cross-sectional diagram of a structure after forming a conductive electrode according to one embodiment of the present disclosure.
- a conductive layer filling up the recess 152 may be formed by appropriate deposition and etching processes.
- a patterned mask 160 having an opening pattern 162 may be formed, and the conductive layer exposed from the opening pattern 162 may be etched to thereby form separated conductive layers, e.g., a first electrode 120 and a second electrode 130 .
- the first electrode 120 includes a body portion 122 , a horizontal extension portion 124 , and a vertical extension portion 126 .
- FIG. 9 is a schematic cross-sectional diagram of the structure after exposing the gate capping layer according to one embodiment of the present disclosure.
- a patterned mask 170 having an opening pattern 172 may be formed, and the dielectric layer 144 A exposed from the opening pattern 172 may be etched to thereby expose the gate capping layer 110 .
- a gate electrode 112 may be formed on the gate capping layer 110 by a suitable deposition and etching process to thereby obtain the semiconductor device shown in FIG. 1 .
- the horizontal extension portion 124 or the vertical extension portion 126 of the first electrode 120 may be regarded as a field plate for controlling or adjusting the distribution of electric field in the semiconductor barrier layer 108 and the semiconductor channel layer 106 .
- VBR breakdown voltage
- FIG. 10 is a diagram showing the relationship between the electric field and the position in the semiconductor devices according to embodiments and comparative embodiments of the present disclosure.
- the vertical length Lv of the vertical extension portion 126 in the semiconductor device 100 - 1 shown in FIG. 1 may be adjusted, and the impact ionization rate at various depths of the semiconductor device may be measured.
- the “position” shown in the vertical axis of FIG. 10 refers to a “vertical position”, and the position of “0” substantially corresponds to the top surface of the first electrode of the semiconductor device. When the value in the vertical axis becomes larger, the corresponding position becomes more close to the substrate. Referring to FIG.
- the horizontal length of the horizontal extension electrode may be fixed at 1.5 ⁇ m
- the vertical length Lv of the vertical extension portion of the first electrode 120 may be set at 1 ⁇ m, 1.5 ⁇ m, and 2 ⁇ m, respectively.
- the corresponding curves are represented by the curve C 1 , the curve C 2 , and the curve C 3 , respectively.
- the peak position of the electric field may become deeper.
- the peak intensity of the electric field may be the smallest (corresponding to curve C 2 ). Therefore, by providing the vertical extension portion, the distribution of electric field may be modified so as to reduce the peak value of the electric field. Accordingly, the semiconductor device is less likely to generate impact ionization.
- FIG. 11 is a diagram showing the relationship between the electric field and the position in the semiconductor devices of the embodiments and comparative embodiments of the present disclosure.
- the horizontal length Lh of the horizontal extension portion 124 in the semiconductor device 100 - 1 shown in FIG. 1 may be adjusted, and the impact ionization rate at various positions of the semiconductor device may be measured.
- the “position” in the horizontal axis in FIG. 11 refers to a “horizontal position”, and the position of “0” substantially corresponds to one side of the second electrode of the semiconductor device. When the value in the horizontal axis becomes larger, the corresponding position becomes more close to the first electrode. Referring to FIG.
- the vertical length of the vertical extension electrode may be fixed at 1.5 ⁇ m, and the horizontal length Lh of the horizontal extension portion of the first electrode may be set at 1 ⁇ m, 1.5 ⁇ m and 2 ⁇ m.
- the horizontal length Lh of the horizontal extension portion of the first electrode may be set at 1 ⁇ m, 1.5 ⁇ m and 2 ⁇ m.
- the horizontal length Lh of the horizontal extension portion of the first electrode may be set at 1 ⁇ m, 1.5 ⁇ m and 2 ⁇ m.
- the horizontal length of the horizontal extension portion when the horizontal length of the horizontal extension portion is longer, the peak position of the electric field becomes closer to the gate electrode, and the peak intensity of the electric field may be reduced.
- the length of the horizontal extension portion is 1.5 ⁇ m, the distribution of electric field shows double peaks, and each peak intensity ( ⁇ 1E11) is less than any peak intensity of other embodiments. Therefore, by providing the horizontal extension portion, the distribution of electric field may be modified so as to reduce the peak value of the electric field. Accordingly, the semiconductor device is less likely to
- FIG. 12 shows electrical performance regarding IDS-VDS and breakdown voltage (VBR) of a semiconductor device according to one embodiment of the present disclosure.
- Comparative example 1 corresponds to a conventional semiconductor device, and the first electrode of the comparative example 1 does not include a horizontal extension portion and a vertical extension portion.
- Embodiment 1 corresponds to the semiconductor device 100 - 1 of FIG. 1 but without a vertical extension portion;
- Embodiment 2 corresponds to the semiconductor device 100 - 1 of FIG. 1 but without a horizontal extension;
- Embodiment 2 corresponds to the semiconductor device 100 - 1 shown in FIG. 1 including a vertical extension portion and a horizontal extension portion.
- VDS breakdown voltage
- the breakdown voltages of the devices of the embodiments 1 to 3 are 221V, 259V and 388V, respectively, which are higher than the breakdown voltage, which is 127V, of the device of comparative embodiment 1.
Abstract
Description
- This application is a division of U.S. Application No. 17/148,539, filed on Jan. 13, 2021. The content of the application is incorporated herein by reference.
- The present invention relates to the field of semiconductor devices, and more particularly to high electron mobility transistors and fabricating method thereof.
- In semiconductor technology, group III-V semiconductor compounds may be used to form various integrated circuit (IC) devices, such as high power field-effect transistors (FETs), high frequency transistors, or high electron mobility transistors (HEMTs). A HEMT is a field effect transistor having a two dimensional electron gas (2-DEG) layer close to a junction between two materials with different band gaps (i.e., a heterojunction) . The 2-DEG layer is used as the transistor channel instead of a doped region, as is generally the case for metal oxide semiconductor field effect transistors (MOSFETs) . Compared with MOSFETs, HEMTs have a number of attractive properties such as high electron mobility and the ability to transmit signals at high frequencies. However, there is still a need to improve the breakdown voltage (VBR) of conventional HEMTs in order to meet the requirements of the industry.
- In view of this, it is necessary to provide an improved high electron mobility transistor so as to meet the requirements of the industry.
- According to one embodiment of the present invention, a semiconductor device is disclosed and includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.
- According to one embodiment of the present disclosure, a method of fabricating a semiconductor device is disclosed and includes the following steps: providing a substrate; forming a semiconductor channel layer on the substrate; forming a semiconductor barrier layer on the semiconductor channel layer; performing an etching process to expose a portion of the semiconductor channel layer; forming a dielectric layer covering the semiconductor barrier layer and the exposed semiconductor channel layer; and forming a first electrode after forming the dielectric layer, where the first electrode comprises a body portion and a vertical extension portion, the body portion is electrically connected to the semiconductor barrier layer, and a bottom surface of the vertical extension portion is lower than a top surface of the semiconductor channel layer.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
- Aspects of the present invention are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 is a schematic cross-sectional diagram of a semiconductor device according to one embodiment of the present disclosure. -
FIG. 2 is a schematic cross-sectional diagram of a semiconductor device with a vertical extension portion according to a modified embodiment of the present disclosure -
FIG. 3 is a schematic cross-sectional diagram of a semiconductor device with a vertical extension portion according to a modified embodiment of the present disclosure. -
FIG. 4 is a schematic cross-sectional diagram of a semiconductor device with a conformal dielectric layer according to a modified embodiment of the present disclosure. -
FIG. 5 is a schematic cross-sectional diagram of a structure after a recess is formed in a semiconductor buffer layer according to one embodiment of the present disclosure. -
FIG. 6 is a schematic cross-sectional diagram of a structure after forming a dielectric layer according to one embodiment of the present disclosure. -
FIG. 7 is a schematic cross-sectional diagram of the structure after etching part of the dielectric layer according to one embodiment of the present disclosure. -
FIG. 8 is a schematic cross-sectional diagram of a structure after forming a conductive electrode according to one embodiment of the present disclosure. -
FIG. 9 is a schematic cross-sectional diagram of the structure after exposing the gate capping layer according to one embodiment of the present disclosure. -
FIG. 10 is a diagram showing the relationship between the electric field and the position in the semiconductor devices according to embodiments and comparative embodiments of the present disclosure. -
FIG. 11 is a diagram showing the relationship between the electric field and the position in the semiconductor devices of the embodiments and comparative embodiments of the present disclosure. -
FIG. 12 shows electrical performance regarding IDS-VDS and breakdown voltage (VBR) of a semiconductor device according to one embodiment of the present disclosure. - The present disclosure may be understood by reference to the following detailed description, taken in conjunction with the drawings as described below. It is noted that, for purposes of illustrative clarity and being easily understood by the readers, various drawings of this disclosure show a portion of the device, and certain elements in various drawings may not be drawn to scale. In addition, the number and dimension of each device shown in drawings are only illustrative and are not intended to limit the scope of the present disclosure.
- Certain terms are used throughout the following description to refer to particular components. One of ordinary skill in the art would understand that electronic equipment manufacturers may use different technical terms to describe the same component. The present disclosure does not intend to distinguish between the components that differ only in name but not function. In the following description and claims, the terms “include”, “comprise”, and “have” are used in an open-ended fashion and thus should be interpreted as the meaning of “include, but not limited to”.
- It is understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer and/or section from another region, layer and/or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the teachings of the embodiments.
- When an element or layer is referred to as being “coupled to” or “connected to” another element or layer, it may be directly coupled or connected to the other element or layer, or intervening elements or layers may be presented. In contrast, when an element is referred to as being “directly coupled to” or “directly connected to” another element or layer, there are no intervening elements or layers presented.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the term “about” generally means in 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term “about” means in an acceptable standard error of the mean when considered by one of ordinary skill in the art. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that may vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.
- It should be noted that the technical features in different embodiments described in the following may be replaced, recombined, or mixed with one another to constitute another embodiment without departing from the spirit of the present invention.
- The present invention is directed to a high electron mobility transistor (HEMT) and method for fabricating the same, where HEMTs may be used as power switching transistors for voltage converter applications. Compared to silicon power transistors, group III-V HEMTs feature low on-state resistances and low switching losses due to wide bandgap properties. In the present disclosure, a “group III-V semiconductor” is referred to as a compound semiconductor that includes at least one group III element and at least one group V element, where group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and group V element may be nitrogen (N) , phosphorous (P), arsenic (As), or antimony (Sb). Furthermore, the group III-V semiconductor may refer to, but not limited to, gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), and the like, or a combination thereof. In a similar manner, a “III-nitride semiconductor” is referred to as a compound semiconductor that includes nitrogen and at least one group III element, such as, but not limited to, GaN, aluminum nitride (AlN), indium nitride (InN), AlGaN, InGaN, InAlGaN, and the like, or a combination thereof, but is not limited thereto.
-
FIG. 1 is a schematic cross-sectional diagram of a semiconductor device according to one embodiment of the present disclosure. Referring toFIG. 1 , a semiconductor device 100-1 includes at least asubstrate 102, asemiconductor channel layer 106, asemiconductor barrier layer 108, agate electrode 112, and adielectric layer 116. Thesemiconductor channel layer 106 is disposed on thesubstrate 102, thesemiconductor barrier layer 108 is disposed on thesemiconductor channel layer 106, and thegate electrode 112 is disposed on thesemiconductor barrier layer 108. Thefirst electrode 120 is disposed at one side of thegate electrode 112, where thefirst electrode 120 may include abody portion 122, avertical extension portion 126, and an optionalhorizontal extension portion 124. Thebody portion 122 may be electrically connected to thevertical extension portion 126 and thehorizontal extension portion 124, and thebody portion 122 may be electrically connected to thesemiconductor barrier layer 106. Abottom surface 126B of thevertical extension portion 126 is lower than atop surface 106T of thesemiconductor channel layer 106. In addition, thedielectric layer 116 may be disposed between thevertical extension portion 126 and thesemiconductor channel layer 106. Furthermore, according to one embodiment of the present disclosure, the semiconductor device 100-1 may further include abuffer layer 104, agate capping layer 110 and asecond electrode 130. Thesemiconductor buffer layer 104 may be disposed between thesubstrate 102 and thesemiconductor channel layer 106, which may be used to reduce leakage current between thesubstrate 102 and thesemiconductor channel layer 106, or to reduce stress accumulation or lattice mismatch between thesubstrate 102 and thesemiconductor channel layer 106. Thegate capping layer 110 may be disposed between thesemiconductor barrier layer 108 and thegate electrode 112. Thefirst electrode 120 and thesecond electrode 130 may be disposed at both sides of thegate electrode 112, respectively. According to one embodiment of the present disclosure, a two-dimensional electron gas (2-DEG) may be generated at the junction of thesemiconductor channel layer 106 and thesemiconductor barrier layer 108. By providing thegate capping layer 110, two-dimensional electron gas will not be generated in the correspondingsemiconductor channel layer 106 below it, so that part of the two-dimensional electron gas will be cut off. - According to one embodiment of the present invention, the
substrate 102 may be a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, but not limited thereto. The stacked layers on thesubstrate 102 may be formed by performing any suitable processes, such as molecular-beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), or other suitable methods, to thereby form thebuffer layer 104, thesemiconductor channel layer 106, thesemiconductor barrier layer 108, and thegate capping layer 110 disposed on thesubstrate 102. - The
buffer layer 104 may include a plurality of sub-semiconductor layers (i.e., multiple layers) and the overall resistance of thebuffer layer 104 may be higher than the resistance of other layers on thesubstrate 102. Specifically, the ratio of some elements, such as metal element, of thebuffer layer 104 may be changed gradually along a direction from thesubstrate 102 to thesemiconductor channel layer 106. For example, for a case where thesubstrate 102 and thesemiconductor channel layer 106 are a silicon substrate and a GaN layer, respectively, thebuffer layer 104 may be graded aluminum gallium nitride (AlxGa(1-x)N) where there is a continuous or stepwise decrease in the x ratio from 0.9 to 0.15 along the direction from thesubstrate 102 to thesemiconductor channel layer 106. In another case, thebuffer layer 104 may have a superlattice structure. - The
semiconductor channel layer 106 may include one or more layers of group III-V semiconductor composed of GaN, AlGaN, InGaN, or InAlGaN, but not limited thereto. In addition, thesemiconductor channel layer 106 may also be one or more layers of doped group III-V semiconductor, such as p-type III-V semiconductor. For the p-type group III-V semiconductor, the dopants of which may be C, Fe, Mg or Zn, but not limited thereto. The thickness of thesemiconductor channel layer 106 may range from 50 nm to 350 nm, such as 200 nm, but not limited thereto. - The
semiconductor barrier layer 108 may include one or more layers of group III-V semiconductor with the composition different from that of the group III-V semiconductor of thesemiconductor channel layer 106. For example, thesemiconductor barrier layer 108 may include AlN, AlyGa(1-y)N (0<y<1), or a combination thereof. In accordance with one embodiment, thesemiconductor channel layer 106 may be an undoped GaN layer, and thesemiconductor barrier layer 108 may be an inherent n-type AlGaN layer. Since there is a bandgap discontinuity between thesemiconductor channel layer 106 and thesemiconductor barrier layer 108, by stacking thesemiconductor channel layer 106 and thesemiconductor barrier layer 108 on each other (and vice versa), a thin layer with high electron mobility, also called a two-dimensional electron gas, may be accumulated near the heterojunction between thesemiconductor channel layer 106 and thesemiconductor barrier layer 108 due to the piezoelectric effect. - The
dielectric layer 116, or passivation layer, may be disposed along the surface of thesemiconductor barrier layer 108 and between thevertical extension portion 126 of thefirst electrode 120 and thesemiconductor channel layer 106, or further between thehorizontal extension portion 124 of thefirst electrode 120 and thesemiconductor barrier layer 108. The thicknesses of thedielectric layers 116 disposed in different regions may be the same or different. For example, thedielectric layer 116 between thevertical extension portion 126 and thesemiconductor channel layer 106 may have a thickness T3, while thedielectric layer 116 between thehorizontal extension portion 124 and thesemiconductor barrier layer 108 may have a thickness T4. The thickness T3 and the thickness T4 may be each slightly thinner than the thickness T1 ofsemiconductor barrier layer 108, and the thickness T3 and the thickness T4 may be the same or different. According to one embodiment of the present disclosure, thedielectric layer 116 may directly contact thesemiconductor channel layer 106 and thevertical extension portion 126 of thefirst electrode 122. Thedielectric layer 116 may cover the sidewall and thebottom surface 126B of thevertical extension portion 126, and the thickness T3 of thedielectric layer 116 may be less than the vertical length Lv of thevertical extension portion 126. The composition of thedielectric layer 116 may include dielectric material, such as a high dielectric constant (high-k) material with a dielectric constant greater than 4. The material of the high-k dielectric may be selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST), or a combination thereof. - The
gate capping layer 110 may include one or more layers of group III-V semiconductor with the composition different from that of the group III-V semiconductor of thesemiconductor barrier layer 108, such as p-type III-V semiconductor. For the p-type group III-V semiconductor, the dopants of which may be C, Fe, Mg or Zn, but not limited thereto. According to one embodiment of the present invention, thegate capping layer 110 may be a p-type GaN layer. - According to one embodiment of the present disclosure, the
body portion 122 of thefirst electrode 120 may be in direct contact with and electrically connected to thesemiconductor barrier layer 106. Thebottom surface 122B of thebody portion 122 may be level with or deeper than thetop surface 106T of thesemiconductor channel layer 106. Thevertical extension portion 126 of thefirst electrode 120 may extend downward from thebottom surface 122B of thebody portion 122, so that thebottom surface 126B of thevertical extension portion 126 may be lower than thetop surface 104T of thesemiconductor buffer layer 104. The vertical length Lv of thevertical extension portion 126 may be 0.5 µm to 3 µm, but not limited thereto. In addition, since thedielectric layer 116 is disposed between thevertical extension portion 126 and the underlying layers (i.e., thesemiconductor channel layer 106 and the semiconductor buffer layer 104), it is possible to prevent current from flowing from thevertical extension portion 126 into thesemiconductor channel layer 106 or thesemiconductor buffer layer 104. Thehorizontal extension portion 124 of thefirst electrode 120 may extend from one side of thebody portion 122 toward thegate electrode 112. The horizontal length Lh of thehorizontal extension portion 124 may be 0.5 µm to 3 µm, but not limited thereto. In addition, since thedielectric layer 116 is disposed between thehorizontal extension portion 124 and thesemiconductor barrier layer 108, it is possible to prevent current from flowing from thehorizontal extension portion 124 into thesemiconductor barrier layer 108. Thefirst electrode 120, thesecond electrode 130, and thegate electrode 112 may be single-layer or multi-layer structures, and their compositions can include low-resistance semiconductors, metals, or alloys, such as Al, Cu, W, Au, Pt, Ti, and polysilicon, but not limited thereto. In addition, thefirst electrode 120 and thesecond electrode 130 may form ohmic contact with the underlyingsemiconductor channel layer 106. - According to one embodiment, when operating the semiconductor device 100-1, the
first electrode 120 may be, for example, a drain electrode electrically connected to an external high voltage (e.g., 10V-200V), while thesecond electrode 130 may be, for example, a source electrode electrically connected to an external voltage of lower voltage (e.g., 0V), but is not limited thereto. According to one embodiment of the present disclosure, thefirst electrode 120 may be, for example, a source electrode, and thesecond electrode 130 may be, for example, a drain electrode. By applying appropriate bias voltages to thefirst electrode 120 and thesecond electrode 130, current can flow into or out of the semiconductor device 100-1. In addition, by applying an appropriate bias voltage to thegate electrode 112, the conductivity of the channel region below thegate electrode 112 may be adjusted, so that current can flow between thefirst electrode 120 and thesecond electrode 130. - In addition, the semiconductor device 100-1 may further include an interlayer dielectric layer covering the
first electrode 120, thesecond electrode 130, and thegate electrode 112. According to one embodiment of the present disclosure, contact holes may be provided in the interlayer dielectric layer for accommodating contact plugs respectively. The contact plugs may be electrically connected to thefirst electrode 120, thesecond electrode 130, and thegate electrode 112, respectively. - In addition to the above embodiments, the present invention may further include other modifications about semiconductor devices. For the sake of simplicity, the description below is mainly focused on differences among these embodiments. In addition, the present invention may repeat reference numerals and/or letters in the various modifications and variations. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
-
FIG. 2 is a schematic cross-sectional diagram of a semiconductor device with a vertical extension portion according to a modified embodiment of the present disclosure. Referring toFIG. 2 , the structure of the semiconductor device 100-2 is similar to that of the semiconductor device 100-1 shown in the embodiment ofFIG. 1 , with the main difference in that thefirst electrode 120 does not include a horizontal extension portion. -
FIG. 3 is a schematic cross-sectional diagram of a semiconductor device with a vertical extension portion according to a modified embodiment of the present disclosure. Referring toFIG. 3 , the structure of the semiconductor device 100-3 is similar to that of the semiconductor device 100-1 shown in the embodiment ofFIG. 1 . the main difference between these two embodiments is that thesecond electrode 130 of the semiconductor device 100-3 includes abody portion 132 and avertical extension portion 136. Thebody portion 132 may be electrically connected to thesemiconductor barrier layer 106. Thevertical extension portion 136 may extend downward from the bottom surface of thebody portion 132, so that thebottom surface 136B of thevertical extension portion 136 may be lower than thetop surface 104T of thesemiconductor buffer layer 104. The vertical length Lv of thevertical extension portion 126 may be 0.5 µm to 3 µm, but not limited thereto. In addition, since thedielectric layer 116 is disposed between thevertical extension portion 136 and the underlying layers (i.e., thesemiconductor channel layer 106 and the semiconductor buffer layer 104), it is possible to prevent current from flowing from thevertical extension portion 126 into thesemiconductor channel layer 106 or thesemiconductor buffer layer 104. According to the embodiment shown inFIG. 3 , one of thefirst electrode 120 and thesecond electrode 130 may be a source electrode, and the other one of thefirst electrode 120 and thesecond electrode 130 may be a drain electrode, so either the source electrode or the drain electrode may havevertical extension portions -
FIG. 4 is a schematic cross-sectional diagram of a semiconductor device with a conformal dielectric layer according to a modified embodiment of the present disclosure. Referring toFIG. 4 , the structure of the semiconductor device 100-4 is similar to that of the semiconductor device 100-1 shown in the embodiment ofFIG. 1 , the main difference is that thebody portion 132, thehorizontal extension portion 124 and thevertical extension portion 126 of thefirst electrode 120 conformally cover thedielectric layer 116 and thesemiconductor barrier layer 106. - In order to enable one of ordinary skill in the art to implement the present disclosure, some embodiments of a method of fabricating a semiconductor device is further described below.
-
FIG. 5 is a schematic cross-sectional diagram of a structure after a recess is formed in a semiconductor buffer layer according to one embodiment of the present disclosure. Referring toFIG. 5 , asemiconductor buffer layer 104, asemiconductor channel layer 106, asemiconductor barrier layer 108, and agate capping layer 110 may be sequentially formed on asubstrate 102 to obtain a semiconductor structure 100-5. Thereafter, apatterned mask 140 may be formed, and thesemiconductor barrier layer 108, thesemiconductor channel layer 106, and thesemiconductor buffer layer 104 exposed from the patternedmask 140 may be etched to form arecess 142. Therecess 142 may expose thesidewall 108S of thesemiconductor barrier layer 108, thesidewall 106S of thesemiconductor channel layer 106, and thevertical surface 105S and thehorizontal surface 105T of thesemiconductor buffer layer 104. Subsequently, the patternedmask 140 may be further removed. -
FIG. 6 is a schematic cross-sectional diagram of a structure after forming a dielectric layer according to one embodiment of the present disclosure. Referring toFIG. 6 , adielectric layer 144 may be deposited to conformally cover thegate capping layer 110, thesidewall 108S of thesemiconductor barrier layer 108, thesidewall 106S of thesemiconductor channel layer 106, and thevertical surface 105S and thehorizontal surface 105T of thesemiconductor buffer layer 104. In a subsequent process, thedielectric layer 144 may be further etched to thereby form thedielectric layer 116 disclosed in the above embodiment. -
FIG. 7 is a schematic cross-sectional diagram of the structure after etching part of the dielectric layer according to one embodiment of the present disclosure. Referring toFIG. 7 , apatterned mask 150 may be formed, and thedielectric layer 144 and thesemiconductor barrier layer 108 exposed from the patternedmask 150 may be etched to thereby formdielectric layers recesses 152 at both sides of thegate capping layer 110. The bottom surface of therecess 152 may be level with or lower than the top surface of thesemiconductor channel layer 106. -
FIG. 8 is a schematic cross-sectional diagram of a structure after forming a conductive electrode according to one embodiment of the present disclosure. After the process shown inFIG. 7 , a conductive layer filling up therecess 152 may be formed by appropriate deposition and etching processes. Thereafter, apatterned mask 160 having anopening pattern 162 may be formed, and the conductive layer exposed from theopening pattern 162 may be etched to thereby form separated conductive layers, e.g., afirst electrode 120 and asecond electrode 130. Thefirst electrode 120 includes abody portion 122, ahorizontal extension portion 124, and avertical extension portion 126. -
FIG. 9 is a schematic cross-sectional diagram of the structure after exposing the gate capping layer according to one embodiment of the present disclosure. Referring toFIG. 9 , apatterned mask 170 having anopening pattern 172 may be formed, and thedielectric layer 144A exposed from theopening pattern 172 may be etched to thereby expose thegate capping layer 110. Then, agate electrode 112 may be formed on thegate capping layer 110 by a suitable deposition and etching process to thereby obtain the semiconductor device shown inFIG. 1 . - The electrical performance of the semiconductor devices according to some embodiment of the disclosure are further described in the following paragraphs. According to the semiconductor devices 100-1, 100-2, 100-3, 100-4 disclosed in the above embodiments, the
horizontal extension portion 124 or thevertical extension portion 126 of thefirst electrode 120 may be regarded as a field plate for controlling or adjusting the distribution of electric field in thesemiconductor barrier layer 108 and thesemiconductor channel layer 106. By providing thevertical extension portion 126, the breakdown voltage (VBR) of each of the semiconductor devices 100-1, 100-2, 100-3, 100-4 is improved, thus improving the electrical performance of the semiconductor devices 100-1, 100-2, 100-3, 100-4. -
FIG. 10 is a diagram showing the relationship between the electric field and the position in the semiconductor devices according to embodiments and comparative embodiments of the present disclosure. According to one embodiment of the present disclosure, the vertical length Lv of thevertical extension portion 126 in the semiconductor device 100-1 shown inFIG. 1 may be adjusted, and the impact ionization rate at various depths of the semiconductor device may be measured. The “position” shown in the vertical axis ofFIG. 10 refers to a “vertical position”, and the position of “0” substantially corresponds to the top surface of the first electrode of the semiconductor device. When the value in the vertical axis becomes larger, the corresponding position becomes more close to the substrate. Referring toFIG. 10 , the horizontal length of the horizontal extension electrode may be fixed at 1.5 µm, and the vertical length Lv of the vertical extension portion of thefirst electrode 120 may be set at 1 µm, 1.5 µm, and 2 µm, respectively. The corresponding curves are represented by the curve C1, the curve C2, and the curve C3, respectively. Referring toFIG. 10 , when the vertical length of the vertical extension portion is longer, the peak position of the electric field may become deeper. However, when the bottom surface of the vertical extension portion is located in the semiconductor buffer layer and adjacent to the semiconductor channel layer, the peak intensity of the electric field may be the smallest (corresponding to curve C2). Therefore, by providing the vertical extension portion, the distribution of electric field may be modified so as to reduce the peak value of the electric field. Accordingly, the semiconductor device is less likely to generate impact ionization. -
FIG. 11 is a diagram showing the relationship between the electric field and the position in the semiconductor devices of the embodiments and comparative embodiments of the present disclosure. According to one embodiment of the present disclosure, the horizontal length Lh of thehorizontal extension portion 124 in the semiconductor device 100-1 shown inFIG. 1 may be adjusted, and the impact ionization rate at various positions of the semiconductor device may be measured. The “position” in the horizontal axis inFIG. 11 refers to a “horizontal position”, and the position of “0” substantially corresponds to one side of the second electrode of the semiconductor device. When the value in the horizontal axis becomes larger, the corresponding position becomes more close to the first electrode. Referring toFIG. 11 , the vertical length of the vertical extension electrode may be fixed at 1.5 µm, and the horizontal length Lh of the horizontal extension portion of the first electrode may be set at 1 µm, 1.5 µm and 2 µm. Referring toFIG. 11 , when the horizontal length of the horizontal extension portion is longer, the peak position of the electric field becomes closer to the gate electrode, and the peak intensity of the electric field may be reduced. However, when the length of the horizontal extension portion is 1.5 µm, the distribution of electric field shows double peaks, and each peak intensity (≦1E11) is less than any peak intensity of other embodiments. Therefore, by providing the horizontal extension portion, the distribution of electric field may be modified so as to reduce the peak value of the electric field. Accordingly, the semiconductor device is less likely to generate impact ionization. -
FIG. 12 shows electrical performance regarding IDS-VDS and breakdown voltage (VBR) of a semiconductor device according to one embodiment of the present disclosure. Comparative example 1 corresponds to a conventional semiconductor device, and the first electrode of the comparative example 1 does not include a horizontal extension portion and a vertical extension portion.Embodiment 1 corresponds to the semiconductor device 100-1 ofFIG. 1 but without a vertical extension portion;Embodiment 2 corresponds to the semiconductor device 100-1 ofFIG. 1 but without a horizontal extension;Embodiment 2 corresponds to the semiconductor device 100-1 shown inFIG. 1 including a vertical extension portion and a horizontal extension portion. Referring toFIG. 12 , when VDS is less than 100V,comparative embodiment 1 shows larger IDS thanembodiments 1 to 3 do. However, when VDS is greater than 100V, the semiconductor device ofcomparative embodiment 1 is more likely to be broken down. In contrast, the breakdown voltages of the devices of theembodiments 1 to 3 are 221V, 259V and 388V, respectively, which are higher than the breakdown voltage, which is 127V, of the device ofcomparative embodiment 1. - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (8)
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