US20230010043A1 - Multi-component digital predistortion - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3252—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using multiple parallel paths between input and output
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B1/0475—Circuits with means for limiting noise, interference or distortion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/36—Modulator circuits; Transmitter circuits
- H04L27/366—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator
- H04L27/367—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion
- H04L27/368—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion adaptive predistortion
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- H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
- H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
- H03F2201/3233—Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
Definitions
- This document pertains generally, but not by way of limitation, to integrated circuits and communication systems, and particularly, but not by way of limitation to digital predistortion for non-linear components, such as power amplifiers.
- the PA circuit may include a PA with a nonlinear gain characteristic, such as gain compression, that occurs at higher power output levels.
- the nonlinear gain characteristic can lead to signal distortion at the higher power levels.
- Digital predistortion (DPD) is used to compensate for amplifier nonlinearities.
- a DPD circuit applies predistortion to the amplifier input signal.
- the predistortion is determined using an inverse model of the amplifier's transfer characteristic, including distortion terms.
- a goal of the predistortion is to reduce distortion in the transmitted signal due to the PA gain nonlinearity.
- FIG. 1 is a diagram showing one example of an environment for implementing multi-component digital predistortion.
- FIG. 2 is a flowchart showing one example of a process flow that may be executed in the environment to train the DPD circuit.
- FIG. 3 is a diagram showing one example of an environment including a DPD circuit for driving multiple PAs for transmitting over cable media.
- FIG. 4 is a diagram showing one example of the environment of FIG. 3 configured to generate predistortion parameters.
- FIG. 5 is a diagram showing one example of the environment of FIG. 3 configured to generate tilt reference parameters for the tilt reference circuit.
- FIG. 6 is a flowchart showing one example of a process flow that may be executed in the environment, for example, in the arrangement shown in FIG. 5 , to generate tilt reference parameters reference parameters.
- FIG. 7 is a diagram showing one example of the environment of FIG. 3 configured to generate tilt equalizer parameters for the tilt equalizer circuit.
- FIG. 8 is a flowchart showing one example of a process flow that may be executed in the environment, for example, in the arrangement shown in FIG. 7 , to generate tilt equalizer parameters equalizer parameters.
- FIG. 9 shows four plots illustrating outputs of four PAs in the arrangement of the PAs with components trained as described with respect to FIGS. 3 - 8 .
- FIG. 10 is a diagram showing one example of an environment including an array of PAs and an array DPD circuit.
- FIG. 11 is a block diagram illustrating a computing device hardware architecture, within which a set or sequence of instructions can be executed to cause a machine to perform examples of any one of the methodologies discussed herein.
- Various examples described herein are directed to systems and methods implementing multi-component DPD where one DPD generates a pre-distorted signal that is provided to multiple PAs.
- one DPD generates a pre-distorted signal that is provided to multiple PAs.
- One example is in cable television and related cable communications where the same input signal (e.g., representing different television channel signals or other signals) may be transmitted to different customers across different coaxial and/or fiber trunk lines.
- Another example is in mobile telephony.
- Some mobile telephony technologies, such as 5 th Generation (5G) wireless systems utilize electromagnetic beamforming that involves transmitting the same input signal from different antennas at different power levels and phases.
- 5G 5 th Generation
- a DPD trained for the transfer characteristic of one PA may not produce acceptable results when used with another PA (e.g., another PA having different nonlinearities). Accordingly, in a situation where multiple PAs receive a common input signal, it may be desirable to have a dedicated, trained DPD for each PA. Such an arrangement, however, may be expensive to build and resource-intensive to train.
- the examples described herein address this and other problems by providing an adaption arrangement for a single DPD circuit that trains the DPD circuit to provide a pre-distorted signal that is suitable for use with multiple PAs.
- the multiple PAs may be arranged in parallel, with each PA receiving the pre-distorted signal generated by the DPD circuit.
- An adaption circuit generates predistortion parameters for the DPD circuit to configure the DPD circuit to generate the pre-distorted signal for the multiple PAs.
- the adaption circuit receives the pre-distorted signal from the DPD circuit and feedback signals from the multiple PAs. From the pre-distorted signal and the feedback signals, the adaption circuit generates predistortion correlation data based on basis matrices and error vectors generated using the various feedback signals from the PAs.
- the adaption circuit may sequentially sample feedback signals of the PAs. For each PA, the adaption circuit generates a basis matrix Y and error vector ⁇ gmpn For example, a first basis matrix Y 1 and first error vector ⁇ gmp1 are generated from a first feedback signal from a first PA and a corresponding portion of the pre-distorted signal. The first basis matrix Y 1 and first error vector ⁇ gmp1 are used to generate and/or update predistortion correlation data. A second basis matrix Y 2 and second error vector ⁇ gmp2 are generated using a second feedback signal from the second PA. The second basis matrix Y 2 and the second error vector ⁇ gmp2 are then used to update the predistortion correlation data.
- the predistortion correlation data may be updated in this manner, for example, until all PAs have been sampled and used to make a corresponding update to the predistortion correlation data.
- the adaption circuit may use the updated predistortion correlation data to generate predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k for the DPD circuit.
- the DPD circuit utilizes the predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k to generate the pre-distorted signal that is provided to the multiple PAs.
- FIG. 1 is a diagram showing one example of an environment 100 for implementing multi-component digital predistortion.
- the environment 100 includes a DPD circuit 102 and a plurality of power amplifiers 104 A, 104 B, 104 C, 104 N. Although four power amplifiers 104 A, 104 B, 104 C, 104 N are shown, the environment 100 may include any suitable number of power amplifiers, for example, any suitable number greater than one.
- the DPD circuit 102 generates a pre-distorted signal v.
- the pre-distorted signal v is provided to a digital-to-analog converter (DAC) 108 .
- the DAC 108 generates an analog pre-distorted signal v.
- the analog pre-distorted signal v is provided to the PAs 104 A, 104 B, 104 C, 104 N, which generate respective output signals, for example, for wired or wireless transmission.
- FIG. 1 also shows an optional digital upconverter (DUC) 106 .
- the DUC 106 receives one or more baseband input signals, and up-converts them to an IF or RF carrier frequency.
- the DUC 106 provides an upconverted input signal to the DPD circuit 102 .
- the input signal provided to the DPD circuit 102 may be the up-converted input signal generated by the DUC 106 .
- the outputs of the respective PAs 104 A, 104 B, 104 C, 104 N are provided to a feedback switching circuit 110 that selectively provides feedback signals y n from the various PAs 104 A, 104 B, 104 C, 104 N to a feedback analog-to-digital converter (ADC) 112 .
- ADC analog-to-digital converter
- the feedback switching circuit 110 may have a first position forming a first signal path in which a feedback signal y 1 of the power amplifier 104 A is provided to the feedback ADC 112 , a second position forming a second signal path in which a feedback signal y 2 of the power amplifier 104 B is provided to the feedback ADC 112 , a third position forming a third signal path in which a feedback signal y 3 of the power amplifier 104 C is provided to the feedback ADC 112 , and so on.
- the feedback ADC 112 provides a digital feedback signal y n to a capture buffer 114 .
- the digital feedback signal y n is a digital version of the feedback signal y n provided to the feedback ADC 112 by the feedback switching circuit 110 . It will be appreciated that other feedback circuitry arrangements may be used. For example, although one feedback ADC 112 is shown in FIG. 1 , some examples may use more than one feedback ADC 112 .
- the capture buffer 114 may also receive the digital pre-distorted signal v from the output of the DPD circuit 102 . Although one capture buffer 114 is shown, in some examples, separate capture buffers may be included with one buffer to receive the feedback signal y n and another buffer to capture the pre-distorted signal v.
- a time alignment circuit 116 is configured to match or time align values of the feedback signal y n to corresponding values of the pre-distorted signal v. For example, the time alignment circuit 116 may match values of the pre-distorted signal v to values of the feedback signal y n that were generated therefrom. Sets of time-aligned values of the pre-distorted signal v and the feedback signal y n are provided to the adaption circuit 118 .
- the adaption circuit 118 generates predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k for the DPD circuit 102 from the feedback signal y n and pre-distorted signal v.
- the predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k include a set of coefficients that may be used by the DPD circuit 102 to implement a polynomial approximation of the inverse model of the PAs 104 A, 104 B, 104 C, 104 N.
- the coefficients may be used as coefficients for taps of a digital filter that implements all or part of the DPD circuit 102 .
- the predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k include a lookup table (LUT) that is applied by the DPD circuit 102 to generate the pre-distorted signal v.
- LUT lookup table
- FIG. 2 is a flowchart showing one example of a process flow 200 that may be executed in the environment 100 to train the DPD circuit 102 .
- the feedback switching circuit is configured to provide a feedback signal from a first power amplifier 104 A, 104 B, 104 C, 104 N to the capture buffer 114 (e.g., via the feedback ADC 112 ).
- the capture buffer 114 captures values of the feedback signal y 1 and corresponding values of the pre-distorted signal v.
- the feedback signal y 1 may be taken at the output of the DPD circuit 102 as shown in FIG. 1 or in, some examples, may be taken from the input of the DPD circuit 102 in a direct adaption arrangement.
- the adaption circuit 118 generates and/or updates predistortion correlation data.
- the adaption circuit 118 may utilize the feedback signal y i and the corresponding values of the pre-distorted signal v to generate a basis matrix Y 1 and an error vector ⁇ gmp1 .
- the basis matrix Y 1 describes features of the DPD circuit 102 chosen to reflect the dynamic composition of the inverse PA behavior, such as; past and present linear terms and past and present nonlinear terms.
- the error vector ⁇ gmp1 is an indication of the error between the estimated inverse PA response and the actual DPD output v. and the corresponding values of the pre-distorted signal v.
- the adaption circuit 118 uses the basis matrix Y 1 and an error vector ⁇ gmp1 to generate predistortion correlation data.
- the predistortion correlation data may include an autocorrelation matrix R yy and a cross-correlation vector r y ⁇ .
- the autocorrelation matrix R yy indicates a correlation between the various features of the basis matrix Y 1 .
- the autocorrelation vector R yy is given by Equation [1] below:
- Equation [1] an inner product is taken between the autocorrelation matrix (in this example Y 1 ) and the Hermitian transpose of the autocorrelation matrix (indicated by the operator “ H ”). The result of the inner product is added to a previous iteration of the autocorrelation matrix R yy .
- the previous version of the autocorrelation matrix R yy may be set to the null matrix (e.g., a matrix of zeros).
- the autocorrelation matrix is a square matrix having an order based on the number of features in the basis matrix Y. For example, if the basis matrix Y has twenty features, then the autocorrelation matrix R yy may be a 20 ⁇ 20 matrix.
- the cross-correlation vector r y ⁇ indicates a correlation between the basis matrix Y and the error vector ⁇ gmp .
- the cross-correlation vector r y ⁇ is given by Equation [2] below:
- Equation [2] an inner product is taken between the Hermitian transpose of the basis matrix Y and the error vector ⁇ gmp . The result is added to a previous iteration of the cross-correlation vector r y ⁇ .
- the previous iteration of the cross-correlation vector r y ⁇ may be set to the null vector.
- the result of the operation 206 may be generated and/or updated predistortion correlation data including, for example, a value for the autocorrelation matrix R yy and a value for the cross-correlation vector or r y ⁇ .
- the feedback switching circuit 110 is configured to provide a feedback signal from a next power amplifier 104 A, 104 B, 104 C, 104 N to the capture buffer 114 (e.g., via the feedback ADC 112 ).
- the capture buffer 114 captures values of the feedback signal y n from the next PA 104 A, 104 B, 104 C, 104 N and corresponding values of the pre-distorted signal v.
- the adaption circuit 118 generates updated predistortion correlation data.
- the adaption circuit 118 may utilize Equations [1] and [2] above to generate an updated autocorrelation matrix R yy and an updated cross-correlation vector r y ⁇ , where the previous versions of R yy and r y ⁇ are as determined the previous time that the operation 206 was executed.
- operation 212 may follow.
- the adaption circuit 118 utilizes a linear solver to generate predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k for the DPD circuit 102 using the updated predistortion correlation data. Equation [3] below provides an example that may be implemented by the adaption circuit 118 to generate the predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k :
- ⁇ circumflex over ( ⁇ ) ⁇ k ⁇ circumflex over ( ⁇ ) ⁇ k ⁇ 1 + ⁇ R yy + ⁇ I ⁇ ⁇ 1 r y ⁇ [3]
- Equation [3] ⁇ circumflex over ( ⁇ ) ⁇ k ⁇ 1 is the previous iteration of the predistortion parameters.
- the value ⁇ is a real scaler that may be chosen to trade off noise immunity against the adaption rate (e.g., the rate at which the DPD circuit 102 is updated).
- the term ⁇ is a scaler that is a regularization factor that may be chosen to improve the numerical conditioning of the calculations and minimize over fitting.
- I is the identity matrix of appropriate dimension.
- the adaption circuit 118 determines whether the solution attempted at operation 212 has converged. If there is no convergence, the adaption circuit 118 may return to operation 204 to re-sample the PAs 104 A, 104 B, 104 C, 104 N before re-attempting to solve for the predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k . If the solution does converge, then the predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k are provided to the DPD circuit and the environment proceeds with use of the PAs 104 A, 104 B, 104 C, 104 N at operation 216 .
- the techniques described herein can be applied to arrangements where the transmission medium exhibits frequency-dependent attenuation.
- a medium is coaxial cable. Cable exhibits a high-frequency roll-off characteristic in which higher frequencies are attenuated at higher levels than lower frequencies. In some examples, cables exhibit about 2 dB of signal amplitude reduction per 100 MHz of frequency, such as at frequencies above 50 MHz.
- a tilt filter is added, for example, after a digital-to-analog converter (DAC).
- DAC digital-to-analog converter
- the tilt filter applies an “uptilt” frequency characteristic to the pre-distorted signal.
- the tilt frequency characteristic amplifies higher frequency portions of the signal that are attenuated by the cable so as to reduce frequency-dependent distortions at the signal destination.
- the tilt frequency characteristic increases in gain by frequency according to a tilt slope, with the signal amplitude increasing as frequency increases.
- the DPD circuit may also include a tilt reference filter and a tilt equalizer circuit.
- the tilt reference filter (positioned to operate on the input signal prior to predistortion) and the tilt equalizer circuit (positioned to operate on the pre-distorted signal) place a tilt characteristic onto the pre-distorted signal, for example, prior to the tilt filter.
- the tilt characteristic attenuates higher frequency portions of the signal.
- the inverse tilt characteristic decreases in gain by frequency according to a tilt slope, which may be the inverse of the tilt slope up the tilt filter.
- FIGS. 1 and 2 shows an indirect learning algorithm where the training error ⁇ gmp is the difference between the actual output of the DPD circuit 102 and the inverse model of the PAs 104 A, 104 B, 104 C, 104 N.
- a direct approach is used where the training error ⁇ gmp is the difference between the input to the DPD circuit 102 and the observed output.
- a direct or indirect learning algorithm may be used with the other examples described herein, as appropriate.
- FIG. 3 is a diagram showing one example of an environment 300 including a DPD circuit 302 for driving multiple PAs 304 A, 304 B, 304 C 304 N for transmitting over cable media 334 A, 334 B, 334 C, 334 N.
- a tilt filter circuit 321 applies tilt filter characteristics to the respective PAs 304 A, 304 B, 304 C, 304 N.
- a first stage tilt filter 324 provides a first stage tilt filter characteristic common to all of the PAs 304 A, 304 B, 304 C, 304 N.
- Second stage tilt filters 326 A, 326 B, 326 C, 326 N receive the output of the first stage tilt filter 324 and apply second stage tilt filter characteristics that are, for example, selected to correspond to the frequency-dependent attenuation characteristics of the respective cable media 334 A, 334 B, 334 C, 334 N. Different arrangements can be used.
- the first stage tilt filter 324 is omitted. In other examples, additional stages may be used.
- the tilt filter circuit 321 in some examples, is implemented utilizing analog components to achieve the desired characteristic.
- the environment 300 also includes a tilt reference filter circuit 320 and tilt equalizer circuit 322 .
- the tilt reference filter circuit 320 and tilt equalizer circuit 322 place a tilt characteristic onto the pre-distorted signal v to compensate for the effect of the tilt filter circuit 321 .
- the tilt filter circuit 321 imposes a linear distortion to the signal provided to the respective PAs 304 A, 304 B, 304 C, 304 N.
- the tilt reference filter circuit 320 positioned between the optional DUC 306 and the DPD circuit 302 corrects for this linear distortion, for example, by attempting to replicate it in the digital domain.
- the tilt equalizer circuit 322 positioned between the DPD circuit 302 and the DAC 308 , may be the inverse of the tilt reference filter circuit 320 .
- the tilt reference filter 320 and tilt equalizer circuit 322 are implemented using one or more digital signal processors (DSPs) or other suitable hardware arrangement, such as the architecture 1100 described herein below.
- DSPs digital signal processors
- the tilt reference filter circuit 320 and tilt equalizer circuit 322 it is desirable in some examples to train the tilt reference filter circuit 320 and tilt equalizer circuit 322 to match the nonlinearities of the respective output processing paths to the respective PAs 304 A, 304 B, 304 C, 304 N. Accordingly, training the tilt reference filter circuit 320 and tilt equalizer circuit 322 to operate with multiple output processing paths can present issues similar to those encountered when training the DPD circuit 302 to operate with multiple PAs 304 A, 304 B, 304 C, 304 N.
- FIG. 3 shows an example way to address the training of the tilt reference filter circuit 320 and tilt equalizer circuit 322 for use with multiple output processing paths to multiple PAs 304 A, 304 B, 304 C, 304 N.
- a feedback switching circuit 310 is configured to selectively sample feedback signals y n from the PAs 304 A, 304 B, 304 C, 304 N.
- a feedback ADC 312 , capture buffers 314 A, 314 B and time alignment circuit 316 may work in a manner similar to feedback ADC 112 , capture buffer 114 , and time alignment circuit 116 to provide time-aligned signals to an adaption circuit 318 .
- the adaptation circuit 318 may comprise a PA inverse model 330 for generating predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k , a tilt equalizer model 332 for generating tilt equalizer parameters ⁇ circumflex over ( ⁇ ) ⁇ equk for the tilt equalizer circuit 322 and a tilt reference model 328 for generating tilt reference parameters.
- the adaption circuit 318 is implemented using a processor arrangement, for example, similar to the architecture 1100 described herein below.
- Time alignment circuit 316 and buffer circuits 314 A, 314 B may also be implemented using all or a portion of an arrangement similar to the architecture 1100 .
- the time alignment 316 and buffer circuits 314 A, 314 B can be implemented utilizing one or more shift registers or other suitable components.
- FIG. 4 is a diagram showing one example of the environment 300 of FIG. 3 configured to generate predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k .
- the example arrangement of FIG. 4 shows the PA inverse model 330 including a feature generation circuit 408 to generate basis matrix Y and an inverse model error circuit 410 to generate error vector ⁇ gmp , for example, as described herein.
- the DPD circuit 302 may be trained according to the process flow 200 described herein.
- the feature generation circuit 408 may generate basis matrix Y based on the respective feedback signals from the PAs 304 A, 304 B, 304 C, 304 N and the pre-distorted signal v.
- the inverse model error circuit 410 may generate error vectors ⁇ gmp based on the estimated inverse model of the measured output of each of the PAs 304 A, 304 B, 304 C, 304 N and the pre-distorted signal v.
- the correlation engine 402 may generate correlation data, for example, according to Equations [1] and [ 2 ] above.
- a linear solver circuit 404 may be configured to generate the predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k , for example, according to Equation [3] described above.
- FIG. 5 is a diagram showing one example of the environment 300 of FIG. 3 configured to generate tilt reference parameters ⁇ circumflex over ( ⁇ ) ⁇ ref for the tilt reference filter circuit 320 .
- the example arrangement of FIG. 5 shows the tilt reference model 328 including a feature generation circuit 504 to generate basis matrix Y and an inverse model error circuit 502 to generate error vectors ⁇ ref .
- FIG. 6 is a flowchart showing one example of a process flow 600 that may be executed in the environment, for example, in the arrangement shown in FIG. 5 , to generate tilt reference parameters reference parameters ⁇ circumflex over ( ⁇ ) ⁇ ref .
- the PAs 304 A, 304 B, 304 C, 304 N are biased in a linear mode with the DPD circuit 302 turned off. Biasing the PAs 304 A, 304 B, 304 C, 304 N in linear mode may include biasing the PAs 304 A, 304 B, 304 C, 304 N such that nonlinearities of the PAs 304 A, 304 B, 304 C, 304 N do not affect or minimally affect the outputs of the PAs 304 A, 304 B, 304 C, 304 N.
- Turning off the DPD circuit 302 may include, for example, bypassing the DPD circuit 302 , removing power to the DPD circuit 302 and/or otherwise removing it from the circuit. This is illustrated in FIG. 5 by the absence of the DPD circuit 302 . As shown, the output of the tilt reference filter circuit 320 is provided directly to the tilt equalizer circuit 322 .
- the feedback switching circuit 310 is configured to provide a feedback signal y 1 from a first power amplifier 304 A, 304 B, 304 C, 304 N to the capture buffer 314 B (e.g., via the feedback ADC 312 ).
- the capture buffers 314 A, 314 B capture values of the feedback signal y 1 and corresponding values of the tilt reference filter circuit 320 .
- values of the feedback signal y 1 may be captured at the capture buffer 314 B and values of the output of the tilt reference filter circuit 320 may be captured at the capture buffer 314 A.
- the adaption circuit 318 can be arranged to perform indirect adaption for the tilt reference filter circuit 320 .
- the adaption circuit 318 may be configured to capture feedback from an input to the tilt reference filter 320 (e.g., instead of or in addition to capturing feedback from the output as shown in FIG. 5 ).
- the adaption circuit 318 generates and/or updates tilt reference correlation data.
- the adaption circuit 318 may utilize the feedback signal y 1 and the corresponding values of the output of the tilt reference filter circuit 320 to generate a basis matrix Y 1 and an error vector ⁇ ref1 .
- the basis matrix Y 1 describes features of the DPD circuit 102 to minimize the error between the feedback signal y 1 and the corresponding values of the tilt reference filter circuit 320 output.
- the error vector ⁇ ref1 is an indication of the error between the feedback signal y 1 and the corresponding values of the output of the tilt reference filter circuit 320 .
- the adaption circuit 318 uses the basis matrix Y 1 and an error vector ⁇ ref1 to generate tilt reference correlation data.
- the tilt reference correlation data can be generated, for example, by the correlation engine 402 .
- the tilt reference correlation data may include an autocorrelation matrix R yy and a cross-correlation vector r y ⁇ .
- the autocorrelation matrix R yy indicates a correlation between the various features of the basis matrix Y 1 .
- the autocorrelation vector R yy is given by Equation [1] above.
- the cross-correlation vector r y ⁇ indicates a correlation between the basis matrix Y and the error vector ⁇ ref , for example, as given by Equation [2] above.
- the feedback switching circuit 310 is configured at operation 612 to provide a feedback signal from a next power amplifier 304 A, 304 B, 304 C, 304 N to the capture buffer 314 B (e.g., via the feedback ADC 312 ).
- the capture buffer 314 B captures values of the feedback signal y n from the next PA 304 A, 304 B, 304 C, 304 N and corresponding values of the output of the tilt reference filter circuit 320 .
- the adaption circuit 318 generates updated tilt reference correlation data.
- the adaption circuit 318 may utilize Equations [1] and [4] above to generate an updated autocorrelation matrix R yy and an updated cross-correlation vector r y ⁇ , where the previous versions of R yy and r y ⁇ are as determined the previous time that the operation 608 was executed.
- the adaption circuit 318 utilizes the linear solver 404 to generate tilt reference parameters ⁇ circumflex over ( ⁇ ) ⁇ ref for the tilt reference filter circuit 320 using the updated tilt reference correlation data, for example, by optimizing Equation [4] below provides an example that may be implemented by the adaption circuit 318 to generate the tilt reference parameters ⁇ circumflex over ( ⁇ ) ⁇ ref :
- ⁇ circumflex over ( ⁇ ) ⁇ ref ⁇ circumflex over ( ⁇ ) ⁇ ref ⁇ 1 + ⁇ R yy + ⁇ I ⁇ ⁇ 1 r y ⁇ [4]
- Equation [5] ⁇ circumflex over ( ⁇ ) ⁇ ref ⁇ 1 is the previous iteration of the tilt reference parameters.
- the values ⁇ and ⁇ may be as described with respect to Equation [3] above.
- the adaption circuit 318 determines whether the solution attempted at operation 614 has converged. If there is no convergence, the adaption circuit 318 may return to operation 604 to re-sample the PAs 304 A, 304 B, 304 C, 304 N before re-attempting to solve for the tilt reference parameters ⁇ circumflex over ( ⁇ ) ⁇ ref . If the solution does converge, then the tilt reference parameters ⁇ circumflex over ( ⁇ ) ⁇ ref are provided to the tilt reference filter circuit 320 . The DPD circuit 302 may be re-activated and the environment may proceed with use of the PAs 304 A, 304 B, 304 C, 304 N at operation 618 .
- FIG. 7 is a diagram showing one example of the environment 300 of FIG. 3 configured to generate tilt equalizer parameters ⁇ circumflex over ( ⁇ ) ⁇ equ for the tilt equalizer circuit 322 .
- the example arrangement of FIG. 7 shows the tilt equalizer model 332 including a feature generation circuit 704 to generate a basis matrix Y and an inverse model error circuit 702 to generate error vectors ⁇ equ .
- FIG. 8 is a flowchart showing one example of a process flow 800 that may be executed in the environment, for example, in the arrangement shown in FIG. 7 , to generate tilt equalizer parameters, ⁇ circumflex over ( ⁇ ) ⁇ equ .
- the PAs 304 A, 304 B, 304 C, 304 N are biased in a linear mode with the DPD circuit 302 turned off.
- the feedback switching circuit 310 is configured to provide a feedback signal y i from a first power amplifier 304 A, 304 B, 304 C, 304 N to the capture buffer 314 B (e.g., via the feedback ADC 312 ). This description will assume that the feedback signal y 1 from the PA 304 A is provided first; however, as described herein any suitable PA 304 A, 304 B, 304 C, 304 N may be selected first.
- the capture buffers 314 A, 314 B capture values of the feedback signal y 1 and corresponding values of the tilt equalizer circuit 322 input.
- values of the feedback signal y 1 may be captured at the capture buffer 314 B and values of the output from the tilt equalizer circuit 322 may be captured at the capture buffer 314 A.
- the adaption circuit 318 can be arranged to perform indirect adaption for the tilt equalizer circuit 322 .
- the adaption circuit 318 may be configured to capture feedback from an input to the tilt equalizer circuit 322 (e.g., instead of or in addition to capturing feedback from the output as shown in FIG. 7 ).
- the adaption circuit 318 generates and/or updates tilt equalizer correlation data.
- the adaption circuit 318 may utilize the feedback signal y 1 and the corresponding values of the output of the tilt equalizer circuit 322 to generate a basis matrix Y 1 and an error vector ⁇ equ1 .
- the basis matrix Y 1 describes (linear) features to minimize the error between the feedback signal y 1 and the corresponding values of the output of the tilt equalizer circuit 322 .
- the error vector ⁇ equ1 is an indication of the error between the feedback signal y i and the corresponding values of the output of the tilt equalizer circuit 322 .
- the basis matrix Y 1 for generating the tilt equalizer circuit 322 and tilt reference circuit 320 parameters include linear terms while the basis matrix Y 1 for generating DPD circuit 302 parameters may include linear and/or non-linear terms.
- the adaption circuit 318 uses the basis matrix Y 1 and an error vector ⁇ equ1 to generate tilt equalizer correlation data.
- the tilt equalizer correlation data can be generated, for example, by the correlation engine 402 .
- the tilt equalizer correlation data may include an autocorrelation matrix R yy and a cross-correlation vector r y ⁇ , as described herein.
- the autocorrelation matrix R yy indicates a correlation between the various features of the basis matrix Y 1 .
- the autocorrelation vector R yy is given by Equation [1] above.
- the cross-correlation vector r y ⁇ indicates a correlation between the basis matrix Y and the error vector ⁇ equ1 .
- the cross-correlation vector r y ⁇ is given by Equation [2] above.
- the feedback switching circuit 310 is configured at operation 812 to provide a feedback signal from a next power amplifier 304 A, 304 B, 304 C, 304 N to the capture buffer 314 B (e.g., via the feedback ADC 312 ).
- the capture buffer 314 B captures values of the feedback signal y n from the next PA 304 A, 304 B, 304 C, 304 N and corresponding values of the input to the tilt equalizer circuit 322 .
- the adaption circuit 318 generates updated equalizer correlation data.
- the adaption circuit 318 may utilize Equations [1] and [4] above to generate an updated autocorrelation matrix R yy and an updated cross-correlation vector r y ⁇ , where the previous versions of R yy and r y ⁇ are as determined the previous time that the operation 808 was executed.
- the adaption circuit 318 utilizes the linear solver 404 to generate tilt equalizer parameters ⁇ circumflex over ( ⁇ ) ⁇ equ for the tilt equalizer circuit 322 using the updated tilt equalizer correlation data, for example, by optimizing Equation [5] below provides an example that may be implemented by the adaption circuit 318 to generate the tilt equalizer parameters ⁇ circumflex over ( ⁇ ) ⁇ equ :
- Equation [5] ⁇ circumflex over ( ⁇ ) ⁇ equ ⁇ 1 is the previous iteration of the tilt equalizer parameters.
- the values ⁇ and ⁇ may be as described with respect to Equation [3] above.
- the adaption circuit 318 determines whether the solution attempted at operation 814 has converged. If there is no convergence, the adaption circuit 318 may return to operation 804 to re-sample the PAs 304 A, 304 B, 304 C, 304 N before re-attempting to solve for the tilt equalizer parameters ⁇ circumflex over ( ⁇ ) ⁇ equ . If the solution does converge, then the tilt equalizer parameters ⁇ circumflex over ( ⁇ ) ⁇ equ are provided to the tilt equalizer circuit 322 . The DPD circuit 302 may be re-activated and the environment may proceed with use of the PAs 304 A, 304 B, 304 C, 304 N at operation 818 .
- the tilt equalizer circuit 322 and tilt reference filter circuit 320 are trained independently of the DPD circuit 302 .
- the tilt reference filter parameters ⁇ circumflex over ( ⁇ ) ⁇ equ and tilt reference parameters ⁇ circumflex over ( ⁇ ) ⁇ ref may be determined first, for example, as illustrated and described with respect to FIGS. 5 - 8 .
- the DPD circuit 302 may be trained, for example, as described herein.
- FIG. 9 shows four plots 902 , 904 , 906 , 908 illustrating outputs of four PAs in the arrangement of the PAs 304 A, 304 B, 304 C, 304 N, with components trained as described with respect to FIGS. 3 - 8 .
- Plot 902 shows signal strength in decibels (dB) versus frequency for a first PA, such as PA 304 A.
- Plot 904 shows signal strength in dB versus frequency for a second PA, such as PA 304 B.
- Plot 906 shows signal strength in dB versus frequency for a third PA, such as PA 304 C.
- Plot 908 shows signal strength in dB versus frequency for a fourth PA, such as PA 304 N.
- the plots 902 , 904 , 906 , 908 show tilt provided by the tilt circuit 321 as the displayed signals are higher at higher frequency to compensate for the higher attenuation of the cable media 334 A, 334 B, 334 C, 334 N at higher frequencies. Also, as shown, the outputs are substantially similar despite being driven by a single DPD circuit 302 .
- FIG. 10 is a diagram showing one example of an environment 1000 including an array 1034 of PAs and an array DPD circuit 1002 .
- a single input signal e.g., processed by the optional DUC 1006
- the array DPD circuit 1002 generates a pre-distorted signal v.
- a DAC 1008 converts the pre-distorted signal v to an analog pre-distorted signal v.
- a mixer 1030 and mixer array 1032 mix the pre-distorted signal v with an array of values for a given downtilt angle ⁇ and a horizontal scan angle ⁇ to modify the amplitude and phase of the pre-distorted signal v.
- the mixer 1030 may be or include a frequency translation mixer that takes a lower-centered frequency signal (e.g., IF, such as about 100 MHz) and coverts it to a higher-centered frequency signal (e.g., about 30 GHz).
- the result of the mixer 1030 and mixer array 1032 may be a set of amplitude-modified and phase-shifted pre-distorted signals v, with each distinct signal being shifted by a phase and amplitude to bring about a transmission beam 1038 of a desired shape and direction.
- the phase-shifted and amplitude-modified pre-distorted signals are provided to PAs of a PA array 1034 .
- the PAs of the PA array amplify their respective received signals, which are provided to separate antennas of an antenna array 1036 .
- the phase shifting and amplitude modifying of the inputs to the PAs of the PA array result in a beam 1038 having the desired downtilt angle ⁇ and horizontal scan angle ⁇ .
- the array DPD circuit 1002 may be trained in a manner similar to that described herein with respect to FIGS. 1 and 2 .
- a feedback switching circuit 1010 is configured to sequentially provide feedback signals y n from the PAs of the PA array 1034 to an adaption circuit 1018 via a, mixer 1042 , and feedback ADC 1012 .
- the mixer 1042 for example, man down-convert the feedback signals y n , for example, as the inverse of the mixer 1030 .
- the adaption circuit 1018 may receive the feedback signals y n and the digital pre-distorted signal v from the output of the array DPD circuit 1002 .
- the adaption circuit 1018 may perform time alignment to match or time align values of the feedback signal y n to corresponding values of the pre-distorted signal v.
- the adaption circuit 1018 generates predistortion parameters ⁇ circumflex over ( ⁇ ) ⁇ k for the array DPD circuit 1002 from the feedback signal y n and pre-distorted signal v, for example, as described herein with respect to FIG. 2 .
- FIG. 11 is a block diagram illustrating a computing device hardware architecture 1100 , within which a set or sequence of instructions can be executed to cause a machine to perform examples of any one of the methodologies discussed herein.
- the architecture 1100 may describe one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or similar hardware that may be used, in some examples, to implement any of the circuits described herein.
- DPD circuit 102 , adaption circuit 118 may be implemented using all or portions of a hardware architecture such as the architecture 1100 .
- the capture buffer 114 and time alignment circuit 116 in some examples, may also be implemented using all or portions of a hardware architecture such as the architecture 1100 .
- the architecture 1100 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the architecture 1100 may operate in the capacity of either a server or a client machine in server-client network environments, or it may act as a peer machine in peer-to-peer (or distributed) network environments.
- the architecture 1100 can be implemented in an embedded system, a personal computer (PC), a tablet PC, a hybrid tablet, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, a network switch, a network bridge, or any machine capable of executing instructions (sequential or otherwise) that specify operations to be taken by that machine.
- the example architecture 1100 includes a processor unit 1102 comprising at least one processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or both, processor cores, compute nodes).
- the architecture 1100 may further comprise a main memory 1104 and a static memory 1106 , which communicate with each other via a link 1108 (e.g., a bus).
- the architecture 1100 can further include a video display unit 1110 , an input device 1112 (e.g., a keyboard), and a UI navigation device 1114 (e.g., a mouse).
- the video display unit 1110 , input device 1112 , and UI navigation device 1114 are incorporated into a touchscreen display.
- the architecture 1100 may additionally include a storage device 1116 (e.g., a drive unit), a signal generation device 1118 (e.g., a speaker), a network interface device 1120 , and one or more sensors (not shown), such as a Global Positioning System (GPS) sensor, compass, accelerometer, or other sensor.
- a storage device 1116 e.g., a drive unit
- a signal generation device 1118 e.g., a speaker
- a network interface device 1120 e.g., a Wi-Fi
- sensors not shown
- GPS Global Positioning System
- the processor unit 1102 or another suitable hardware component may support a hardware interrupt.
- the processor unit 1102 may pause its processing and execute an ISR, for example, as described herein.
- the storage device 1116 includes a machine-readable medium 1122 on which is stored one or more sets of data structures and instructions 1124 (e.g., software) embodying or used by any one or more of the methodologies or functions described herein.
- the instructions 1124 can also reside, completely or at least partially, within the main memory 1104 , within the static memory 1106 , and/or within the processor unit 1102 during execution thereof by the architecture 1100 , with the main memory 1104 , the static memory 1106 , and the processor unit 1102 also constituting machine-readable media.
- the various memories i.e., 1104 , 1106 , and/or memory of the processor unit(s) 1102
- the storage device 1116 may store one or more sets of instructions and data structures (e.g., the instructions 1124 ) embodying or used by any one or more of the methodologies or functions described herein. These instructions, when executed by the processor unit(s) 1102 , cause various operations to implement the disclosed examples.
- machine-storage medium As used herein, the terms “machine-storage medium,” “device-storage medium,” and “computer-storage medium” (referred to collectively as “machine-storage medium”) mean the same thing and may be used interchangeably.
- the terms refer to a single or multiple storage devices and/or media (e.g., a centralized or distributed database, and/or associated caches and servers) that store executable instructions and/or data, as well as cloud-based storage systems or storage networks that include multiple storage apparatus or devices.
- the terms shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media, including memory internal or external to processors.
- machine-storage media examples include non-volatile memory, including by way of example semiconductor memory devices, e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), field-programmable gate array (FPGA), and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.
- semiconductor memory devices e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), field-programmable gate array (FPGA), and flash memory devices
- magnetic disks such as internal hard disks and removable disks
- magneto-optical disks magneto-optical disks
- CD-ROM and DVD-ROM disks examples include CD-ROM and DVD-ROM disks.
- signal medium or “transmission medium” shall be taken to include any form of modulated data signal, carrier wave, and so forth.
- modulated data signal means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal.
- machine-readable medium means the same thing and may be used interchangeably in this disclosure.
- the terms are defined to include both machine-storage media and signal media.
- the terms include both storage devices/media and carrier waves/modulated data signals.
- the instructions 1124 can further be transmitted or received over a communications network 1126 using a transmission medium via the network interface device 1120 using any one of a number of well-known transfer protocols (e.g., Hypertext Transfer Protocol (HTTP)).
- HTTP Hypertext Transfer Protocol
- Examples of communication networks include a local area network (LAN), a wide area network (WAN), the Internet, mobile telephone networks, plain old telephone service (POTS) networks, and wireless data networks (e.g., Wi-Fi, 3G, 4G Long-Term Evolution (LTE)/LTE-A, 5G, or WiMAX networks).
- Example 1 is a system for operating a plurality of power amplifiers, the system comprising: a predistortion circuit configured to pre-distort an input signal according to a predistortion configuration to generate a pre-distorted signal for the plurality of power amplifiers; and an adaption circuit, configured to perform operations comprising: receiving a first feedback signal from a first power amplifier of the plurality of power amplifiers; generating predistortion correlation data describing a correlation between parameters of a model describing the plurality of power amplifiers; receiving a first feedback signal from a second power amplifier of the plurality of power amplifiers; updating the predistortion correlation data to generate updated predistortion correlation data, the updating using the first feedback signal from the second power amplifier; and generating the predistortion configuration using the updated predistortion correlation data.
- Example 2 the subject matter of Example 1 optionally includes wherein generating the predistortion correlation data comprises: generating a first basis matrix using the first feedback signal of the first power amplifier and the pre-distorted signal; generating a first error vector using the first feedback signal of the first power amplifier and the pre-distorted signal; generating an autocorrelation matrix using the first basis matrix; and generating a cross-correlation vector using the first error vector.
- Example 3 the subject matter of Example 2 optionally includes wherein updating the predistortion correlation data comprises: generating a second basis matrix using the first feedback signal of the second power amplifier and the pre-distorted signal; generating a second error vector using the first feedback signal of the second power amplifier and the pre-distorted signal; generating an updated autocorrelation matrix using the second basis matrix and the autocorrelation matrix; and generating an updated cross-correlation vector using the second error vector and the cross-correlation vector.
- Example 4 the subject matter of Example 3 optionally includes wherein generating the predistortion configuration is based at least in part on the updated autocorrelation matrix and the updated cross-correlation vector.
- Example 5 the subject matter of any one or more of Examples 3-4 optionally includes wherein generating the predistortion configuration is based at least in part on a previous predistortion configuration, the updated autocorrelation matrix, and the updated cross-correlation vector.
- Example 6 the subject matter of any one or more of Examples 1-5 optionally includes a tilt equalizer circuit electrically coupled to the predistortion circuit to apply a frequency characteristic to the pre-distorted signal according to a tilt equalizer configuration, the operations further comprising: receiving a second feedback signal from the first power amplifier, the second feedback signal from the first power amplifier taken while the first power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; generating tilt equalizer correlation data describing a correlation between the plurality of power amplifiers and a tilt equalizer input signal using the second feedback signal of the first power amplifier; receiving a second feedback signal from the second power amplifier, the second feedback signal from the second power amplifier taken while the second power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; updating the tilt equalizer correlation data to generate updated tilt equalizer correlation data, the updating using the second feedback signal of the second power amplifier; and generating the tilt equalizer configuration for the tilt equalizer circuit using the updated tilt equalizer correlation data.
- Example 7 the subject matter of any one or more of Examples 1-6 optionally includes a tilt reference circuit electrically coupled prior to the predistortion circuit to apply a frequency characteristic to the pre-distorted signal according to a tilt reference configuration, the operations further comprising: receiving a third feedback signal of the first power amplifier, the third feedback signal from the first power amplifier taken while the first power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; generating, by the adaption circuit, tilt reference correlation data describing a correlation between the plurality of power amplifiers and a tilt reference input signal using the third feedback signal of the first power amplifier; receiving a third feedback signal of the second power amplifier, the third feedback signal from the second power amplifier taken while the second power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; updating, by the adaption circuit, the tilt reference correlation data to generate updated tilt reference correlation data, the updating using the third feedback signal of the second power amplifier; and generating, by the adaption circuit, a first
- Example 8 the subject matter of any one or more of Examples 1-7 optionally includes a beamforming circuit is positioned between the predistortion circuit and the first power amplifier, wherein the beamforming circuit is configured to perform operations comprising: applying a first amplitude modification and a first phase shift to the pre-distorted signal to generate a first modified pre-distorted signal; applying a second amplitude modification and a second phase shift to the pre-distorted signal to generate a second modified pre-distorted signal; providing the first modified pre-distorted signal to the first power amplifier; and providing the second modified pre-distorted signal to the second power amplifier.
- a beamforming circuit is positioned between the predistortion circuit and the first power amplifier, wherein the beamforming circuit is configured to perform operations comprising: applying a first amplitude modification and a first phase shift to the pre-distorted signal to generate a first modified pre-distorted signal; applying a second amplitude modification and a second phase shift to the pre-distorted signal to generate a second modified pre-distorted signal; providing the first modified pre-distorted signal to the
- Example 9 is a method for operating a predistortion circuit with a plurality of power amplifiers, the method comprising: configuring an adaption circuit to receive a first feedback signal from a first power amplifier of the plurality of power amplifiers; generating, by the adaption circuit, predistortion correlation data describing a correlation between parameters of a model describing the plurality of power amplifiers; configuring the adaption circuit to receive a first feedback signal from a second power amplifier of the plurality of power amplifiers; updating the predistortion correlation data, by the adaption circuit, to generate updated predistortion correlation data, the updating using the first feedback signal from the second power amplifier; generating, by the adaption circuit, a predistortion configuration for the predistortion circuit using the updated predistortion correlation data; generating, by the predistortion circuit, a pre-distorted signal based at least in part on the predistortion configuration; and providing the pre-distorted signal to the plurality of power amplifiers.
- Example 10 the subject matter of Example 9 optionally includes wherein generating the predistortion correlation data comprises: generating a first basis matrix using the first feedback signal of the first power amplifier and the pre-distorted signal; generating a first error vector using the first feedback signal of the first power amplifier and the pre-distorted signal; generating an autocorrelation matrix using the first basis matrix; and generating a cross-correlation vector using the first error vector.
- Example 11 the subject matter of Example 10 optionally includes wherein updating the predistortion correlation data comprises: generating a second basis matrix using the first feedback signal of the second power amplifier and the pre-distorted signal; generating a second error vector using the first feedback signal of the second power amplifier and the pre-distorted signal; generating an updated autocorrelation matrix using the second basis matrix and the autocorrelation matrix; and generating an updated cross-correlation vector using the second error vector and the cross-correlation vector.
- Example 12 the subject matter of Example 11 optionally includes wherein generating the predistortion configuration is based at least in part on the updated autocorrelation matrix and the updated cross-correlation vector.
- Example 13 the subject matter of any one or more of Examples 11-12 optionally includes wherein generating the predistortion configuration is based at least in part on a previous predistortion configuration, the updated autocorrelation matrix, and the updated cross-correlation vector.
- Example 14 the subject matter of any one or more of Examples 9-13 optionally includes configuring a tilt equalizer circuit electrically coupled between the predistortion circuit and the plurality of power amplifiers, the configuring of the tilt equalizer comprising: biasing the plurality of power amplifiers to operate in a linear mode; deactivating the predistortion circuit; configuring the adaption circuit to receive a second feedback signal from the first power amplifier; generating, by the adaption circuit, tilt equalizer correlation data describing a correlation between the plurality of power amplifiers and a tilt equalizer input signal using the second feedback signal of the first power amplifier; configuring the tilt equalizer circuit to receive a second feedback signal from the second power amplifier; updating, by the adaption circuit, the tilt equalizer correlation data to generate updated tilt equalizer correlation data, the updating using the second feedback signal of the second power amplifier; and generating, by the adaption circuit, a first tilt equalizer configuration for the tilt equalizer using the updated tilt equalizer correlation data.
- Example 15 the subject matter of any one or more of Examples 9-14 optionally includes configuring a tilt reference circuit electrically coupled prior to the predistortion circuit, the configuring of the tilt reference circuit comprising: biasing the plurality of power amplifiers to operate in a linear mode; deactivating the predistortion circuit; configuring the adaption circuit to receive a third feedback signal of the first power amplifier; generating, by the adaption circuit, tilt reference correlation data describing a correlation between the plurality of power amplifiers and a tilt reference input signal using the third feedback signal of the first power amplifier; configuring the tilt reference circuit to receive a third feedback signal of the second power amplifier; updating, by the adaption circuit, the tilt reference correlation data to generate updated tilt reference correlation data, the updating using the third feedback signal of the second power amplifier; and generating, by the adaption circuit, a first tilt reference configuration for the tilt reference circuit using the updated tilt reference correlation data.
- Example 16 the subject matter of any one or more of Examples 9-15 optionally includes wherein a beamforming circuit is positioned between the predistortion circuit and the first power amplifier, further comprising: applying, by the beamforming circuit, a first amplitude modification and a first phase shift to the pre-distorted signal to generate a first modified pre-distorted signal; applying, by the beamforming circuit, a second amplitude modification and a second phase shift to the pre-distorted signal to generate a second modified pre-distorted signal; providing the first modified pre-distorted signal to the first power amplifier; and providing the second modified pre-distorted signal to the second power amplifier.
- a beamforming circuit is positioned between the predistortion circuit and the first power amplifier, further comprising: applying, by the beamforming circuit, a first amplitude modification and a first phase shift to the pre-distorted signal to generate a first modified pre-distorted signal; applying, by the beamforming circuit, a second amplitude modification and a second phase shift to the pre-distorted signal to generate a second modified pre-distorted signal;
- Example 17 is a system for operating a plurality of power amplifiers, comprising: a first signal path for receiving a first feedback signal from a first power amplifier of the plurality of power amplifiers; means for generating predistortion correlation data describing a correlation between parameters of a model describing the plurality of power amplifiers; a second signal path for receiving a first feedback signal from a second power amplifier of the plurality of power amplifiers; means for updating the predistortion correlation data to generate updated predistortion correlation data, the updating using the first feedback signal from the second power amplifier; means for generating a predistortion configuration for a predistortion circuit using the updated predistortion correlation data; and means for generating a pre-distorted signal for providing to the plurality of power amplifiers based at least in part on the predistortion configuration.
- Example 18 the subject matter of Example 17 optionally includes means for receiving a second feedback signal from the first power amplifier, the second feedback signal from the first power amplifier taken while the first power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; means for generating tilt equalizer correlation data describing a correlation between the plurality of power amplifiers and a tilt equalizer input signal provided to a tilt equalizer, the generating using the second feedback signal of the first power amplifier; means for receiving a second feedback signal from the second power amplifier, the second feedback signal from the second power amplifier taken while the second power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; means for updating the tilt equalizer correlation data to generate updated tilt equalizer correlation data, the updating using the second feedback signal of the second power amplifier; and means for generating a tilt equalizer configuration using the updated tilt equalizer correlation data.
- Example 19 the subject matter of any one or more of Examples 17-18 optionally includes means for receiving a third feedback signal of the first power amplifier, the third feedback signal from the first power amplifier taken while the first power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; means for generating tilt reference correlation data describing a correlation between the plurality of power amplifiers and a tilt reference input signal using the third feedback signal of the first power amplifier; means for receiving a third feedback signal of the second power amplifier, the third feedback signal from the second power amplifier taken while the second power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; means for updating the tilt reference correlation data to generate updated tilt reference correlation data, the updating using the third feedback signal of the second power amplifier; and means for generating a first tilt reference configuration using the updated tilt reference correlation data.
- Example 20 the subject matter of any one or more of Examples 17-19 optionally includes means for applying a first amplitude modification and a first phase shift to the pre-distorted signal to generate a first modified pre-distorted signal; means for applying a second amplitude modification and a second phase shift to the pre-distorted signal to generate a second modified pre-distorted signal; means for providing the first modified pre-distorted signal to the first power amplifier; and means for providing the second modified pre-distorted signal to the second power amplifier.
- the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.”
- the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated.
- Geometric terms such as “parallel”, “perpendicular”, “round”, or “square”, are not intended to require absolute mathematical precision, unless the context indicates otherwise. Instead, such geometric terms allow for variations due to manufacturing or equivalent functions. For example, if an element is described as “round” or “generally round,” a component that is not precisely circular (e.g., one that is slightly oblong or is a many-sided polygon) is still encompassed by this description.
- circuit can include a dedicated hardware circuit, a general-purpose microprocessor, digital signal processor, or other processor circuit, and may be structurally configured from a general purpose circuit to a specialized circuit such as using firmware or software.
- any one or more of the techniques (e.g., methodologies) discussed herein may be performed on a machine.
- the machine may operate as a standalone device or may be connected (e.g., networked) to other machines.
- the machine may operate in the capacity of a server machine, a client machine, or both in server-client network environments.
- the machine may act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment.
- P2P peer-to-peer
- the machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine.
- PC personal computer
- PDA personal digital assistant
- STB set-top box
- PDA personal digital assistant
- mobile telephone a web appliance
- web appliance a web appliance
- network router network router, switch or bridge
- machine may also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.
- SaaS software as a service
- Circuit sets are a collection of circuits implemented in tangible entities that include hardware (e.g., simple circuits, gates, logic, etc.). Circuit set membership may be flexible over time and underlying hardware variability. Circuit sets include members that may, alone or in combination, perform specified operations when operating. In an example, hardware of the circuit set may be immutably designed to carry out a specific operation (e.g., hardwired).
- the hardware of the circuit set may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a computer readable medium physically modified (e.g., magnetically, electrically, moveable placement of invariant massed particles, etc.) to encode instructions of the specific operation.
- a computer readable medium physically modified (e.g., magnetically, electrically, moveable placement of invariant massed particles, etc.) to encode instructions of the specific operation.
- the instructions can enable embedded hardware (e.g., the execution units or a loading mechanism) to create members of the circuit set in hardware via the variable connections to carry out portions of the specific operation when in operation.
- the computer readable medium is communicatively coupled to the other components of the circuit set member when the device is operating.
- any of the physical components may be used in more than one member of more than one circuit set.
- execution units may be used in a first circuit of a first circuit set at one point in time and reused by a second circuit in the first circuit set, or by a third circuit in a second circuit set at a different time.
- a machine e.g., computer system
- a hardware processor e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof
- main memory e.g., main memory
- static memory some or all of which may communicate with each other via an interlink (e.g., bus).
- the machine may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse).
- the display unit, input device and UI navigation device may be a touch screen display.
- the machine may additionally include a storage device (e.g., drive unit), a signal generation device (e.g., a speaker), a network interface device, and one or more sensors, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor.
- the machine may include an output controller, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).
- a serial e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).
- USB universal serial bus
- IR infrared
- NFC near field communication
- the storage device may include a machine readable medium on which is stored one or more sets of data structures or instructions (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein.
- the instructions may also reside, completely or at least partially, within the main memory, within static memory, or within the hardware processor during execution thereof by the machine.
- one or any combination of the hardware processor, the main memory, the static memory, or the storage device may constitute machine readable media.
- machine readable medium can include a single medium
- machine readable medium may include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) configured to store the one or more instructions.
- machine readable medium may include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine and that cause the machine to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions.
- Non-limiting machine readable medium examples may include solid-state memories, and optical and magnetic media.
- a massed machine readable medium comprises a machine readable medium with a plurality of particles having invariant (e.g., rest) mass. Accordingly, massed machine-readable media are not transitory propagating signals.
- massed machine readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.
- non-volatile memory such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices
- EPROM Electrically Programmable Read-Only Memory
- EEPROM Electrically Erasable Programmable Read-Only Memory
- flash memory devices e.g., electrically Erasable Programmable Read-Only Memory (EEPROM)
- EPROM Electrically Programmable Read-Only Memory
- EEPROM Electrically Erasable Programmable Read-Only Memory
- flash memory devices e.g., electrical
- the instructions may further be transmitted or received over a communications network using a transmission medium via the network interface device utilizing any one of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.).
- transfer protocols e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.
- Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi®, IEEE 802.16 family of standards known as WiMax®), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, among others.
- the network interface device may include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to the communications network.
- the network interface device may include a plurality of antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques.
- SIMO single-input multiple-output
- MIMO multiple-input multiple-output
- MISO multiple-input single-output
- transmission medium shall be taken to include any intangible medium that is capable of storing, encoding or carrying instructions for execution by the machine, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software.
- Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples.
- An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times.
- Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.
Abstract
Description
- This application is a continuation of U.S. Non-Provisional patent application Ser. No. 16/992,902, filed Aug. 13, 2020, which is hereby incorporated by reference herein in its entirety.
- This document pertains generally, but not by way of limitation, to integrated circuits and communication systems, and particularly, but not by way of limitation to digital predistortion for non-linear components, such as power amplifiers.
- Communications over wired media, such as coaxial cable and over wireless media, such as RF transmission, often use a power amplifier (PA) in a transmitter to produce a signal for transmission over the medium. The PA circuit may include a PA with a nonlinear gain characteristic, such as gain compression, that occurs at higher power output levels. The nonlinear gain characteristic can lead to signal distortion at the higher power levels. Digital predistortion (DPD) is used to compensate for amplifier nonlinearities. A DPD circuit applies predistortion to the amplifier input signal. The predistortion is determined using an inverse model of the amplifier's transfer characteristic, including distortion terms. A goal of the predistortion is to reduce distortion in the transmitted signal due to the PA gain nonlinearity.
- In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
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FIG. 1 is a diagram showing one example of an environment for implementing multi-component digital predistortion. -
FIG. 2 is a flowchart showing one example of a process flow that may be executed in the environment to train the DPD circuit. -
FIG. 3 is a diagram showing one example of an environment including a DPD circuit for driving multiple PAs for transmitting over cable media. -
FIG. 4 is a diagram showing one example of the environment ofFIG. 3 configured to generate predistortion parameters. -
FIG. 5 is a diagram showing one example of the environment ofFIG. 3 configured to generate tilt reference parameters for the tilt reference circuit. -
FIG. 6 is a flowchart showing one example of a process flow that may be executed in the environment, for example, in the arrangement shown inFIG. 5 , to generate tilt reference parameters reference parameters. -
FIG. 7 is a diagram showing one example of the environment ofFIG. 3 configured to generate tilt equalizer parameters for the tilt equalizer circuit. -
FIG. 8 is a flowchart showing one example of a process flow that may be executed in the environment, for example, in the arrangement shown inFIG. 7 , to generate tilt equalizer parameters equalizer parameters. -
FIG. 9 shows four plots illustrating outputs of four PAs in the arrangement of the PAs with components trained as described with respect toFIGS. 3-8 . -
FIG. 10 is a diagram showing one example of an environment including an array of PAs and an array DPD circuit. -
FIG. 11 is a block diagram illustrating a computing device hardware architecture, within which a set or sequence of instructions can be executed to cause a machine to perform examples of any one of the methodologies discussed herein. - Various examples described herein are directed to systems and methods implementing multi-component DPD where one DPD generates a pre-distorted signal that is provided to multiple PAs. For example, there are many contexts in which it is desirable to provide the same input signal to multiple PAs. One example is in cable television and related cable communications where the same input signal (e.g., representing different television channel signals or other signals) may be transmitted to different customers across different coaxial and/or fiber trunk lines. Another example is in mobile telephony. Some mobile telephony technologies, such as 5th Generation (5G) wireless systems, utilize electromagnetic beamforming that involves transmitting the same input signal from different antennas at different power levels and phases.
- Because different PAs have different nonlinearities, a DPD trained for the transfer characteristic of one PA may not produce acceptable results when used with another PA (e.g., another PA having different nonlinearities). Accordingly, in a situation where multiple PAs receive a common input signal, it may be desirable to have a dedicated, trained DPD for each PA. Such an arrangement, however, may be expensive to build and resource-intensive to train.
- The examples described herein address this and other problems by providing an adaption arrangement for a single DPD circuit that trains the DPD circuit to provide a pre-distorted signal that is suitable for use with multiple PAs. The multiple PAs may be arranged in parallel, with each PA receiving the pre-distorted signal generated by the DPD circuit.
- An adaption circuit generates predistortion parameters for the DPD circuit to configure the DPD circuit to generate the pre-distorted signal for the multiple PAs. The adaption circuit receives the pre-distorted signal from the DPD circuit and feedback signals from the multiple PAs. From the pre-distorted signal and the feedback signals, the adaption circuit generates predistortion correlation data based on basis matrices and error vectors generated using the various feedback signals from the PAs.
- The adaption circuit may sequentially sample feedback signals of the PAs. For each PA, the adaption circuit generates a basis matrix Y and error vector ϵgmpn For example, a first basis matrix Y1 and first error vector ϵgmp1 are generated from a first feedback signal from a first PA and a corresponding portion of the pre-distorted signal. The first basis matrix Y1 and first error vector ϵgmp1 are used to generate and/or update predistortion correlation data. A second basis matrix Y2 and second error vector ϵgmp2 are generated using a second feedback signal from the second PA. The second basis matrix Y2 and the second error vector ϵgmp2 are then used to update the predistortion correlation data. The predistortion correlation data may be updated in this manner, for example, until all PAs have been sampled and used to make a corresponding update to the predistortion correlation data. The adaption circuit may use the updated predistortion correlation data to generate predistortion parameters {circumflex over (θ)}k for the DPD circuit. The DPD circuit utilizes the predistortion parameters {circumflex over (θ)}k to generate the pre-distorted signal that is provided to the multiple PAs.
-
FIG. 1 is a diagram showing one example of anenvironment 100 for implementing multi-component digital predistortion. Theenvironment 100 includes aDPD circuit 102 and a plurality ofpower amplifiers power amplifiers environment 100 may include any suitable number of power amplifiers, for example, any suitable number greater than one. According to theenvironment 100, theDPD circuit 102 generates a pre-distorted signal v. The pre-distorted signal v is provided to a digital-to-analog converter (DAC) 108. TheDAC 108 generates an analog pre-distorted signal v. The analog pre-distorted signal v is provided to thePAs FIG. 1 also shows an optional digital upconverter (DUC) 106. The DUC 106 receives one or more baseband input signals, and up-converts them to an IF or RF carrier frequency. The DUC 106 provides an upconverted input signal to theDPD circuit 102. In examples where the DUC 106 is present, the input signal provided to theDPD circuit 102 may be the up-converted input signal generated by the DUC 106. - In the example of
FIG. 1 , the outputs of therespective PAs feedback switching circuit 110 that selectively provides feedback signals yn from thevarious PAs feedback switching circuit 110 may have a first position forming a first signal path in which a feedback signal y1 of thepower amplifier 104A is provided to thefeedback ADC 112, a second position forming a second signal path in which a feedback signal y2 of thepower amplifier 104B is provided to thefeedback ADC 112, a third position forming a third signal path in which a feedback signal y3 of thepower amplifier 104C is provided to thefeedback ADC 112, and so on. The feedback ADC 112 provides a digital feedback signal yn to acapture buffer 114. The digital feedback signal yn is a digital version of the feedback signal yn provided to the feedback ADC 112 by thefeedback switching circuit 110. It will be appreciated that other feedback circuitry arrangements may be used. For example, although onefeedback ADC 112 is shown inFIG. 1 , some examples may use more than onefeedback ADC 112. - The
capture buffer 114 may also receive the digital pre-distorted signal v from the output of theDPD circuit 102. Although onecapture buffer 114 is shown, in some examples, separate capture buffers may be included with one buffer to receive the feedback signal yn and another buffer to capture the pre-distorted signal v. Atime alignment circuit 116 is configured to match or time align values of the feedback signal yn to corresponding values of the pre-distorted signal v. For example, thetime alignment circuit 116 may match values of the pre-distorted signal v to values of the feedback signal yn that were generated therefrom. Sets of time-aligned values of the pre-distorted signal v and the feedback signal yn are provided to theadaption circuit 118. - The
adaption circuit 118 generates predistortion parameters {circumflex over (θ)}k for theDPD circuit 102 from the feedback signal yn and pre-distorted signal v. In some examples, the predistortion parameters {circumflex over (θ)}k include a set of coefficients that may be used by theDPD circuit 102 to implement a polynomial approximation of the inverse model of thePAs DPD circuit 102. Also, in some examples, the predistortion parameters {circumflex over (θ)}k include a lookup table (LUT) that is applied by theDPD circuit 102 to generate the pre-distorted signal v. -
FIG. 2 is a flowchart showing one example of a process flow 200 that may be executed in theenvironment 100 to train theDPD circuit 102. At operation 202, the feedback switching circuit is configured to provide a feedback signal from afirst power amplifier PA 104A is provided first, however, anysuitable PA operation 204, thecapture buffer 114 captures values of the feedback signal y1 and corresponding values of the pre-distorted signal v. The feedback signal y1 may be taken at the output of theDPD circuit 102 as shown inFIG. 1 or in, some examples, may be taken from the input of theDPD circuit 102 in a direct adaption arrangement. - At
operation 206, theadaption circuit 118 generates and/or updates predistortion correlation data. For example, theadaption circuit 118 may utilize the feedback signal yi and the corresponding values of the pre-distorted signal v to generate a basis matrix Y1 and an error vector ϵgmp1. The basis matrix Y1 describes features of theDPD circuit 102 chosen to reflect the dynamic composition of the inverse PA behavior, such as; past and present linear terms and past and present nonlinear terms. The error vector ϵgmp1 is an indication of the error between the estimated inverse PA response and the actual DPD output v. and the corresponding values of the pre-distorted signal v. - The
adaption circuit 118 uses the basis matrix Y1 and an error vector ϵgmp1 to generate predistortion correlation data. The predistortion correlation data may include an autocorrelation matrix Ryy and a cross-correlation vector ryϵ. The autocorrelation matrix Ryy indicates a correlation between the various features of the basis matrix Y1. In some examples, the autocorrelation vector Ryy is given by Equation [1] below: -
R yy =R yy +Y H Y [1] - In Equation [1], an inner product is taken between the autocorrelation matrix (in this example Y1) and the Hermitian transpose of the autocorrelation matrix (indicated by the operator “H”). The result of the inner product is added to a previous iteration of the autocorrelation matrix Ryy. When the
operation 206 is executed for the first time, the previous version of the autocorrelation matrix Ryy may be set to the null matrix (e.g., a matrix of zeros). In some examples, the autocorrelation matrix is a square matrix having an order based on the number of features in the basis matrix Y. For example, if the basis matrix Y has twenty features, then the autocorrelation matrix Ryy may be a 20×20 matrix. - The cross-correlation vector ryϵ indicates a correlation between the basis matrix Y and the error vector ϵgmp. In some examples, the cross-correlation vector ryϵ is given by Equation [2] below:
-
r yϵ =r yϵ +Y Hϵ [2] - According to Equation [2], an inner product is taken between the Hermitian transpose of the basis matrix Y and the error vector ϵgmp. The result is added to a previous iteration of the cross-correlation vector ryϵ. When the
operation 206 is executed for the first time, the previous iteration of the cross-correlation vector ryϵ may be set to the null vector. The result of theoperation 206 may be generated and/or updated predistortion correlation data including, for example, a value for the autocorrelation matrix Ryy and a value for the cross-correlation vector or ryϵ. - At
operation 208, it is determined whether there are anyadditional PAs PAs additional PAs feedback switching circuit 110 is configured to provide a feedback signal from anext power amplifier operation 204, thecapture buffer 114 captures values of the feedback signal yn from thenext PA - Returning to
operation 206, theadaption circuit 118 generates updated predistortion correlation data. For example, theadaption circuit 118 may utilize Equations [1] and [2] above to generate an updated autocorrelation matrix Ryy and an updated cross-correlation vector ryϵ, where the previous versions of Ryy and ryϵ are as determined the previous time that theoperation 206 was executed. - If at
operation 208 it is determined that allPAs operation 204 and corresponding updates to the predistortion correlation data made atoperation 206, then operation 212 may follow. At operation 212, theadaption circuit 118 utilizes a linear solver to generate predistortion parameters {circumflex over (θ)}k for theDPD circuit 102 using the updated predistortion correlation data. Equation [3] below provides an example that may be implemented by theadaption circuit 118 to generate the predistortion parameters {circumflex over (θ)}k: -
{circumflex over (θ)}k={circumflex over (θ)}k−1 +μ{R yy +λI} −1 r yϵ [3] - In Equation [3], {circumflex over (θ)}k−1 is the previous iteration of the predistortion parameters. The value μ is a real scaler that may be chosen to trade off noise immunity against the adaption rate (e.g., the rate at which the
DPD circuit 102 is updated). The term λ is a scaler that is a regularization factor that may be chosen to improve the numerical conditioning of the calculations and minimize over fitting. I is the identity matrix of appropriate dimension. - At
operation 214, theadaption circuit 118 determines whether the solution attempted at operation 212 has converged. If there is no convergence, theadaption circuit 118 may return tooperation 204 to re-sample thePAs PAs operation 216. - In some examples, the techniques described herein can be applied to arrangements where the transmission medium exhibits frequency-dependent attenuation. One example of such a medium is coaxial cable. Cable exhibits a high-frequency roll-off characteristic in which higher frequencies are attenuated at higher levels than lower frequencies. In some examples, cables exhibit about 2 dB of signal amplitude reduction per 100 MHz of frequency, such as at frequencies above 50 MHz. To compensate for this, a tilt filter is added, for example, after a digital-to-analog converter (DAC). The tilt filter applies an “uptilt” frequency characteristic to the pre-distorted signal. The tilt frequency characteristic amplifies higher frequency portions of the signal that are attenuated by the cable so as to reduce frequency-dependent distortions at the signal destination. In some examples, the tilt frequency characteristic increases in gain by frequency according to a tilt slope, with the signal amplitude increasing as frequency increases.
- When a tilt filter is used, for example, in a cable implementation, the DPD circuit may also include a tilt reference filter and a tilt equalizer circuit. The tilt reference filter (positioned to operate on the input signal prior to predistortion) and the tilt equalizer circuit (positioned to operate on the pre-distorted signal) place a tilt characteristic onto the pre-distorted signal, for example, prior to the tilt filter. The tilt characteristic attenuates higher frequency portions of the signal. In some examples, the inverse tilt characteristic decreases in gain by frequency according to a tilt slope, which may be the inverse of the tilt slope up the tilt filter.
- The example illustrated by
FIGS. 1 and 2 shows an indirect learning algorithm where the training error ϵgmp is the difference between the actual output of theDPD circuit 102 and the inverse model of thePAs DPD circuit 102 and the observed output. In various examples, a direct or indirect learning algorithm may be used with the other examples described herein, as appropriate.FIG. 3 is a diagram showing one example of anenvironment 300 including aDPD circuit 302 for drivingmultiple PAs 304 C 304N for transmitting overcable media environment 300, atilt filter circuit 321 applies tilt filter characteristics to therespective PAs FIG. 3 , a firststage tilt filter 324 provides a first stage tilt filter characteristic common to all of thePAs stage tilt filter 324 and apply second stage tilt filter characteristics that are, for example, selected to correspond to the frequency-dependent attenuation characteristics of therespective cable media stage tilt filter 324 is omitted. In other examples, additional stages may be used. Thetilt filter circuit 321, in some examples, is implemented utilizing analog components to achieve the desired characteristic. - In the example of
FIG. 3 , theenvironment 300 also includes a tiltreference filter circuit 320 andtilt equalizer circuit 322. The tiltreference filter circuit 320 andtilt equalizer circuit 322 place a tilt characteristic onto the pre-distorted signal v to compensate for the effect of thetilt filter circuit 321. For example, thetilt filter circuit 321 imposes a linear distortion to the signal provided to therespective PAs reference filter circuit 320, positioned between theoptional DUC 306 and theDPD circuit 302 corrects for this linear distortion, for example, by attempting to replicate it in the digital domain. Thetilt equalizer circuit 322, positioned between theDPD circuit 302 and theDAC 308, may be the inverse of the tiltreference filter circuit 320. In some examples, thetilt reference filter 320 andtilt equalizer circuit 322 are implemented using one or more digital signal processors (DSPs) or other suitable hardware arrangement, such as thearchitecture 1100 described herein below. - As with the
DPD circuit 302 itself, it is desirable in some examples to train the tiltreference filter circuit 320 andtilt equalizer circuit 322 to match the nonlinearities of the respective output processing paths to therespective PAs reference filter circuit 320 andtilt equalizer circuit 322 to operate with multiple output processing paths can present issues similar to those encountered when training theDPD circuit 302 to operate withmultiple PAs - The example arrangement of
FIG. 3 shows an example way to address the training of the tiltreference filter circuit 320 andtilt equalizer circuit 322 for use with multiple output processing paths tomultiple PAs feedback switching circuit 310 is configured to selectively sample feedback signals yn from thePAs feedback ADC 312, capture buffers 314A, 314B andtime alignment circuit 316 may work in a manner similar tofeedback ADC 112,capture buffer 114, andtime alignment circuit 116 to provide time-aligned signals to anadaption circuit 318. Theadaptation circuit 318 may comprise a PAinverse model 330 for generating predistortion parameters {circumflex over (θ)}k, atilt equalizer model 332 for generating tilt equalizer parameters {circumflex over (θ)}equk for thetilt equalizer circuit 322 and atilt reference model 328 for generating tilt reference parameters. In some examples, theadaption circuit 318 is implemented using a processor arrangement, for example, similar to thearchitecture 1100 described herein below.Time alignment circuit 316 andbuffer circuits architecture 1100. In some examples, thetime alignment 316 andbuffer circuits -
FIG. 4 is a diagram showing one example of theenvironment 300 ofFIG. 3 configured to generate predistortion parameters {circumflex over (θ)}k. The example arrangement ofFIG. 4 shows the PAinverse model 330 including afeature generation circuit 408 to generate basis matrix Y and an inversemodel error circuit 410 to generate error vector ϵgmp, for example, as described herein. In the arrangement shown inFIG. 4 , theDPD circuit 302 may be trained according to the process flow 200 described herein. For example, thefeature generation circuit 408 may generate basis matrix Y based on the respective feedback signals from thePAs model error circuit 410 may generate error vectors ϵgmp based on the estimated inverse model of the measured output of each of thePAs correlation engine 402 may generate correlation data, for example, according to Equations [1] and [2] above. Alinear solver circuit 404 may be configured to generate the predistortion parameters {circumflex over (θ)}k, for example, according to Equation [3] described above. -
FIG. 5 is a diagram showing one example of theenvironment 300 ofFIG. 3 configured to generate tilt reference parameters {circumflex over (θ)}ref for the tiltreference filter circuit 320. The example arrangement ofFIG. 5 shows thetilt reference model 328 including afeature generation circuit 504 to generate basis matrix Y and an inversemodel error circuit 502 to generate error vectors ϵref.FIG. 6 is a flowchart showing one example of aprocess flow 600 that may be executed in the environment, for example, in the arrangement shown inFIG. 5 , to generate tilt reference parameters reference parameters {circumflex over (θ)}ref. - At operation 602, the
PAs DPD circuit 302 turned off. Biasing thePAs PAs PAs PAs DPD circuit 302 may include, for example, bypassing theDPD circuit 302, removing power to theDPD circuit 302 and/or otherwise removing it from the circuit. This is illustrated inFIG. 5 by the absence of theDPD circuit 302. As shown, the output of the tiltreference filter circuit 320 is provided directly to thetilt equalizer circuit 322. - At
operation 604, thefeedback switching circuit 310 is configured to provide a feedback signal y1 from afirst power amplifier capture buffer 314B (e.g., via the feedback ADC 312). This description will assume that the feedback signal y1 from thePA 304A is provided first, however, as described herein anysuitable PA operation 606, the capture buffers 314A, 314B capture values of the feedback signal y1 and corresponding values of the tiltreference filter circuit 320. For example, values of the feedback signal y1 may be captured at thecapture buffer 314B and values of the output of the tiltreference filter circuit 320 may be captured at thecapture buffer 314A. In some examples, theadaption circuit 318 can be arranged to perform indirect adaption for the tiltreference filter circuit 320. For example, theadaption circuit 318 may be configured to capture feedback from an input to the tilt reference filter 320 (e.g., instead of or in addition to capturing feedback from the output as shown inFIG. 5 ). - At
operation 608, theadaption circuit 318 generates and/or updates tilt reference correlation data. For example, theadaption circuit 318 may utilize the feedback signal y1 and the corresponding values of the output of the tiltreference filter circuit 320 to generate a basis matrix Y1 and an error vector ϵref1. The basis matrix Y1 describes features of theDPD circuit 102 to minimize the error between the feedback signal y1 and the corresponding values of the tiltreference filter circuit 320 output. The error vector ϵref1 is an indication of the error between the feedback signal y1 and the corresponding values of the output of the tiltreference filter circuit 320. - The
adaption circuit 318 uses the basis matrix Y1 and an error vector ϵref1 to generate tilt reference correlation data. The tilt reference correlation data can be generated, for example, by thecorrelation engine 402. The tilt reference correlation data may include an autocorrelation matrix Ryy and a cross-correlation vector ryϵ. The autocorrelation matrix Ryy indicates a correlation between the various features of the basis matrix Y1. In some examples, the autocorrelation vector Ryy is given by Equation [1] above. The cross-correlation vector ryϵ indicates a correlation between the basis matrix Y and the error vector ϵref, for example, as given by Equation [2] above. - At
operation 610, it is determined whether there are anyadditional PAs PAs process flow 600. If there are anyadditional PAs feedback switching circuit 310 is configured atoperation 612 to provide a feedback signal from anext power amplifier capture buffer 314B (e.g., via the feedback ADC 312). Atoperation 606, thecapture buffer 314B captures values of the feedback signal yn from thenext PA reference filter circuit 320. - Returning to
operation 608, theadaption circuit 318 generates updated tilt reference correlation data. For example, theadaption circuit 318 may utilize Equations [1] and [4] above to generate an updated autocorrelation matrix Ryy and an updated cross-correlation vector ryϵ, where the previous versions of Ryy and ryϵ are as determined the previous time that theoperation 608 was executed. - If, at
operation 610 it is determined that allPAs operation 606 and corresponding updates to the tilt reference correlation data made atoperation 608, thenoperation 614 may follow. Atoperation 614, theadaption circuit 318 utilizes thelinear solver 404 to generate tilt reference parameters {circumflex over (θ)}ref for the tiltreference filter circuit 320 using the updated tilt reference correlation data, for example, by optimizing Equation [4] below provides an example that may be implemented by theadaption circuit 318 to generate the tilt reference parameters {circumflex over (θ)}ref: -
{circumflex over (θ)}ref={circumflex over (θ)}ref−1 +μ{R yy +λI} −1 r yϵ [4] - In Equation [5], {circumflex over (θ)}ref−1 is the previous iteration of the tilt reference parameters. The values μ and λ may be as described with respect to Equation [3] above.
- At
operation 616, theadaption circuit 318 determines whether the solution attempted atoperation 614 has converged. If there is no convergence, theadaption circuit 318 may return tooperation 604 to re-sample thePAs reference filter circuit 320. TheDPD circuit 302 may be re-activated and the environment may proceed with use of thePAs operation 618. -
FIG. 7 is a diagram showing one example of theenvironment 300 ofFIG. 3 configured to generate tilt equalizer parameters {circumflex over (θ)}equ for thetilt equalizer circuit 322. The example arrangement ofFIG. 7 shows thetilt equalizer model 332 including afeature generation circuit 704 to generate a basis matrix Y and an inversemodel error circuit 702 to generate error vectors ϵequ.FIG. 8 is a flowchart showing one example of a process flow 800 that may be executed in the environment, for example, in the arrangement shown inFIG. 7 , to generate tilt equalizer parameters, {circumflex over (θ)}equ. - At operation 802, the
PAs DPD circuit 302 turned off. Atoperation 804, thefeedback switching circuit 310 is configured to provide a feedback signal yi from afirst power amplifier capture buffer 314B (e.g., via the feedback ADC 312). This description will assume that the feedback signal y1 from thePA 304A is provided first; however, as described herein anysuitable PA operation 806, the capture buffers 314A, 314B capture values of the feedback signal y1 and corresponding values of thetilt equalizer circuit 322 input. For example, values of the feedback signal y1 may be captured at thecapture buffer 314B and values of the output from thetilt equalizer circuit 322 may be captured at thecapture buffer 314A. In some examples, theadaption circuit 318 can be arranged to perform indirect adaption for thetilt equalizer circuit 322. For example, theadaption circuit 318 may be configured to capture feedback from an input to the tilt equalizer circuit 322 (e.g., instead of or in addition to capturing feedback from the output as shown inFIG. 7 ). - At
operation 808, theadaption circuit 318 generates and/or updates tilt equalizer correlation data. For example, theadaption circuit 318 may utilize the feedback signal y1 and the corresponding values of the output of thetilt equalizer circuit 322 to generate a basis matrix Y1 and an error vector ϵequ1. The basis matrix Y1 describes (linear) features to minimize the error between the feedback signal y1 and the corresponding values of the output of thetilt equalizer circuit 322. The error vector ϵequ1 is an indication of the error between the feedback signal yi and the corresponding values of the output of thetilt equalizer circuit 322. In some examples, the basis matrix Y1 for generating thetilt equalizer circuit 322 andtilt reference circuit 320 parameters include linear terms while the basis matrix Y1 for generatingDPD circuit 302 parameters may include linear and/or non-linear terms. - The
adaption circuit 318 uses the basis matrix Y1 and an error vector ϵequ1 to generate tilt equalizer correlation data. The tilt equalizer correlation data can be generated, for example, by thecorrelation engine 402. The tilt equalizer correlation data may include an autocorrelation matrix Ryy and a cross-correlation vector ryϵ, as described herein. The autocorrelation matrix Ryy indicates a correlation between the various features of the basis matrix Y1. In some examples, the autocorrelation vector Ryy is given by Equation [1] above. The cross-correlation vector ryϵ indicates a correlation between the basis matrix Y and the error vector ϵequ1. In some examples, the cross-correlation vector ryϵ is given by Equation [2] above. - At
operation 810, it is determined whether there are anyadditional PAs PAs additional PAs feedback switching circuit 310 is configured atoperation 812 to provide a feedback signal from anext power amplifier capture buffer 314B (e.g., via the feedback ADC 312). Atoperation 806, thecapture buffer 314B captures values of the feedback signal yn from thenext PA tilt equalizer circuit 322. - Returning to
operation 808, theadaption circuit 318 generates updated equalizer correlation data. For example, theadaption circuit 318 may utilize Equations [1] and [4] above to generate an updated autocorrelation matrix Ryy and an updated cross-correlation vector ryϵ, where the previous versions of Ryy and ryϵ are as determined the previous time that theoperation 808 was executed. - If at
operation 810 it is determined that allPAs operation 806 and corresponding updates to the tilt equalizer correlation data made atoperation 808, thenoperation 814 may follow. Atoperation 814, theadaption circuit 318 utilizes thelinear solver 404 to generate tilt equalizer parameters {circumflex over (θ)}equ for thetilt equalizer circuit 322 using the updated tilt equalizer correlation data, for example, by optimizing Equation [5] below provides an example that may be implemented by theadaption circuit 318 to generate the tilt equalizer parameters {circumflex over (θ)}equ: -
{circumflex over (θ)}equ={circumflex over (θ)}equ−1 +μ{R yy +λI} −1 r yϵ [5] - In Equation [5], {circumflex over (θ)}equ−1 is the previous iteration of the tilt equalizer parameters. The values μ and λ may be as described with respect to Equation [3] above.
- At
operation 816, theadaption circuit 318 determines whether the solution attempted atoperation 814 has converged. If there is no convergence, theadaption circuit 318 may return tooperation 804 to re-sample thePAs tilt equalizer circuit 322. TheDPD circuit 302 may be re-activated and the environment may proceed with use of thePAs operation 818. In some examples, thetilt equalizer circuit 322 and tiltreference filter circuit 320 are trained independently of theDPD circuit 302. For example, the tilt reference filter parameters {circumflex over (θ)}equ and tilt reference parameters {circumflex over (θ)}ref may be determined first, for example, as illustrated and described with respect toFIGS. 5-8 . After the tiltreference filter circuit 320 andtilt equalizer circuit 322 are trained, theDPD circuit 302 may be trained, for example, as described herein. -
FIG. 9 shows fourplots PAs FIGS. 3-8 . Plot 902 shows signal strength in decibels (dB) versus frequency for a first PA, such asPA 304A. Plot 904 shows signal strength in dB versus frequency for a second PA, such asPA 304B. Plot 906 shows signal strength in dB versus frequency for a third PA, such asPA 304C. Plot 908 shows signal strength in dB versus frequency for a fourth PA, such asPA 304N. Theplots tilt circuit 321 as the displayed signals are higher at higher frequency to compensate for the higher attenuation of thecable media single DPD circuit 302. -
FIG. 10 is a diagram showing one example of anenvironment 1000 including anarray 1034 of PAs and anarray DPD circuit 1002. In the environment 1000 a single input signal (e.g., processed by the optional DUC 1006) is provided to thearray DPD circuit 1002. Thearray DPD circuit 1002 generates a pre-distorted signal v. ADAC 1008 converts the pre-distorted signal v to an analog pre-distorted signal v. Amixer 1030 andmixer array 1032 mix the pre-distorted signal v with an array of values for a given downtilt angle θ and a horizontal scan angle φ to modify the amplitude and phase of the pre-distorted signal v. Themixer 1030 may be or include a frequency translation mixer that takes a lower-centered frequency signal (e.g., IF, such as about 100 MHz) and coverts it to a higher-centered frequency signal (e.g., about 30 GHz). The result of themixer 1030 andmixer array 1032 may be a set of amplitude-modified and phase-shifted pre-distorted signals v, with each distinct signal being shifted by a phase and amplitude to bring about atransmission beam 1038 of a desired shape and direction. The phase-shifted and amplitude-modified pre-distorted signals are provided to PAs of aPA array 1034. The PAs of the PA array amplify their respective received signals, which are provided to separate antennas of anantenna array 1036. The phase shifting and amplitude modifying of the inputs to the PAs of the PA array result in abeam 1038 having the desired downtilt angle θ and horizontal scan angle φ. - In the arrangement of
FIG. 10 , thearray DPD circuit 1002 may be trained in a manner similar to that described herein with respect toFIGS. 1 and 2 . For example, afeedback switching circuit 1010 is configured to sequentially provide feedback signals yn from the PAs of thePA array 1034 to anadaption circuit 1018 via a,mixer 1042, andfeedback ADC 1012. Themixer 1042, for example, man down-convert the feedback signals yn, for example, as the inverse of themixer 1030. - The
adaption circuit 1018 may receive the feedback signals yn and the digital pre-distorted signal v from the output of thearray DPD circuit 1002. Theadaption circuit 1018 may perform time alignment to match or time align values of the feedback signal yn to corresponding values of the pre-distorted signal v. Theadaption circuit 1018 generates predistortion parameters {circumflex over (θ)}k for thearray DPD circuit 1002 from the feedback signal yn and pre-distorted signal v, for example, as described herein with respect toFIG. 2 . -
FIG. 11 is a block diagram illustrating a computingdevice hardware architecture 1100, within which a set or sequence of instructions can be executed to cause a machine to perform examples of any one of the methodologies discussed herein. For example, thearchitecture 1100 may describe one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or similar hardware that may be used, in some examples, to implement any of the circuits described herein. For example, theDPD circuit 102,adaption circuit 118 may be implemented using all or portions of a hardware architecture such as thearchitecture 1100. Thecapture buffer 114 andtime alignment circuit 116, in some examples, may also be implemented using all or portions of a hardware architecture such as thearchitecture 1100. - The
architecture 1100 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, thearchitecture 1100 may operate in the capacity of either a server or a client machine in server-client network environments, or it may act as a peer machine in peer-to-peer (or distributed) network environments. Thearchitecture 1100 can be implemented in an embedded system, a personal computer (PC), a tablet PC, a hybrid tablet, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, a network switch, a network bridge, or any machine capable of executing instructions (sequential or otherwise) that specify operations to be taken by that machine. - The
example architecture 1100 includes aprocessor unit 1102 comprising at least one processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or both, processor cores, compute nodes). Thearchitecture 1100 may further comprise amain memory 1104 and astatic memory 1106, which communicate with each other via a link 1108 (e.g., a bus). Thearchitecture 1100 can further include a video display unit 1110, an input device 1112 (e.g., a keyboard), and a UI navigation device 1114 (e.g., a mouse). In some examples, the video display unit 1110,input device 1112, andUI navigation device 1114 are incorporated into a touchscreen display. Thearchitecture 1100 may additionally include a storage device 1116 (e.g., a drive unit), a signal generation device 1118 (e.g., a speaker), anetwork interface device 1120, and one or more sensors (not shown), such as a Global Positioning System (GPS) sensor, compass, accelerometer, or other sensor. - In some examples, the
processor unit 1102 or another suitable hardware component may support a hardware interrupt. In response to a hardware interrupt, theprocessor unit 1102 may pause its processing and execute an ISR, for example, as described herein. - The
storage device 1116 includes a machine-readable medium 1122 on which is stored one or more sets of data structures and instructions 1124 (e.g., software) embodying or used by any one or more of the methodologies or functions described herein. Theinstructions 1124 can also reside, completely or at least partially, within themain memory 1104, within thestatic memory 1106, and/or within theprocessor unit 1102 during execution thereof by thearchitecture 1100, with themain memory 1104, thestatic memory 1106, and theprocessor unit 1102 also constituting machine-readable media. - The various memories (i.e., 1104, 1106, and/or memory of the processor unit(s) 1102) and/or the
storage device 1116 may store one or more sets of instructions and data structures (e.g., the instructions 1124) embodying or used by any one or more of the methodologies or functions described herein. These instructions, when executed by the processor unit(s) 1102, cause various operations to implement the disclosed examples. - As used herein, the terms “machine-storage medium,” “device-storage medium,” and “computer-storage medium” (referred to collectively as “machine-storage medium”) mean the same thing and may be used interchangeably. The terms refer to a single or multiple storage devices and/or media (e.g., a centralized or distributed database, and/or associated caches and servers) that store executable instructions and/or data, as well as cloud-based storage systems or storage networks that include multiple storage apparatus or devices. The terms shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media, including memory internal or external to processors. Specific examples of machine-storage media, computer-storage media, and/or device-storage media include non-volatile memory, including by way of example semiconductor memory devices, e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), field-programmable gate array (FPGA), and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The terms “machine-storage media,” “computer-storage media,” and “device-storage media” specifically exclude carrier waves, modulated data signals, and other such media, at least some of which are covered under the term “signal medium” discussed below.
- The term “signal medium” or “transmission medium” shall be taken to include any form of modulated data signal, carrier wave, and so forth. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal.
- The terms “machine-readable medium,” “computer-readable medium” and “device-readable medium” mean the same thing and may be used interchangeably in this disclosure. The terms are defined to include both machine-storage media and signal media. Thus, the terms include both storage devices/media and carrier waves/modulated data signals.
- The
instructions 1124 can further be transmitted or received over acommunications network 1126 using a transmission medium via thenetwork interface device 1120 using any one of a number of well-known transfer protocols (e.g., Hypertext Transfer Protocol (HTTP)). Examples of communication networks include a local area network (LAN), a wide area network (WAN), the Internet, mobile telephone networks, plain old telephone service (POTS) networks, and wireless data networks (e.g., Wi-Fi, 3G, 4G Long-Term Evolution (LTE)/LTE-A, 5G, or WiMAX networks). - Example 1 is a system for operating a plurality of power amplifiers, the system comprising: a predistortion circuit configured to pre-distort an input signal according to a predistortion configuration to generate a pre-distorted signal for the plurality of power amplifiers; and an adaption circuit, configured to perform operations comprising: receiving a first feedback signal from a first power amplifier of the plurality of power amplifiers; generating predistortion correlation data describing a correlation between parameters of a model describing the plurality of power amplifiers; receiving a first feedback signal from a second power amplifier of the plurality of power amplifiers; updating the predistortion correlation data to generate updated predistortion correlation data, the updating using the first feedback signal from the second power amplifier; and generating the predistortion configuration using the updated predistortion correlation data.
- In Example 2, the subject matter of Example 1 optionally includes wherein generating the predistortion correlation data comprises: generating a first basis matrix using the first feedback signal of the first power amplifier and the pre-distorted signal; generating a first error vector using the first feedback signal of the first power amplifier and the pre-distorted signal; generating an autocorrelation matrix using the first basis matrix; and generating a cross-correlation vector using the first error vector.
- In Example 3, the subject matter of Example 2 optionally includes wherein updating the predistortion correlation data comprises: generating a second basis matrix using the first feedback signal of the second power amplifier and the pre-distorted signal; generating a second error vector using the first feedback signal of the second power amplifier and the pre-distorted signal; generating an updated autocorrelation matrix using the second basis matrix and the autocorrelation matrix; and generating an updated cross-correlation vector using the second error vector and the cross-correlation vector.
- In Example 4, the subject matter of Example 3 optionally includes wherein generating the predistortion configuration is based at least in part on the updated autocorrelation matrix and the updated cross-correlation vector.
- In Example 5, the subject matter of any one or more of Examples 3-4 optionally includes wherein generating the predistortion configuration is based at least in part on a previous predistortion configuration, the updated autocorrelation matrix, and the updated cross-correlation vector.
- In Example 6, the subject matter of any one or more of Examples 1-5 optionally includes a tilt equalizer circuit electrically coupled to the predistortion circuit to apply a frequency characteristic to the pre-distorted signal according to a tilt equalizer configuration, the operations further comprising: receiving a second feedback signal from the first power amplifier, the second feedback signal from the first power amplifier taken while the first power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; generating tilt equalizer correlation data describing a correlation between the plurality of power amplifiers and a tilt equalizer input signal using the second feedback signal of the first power amplifier; receiving a second feedback signal from the second power amplifier, the second feedback signal from the second power amplifier taken while the second power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; updating the tilt equalizer correlation data to generate updated tilt equalizer correlation data, the updating using the second feedback signal of the second power amplifier; and generating the tilt equalizer configuration for the tilt equalizer circuit using the updated tilt equalizer correlation data.
- In Example 7, the subject matter of any one or more of Examples 1-6 optionally includes a tilt reference circuit electrically coupled prior to the predistortion circuit to apply a frequency characteristic to the pre-distorted signal according to a tilt reference configuration, the operations further comprising: receiving a third feedback signal of the first power amplifier, the third feedback signal from the first power amplifier taken while the first power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; generating, by the adaption circuit, tilt reference correlation data describing a correlation between the plurality of power amplifiers and a tilt reference input signal using the third feedback signal of the first power amplifier; receiving a third feedback signal of the second power amplifier, the third feedback signal from the second power amplifier taken while the second power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; updating, by the adaption circuit, the tilt reference correlation data to generate updated tilt reference correlation data, the updating using the third feedback signal of the second power amplifier; and generating, by the adaption circuit, a first tilt reference configuration for the tilt reference circuit using the updated tilt reference correlation data.
- In Example 8, the subject matter of any one or more of Examples 1-7 optionally includes a beamforming circuit is positioned between the predistortion circuit and the first power amplifier, wherein the beamforming circuit is configured to perform operations comprising: applying a first amplitude modification and a first phase shift to the pre-distorted signal to generate a first modified pre-distorted signal; applying a second amplitude modification and a second phase shift to the pre-distorted signal to generate a second modified pre-distorted signal; providing the first modified pre-distorted signal to the first power amplifier; and providing the second modified pre-distorted signal to the second power amplifier.
- Example 9 is a method for operating a predistortion circuit with a plurality of power amplifiers, the method comprising: configuring an adaption circuit to receive a first feedback signal from a first power amplifier of the plurality of power amplifiers; generating, by the adaption circuit, predistortion correlation data describing a correlation between parameters of a model describing the plurality of power amplifiers; configuring the adaption circuit to receive a first feedback signal from a second power amplifier of the plurality of power amplifiers; updating the predistortion correlation data, by the adaption circuit, to generate updated predistortion correlation data, the updating using the first feedback signal from the second power amplifier; generating, by the adaption circuit, a predistortion configuration for the predistortion circuit using the updated predistortion correlation data; generating, by the predistortion circuit, a pre-distorted signal based at least in part on the predistortion configuration; and providing the pre-distorted signal to the plurality of power amplifiers.
- In Example 10, the subject matter of Example 9 optionally includes wherein generating the predistortion correlation data comprises: generating a first basis matrix using the first feedback signal of the first power amplifier and the pre-distorted signal; generating a first error vector using the first feedback signal of the first power amplifier and the pre-distorted signal; generating an autocorrelation matrix using the first basis matrix; and generating a cross-correlation vector using the first error vector.
- In Example 11, the subject matter of Example 10 optionally includes wherein updating the predistortion correlation data comprises: generating a second basis matrix using the first feedback signal of the second power amplifier and the pre-distorted signal; generating a second error vector using the first feedback signal of the second power amplifier and the pre-distorted signal; generating an updated autocorrelation matrix using the second basis matrix and the autocorrelation matrix; and generating an updated cross-correlation vector using the second error vector and the cross-correlation vector.
- In Example 12, the subject matter of Example 11 optionally includes wherein generating the predistortion configuration is based at least in part on the updated autocorrelation matrix and the updated cross-correlation vector.
- In Example 13, the subject matter of any one or more of Examples 11-12 optionally includes wherein generating the predistortion configuration is based at least in part on a previous predistortion configuration, the updated autocorrelation matrix, and the updated cross-correlation vector.
- In Example 14, the subject matter of any one or more of Examples 9-13 optionally includes configuring a tilt equalizer circuit electrically coupled between the predistortion circuit and the plurality of power amplifiers, the configuring of the tilt equalizer comprising: biasing the plurality of power amplifiers to operate in a linear mode; deactivating the predistortion circuit; configuring the adaption circuit to receive a second feedback signal from the first power amplifier; generating, by the adaption circuit, tilt equalizer correlation data describing a correlation between the plurality of power amplifiers and a tilt equalizer input signal using the second feedback signal of the first power amplifier; configuring the tilt equalizer circuit to receive a second feedback signal from the second power amplifier; updating, by the adaption circuit, the tilt equalizer correlation data to generate updated tilt equalizer correlation data, the updating using the second feedback signal of the second power amplifier; and generating, by the adaption circuit, a first tilt equalizer configuration for the tilt equalizer using the updated tilt equalizer correlation data.
- In Example 15, the subject matter of any one or more of Examples 9-14 optionally includes configuring a tilt reference circuit electrically coupled prior to the predistortion circuit, the configuring of the tilt reference circuit comprising: biasing the plurality of power amplifiers to operate in a linear mode; deactivating the predistortion circuit; configuring the adaption circuit to receive a third feedback signal of the first power amplifier; generating, by the adaption circuit, tilt reference correlation data describing a correlation between the plurality of power amplifiers and a tilt reference input signal using the third feedback signal of the first power amplifier; configuring the tilt reference circuit to receive a third feedback signal of the second power amplifier; updating, by the adaption circuit, the tilt reference correlation data to generate updated tilt reference correlation data, the updating using the third feedback signal of the second power amplifier; and generating, by the adaption circuit, a first tilt reference configuration for the tilt reference circuit using the updated tilt reference correlation data.
- In Example 16, the subject matter of any one or more of Examples 9-15 optionally includes wherein a beamforming circuit is positioned between the predistortion circuit and the first power amplifier, further comprising: applying, by the beamforming circuit, a first amplitude modification and a first phase shift to the pre-distorted signal to generate a first modified pre-distorted signal; applying, by the beamforming circuit, a second amplitude modification and a second phase shift to the pre-distorted signal to generate a second modified pre-distorted signal; providing the first modified pre-distorted signal to the first power amplifier; and providing the second modified pre-distorted signal to the second power amplifier.
- Example 17 is a system for operating a plurality of power amplifiers, comprising: a first signal path for receiving a first feedback signal from a first power amplifier of the plurality of power amplifiers; means for generating predistortion correlation data describing a correlation between parameters of a model describing the plurality of power amplifiers; a second signal path for receiving a first feedback signal from a second power amplifier of the plurality of power amplifiers; means for updating the predistortion correlation data to generate updated predistortion correlation data, the updating using the first feedback signal from the second power amplifier; means for generating a predistortion configuration for a predistortion circuit using the updated predistortion correlation data; and means for generating a pre-distorted signal for providing to the plurality of power amplifiers based at least in part on the predistortion configuration.
- In Example 18, the subject matter of Example 17 optionally includes means for receiving a second feedback signal from the first power amplifier, the second feedback signal from the first power amplifier taken while the first power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; means for generating tilt equalizer correlation data describing a correlation between the plurality of power amplifiers and a tilt equalizer input signal provided to a tilt equalizer, the generating using the second feedback signal of the first power amplifier; means for receiving a second feedback signal from the second power amplifier, the second feedback signal from the second power amplifier taken while the second power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; means for updating the tilt equalizer correlation data to generate updated tilt equalizer correlation data, the updating using the second feedback signal of the second power amplifier; and means for generating a tilt equalizer configuration using the updated tilt equalizer correlation data.
- In Example 19, the subject matter of any one or more of Examples 17-18 optionally includes means for receiving a third feedback signal of the first power amplifier, the third feedback signal from the first power amplifier taken while the first power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; means for generating tilt reference correlation data describing a correlation between the plurality of power amplifiers and a tilt reference input signal using the third feedback signal of the first power amplifier; means for receiving a third feedback signal of the second power amplifier, the third feedback signal from the second power amplifier taken while the second power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated; means for updating the tilt reference correlation data to generate updated tilt reference correlation data, the updating using the third feedback signal of the second power amplifier; and means for generating a first tilt reference configuration using the updated tilt reference correlation data.
- In Example 20, the subject matter of any one or more of Examples 17-19 optionally includes means for applying a first amplitude modification and a first phase shift to the pre-distorted signal to generate a first modified pre-distorted signal; means for applying a second amplitude modification and a second phase shift to the pre-distorted signal to generate a second modified pre-distorted signal; means for providing the first modified pre-distorted signal to the first power amplifier; and means for providing the second modified pre-distorted signal to the second power amplifier.
- The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
- In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.
- In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
- Geometric terms, such as “parallel”, “perpendicular”, “round”, or “square”, are not intended to require absolute mathematical precision, unless the context indicates otherwise. Instead, such geometric terms allow for variations due to manufacturing or equivalent functions. For example, if an element is described as “round” or “generally round,” a component that is not precisely circular (e.g., one that is slightly oblong or is a many-sided polygon) is still encompassed by this description.
- The term “circuit” can include a dedicated hardware circuit, a general-purpose microprocessor, digital signal processor, or other processor circuit, and may be structurally configured from a general purpose circuit to a specialized circuit such as using firmware or software.
- Any one or more of the techniques (e.g., methodologies) discussed herein may be performed on a machine. In various embodiments, the machine may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine may operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine may act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.
- Examples, as described herein, may include, or may operate by, logic or a number of components, or mechanisms. Circuit sets are a collection of circuits implemented in tangible entities that include hardware (e.g., simple circuits, gates, logic, etc.). Circuit set membership may be flexible over time and underlying hardware variability. Circuit sets include members that may, alone or in combination, perform specified operations when operating. In an example, hardware of the circuit set may be immutably designed to carry out a specific operation (e.g., hardwired). In an example, the hardware of the circuit set may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a computer readable medium physically modified (e.g., magnetically, electrically, moveable placement of invariant massed particles, etc.) to encode instructions of the specific operation. In connecting the physical components, the underlying electrical properties of a hardware constituent are changed, for example, from an insulator to a conductor or vice versa. The instructions can enable embedded hardware (e.g., the execution units or a loading mechanism) to create members of the circuit set in hardware via the variable connections to carry out portions of the specific operation when in operation. Accordingly, the computer readable medium is communicatively coupled to the other components of the circuit set member when the device is operating. In an example, any of the physical components may be used in more than one member of more than one circuit set. For example, under operation, execution units may be used in a first circuit of a first circuit set at one point in time and reused by a second circuit in the first circuit set, or by a third circuit in a second circuit set at a different time.
- Particular implementations of the systems and methods described herein may involve use of a machine (e.g., computer system) that may include a hardware processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory and a static memory, some or all of which may communicate with each other via an interlink (e.g., bus). The machine may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, the display unit, input device and UI navigation device may be a touch screen display. The machine may additionally include a storage device (e.g., drive unit), a signal generation device (e.g., a speaker), a network interface device, and one or more sensors, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine may include an output controller, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).
- The storage device may include a machine readable medium on which is stored one or more sets of data structures or instructions (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions may also reside, completely or at least partially, within the main memory, within static memory, or within the hardware processor during execution thereof by the machine. In an example, one or any combination of the hardware processor, the main memory, the static memory, or the storage device may constitute machine readable media.
- While the machine readable medium can include a single medium, the term “machine readable medium” may include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) configured to store the one or more instructions.
- The term “machine readable medium” may include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine and that cause the machine to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting machine readable medium examples may include solid-state memories, and optical and magnetic media. In an example, a massed machine readable medium comprises a machine readable medium with a plurality of particles having invariant (e.g., rest) mass. Accordingly, massed machine-readable media are not transitory propagating signals.
- Specific examples of massed machine readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.
- The instructions may further be transmitted or received over a communications network using a transmission medium via the network interface device utilizing any one of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi®, IEEE 802.16 family of standards known as WiMax®), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, among others. In an example, the network interface device may include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to the communications network. In an example, the network interface device may include a plurality of antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term “transmission medium” shall be taken to include any intangible medium that is capable of storing, encoding or carrying instructions for execution by the machine, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software.
- Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.
- The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
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Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5808511A (en) | 1996-08-09 | 1998-09-15 | Trw Inc. | Active feedback pre-distortion linearization |
CN100578922C (en) | 2007-12-17 | 2010-01-06 | 华为技术有限公司 | High efficiency power amplifier |
US8374282B2 (en) | 2008-07-24 | 2013-02-12 | Motorola Mobility Llc | Method and apparatus for improving digital predistortion correction with amplifier device biasing |
WO2010054499A1 (en) | 2008-11-11 | 2010-05-20 | Telefonaktiebolaget L M Ericsson (Publ) | A dpd system with multiple transmitter paths |
US8154432B2 (en) | 2010-03-22 | 2012-04-10 | Raytheon Company | Digital to analog converter (DAC) having high dynamic range |
WO2013074890A1 (en) | 2011-11-17 | 2013-05-23 | Analog Devices, Inc. | System linearization |
US8829993B2 (en) | 2012-10-30 | 2014-09-09 | Eta Devices, Inc. | Linearization circuits and methods for multilevel power amplifier systems |
WO2014085097A1 (en) | 2012-11-27 | 2014-06-05 | Eta Devices, Inc. | Linearization circuits and methods for multilevel power amplifier systems |
US9564876B2 (en) | 2014-09-22 | 2017-02-07 | Nanosemi, Inc. | Digital compensation for a non-linear analog receiver |
US10480970B2 (en) | 2015-11-30 | 2019-11-19 | Analog Devices Global | Electromagnetic flow sensor interface allowing differential dc coupling |
KR102586418B1 (en) | 2016-03-23 | 2023-10-06 | 삼성전기주식회사 | Apparatus for pre-distorting high frequency signal and apparatus for compensating nonlinear distortion of power amplifier |
US10033413B2 (en) | 2016-05-19 | 2018-07-24 | Analog Devices Global | Mixed-mode digital predistortion |
US10224970B2 (en) | 2016-05-19 | 2019-03-05 | Analog Devices Global | Wideband digital predistortion |
US10686415B2 (en) | 2016-12-29 | 2020-06-16 | Patrick Pratt | Digital predistortion for multiple power amplifiers |
WO2018224161A1 (en) | 2017-06-09 | 2018-12-13 | Nokia Technologies Oy | Reducing distortions in amplified signals to be radiated by an antenna |
US10218318B2 (en) * | 2017-07-20 | 2019-02-26 | Arris Enterprises Llc | Amplifier with digital linearization and multiple output stages |
GB2569121A (en) * | 2017-12-05 | 2019-06-12 | Nokia Technologies Oy | Method, apparatus and arrangement for linearizing of a transmitter array |
US10320340B1 (en) * | 2018-01-11 | 2019-06-11 | Analog Devices Global Unlimited Company | Frequency-shaped digital predistortion |
CN109818585B (en) | 2018-12-25 | 2023-06-16 | 深圳三星通信技术研究有限公司 | Digital predistortion device and method |
US11133834B2 (en) * | 2019-03-07 | 2021-09-28 | Samsung Electronics Co., Ltd. | Device and method of compensating for nonlinearity of power amplifier |
US10715702B1 (en) * | 2019-03-12 | 2020-07-14 | Xilinx, Inc. | Method of and circuit for predistortion for a cable TV amplifier |
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