US20220399489A1 - Storage device - Google Patents
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- US20220399489A1 US20220399489A1 US17/549,236 US202117549236A US2022399489A1 US 20220399489 A1 US20220399489 A1 US 20220399489A1 US 202117549236 A US202117549236 A US 202117549236A US 2022399489 A1 US2022399489 A1 US 2022399489A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
- H10N70/235—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect between different crystalline phases, e.g. cubic and hexagonal
-
- H01L45/065—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H01L27/2481—
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- H01L45/144—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/10—Phase change RAM [PCRAM, PRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
- H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
Definitions
- Embodiments of the present invention relate to a storage device.
- a storage device of a new scheme which referred to as a “phase change memory”, has been developed as a storage device used for an information instrument such as a cellular phone.
- a storage device for example, a storage device that causes a phase change material to reversibly transition between a high-resistive non-crystal state and a low-resistive crystal state by applying a voltage pulse to the phase change material has been proposed.
- a storage device that changes the distribution of a specific element (for example, Ge) contained in a phase change material by applying a voltage pulse to the phase change material, thus changing the electric resistance of the phase change material has also been proposed.
- the electric resistance of the phase change material is stably maintained even after a power source is disconnected, and thus information corresponding to the electric resistance can be stored.
- FIG. 1 is a diagram schematically illustrating the configuration of a storage device according to a first embodiment
- FIG. 2 is a diagram illustrating the configuration of a memory cell array in FIG. 1 ;
- FIG. 3 is a diagram illustrating another exemplary configuration of the memory cell array in FIG. 1 ;
- FIG. 4 is a cross-sectional view illustrating the configuration of a memory cell and its vicinity in the storage device according to the first embodiment
- FIG. 5 is a diagram illustrating the crystal structure of an adjacent layer
- FIGS. 6 A and 6 B are each a diagram schematically illustrating distribution of germanium in a resistance change layer
- FIGS. 7 A and 7 B are each a diagram illustrating a voltage pulse applied to the resistance change layer and the adjacent layer;
- FIG. 9 is a diagram for explaining the method of manufacturing the storage device according to the first embodiment.
- FIG. 10 is a diagram for explaining the method of manufacturing the storage device according to the first embodiment
- FIG. 11 is a diagram for explaining the method of manufacturing the storage device according to the first embodiment
- FIG. 12 is a diagram schematically illustrating the configuration of a storage device according to a second embodiment.
- FIG. 13 is a diagram schematically illustrating the configuration of a storage device according to a third embodiment.
- a storage device 10 is an interface resistance random access phase change memory exploiting elemental segregation. As illustrated in FIG. 1 , the storage device 10 includes a memory cell array MCA, a word line driver 11 , a bit line driver 12 , and a control circuit 13 .
- the memory cell array MCA is a part including a plurality of memory cells MC in which data is stored.
- the storage device 10 is provided with a plurality of word lines 20 and a plurality of bit lines 30 . These lines are formed as a wiring layer for applying voltage to the memory cells MC.
- One end of each memory cell MC is connected to a word line 20 , and the other end is connected to a bit line 30 .
- each memory cell MC is provided at a position where the corresponding word line 20 and the corresponding bit line 30 intersect each other. Note that FIG. 1 illustrates only some of the plurality of memory cells MC included in the memory cell array MCA.
- Each memory cell MC includes a phase change layer 40 and a selector 60 . As illustrated with an equivalent circuit in FIG. 1 , the phase change layer 40 and the selector 60 are electrically connected in series between the corresponding word line 20 and the corresponding bit line 30 . Note that, although FIG. 1 illustrates that the phase change layer 40 is disposed on the bit line 30 side and the selector 60 is disposed on the word line 20 side, disposition of the phase change layer 40 and the selector 60 is not limited thereto. In each of some or all memory cells MC, disposition of the phase change layer 40 and the selector 60 may be opposite to the disposition in FIG. 1 .
- the phase change layer 40 is a layer formed of a phase change material and is a part that stores information corresponding to the value of its electric resistance.
- the phase change material is a chalcogenide material made of antimony telluride (Sb 2 Te 3 ).
- the material of the phase change layer 40 is not limited thereto but may be any other phase change material.
- the phase change material is preferably a compound containing at least tellurium.
- the electric resistance (specifically, electric resistance at a vicinity part of an interface with a diffusion layer 50 to be described later) of the phase change layer 40 changes when a predetermined voltage pulse is applied to the phase change layer 40 .
- the phase change layer 40 reversibly transitions between a first state in which the electric resistance is relatively high and a second state in which the electric resistance is relatively low in accordance with the waveform of the applied voltage pulse.
- Information (0 or 1) corresponding to the electric resistance of the phase change layer 40 is stored in each memory cell MC.
- the word line driver 11 is a circuit for adjusting the potential of each word line 20 .
- One end of each word line 20 is connected to the word line driver 11 .
- the word line driver 11 includes a non-illustrated switch group for switching opening and closing between each word line 20 and a voltage generation circuit (not illustrated). Operation of the word line driver 11 is controlled by the control circuit 13 to be described later.
- the control circuit 13 is a circuit configured to collectively control the entire operation of the storage device 10 .
- the control circuit 13 performs, for example, voltage pulse application to each memory cell MC by controlling operation of the word line driver 11 and the bit line driver 12 as described above.
- the control circuit 13 changes the electric resistance of the phase change layer 40 of each writing target memory cell MC to a value corresponding to writing data by applying a voltage pulse in accordance with the writing data to the memory cell MC.
- the control circuit 13 applies voltage to each reading target memory cell MC and reads data corresponding to the electric resistance value of the phase change layer 40 based on current flowing through the memory cell MC.
- FIG. 2 schematically illustrates the configuration of the memory cell array MCA. Note that FIG. 2 only illustrates the word lines 20 , the bit lines 30 , the memory cells MC, and a semiconductor substrate BP (to be described later) in the memory cell array MCA, and omits illustration of insulating layers 81 and 82 (refer to FIG. 4 ) formed in the vicinity of the memory cells MC and the like.
- an x axis is set in a direction in which the word lines 20 extend.
- a y axis is set in a direction in which the bit lines 30 extend
- a z axis is set in the up-down direction.
- the x axis, the y axis, and the z axis are orthogonal to each other.
- a direction along the x axis will be also referred to as an “x direction”.
- a direction along the y axis will be also referred to as a “y direction”.
- a direction along the z axis will be also referred to as a “z direction” below.
- the configuration of each component may be described by using the x axis, the y axis, the z axis, the x direction, the y direction, and the z direction as described above.
- the memory cell array MCA is formed on the upper side of the semiconductor substrate BP.
- the semiconductor substrate BP is, for example, a silicon substrate.
- Each word line 20 extends in the x direction as described above, and the plurality of word lines 20 are arranged in the y direction.
- Each bit line 30 extends in the y direction as described above, and the plurality of bit lines 30 are arranged in the x direction.
- the plurality of bit lines 30 are disposed in each of the parts on the lower and upper sides of the word lines 20 .
- the memory cells MC each provided at a part where a word line 20 and a bit line 30 intersect when viewed from the top are provided between each word line 20 and the corresponding bit line 30 on its lower side and between each word line 20 and the corresponding bit line 30 on its upper side.
- Each bit line 30 disposed on the lower side of a word line 20 will be also referred to as a “bit line 31 ” in the following description.
- Each bit line 30 disposed on the upper side of a word line 20 will be also referred to as a “bit line 32 ” in the following description.
- the plurality of bit lines 30 may be disposed only on the upper side of the word lines 20 as illustrated in FIG. 3 .
- the memory cells MC are provided only between each word line 20 and the corresponding bit line 30 on its upper side.
- FIG. 4 illustrates a section of a part corresponding to each cell memory MC and its vicinity, which is taken along a surface orthogonal to the x axis.
- FIG. 4 illustrates a section of a pair of memory cells MC disposed on the upper and lower sides of a word line 20 .
- the selector 60 and the phase change layer 40 in each memory cell MC are disposed side by side in the stated order in the z direction.
- the disposition order of the selector 60 and the phase change layer 40 in each memory cell MC may be opposite.
- the disposition order of the selector 60 and the phase change layer 40 in each memory cell MC on the upper side may be opposite to the disposition order of the selector 60 and the phase change layer 40 in each memory cell MC on the lower side.
- Each memory cell MC disposed on the lower side of a word line 20 will be also referred to as a “memory cell MC 1 ” in the following description.
- Each memory cell MC disposed on the upper side of a word line 20 will be also referred to as a “memory cell MC 2 ” in the following description.
- the phase change layer 40 and the selector 60 included in each memory cell MC 1 on the lower side will be also referred to as a “phase change layer 41 ” and a “selector 61 ”, respectively, in the following description.
- the phase change layer 40 and the selector 60 included in each memory cell MC 2 on the upper side will be also referred to as a “phase change layer 42 ” and a “selector 62 ”, respectively, in the following description.
- Each memory cell MC further includes the diffusion layer 50 adjacent to the phase change layer 40 in the z direction.
- the phase change layer 40 corresponds to a “resistance change layer” in the present embodiment
- the diffusion layer 50 corresponds to an “adjacent layer” in the present embodiment.
- the diffusion layer 50 included in each memory cell MC 1 on the lower side will be also referred to as a “diffusion layer 51 ” in the following description.
- the diffusion layer 50 included in each memory cell MC 2 on the upper side will be also referred to as a “diffusion layer 52 ” in the following description.
- each memory cell MC 1 includes the selector 61 , a conductive layer 72 , the phase change layer 41 , and the diffusion layer 51 in a configuration in which these components are stacked in the z direction sequentially from the lower side.
- the phase change layer 41 and the diffusion layer 51 are disposed side by side in the stated order in the z direction.
- the disposition order of the phase change layer 41 and the diffusion layer 51 in each memory cell MC 1 may be opposite.
- the disposition order of the phase change layer 42 and the diffusion layer 52 in each memory cell MC 2 on the upper side may be opposite to the disposition order of the phase change layer 41 and the diffusion layer 51 in each memory cell MC 1 on the lower side.
- the conductive layer 72 is a layer made of a metallic material the same as that of the conductive layer 71 and formed between the selector 61 and the phase change layer 41 .
- a Te-Te gap as a part denoted by the text “Gap” in FIG. 5 is formed along the x-y plane.
- a plurality of such Te-Te gaps are further arranged in the direction of the C axis (the z direction).
- the diffusion layer 51 is disposed at a position between the corresponding word line 20 and the phase change layer 41 and adjacent to the phase change layer 41 .
- the diffusion layer 51 is a layer containing a high-concentration diffusive material as described above, and germanium (Ge) is used as the diffusive material in the present embodiment.
- the diffusion layer 51 is formed to directly cover the upper surface of the phase change layer 41 .
- the length of the diffusion layer 51 in the y direction is shorter than the length of the phase change layer 41 in the y direction.
- a sectional shape of the diffusion layer 51 when viewed in the z direction is smaller than a sectional shape of the phase change layer 41 when viewed in the z direction.
- the length of the diffusion layer 51 in the x direction may be shorter than the length of the phase change layer 41 in the x direction.
- the radius of the diffusion layer 51 may be shorter than the radius of the phase change layer 41 .
- each memory cell MC 2 is identical to the configuration of each memory cell MC 1 described above.
- the materials and structures of the selector 62 , the phase change layer 42 , and the diffusion layer 52 included in each memory cell MC 2 are identical to the materials and structures of the selector 61 , the phase change layer 41 , and the diffusion layer 51 , respectively, included in each memory cell MC 1 .
- the disposition order of the selector 62 , the phase change layer 42 , and the diffusion layer 52 in each memory cell MC 2 may be different from the disposition order of the selector 61 , the phase change layer 41 , and the diffusion layer 51 in each memory cell MC 1 .
- a conductive layer 74 made of a metallic material the same as that of the conductive layer 71 is provided between the word line 20 and the selector 62 .
- a conductive layer 75 made of a metallic material the same as that of the conductive layer 72 is provided between the selector 62 and the phase change layer 42 .
- a conductive layer 76 made of a metallic material the same as that of the conductive layer 73 is provided between the diffusion layer 52 and the bit line 32 .
- the insulating layer 81 is formed in the vicinity of each memory cell MC.
- the insulating layer 81 is a layer formed of an insulation material such as oxide silicon (SiO 2 ).
- Memory cells MC at different positions in the x direction or the y direction are separated and electrically insulated from each other through the insulating layer 81 .
- the insulating layer 81 is formed of a material having a relatively small thermal conductivity, memory cells MC at different positions are thermally insulated from each other as well. This prevents a situation in which Joule heat generated due to writing operation to some memory cells MC is conveyed to the other memory cells MC and causes false writing (or false erasure).
- each memory cell MC does not contact the insulating layer 81 and is covered by the insulating layer 81 through the insulating layer 82 .
- the insulating layer 82 is a layer formed of an insulation material not containing oxygen, such as silicon nitride (SiN). The insulating layer 82 prevents oxidation of a material such as germanium contained in the diffusion layer 50 .
- FIGS. 6 A and 6 B each schematically illustrate exemplary distribution of Ge inside the phase change layer 40 .
- FIGS. 7 A and 7 B each illustrate an exemplary waveform of a voltage pulse applied between the bit line 30 and the word line 20 .
- the phase change layer 40 (resistance change layer) can reversibly transition between the first state and the second state different from each other in the electric resistance. Such state transition occurs in accordance with distribution of a diffusive material (Ge) having diffused from the diffusion layer 50 to the phase change layer 40 .
- a diffusive material Ge
- FIG. 6 A illustrates exemplary distribution of Ge in the phase change layer 40 in the first state.
- the amount of Ge distributed inside the phase change layer 40 is extremely small in the first state.
- a small amount of Ge having diffused from the diffusion layer 50 is distributed in a narrow range extending from a part contacting the diffusion layer 50 to the negative side in the z direction in the phase change layer 40 .
- the electric resistance is relatively large on a path along which current flows through the phase change layer 40 and the like in the z direction.
- a voltage pulse as illustrated in FIG. 7 A is applied to the bit line 30 and the word line 20 between which the phase change layer 40 is sandwiched.
- the voltage pulse is applied so that potential on the phase change layer 40 side becomes higher than potential on the diffusion layer 50 side.
- the voltage pulse in FIG. 7 A is applied between the bit line 31 and the word line 20 in a direction with which the potential of the bit line 31 becomes higher than the potential of the word line 20 .
- the voltage pulse in FIG. 7 A is applied between the bit line 32 and the word line 20 in a direction with which the potential of the word line 20 becomes higher than the potential of the bit line 32 .
- voltage between the bit line 30 and the word line 20 increases from zero to V1 in the duration from time t0 to time t1. Thereafter, the voltage is maintained at V1 until time t2, and then decreases to V2 in the duration from time t2 to time t4.
- V2 is voltage lower than V1 and higher than a threshold value for setting the selector 60 to be on.
- the voltage between the bit line 30 and the word line 20 is maintained at V2 in the duration from time t4 to time t5 and then returned to zero in the duration from time t5 to time t6.
- the temperatures of the phase change layer 40 and the diffusion layer 50 increase due to Joule heat.
- Ge diffusion is promoted in a direction (the negative z direction) from the diffusion layer 50 to the inside of the phase change layer 40 due to Ge concentration difference between the phase change layer 40 and the diffusion layer 50 .
- Ge diffusion that occurs in this principle will be also referred to as “first diffusion” in the following description.
- Ge atoms having diffused inside the diffusion layer 50 are in a positively charged state.
- the Ge atoms receive force from an electric field in a direction (the z direction) from the inside of the phase change layer 40 toward the diffusion layer 50 . This force promotes Ge diffusion in the z direction.
- Ge diffusion that occurs in this principle will be also referred to as “second diffusion” in the following description.
- the first diffusion and the second diffusion in directions opposite to each other can occur as Ge diffusion in a duration in which a voltage pulse is applied between the bit line 30 and the word line 20 .
- the first diffusion mainly occurs in a duration in which the voltage between the bit line 30 and the word line 20 decreases.
- the second diffusion mainly occurs in a duration in which the above-described voltage is maintained at V1.
- the first diffusion in the direction from the diffusion layer 50 toward the inside of the phase change layer 40 is dominant when the voltage is slowly decreased at stages in cooling as in the example of FIG. 7 A .
- Ge moves toward the inside of the phase change layer 40 , thereby achieving a state in which Ge is distributed to a deeper part in the negative z direction than in FIG. 6 A , in other words, the second state illustrated in FIG. 6 B .
- the phase change layer 40 of the present embodiment has a crystal structure having a C axis oriented in the z direction, and thus a plurality of Te-Te gaps are arranged in the z direction. Ge having diffused from the diffusion layer 50 enters each Te-Te gap and decreases the bandgap at this part. As a result, the electric resistance of the phase change layer 40 decreases at the part.
- the electric resistance near the interface contacting the diffusion layer 50 in the phase change layer 40 is smaller than the electric resistance in the first state in FIG. 6 A .
- the second state is stably maintained after the voltage pulse application is ended, as well.
- the temperatures of the phase change layer 40 and the diffusion layer 50 increase by Joule heat.
- the peak value of the voltage pulse and the like are adjusted in advance so that each temperature does not increase to a temperature beyond which the layer melts.
- the phase change layer 40 remains in a crystal state and does not become a non-crystal state in the process of transition from the first state to the second state.
- a voltage pulse as illustrated in FIG. 7 B is applied to the bit line 30 and the word line 20 between which the phase change layer 40 is sandwiched.
- the voltage pulse is applied so that potential on the phase change layer 40 side becomes higher than potential on the diffusion layer 50 side.
- the voltage pulse in FIG. 7 B is applied between the bit line 31 and the word line 20 in a direction in which the potential of the bit line 31 becomes higher than the potential of the word line 20 .
- the voltage pulse in FIG. 7 B is applied between the bit line 32 and the word line 20 in a direction in which the potential of the word line 20 becomes higher than the potential of the bit line 32 .
- the voltage between the bit line 30 and the word line 20 increases from zero to V1 in the duration from time t0 to time t1. Thereafter, the voltage is maintained at V1 until time t2. Then, the voltage is returned to zero in the duration from time t2 to time t3.
- the peak value of a voltage pulse for transition from the second state to the first state may be different from the peak value (V1) of a voltage pulse for transition from the first state to the second state.
- a duration in which the voltage pulse for transition from the second state to the first state is maintained at its peak value may be different from a duration (duration from time t1 to time t2) in which the voltage pulse for transition from the first state to the second state is maintained at its peak value.
- the voltage does not decrease at stages from time t2 but decreases at a substantially constant speed from the voltage V1 to zero.
- the duration from time t2 to time t3 is shorter than the duration from time t2 to time t6.
- the electric resistance near the interface contacting the diffusion layer 50 in the phase change layer 40 is smaller than the electric resistance in the second state in FIG. 6 B .
- the first state is stably maintained after the voltage pulse application is ended, as well.
- the temperatures of the phase change layer 40 and the diffusion layer 50 increase, but the peak value of the voltage pulse and the like are adjusted in advance so that each temperature does not increase to a temperature beyond which the layer melts.
- the phase change layer 40 remains in the crystal state and does not become the non-crystal state in the process of transition from the second state to the first state, as well.
- the phase change layer 40 is in the crystal state in any of the first state and the second state. Moreover, the phase change layer 40 is maintained in the crystal state and does not become the non-crystal state in any of the process of transition from the first state to the second state and the process of transition from the second state to the first state. Compared to a storage device configured so that the state of the phase change layer transitions between the crystal state and the non-crystal state, the phase change layer 40 does not need to be melted in the present embodiment, and thus current necessary for, for example, writing operation of the storage device 10 is reduced. Accordingly, the storage device 10 can be operated with current smaller than that in conventional cases.
- the length of the diffusion layer 50 in the y direction is shorter than the length of the phase change layer 40 in the y direction. Since a path along which current flows at voltage pulse application is narrowed in the diffusion layer 50 , current necessary for, for example, writing operation of the storage device 10 is further reduced. Moreover, since current passes through a local path in the phase change layer 40 , state transition in the phase change layer 40 is more efficiently performed.
- a line disposed on a side opposite to the diffusion layer 50 (adjacent layer) in the z direction when viewed from the phase change layer 40 (resistance change layer) of the memory cell MC corresponds to a “first wiring layer” in the present embodiment.
- a line disposed on a side opposite to the phase change layer 40 (resistance change layer) in the z direction when viewed from the diffusion layer 50 (adjacent layer) of the memory cell MC corresponds to a “second wiring layer” in the present embodiment.
- the bit line 31 corresponds to the first wiring layer
- the word line 20 corresponds to the second wiring layer
- the bit line 32 corresponds to the second wiring layer.
- the first wiring layer and the second wiring layer are disposed at positions separated from each other in the z direction, and the phase change layer 40 and the diffusion layer 50 are disposed between the wiring layers.
- the thickness of the phase change layer 40 in the z direction is preferably equal to or larger than 5 nm, and the thickness of the diffusion layer 50 in the z direction is preferably equal to or smaller than 5 nm.
- a method of manufacturing the storage device 10 according to the present embodiment will be described below.
- an insulating film is formed on the upper side of the semiconductor substrate BP, and then a plurality of bit lines 31 are formed on the insulating film.
- the bit lines 31 can be formed by, for example, depositing a metal film through CVD and then applying etching using photolithography to the metal film. After the etching is performed, an insulating film is formed through, for example, CVD to cover the bit lines 31 and their vicinity, and flattening processing through CMP is performed on the insulating film. Accordingly, the upper surfaces of the bit lines 31 are exposed.
- FIG. 8 illustrates a partial section after the stacking process as described above is completed.
- FIG. 9 illustrates a partial section after the patterning process is completed.
- FIG. 10 illustrates a partial section after the recess formation process is completed.
- an insulating layer 82 and an insulating layer 81 are formed in the stated order through CVD to fill the vicinity of the plurality of memory cells MC 1 formed in the patterning process.
- the insulating layer 82 which is formed first, enters inside the recess 50 A. In the present embodiment, the recess 50 A is entirely filled by the insulating layer 82 .
- CMP chemical mechanical polishing
- FIG. 11 illustrates a partial section after the insulating layer formation process is completed.
- word lines 20 are formed along the surface S by a method the same as the method of forming the bit lines 31 .
- the stacking process, the patterning process, the recess formation process, and the insulating layer formation process described above are performed again to form memory cells MC 2 at positions directly above the memory cells MC 1 with the word lines 20 interposed therebetween.
- bit lines 32 are formed on the upper side of the memory cells MC 2 by a method the same as the method of forming the bit lines 31 . In this manner, the storage device 10 including memory cells MC as illustrated in FIG. 4 can be manufactured.
- a storage device including a phase change layer having a superlattice structure in which, for example, GeTe and Sb 2 Te 3 are alternately stacked as in a conventional iPCM it is necessary to alternately form a plurality of layers constituting a superlattice.
- the storage device 10 according to the present embodiment it is not necessary to perform a process of alternately stacking a plurality of layers as described above.
- the storage device 10 can be relatively easily manufactured as compared to a case in which the conventional iPCM is manufactured.
- a second embodiment will be described below. The following description is mainly made on any feature different from the first embodiment, and description of any feature common to the first embodiment is omitted as appropriate.
- FIG. 12 illustrates, from the same viewpoint as that of FIG. 4 , the configuration of a part corresponding to each memory cell MC and its vicinity in a storage device 10 according to the present embodiment.
- void spaces GP are formed in the vicinity of the diffusion layer 50 in the present embodiment.
- the “vicinity of the diffusion layer 50 ” means a position between the phase change layer 41 and the conductive layer 73 and adjacent to the diffusion layer 51 , and a position between the phase change layer 42 and the conductive layer 76 and adjacent to the diffusion layer 52 .
- Joule heat generated when a voltage pulse is applied to the memory cell MC can be trapped by the void spaces GP.
- a temperature necessary for transition of the temperature of the phase change layer 40 between the first state and the second state can be reached with smaller current. Accordingly, the storage device 10 can be operated with current further smaller than that in conventional cases.
- the recess 50 A may be formed in a shape with which the void spaces GP are likely to remain by reducing the thickness (dimension in the z direction) of the diffusion layer 51 in the stacking process or increasing a depth dimension (dimension in the y direction) of the recess 50 A in the recess formation process.
- the void spaces GP may be formed by changing a deposition condition of the insulating layer 82 in the insulating layer formation process.
- a third embodiment will be described below. The following description is mainly made on any feature different from the first embodiment, and description of any feature common to the first embodiment is omitted as appropriate.
- FIG. 13 illustrates, from the same viewpoint as that of FIG. 4 , the configuration of a part corresponding to each memory cell MC and its vicinity in a storage device 10 according to the present embodiment.
- a crystal layer 90 is formed at a position adjacent to the phase change layer 40 on the negative side in the z direction in the present embodiment.
- the crystal layer 90 included in each memory cell MC 1 on the lower side will be also referred to as a “crystal layer 91 ” in the following description.
- the crystal layer 90 included in each memory cell MC 2 on the upper side will be also referred to as a “crystal layer 92 ” in the following description.
- a position at which the crystal layer 91 is formed can be expressed as a position between the phase change layer 41 and the bit line 31 .
- a position at which the crystal layer 92 is formed can be expressed as a position between the phase change layer 42 and the word line 20 .
- Each position corresponds to a position between the resistance change layer and the first wiring layer in the memory cell MC.
- the crystal layer 90 is formed of a titanium ditelluride (TiTe 2 ) crystal.
- TiTe 2 is a two-dimensional crystal, and the crystal layer 90 is formed so that the “a” axis and the “b” axis of the crystal are oriented in directions orthogonal to the z direction.
- the material of the crystal layer 90 is not limited to TiTe 2 , and other transition metal compound may be used as the material of the crystal layer 90 .
- a material such as hafnium ditelluride (HfTe 2 ) and zirconium ditelluride (ZrTe 2 ) can be used.
- the crystal layer 91 may be formed after the conductive layer 72 is formed in the stacking process, and the phase change layer 41 may be formed to cover the crystal layer 91 .
- the crystal layer 92 may be formed after the conductive layer 75 is formed, and the phase change layer 42 may be formed to cover the crystal layer 92 .
- the phase change layer 40 is formed on the upper surface of TiTe 2 formed as an orientation layer in advance, and thus a crystal structure having a C axis oriented in the z direction can be achieved more easily. Moreover, higher adhesion can be achieved between the phase change layer 40 and an electrode layer (the conductive layer 72 or the conductive layer 75 ) on the lower side of the phase change layer 40 .
- “high potential” means that the voltage is high in the positive direction unless otherwise defined.
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Abstract
A storage device 10 includes a phase change layer 40 containing tellurium, and a diffusion layer 50 containing at least one of germanium, silicon, carbon, tin, aluminum, gallium, and indium and disposed at a position adjacent to the phase change layer 40. The phase change layer 40 is capable of changing between a first state and a second state different from each other in electric resistance. The phase change layer 40 is in a crystal state in any of the first state and the second state. A length of the diffusion layer 50 in a direction orthogonal to a z direction is shorter than a length of the phase change layer 40 in the direction orthogonal to the z direction.
Description
- This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-097861, filed on Jun. 11, 2021, the entire contents of which are incorporated herein by reference.
- Embodiments of the present invention relate to a storage device.
- A storage device of a new scheme, which referred to as a “phase change memory”, has been developed as a storage device used for an information instrument such as a cellular phone. As such a storage device, for example, a storage device that causes a phase change material to reversibly transition between a high-resistive non-crystal state and a low-resistive crystal state by applying a voltage pulse to the phase change material has been proposed. Moreover, a storage device that changes the distribution of a specific element (for example, Ge) contained in a phase change material by applying a voltage pulse to the phase change material, thus changing the electric resistance of the phase change material has also been proposed. In such a storage device, the electric resistance of the phase change material is stably maintained even after a power source is disconnected, and thus information corresponding to the electric resistance can be stored.
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FIG. 1 is a diagram schematically illustrating the configuration of a storage device according to a first embodiment; -
FIG. 2 is a diagram illustrating the configuration of a memory cell array inFIG. 1 ; -
FIG. 3 is a diagram illustrating another exemplary configuration of the memory cell array inFIG. 1 ; -
FIG. 4 is a cross-sectional view illustrating the configuration of a memory cell and its vicinity in the storage device according to the first embodiment; -
FIG. 5 is a diagram illustrating the crystal structure of an adjacent layer; -
FIGS. 6A and 6B are each a diagram schematically illustrating distribution of germanium in a resistance change layer; -
FIGS. 7A and 7B are each a diagram illustrating a voltage pulse applied to the resistance change layer and the adjacent layer; -
FIG. 8 is a diagram for explaining a method of manufacturing the storage device according to the first embodiment; -
FIG. 9 is a diagram for explaining the method of manufacturing the storage device according to the first embodiment; -
FIG. 10 is a diagram for explaining the method of manufacturing the storage device according to the first embodiment; -
FIG. 11 is a diagram for explaining the method of manufacturing the storage device according to the first embodiment; -
FIG. 12 is a diagram schematically illustrating the configuration of a storage device according to a second embodiment; and -
FIG. 13 is a diagram schematically illustrating the configuration of a storage device according to a third embodiment. - The present embodiments will be described below with reference to the accompanying drawings. To facilitate understanding of description, the same components in the drawings will be denoted by the same reference sign as much as possible, and duplicate description thereof will be omitted.
- A first embodiment will be described below. A
storage device 10 according to the present embodiment is an interface resistance random access phase change memory exploiting elemental segregation. As illustrated inFIG. 1 , thestorage device 10 includes a memory cell array MCA, aword line driver 11, abit line driver 12, and acontrol circuit 13. - The memory cell array MCA is a part including a plurality of memory cells MC in which data is stored. The
storage device 10 is provided with a plurality ofword lines 20 and a plurality ofbit lines 30. These lines are formed as a wiring layer for applying voltage to the memory cells MC. One end of each memory cell MC is connected to aword line 20, and the other end is connected to abit line 30. As illustrated inFIG. 2 , each memory cell MC is provided at a position where thecorresponding word line 20 and thecorresponding bit line 30 intersect each other. Note thatFIG. 1 illustrates only some of the plurality of memory cells MC included in the memory cell array MCA. - Each memory cell MC includes a
phase change layer 40 and aselector 60. As illustrated with an equivalent circuit inFIG. 1 , thephase change layer 40 and theselector 60 are electrically connected in series between thecorresponding word line 20 and thecorresponding bit line 30. Note that, althoughFIG. 1 illustrates that thephase change layer 40 is disposed on thebit line 30 side and theselector 60 is disposed on theword line 20 side, disposition of thephase change layer 40 and theselector 60 is not limited thereto. In each of some or all memory cells MC, disposition of thephase change layer 40 and theselector 60 may be opposite to the disposition inFIG. 1 . - The
phase change layer 40 is a layer formed of a phase change material and is a part that stores information corresponding to the value of its electric resistance. In the present embodiment, the phase change material is a chalcogenide material made of antimony telluride (Sb2Te3). The material of thephase change layer 40 is not limited thereto but may be any other phase change material. The phase change material is preferably a compound containing at least tellurium. - The electric resistance (specifically, electric resistance at a vicinity part of an interface with a
diffusion layer 50 to be described later) of thephase change layer 40 changes when a predetermined voltage pulse is applied to thephase change layer 40. As described later, thephase change layer 40 reversibly transitions between a first state in which the electric resistance is relatively high and a second state in which the electric resistance is relatively low in accordance with the waveform of the applied voltage pulse. Information (0 or 1) corresponding to the electric resistance of thephase change layer 40 is stored in each memory cell MC. - The
selector 60 is a two-terminal switching element and has a non-linear current-voltage characteristic. Substantially no current flows through theselector 60 when voltage applied to both ends of theselector 60 is equal to or lower than a predetermined threshold value. Current abruptly flows through theselector 60 when voltage applied to both ends of theselector 60 exceeds the above-described threshold value. Since theselector 60 is provided in each memory cell MC, it is possible to flow current only to aphase change layer 40 as a data writing or erasure target, thereby changing the electric resistance of thephase change layer 40. - The
word line driver 11 is a circuit for adjusting the potential of eachword line 20. One end of eachword line 20 is connected to theword line driver 11. Theword line driver 11 includes a non-illustrated switch group for switching opening and closing between eachword line 20 and a voltage generation circuit (not illustrated). Operation of theword line driver 11 is controlled by thecontrol circuit 13 to be described later. - The
bit line driver 12 is a circuit for adjusting the potential of eachbit line 30. One end of eachbit line 30 is connected to thebit line driver 12. Thebit line driver 12 includes a non-illustrated switch group for switching opening and closing between eachbit line 30 and a voltage generation circuit (not illustrated). Thebit line driver 12 may include a circuit for acquiring data stored in each memory cell MC based on current flowing through thecorresponding bit line 30. In addition, thebit line driver 12 may include a circuit for adjusting the potential of eachbit line 30 in accordance with writing data. Operation of thebit line driver 12 is controlled by thecontrol circuit 13. - The
control circuit 13 is a circuit configured to collectively control the entire operation of thestorage device 10. Thecontrol circuit 13 performs, for example, voltage pulse application to each memory cell MC by controlling operation of theword line driver 11 and thebit line driver 12 as described above. At data writing to the memory cell array MCA, thecontrol circuit 13 changes the electric resistance of thephase change layer 40 of each writing target memory cell MC to a value corresponding to writing data by applying a voltage pulse in accordance with the writing data to the memory cell MC. At data reading from the memory cell array MCA, thecontrol circuit 13 applies voltage to each reading target memory cell MC and reads data corresponding to the electric resistance value of thephase change layer 40 based on current flowing through the memory cell MC. -
FIG. 2 schematically illustrates the configuration of the memory cell array MCA. Note thatFIG. 2 only illustrates the word lines 20, the bit lines 30, the memory cells MC, and a semiconductor substrate BP (to be described later) in the memory cell array MCA, and omits illustration of insulatinglayers 81 and 82 (refer toFIG. 4 ) formed in the vicinity of the memory cells MC and the like. - In
FIG. 2 , an x axis is set in a direction in which the word lines 20 extend. In addition, a y axis is set in a direction in which the bit lines 30 extend, and a z axis is set in the up-down direction. The x axis, the y axis, and the z axis are orthogonal to each other. Hereinafter, a direction along the x axis will be also referred to as an “x direction”. Similarly, a direction along the y axis will be also referred to as a “y direction”. A direction along the z axis will be also referred to as a “z direction” below. Hereinafter, when another drawing is referred to, the configuration of each component may be described by using the x axis, the y axis, the z axis, the x direction, the y direction, and the z direction as described above. - As illustrated in
FIG. 2 , the memory cell array MCA is formed on the upper side of the semiconductor substrate BP. The semiconductor substrate BP is, for example, a silicon substrate. - Each
word line 20 extends in the x direction as described above, and the plurality ofword lines 20 are arranged in the y direction. Eachbit line 30 extends in the y direction as described above, and the plurality ofbit lines 30 are arranged in the x direction. - In the present embodiment, the plurality of
bit lines 30 are disposed in each of the parts on the lower and upper sides of the word lines 20. Thus, the memory cells MC each provided at a part where aword line 20 and abit line 30 intersect when viewed from the top are provided between eachword line 20 and thecorresponding bit line 30 on its lower side and between eachword line 20 and thecorresponding bit line 30 on its upper side. Eachbit line 30 disposed on the lower side of aword line 20 will be also referred to as a “bit line 31” in the following description. Eachbit line 30 disposed on the upper side of aword line 20 will be also referred to as a “bit line 32” in the following description. - Instead of the aspect in
FIG. 2 , the plurality ofbit lines 30 may be disposed only on the upper side of the word lines 20 as illustrated inFIG. 3 . In this case, the memory cells MC are provided only between eachword line 20 and thecorresponding bit line 30 on its upper side. - A further specific configuration of each memory cell MC will be described below with reference to
FIG. 4 .FIG. 4 illustrates a section of a part corresponding to each cell memory MC and its vicinity, which is taken along a surface orthogonal to the x axis.FIG. 4 illustrates a section of a pair of memory cells MC disposed on the upper and lower sides of aword line 20. In the example illustrated inFIG. 4 , theselector 60 and thephase change layer 40 in each memory cell MC are disposed side by side in the stated order in the z direction. However, the disposition order of theselector 60 and thephase change layer 40 in each memory cell MC may be opposite. Moreover, the disposition order of theselector 60 and thephase change layer 40 in each memory cell MC on the upper side may be opposite to the disposition order of theselector 60 and thephase change layer 40 in each memory cell MC on the lower side. - Each memory cell MC disposed on the lower side of a
word line 20 will be also referred to as a “memory cell MC1” in the following description. Each memory cell MC disposed on the upper side of aword line 20 will be also referred to as a “memory cell MC2” in the following description. Thephase change layer 40 and theselector 60 included in each memory cell MC1 on the lower side will be also referred to as a “phase change layer 41” and a “selector 61”, respectively, in the following description. Similarly, thephase change layer 40 and theselector 60 included in each memory cell MC2 on the upper side will be also referred to as a “phase change layer 42” and a “selector 62”, respectively, in the following description. - Each memory cell MC further includes the
diffusion layer 50 adjacent to thephase change layer 40 in the z direction. Thephase change layer 40 corresponds to a “resistance change layer” in the present embodiment, and thediffusion layer 50 corresponds to an “adjacent layer” in the present embodiment. - The
diffusion layer 50 is formed of germanium (Ge) at high concentration. Note that the “high concentration” may be, for example, 100%, but the atomic concentration of germanium in thediffusion layer 50 only needs to be higher than at least the atomic concentration of germanium in thephase change layer 40. Germanium in thediffusion layer 50 functions as a “diffusive material” that diffuses inside thephase change layer 40. A diffusive material contained in thediffusion layer 50 does not necessarily need to be germanium but may be at least one of silicon (Si), carbon (C), tin (Sn), aluminum (Al), gallium (Ga), and indium (In). Thediffusion layer 50 included in each memory cell MC1 on the lower side will be also referred to as a “diffusion layer 51” in the following description. Similarly, thediffusion layer 50 included in each memory cell MC2 on the upper side will be also referred to as a “diffusion layer 52” in the following description. - The configuration of each memory cell MC1 will be described below. As illustrated in
FIG. 4 , each memory cell MC1 includes theselector 61, aconductive layer 72, thephase change layer 41, and thediffusion layer 51 in a configuration in which these components are stacked in the z direction sequentially from the lower side. In the example illustrated inFIG. 4 , in each memory cell MC1, thephase change layer 41 and thediffusion layer 51 are disposed side by side in the stated order in the z direction. However, the disposition order of thephase change layer 41 and thediffusion layer 51 in each memory cell MC1 may be opposite. Moreover, the disposition order of thephase change layer 42 and thediffusion layer 52 in each memory cell MC2 on the upper side may be opposite to the disposition order of thephase change layer 41 and thediffusion layer 51 in each memory cell MC1 on the lower side. - The
selector 61 is connected to thecorresponding bit line 31 on its lower side through aconductive layer 71. Theconductive layer 71 may be made of a metallic material such as tungsten. Theselector 61 is formed of, for example, a material containing chalcogen elements. - The
conductive layer 72 is a layer made of a metallic material the same as that of theconductive layer 71 and formed between theselector 61 and thephase change layer 41. - The
phase change layer 41 is a layer formed of antimony telluride (Sb2Te3) as described above.FIG. 5 schematically illustrates the crystal structure of Sb2Te3 contained in thephase change layer 41. As illustrated inFIG. 5 , thephase change layer 41 has a hexagonal crystal structure. Note that the arrow “CX” inFIG. 5 illustrates the direction of the C axis in the crystal structure of Sb2Te3. The direction is aligned with the z direction. In this manner, Sb2Te3 of thephase change layer 41 has a crystal structure having a C axis oriented in the z direction (in other words, the direction in which thephase change layer 41 and thediffusion layer 51 are stacked). Note that the “crystal structure having a C axis oriented in the z direction” includes not only a case in which the direction of the C axis of Sb2Te3 is completely aligned with the z direction but also a case in which the direction of the C axis of Sb2Te3 is tilted by several degrees with reference to the z direction. - In a crystal of Sb2Te3 as in
FIG. 5 , a part in which the interval between Te atoms included in the crystal is longer in the direction of the C axis (the z direction), in other words, a Te-Te gap as a part denoted by the text “Gap” inFIG. 5 is formed along the x-y plane. A plurality of such Te-Te gaps are further arranged in the direction of the C axis (the z direction). - Description continues with reference to
FIG. 4 . Thediffusion layer 51 is disposed at a position between thecorresponding word line 20 and thephase change layer 41 and adjacent to thephase change layer 41. Thediffusion layer 51 is a layer containing a high-concentration diffusive material as described above, and germanium (Ge) is used as the diffusive material in the present embodiment. Thediffusion layer 51 is formed to directly cover the upper surface of thephase change layer 41. However, the length of thediffusion layer 51 in the y direction is shorter than the length of thephase change layer 41 in the y direction. Thus, a sectional shape of thediffusion layer 51 when viewed in the z direction is smaller than a sectional shape of thephase change layer 41 when viewed in the z direction. Instead of or in addition to such a configuration, the length of thediffusion layer 51 in the x direction may be shorter than the length of thephase change layer 41 in the x direction. For example, when the sectional shapes are circular, the radius of thediffusion layer 51 may be shorter than the radius of thephase change layer 41. - The
diffusion layer 51 is connected to theword line 20 on its upper side through aconductive layer 73. Theconductive layer 73 is a layer made of a metallic material the same as that of theconductive layers - The configuration of each memory cell MC2 is identical to the configuration of each memory cell MC1 described above. Specifically, the materials and structures of the
selector 62, thephase change layer 42, and thediffusion layer 52 included in each memory cell MC2 are identical to the materials and structures of theselector 61, thephase change layer 41, and thediffusion layer 51, respectively, included in each memory cell MC1. However, as described above, the disposition order of theselector 62, thephase change layer 42, and thediffusion layer 52 in each memory cell MC2 may be different from the disposition order of theselector 61, thephase change layer 41, and thediffusion layer 51 in each memory cell MC1. - A
conductive layer 74 made of a metallic material the same as that of theconductive layer 71 is provided between theword line 20 and theselector 62. Aconductive layer 75 made of a metallic material the same as that of theconductive layer 72 is provided between theselector 62 and thephase change layer 42. Aconductive layer 76 made of a metallic material the same as that of theconductive layer 73 is provided between thediffusion layer 52 and thebit line 32. - As illustrated in
FIG. 4 , the insulatinglayer 81 is formed in the vicinity of each memory cell MC. The insulatinglayer 81 is a layer formed of an insulation material such as oxide silicon (SiO2). Memory cells MC at different positions in the x direction or the y direction are separated and electrically insulated from each other through the insulatinglayer 81. In addition, since the insulatinglayer 81 is formed of a material having a relatively small thermal conductivity, memory cells MC at different positions are thermally insulated from each other as well. This prevents a situation in which Joule heat generated due to writing operation to some memory cells MC is conveyed to the other memory cells MC and causes false writing (or false erasure). - The side surfaces of each memory cell MC and each
word line 20 are covered by the insulatinglayer 82. Thus, each memory cell MC does not contact the insulatinglayer 81 and is covered by the insulatinglayer 81 through the insulatinglayer 82. The insulatinglayer 82 is a layer formed of an insulation material not containing oxygen, such as silicon nitride (SiN). The insulatinglayer 82 prevents oxidation of a material such as germanium contained in thediffusion layer 50. - State change of the
phase change layer 40 and the like in operation of thestorage device 10 will be described below with reference toFIGS. 6A, 6B, 7A, and 7B .FIGS. 6A and 6B each schematically illustrate exemplary distribution of Ge inside thephase change layer 40.FIGS. 7A and 7B each illustrate an exemplary waveform of a voltage pulse applied between thebit line 30 and theword line 20. - As described above, the phase change layer 40 (resistance change layer) can reversibly transition between the first state and the second state different from each other in the electric resistance. Such state transition occurs in accordance with distribution of a diffusive material (Ge) having diffused from the
diffusion layer 50 to thephase change layer 40. -
FIG. 6A illustrates exemplary distribution of Ge in thephase change layer 40 in the first state. As illustrated inFIG. 6A , the amount of Ge distributed inside thephase change layer 40 is extremely small in the first state. However, a small amount of Ge having diffused from thediffusion layer 50 is distributed in a narrow range extending from a part contacting thediffusion layer 50 to the negative side in the z direction in thephase change layer 40. In the first state, the electric resistance is relatively large on a path along which current flows through thephase change layer 40 and the like in the z direction. - When the
phase change layer 40 is to be caused to transition from the first state inFIG. 6A to the second state inFIG. 6B , a voltage pulse as illustrated inFIG. 7A is applied to thebit line 30 and theword line 20 between which thephase change layer 40 is sandwiched. The voltage pulse is applied so that potential on thephase change layer 40 side becomes higher than potential on thediffusion layer 50 side. Thus, for example, when thephase change layer 41 on the lower side is to be caused to transition to the second state, the voltage pulse inFIG. 7A is applied between thebit line 31 and theword line 20 in a direction with which the potential of thebit line 31 becomes higher than the potential of theword line 20. When thephase change layer 42 on the upper side is to be caused to transition to the second state, the voltage pulse inFIG. 7A is applied between thebit line 32 and theword line 20 in a direction with which the potential of theword line 20 becomes higher than the potential of thebit line 32. - In the example of
FIG. 7A , voltage between thebit line 30 and theword line 20 increases from zero to V1 in the duration from time t0 to time t1. Thereafter, the voltage is maintained at V1 until time t2, and then decreases to V2 in the duration from time t2 to time t4. V2 is voltage lower than V1 and higher than a threshold value for setting theselector 60 to be on. The voltage between thebit line 30 and theword line 20 is maintained at V2 in the duration from time t4 to time t5 and then returned to zero in the duration from time t5 to time t6. - In the duration in which voltage is applied between the
bit line 30 and theword line 20, the temperatures of thephase change layer 40 and thediffusion layer 50 increase due to Joule heat. In this case, Ge diffusion is promoted in a direction (the negative z direction) from thediffusion layer 50 to the inside of thephase change layer 40 due to Ge concentration difference between thephase change layer 40 and thediffusion layer 50. Ge diffusion that occurs in this principle will be also referred to as “first diffusion” in the following description. - Ge atoms having diffused inside the
diffusion layer 50 are in a positively charged state. Thus, when a voltage pulse is applied so that potential on thephase change layer 40 side becomes higher than potential on thediffusion layer 50 side, the Ge atoms receive force from an electric field in a direction (the z direction) from the inside of thephase change layer 40 toward thediffusion layer 50. This force promotes Ge diffusion in the z direction. Ge diffusion that occurs in this principle will be also referred to as “second diffusion” in the following description. - As described above, the first diffusion and the second diffusion in directions opposite to each other can occur as Ge diffusion in a duration in which a voltage pulse is applied between the
bit line 30 and theword line 20. The first diffusion mainly occurs in a duration in which the voltage between thebit line 30 and theword line 20 decreases. The second diffusion mainly occurs in a duration in which the above-described voltage is maintained at V1. Thus, the first diffusion in the direction from thediffusion layer 50 toward the inside of thephase change layer 40 is dominant when the voltage is slowly decreased at stages in cooling as in the example ofFIG. 7A . Thus, at a part near the interface contacting thediffusion layer 50 in thephase change layer 40, Ge moves toward the inside of thephase change layer 40, thereby achieving a state in which Ge is distributed to a deeper part in the negative z direction than inFIG. 6A , in other words, the second state illustrated inFIG. 6B . - As described above with reference to
FIG. 5 , thephase change layer 40 of the present embodiment has a crystal structure having a C axis oriented in the z direction, and thus a plurality of Te-Te gaps are arranged in the z direction. Ge having diffused from thediffusion layer 50 enters each Te-Te gap and decreases the bandgap at this part. As a result, the electric resistance of thephase change layer 40 decreases at the part. - In this manner, in the second state in
FIG. 6B , the electric resistance near the interface contacting thediffusion layer 50 in thephase change layer 40 is smaller than the electric resistance in the first state inFIG. 6A . The second state is stably maintained after the voltage pulse application is ended, as well. - Note that, when the voltage pulse is applied, the temperatures of the
phase change layer 40 and thediffusion layer 50 increase by Joule heat. However, for example, the peak value of the voltage pulse and the like are adjusted in advance so that each temperature does not increase to a temperature beyond which the layer melts. Thus, thephase change layer 40 remains in a crystal state and does not become a non-crystal state in the process of transition from the first state to the second state. - In order to transition the
phase change layer 40 from the second state inFIG. 6B to the first state inFIG. 6A , a voltage pulse as illustrated inFIG. 7B is applied to thebit line 30 and theword line 20 between which thephase change layer 40 is sandwiched. Similarly to the case ofFIG. 7A , the voltage pulse is applied so that potential on thephase change layer 40 side becomes higher than potential on thediffusion layer 50 side. Thus, for example, when thephase change layer 41 on the lower side is to be caused to transition to the first state, the voltage pulse inFIG. 7B is applied between thebit line 31 and theword line 20 in a direction in which the potential of thebit line 31 becomes higher than the potential of theword line 20. When thephase change layer 42 on the upper side is to be caused to transition to the second state, the voltage pulse inFIG. 7B is applied between thebit line 32 and theword line 20 in a direction in which the potential of theword line 20 becomes higher than the potential of thebit line 32. - In the example of
FIG. 7B as well, the voltage between thebit line 30 and theword line 20 increases from zero to V1 in the duration from time t0 to time t1. Thereafter, the voltage is maintained at V1 until time t2. Then, the voltage is returned to zero in the duration from time t2 to time t3. - Note that the peak value of a voltage pulse for transition from the second state to the first state may be different from the peak value (V1) of a voltage pulse for transition from the first state to the second state. In addition, a duration in which the voltage pulse for transition from the second state to the first state is maintained at its peak value may be different from a duration (duration from time t1 to time t2) in which the voltage pulse for transition from the first state to the second state is maintained at its peak value.
- In transition from the second state to the first state, the voltage does not decrease at stages from time t2 but decreases at a substantially constant speed from the voltage V1 to zero. The duration from time t2 to time t3 is shorter than the duration from time t2 to time t6.
- In the example of
FIG. 7B , when the voltage is returned to zero in a relatively short time at cooling, the first diffusion in the direction from thediffusion layer 50 toward the inside of thephase change layer 40 is unlikely to occur as compared to the example ofFIG. 7A . Thus, in the example ofFIG. 7B , the second diffusion in the direction from the inside of thephase change layer 40 toward thediffusion layer 50, which occurs in the duration until time t2, is dominant. Thus, in the part of thephase change layer 40 near the interface contacting thediffusion layer 50, Ge that has entered the Te-Te gap of thephase change layer 40 moves toward thediffusion layer 50 side. As a result, thephase change layer 40 returns to the first state illustrated inFIG. 6A . In this case, since Ge moves from a Te-Te gap in thephase change layer 40, the bandgap at this part increases. As a result, the electric resistance of thephase change layer 40 increases at the part. - In this manner, in the first state in
FIG. 6A , the electric resistance near the interface contacting thediffusion layer 50 in thephase change layer 40 is smaller than the electric resistance in the second state inFIG. 6B . The first state is stably maintained after the voltage pulse application is ended, as well. - In the process of transition from the second state to the first state, as well, the temperatures of the
phase change layer 40 and thediffusion layer 50 increase, but the peak value of the voltage pulse and the like are adjusted in advance so that each temperature does not increase to a temperature beyond which the layer melts. Thus, thephase change layer 40 remains in the crystal state and does not become the non-crystal state in the process of transition from the second state to the first state, as well. - As described above, the
phase change layer 40 is in the crystal state in any of the first state and the second state. Moreover, thephase change layer 40 is maintained in the crystal state and does not become the non-crystal state in any of the process of transition from the first state to the second state and the process of transition from the second state to the first state. Compared to a storage device configured so that the state of the phase change layer transitions between the crystal state and the non-crystal state, thephase change layer 40 does not need to be melted in the present embodiment, and thus current necessary for, for example, writing operation of thestorage device 10 is reduced. Accordingly, thestorage device 10 can be operated with current smaller than that in conventional cases. - In the present embodiment, the length of the
diffusion layer 50 in the y direction is shorter than the length of thephase change layer 40 in the y direction. Since a path along which current flows at voltage pulse application is narrowed in thediffusion layer 50, current necessary for, for example, writing operation of thestorage device 10 is further reduced. Moreover, since current passes through a local path in thephase change layer 40, state transition in thephase change layer 40 is more efficiently performed. - Among a
word line 20 and abit line 30 between which a memory cell MC is sandwiched, a line disposed on a side opposite to the diffusion layer 50 (adjacent layer) in the z direction when viewed from the phase change layer 40 (resistance change layer) of the memory cell MC corresponds to a “first wiring layer” in the present embodiment. In addition, a line disposed on a side opposite to the phase change layer 40 (resistance change layer) in the z direction when viewed from the diffusion layer 50 (adjacent layer) of the memory cell MC corresponds to a “second wiring layer” in the present embodiment. - For example, in each memory cell MC1 on the lower side, the
bit line 31 corresponds to the first wiring layer, and theword line 20 corresponds to the second wiring layer. In each memory cell MC2 on the upper side, theword line 20 corresponds to the first wiring layer, and thebit line 32 corresponds to the second wiring layer. In any case, the first wiring layer and the second wiring layer are disposed at positions separated from each other in the z direction, and thephase change layer 40 and thediffusion layer 50 are disposed between the wiring layers. When thephase change layer 40 is to be caused to transition between the first state and the second state, a voltage pulse with which the potential of the first wiring layer becomes higher than the potential of the second wiring layer is applied to thephase change layer 40 and thediffusion layer 50. - To achieve the above-described effect, specifically, the effect of operating the
storage device 10 with current smaller than that in conventional cases, the thickness of thephase change layer 40 in the z direction is preferably equal to or larger than 5 nm, and the thickness of thediffusion layer 50 in the z direction is preferably equal to or smaller than 5 nm. - A method of manufacturing the
storage device 10 according to the present embodiment will be described below. - First in a stacking process, an insulating film is formed on the upper side of the semiconductor substrate BP, and then a plurality of
bit lines 31 are formed on the insulating film. The bit lines 31 can be formed by, for example, depositing a metal film through CVD and then applying etching using photolithography to the metal film. After the etching is performed, an insulating film is formed through, for example, CVD to cover the bit lines 31 and their vicinity, and flattening processing through CMP is performed on the insulating film. Accordingly, the upper surfaces of the bit lines 31 are exposed. - Thereafter, a
conductive layer 71, aselector 61, aconductive layer 72, aphase change layer 41, adiffusion layer 51, and aconductive layer 73 are sequentially formed from below through, for example, CVD to cover the upper side of eachbit line 31.FIG. 8 illustrates a partial section after the stacking process as described above is completed. - In a patterning process following the stacking process, films stacked on the upper side of the bit lines 31 are partially removed by etching using, for example, photolithography. Specifically, only parts to be memory cells MC1 among the stacked films are left intact, and the other part is removed.
FIG. 9 illustrates a partial section after the patterning process is completed. - In a recess formation process following the patterning process, side surface parts of the stacked films left as described above are cleaned by, for example, wet etching. In this process, drug solution having selectiveness for the
diffusion layer 51 is used. Part of thediffusion layer 51 is removed simultaneously with the cleaning, and as a result, the length of thediffusion layer 51 in the y direction becomes shorter than the length of thephase change layer 41 in the y direction. Arecess 50A retracted toward thediffusion layer 51 is formed between thephase change layer 41 and theconductive layer 73.FIG. 10 illustrates a partial section after the recess formation process is completed. - In an insulating layer formation process following the recess formation process, an insulating
layer 82 and an insulatinglayer 81 are formed in the stated order through CVD to fill the vicinity of the plurality of memory cells MC1 formed in the patterning process. The insulatinglayer 82, which is formed first, enters inside therecess 50A. In the present embodiment, therecess 50A is entirely filled by the insulatinglayer 82. After the insulatinglayers layers conductive layer 73 is exposed along a flat surface S.FIG. 11 illustrates a partial section after the insulating layer formation process is completed. - After the memory cells MC1 and their vicinity are formed as described above, word lines 20 are formed along the surface S by a method the same as the method of forming the bit lines 31. Subsequently, the stacking process, the patterning process, the recess formation process, and the insulating layer formation process described above are performed again to form memory cells MC2 at positions directly above the memory cells MC1 with the word lines 20 interposed therebetween. Thereafter,
bit lines 32 are formed on the upper side of the memory cells MC2 by a method the same as the method of forming the bit lines 31. In this manner, thestorage device 10 including memory cells MC as illustrated inFIG. 4 can be manufactured. - To manufacture a storage device including a phase change layer having a superlattice structure in which, for example, GeTe and Sb2Te3 are alternately stacked as in a conventional iPCM, it is necessary to alternately form a plurality of layers constituting a superlattice. However, to manufacture the
storage device 10 according to the present embodiment, it is not necessary to perform a process of alternately stacking a plurality of layers as described above. Thus, thestorage device 10 can be relatively easily manufactured as compared to a case in which the conventional iPCM is manufactured. - A second embodiment will be described below. The following description is mainly made on any feature different from the first embodiment, and description of any feature common to the first embodiment is omitted as appropriate.
-
FIG. 12 illustrates, from the same viewpoint as that ofFIG. 4 , the configuration of a part corresponding to each memory cell MC and its vicinity in astorage device 10 according to the present embodiment. As illustrated inFIG. 12 , void spaces GP are formed in the vicinity of thediffusion layer 50 in the present embodiment. Specifically, the “vicinity of thediffusion layer 50” means a position between thephase change layer 41 and theconductive layer 73 and adjacent to thediffusion layer 51, and a position between thephase change layer 42 and theconductive layer 76 and adjacent to thediffusion layer 52. - In the present embodiment, Joule heat generated when a voltage pulse is applied to the memory cell MC can be trapped by the void spaces GP. Thus, a temperature necessary for transition of the temperature of the
phase change layer 40 between the first state and the second state can be reached with smaller current. Accordingly, thestorage device 10 can be operated with current further smaller than that in conventional cases. - To manufacture the
storage device 10 having such a configuration, it is sufficient to prevent the insulatinglayer 82 from entering inside therecess 50A in the insulating layer formation process. For example, therecess 50A may be formed in a shape with which the void spaces GP are likely to remain by reducing the thickness (dimension in the z direction) of thediffusion layer 51 in the stacking process or increasing a depth dimension (dimension in the y direction) of therecess 50A in the recess formation process. Alternatively, the void spaces GP may be formed by changing a deposition condition of the insulatinglayer 82 in the insulating layer formation process. - A third embodiment will be described below. The following description is mainly made on any feature different from the first embodiment, and description of any feature common to the first embodiment is omitted as appropriate.
-
FIG. 13 illustrates, from the same viewpoint as that ofFIG. 4 , the configuration of a part corresponding to each memory cell MC and its vicinity in astorage device 10 according to the present embodiment. As illustrated inFIG. 13 , acrystal layer 90 is formed at a position adjacent to thephase change layer 40 on the negative side in the z direction in the present embodiment. Thecrystal layer 90 included in each memory cell MC1 on the lower side will be also referred to as a “crystal layer 91” in the following description. Similarly, thecrystal layer 90 included in each memory cell MC2 on the upper side will be also referred to as a “crystal layer 92” in the following description. - A position at which the
crystal layer 91 is formed can be expressed as a position between thephase change layer 41 and thebit line 31. A position at which the crystal layer 92 is formed can be expressed as a position between thephase change layer 42 and theword line 20. Each position corresponds to a position between the resistance change layer and the first wiring layer in the memory cell MC. - The
crystal layer 90 is formed of a titanium ditelluride (TiTe2) crystal. TiTe2 is a two-dimensional crystal, and thecrystal layer 90 is formed so that the “a” axis and the “b” axis of the crystal are oriented in directions orthogonal to the z direction. The material of thecrystal layer 90 is not limited to TiTe2, and other transition metal compound may be used as the material of thecrystal layer 90. As such a material, for example, a material such as hafnium ditelluride (HfTe2) and zirconium ditelluride (ZrTe2) can be used. - To manufacture the
storage device 10 according to the present embodiment, thecrystal layer 91 may be formed after theconductive layer 72 is formed in the stacking process, and thephase change layer 41 may be formed to cover thecrystal layer 91. Similarly, the crystal layer 92 may be formed after theconductive layer 75 is formed, and thephase change layer 42 may be formed to cover the crystal layer 92. - In this case, the
phase change layer 40 is formed on the upper surface of TiTe2 formed as an orientation layer in advance, and thus a crystal structure having a C axis oriented in the z direction can be achieved more easily. Moreover, higher adhesion can be achieved between thephase change layer 40 and an electrode layer (theconductive layer 72 or the conductive layer 75) on the lower side of thephase change layer 40. - In the present invention, “high potential” means that the voltage is high in the positive direction unless otherwise defined.
- The present embodiments are described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Modifications of these specific examples in designing by the skilled person in the art as appropriate are included in the scope of the present disclosure as long as characteristics of the present disclosure are maintained. Each element included in each specific example described above and, for example, the disposition, condition, and shape of the element are not limited to those exemplarily described but may be changed as appropriate. Combinations of elements included in the specific examples described above may be changed as appropriate as long as no technological inconsistency occurs.
Claims (19)
1. A storage device comprising:
a first wiring layer;
a second wiring layer;
a resistance change layer containing tellurium and disposed between the first wiring layer and the second wiring layer; and
an adjacent layer containing at least one of a group consisting of germanium, silicon, carbon, tin, aluminum, gallium, and indium and disposed between the second wiring layer and the resistance change layer and adjacent to the resistance change layer in a first direction, wherein
the resistance change layer is capable of changing between a first state and a second state different from each other in electric resistance,
the resistance change layer is in a crystal state in any of the first state and the second state, and
a length of the adjacent layer in a second direction orthogonal to the first direction is shorter than a length of the resistance change layer in the second direction.
2. The storage device according to claim 1 , wherein the resistance change layer has a crystal structure having a C axis oriented in the first direction.
3. The storage device according to claim 2 , wherein a crystal layer containing transition metal is formed between the resistance change layer and the first wiring layer.
4. The storage device according to claim 1 , wherein the resistance change layer has a thickness equal to or larger than 5 nm in the first direction.
5. The storage device according to claim 1 , wherein when the resistance change layer is caused to change between the first state and the second state, a voltage pulse with which potential of the first wiring layer becomes higher than potential of the second wiring layer is applied to the resistance change layer and the adjacent layer.
6. A storage device comprising:
a first wiring layer;
a second wiring layer;
a resistance change layer disposed between the first wiring layer and the second wiring layer and having a crystal structure having a C axis oriented in the first direction; and
an adjacent layer containing a diffusive material that diffuses inside the resistance change layer and disposed between the second wiring layer and the resistance change layer and adjacent to the resistance change layer in a first direction, wherein
the resistance change layer is capable of changing between a first state and a second state different from each other in electric resistance in accordance with distribution of the diffusive material diffusing from the adjacent layer, and
the resistance change layer is in a crystal state in any of the first state and the second state.
7. The storage device according to claim 6 , wherein a length of the adjacent layer in a second direction orthogonal to the first direction is shorter than a length of the resistance change layer in the second direction.
8. The storage device according to claim 6 , wherein the resistance change layer contains tellurium.
9. The storage device according to claim 6 , wherein the diffusive material is at least one of a group consisting of germanium, silicon, carbon, tin, aluminum, gallium, and indium.
10. The storage device according to claim 6 , wherein the resistance change layer has a thickness equal to or larger than 5 nm in the first direction.
11. The storage device according to claim 6 , wherein when the resistance change layer is caused to change between the first state and the second state, a voltage pulse with which potential of the first wiring layer becomes higher than potential of the second wiring layer is applied to the resistance change layer and the adjacent layer.
12. The storage device according to claim 6 , wherein a crystal layer containing transition metal is formed between the resistance change layer and the first wiring layer.
13. A storage device comprising:
a first wiring layer;
a second wiring layer;
a resistance change layer disposed between the first wiring layer and the second wiring layer; and
an adjacent layer containing a diffusive material that diffuses inside the resistance change layer and disposed between the second wiring layer and the resistance change layer and adjacent to the resistance change layer in a first direction, wherein
the resistance change layer is capable of changing between a first state and a second state different from each other in electric resistance in accordance with distribution of the diffusive material diffusing from the adjacent layer,
the resistance change layer is in a crystal state in any of the first state and the second state, and
a length of the adjacent layer in a second direction orthogonal to the first direction is shorter than a length of the resistance change layer in the second direction.
14. The storage device according to claim 13 , wherein the resistance change layer contains tellurium.
15. The storage device according to claim 13 , wherein the diffusive material is at least one of a group consisting of germanium, silicon, carbon, tin, aluminum, gallium, and indium.
16. The storage device according to claim 13 , wherein the resistance change layer has a crystal structure having a C axis oriented in the first direction.
17. The storage device according to claim 16 , wherein a crystal layer containing transition metal is formed between the resistance change layer and the first wiring layer.
18. The storage device according to claim 13 , wherein the resistance change layer has a thickness equal to or larger than 5 nm in the first direction.
19. The storage device according to claim 13 , wherein when the resistance change layer is caused to change between the first state and the second state, a voltage pulse with which potential of the first wiring layer becomes higher than potential of the second wiring layer is applied to the resistance change layer and the adjacent layer.
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