US20220364222A1 - Cooling Device and Process for Cooling Double-Sided SiP Devices During Sputtering - Google Patents
Cooling Device and Process for Cooling Double-Sided SiP Devices During Sputtering Download PDFInfo
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- US20220364222A1 US20220364222A1 US17/814,796 US202217814796A US2022364222A1 US 20220364222 A1 US20220364222 A1 US 20220364222A1 US 202217814796 A US202217814796 A US 202217814796A US 2022364222 A1 US2022364222 A1 US 2022364222A1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention relates in general to semiconductor manufacturing and, more particularly, to a device and method for cooling double-sided system-in-package (SiP) devices during sputtering.
- SiP system-in-package
- Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
- EMI electromagnetic interference
- RFID radio frequency interference
- harmonic distortion or other inter-device interference, such as capacitive, inductive, or conductive coupling, also known as cross-talk, which can interfere with their operation.
- EMI electromagnetic interference
- RFID radio frequency interference
- cross-talk other inter-device interference
- capacitive, inductive, or conductive coupling, also known as cross-talk can interfere with their operation.
- the high-speed switching of digital circuits also generates interference.
- Conductive layers can be formed over semiconductor packages to shield electronic parts within the package from EMI and other interference. Shielding layers absorb EMI before the signals can hit semiconductor die and discrete components within the package, which might otherwise cause malfunction of the device. Shielding layers are also formed over packages with components that are expected to generate EMI to protect nearby devices.
- the shielding layers are commonly formed by sputtering, which generates a significant amount of heat.
- sputtering which generates a significant amount of heat.
- increasing the temperature of a package during sputtering can cause several problems, such as remelting of solder, extrusion, warpage, or material damage. Therefore, semiconductor packages are typically disposed on a cooling pad during sputtering to keep the package under 150-200 degrees Celsius (° C.). Staying below 200° C. is generally satisfactory, but staying below 150° C. is preferred.
- FIG. 1 illustrates a semiconductor package 30 being sputtered to add a shielding layer.
- Package 30 includes a package substrate 32 .
- a semiconductor die 40 , sub-package 50 with semiconductor die 52 , and other surface mount components are disposed on substrate 32 to provide the electrical functionality of package 30 .
- Solder 54 is used to physically and electrically couple semiconductor die 40 and sub-package 50 to substrate 32 . Melting of solder 54 during sputtering could cause discontinuities in the electrical connections to substrate 32 .
- An encapsulant or molding compound 60 is deposited over substrate 32 , die 40 , and sub-package 50 .
- package 30 is disposed on cooling pad 70 within sputtering machine 72 .
- Package 30 is bombarded with metal molecules 74 , e.g. copper, within sputtering machine 72 to build up a conductive shielding layer 80 .
- the temperature within sputtering machine 72 stays around 400° C. during sputtering, and thermal energy is constantly added to package 30 while sputtering is ongoing.
- Substrate 32 lies flat on cooling pad 70 for good thermal contact between package 30 and the cooling pad.
- Cooling pad 70 is made of a flexible material to tightly adhere to the bottom surface of substrate 32 . Cooling pad 70 withdraws thermal energy through substrate 32 to keep package 30 below a desired target temperature.
- Newer packaging types such as system-in-package devices, commonly use surface mount components on both sides of a package substrate as shown with package 100 in FIG. 2 .
- Substrate 101 of package 100 has passive components 102 and semiconductor die 104 mounted on the bottom surface and passive components 106 mounted on the top surface. Any combination of components can be disposed on any surface of substrate 101 .
- Encapsulant 108 is deposited over substrate 101 and components 106 .
- a frame 110 holds package 100 in sputtering machine 72 while the sputtering process deposits shielding layer 120 over encapsulant 108 .
- package 100 is disposed on cooling pad 70 .
- substrate 101 does not directly contact cooling pad 70 .
- Thermal energy can only be withdrawn from components 106 via semiconductor die 104 .
- Not having direct contact with substrate 101 reduces the rate of thermal energy being extracted from the top part of package 100 and means that the temperature of the package is unlikely to remain satisfactory.
- Package 100 has a high likelihood of manufacturing defects being introduced during sputtering because of the elevated temperature. Therefore, a need exists for an improved cooling mechanism usable with double-sided SiP devices.
- FIG. 1 illustrates sputtering a semiconductor package
- FIG. 2 illustrates sputtering a double-side system-in-package device
- FIGS. 3 a -3 c illustrate a cooling pad having movable pins
- FIG. 4 illustrates the double-sided system-in-package device in a sputtering machine with the cooling pad having movable pins
- FIG. 5 illustrates a cooling circuit including the cooling pad having movable pins
- FIG. 6 illustrates a coating formed on top of the movable pins
- FIGS. 7 a -7 d illustrate movable pins disposed in physical contact with each other and a coating on the sides of the movable pins to reduce friction
- FIGS. 8 a and 8 b illustrate different shapes for the tips of the movable pins
- FIGS. 9 a -9 d illustrate different shapes for the footprints of the movable pins.
- semiconductor die refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
- Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer.
- Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits.
- Active electrical components such as transistors and diodes, have the ability to control the flow of electrical current.
- Passive electrical components such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.
- Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation.
- the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes.
- the wafer is singulated using a laser cutting tool or saw blade.
- the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package.
- the electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds.
- An encapsulant or other molding compound is deposited over the package to provide physical support and electrical isolation.
- the finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
- FIG. 3 a illustrates a cooling pad 150 with movable pins 160 that can be used in a sputtering machine to keep double-sided system-in-package (SiP) devices sufficiently cool.
- Cooling pad 150 has a base 152 with a fluid pathway 154 running through the base. During use, a cooling fluid flows through fluid pathway 154 to carry away thermal energy.
- the cooling fluid can be a chemical coolant, refrigerant, water, oil, gas, or any other suitable fluid.
- Pins 160 extend through openings in the top of base 152 so that the top of the pins are outside of the base and the bottoms of the pins are within fluid pathway 154 .
- the opening in base 152 are just large enough to allow pins 160 to move in the openings without leaking fluid through the openings.
- a gromet or other mechanism is used to seal the opening around pins 160 .
- Pins 160 are formed from a metal, such as copper, aluminum, or gold, or a polymer having high thermal conductivity, or another material having suitable thermal conductivity.
- Pins 160 are spring-loaded with springs 170 so that the pins can be pressed into fluid pathway 154 by a package to be cooled.
- Springs 170 are formed from any suitable material, such as those mentioned above for pins 160 .
- Springs 170 can be made of a thermally conductive material to aid in thermal transfer to the cooling fluid. After the package is removed, pins 160 spring back out to the position shown in FIG. 3 a .
- an elastic material that stretches is used instead of coiled springs. Any suitable elastic mechanism can be used to return pins 160 to their fully extended position.
- FIG. 3 b shows a pin 160 and spring 170 separated from base 152 .
- Pin 160 includes a top portion 162 with a tip 163 .
- Top portion 162 is the portion of pin 160 that extends outside of base 152 .
- a bottom portion 164 of pin 160 is the portion that is disposed within fluid pathway 154 .
- Bottom portion 164 extends into spring 170 to keep the spring on the pin within base 152 .
- top portion 162 and bottom portion 164 are of a uniform cross-section when viewed from tip 163 .
- bottom portion 164 is thinner, thicker, or differently shaped than top portion 162 and may be simply a small bump on the bottom of the pin.
- spring 170 extends into a groove on the bottom of pin 160 rather than around a bump.
- Fluid pathway 154 optionally has bumps or other structures on the bottom of the fluid pathway for holding the opposite ends of springs 170 .
- Pin 160 includes a flange 166 formed around the pin between top portion 162 and bottom portion 164 .
- Flange 166 serves dual purposes, to both keep pin 160 within base 152 and to allow the pin to interact with spring 170 .
- a package to be cooled presses down on tip 163 of pin 160 , the pin moves downward into base 152 .
- Flange 166 presses against the top of spring 170 as pin 160 moves downward, thereby compressing the spring.
- springs 170 decompress and press against flange 166 to move the pin back upward.
- flange 166 hits the top of fluid pathway 154 and springs 170 stop decompressing.
- Flange 166 keeps spring 170 from undesirably pushing pin 160 completely out of base 152 .
- Flange 166 is a disk having a common center with top portion 162 and bottom portion 164 .
- Flange 166 has a circular shape with a circumference extending completely around pin 160 .
- flange 166 is simply two dowels or bumps extending in opposite directions from the pin.
- One dowel or bump on only one side of pin 160 is used in other embodiments.
- Having a flange 166 that does not extend in all directions from the center of pin 160 allows adjacent pins to be disposed closer together.
- the discrete flange 166 portions of adjacent pins 160 can be positioned offset from each other so that the pins can be formed within the distance of a single flange width of each other, rather than having to be spaced by two flange widths.
- No flange is necessary in embodiments where spring 170 extends into a groove on the bottom of pin 160 , or if the springs otherwise apply force to the bottom of the pins.
- a tab of base 152 can extend into pin 160 to keep the pins within the base, rather than relying on flange 166 hitting the top of fluid pathway 154 .
- FIG. 3 c illustrates a top-down plan view of cooling pad 150 with base 152 cross-sectioned to show fluid pathway 154 with a serpentine shape.
- the footprint of cooling pad 150 can be expanded to accommodate any sized semiconductor package, or a multi-device panel that will be singulated after sputtering. Cooling fluid flows back and forth across the entire width of base 152 multiple times to get from fluid inlet 155 to fluid outlet 156 .
- the serpentine shape of fluid pathway 154 forces the cooling fluid to flow across each pin 160 and spring 170 with substantially equal volume per unit time.
- fluid pathway 154 is one large chamber, multiple parallel paths, or any other suitable shape.
- FIG. 4 shows cooling pad 150 disposed in sputtering machine 72 with double-sided SiP device 100 disposed on the cooling pad.
- SiP device 100 is pressed down onto pins 160 . Tips 163 of pins 160 press against SiP device 100 as the SiP device is pressed downward.
- Each pin 160 is pressed down a certain distance depending on what portion of SiP device 100 is directly over the particular pin.
- Pins 160 directly under die 104 are pressed down the most, such that springs 170 are fully or nearly fully compressed.
- Pins 160 that are directly under discrete components 102 are not pressed down as far as pins under die 104 but still have tips 163 that are pressed against the discrete components by springs 170 .
- Pins 160 that are not under any components on the bottom of substrate 101 have tips 163 pressing against the bottom surface of the substrate.
- the pins 160 that contact substrate 101 still compress respective springs 170 somewhat so that the pins apply some force against the substrate.
- substrate 101 is positioned to rest in contact with pins 160 without compressing respective springs 170 .
- Pins 160 draw thermal energy from SiP device 100 through physical contact. Because the heights of pins 160 adjust based on the shape of the bottom of a package being sputtered, the pins provide physical contact of the cooling surface for a much larger surface area than prior art cooling pads. Pins 160 not only draw thermal energy from die 104 , but also directly from substrate 101 and discrete components 102 .
- Pins 160 transfer thermal energy down to within fluid pathway 154 where the thermal energy is further transferred to the cooling fluid and carried away by the flow. Thermal energy is also transferred from pins 160 to springs 170 , which helps present a larger surface area to the flow of cooling fluid due to the coiled shape. All pins contact the bottom of package 100 , which provides sufficient thermal capacity to keep the package under 150-200° C.
- top portion 162 of each pin is made at least as long, from flange 166 to tip 163 , as the tallest expected device to be disposed on the bottom side of a package being sputtered so that in all expected cases pins 160 are able to physically contact substrate 101 .
- FIG. 5 illustrates a full cooling loop with cooling pad 150 , pump 180 , and radiator 182 coupled in a fluid circuit via tubes 184 .
- Pump 180 creates a pressure differential between an input and output of the pump to propel fluid through the system.
- pump 180 pulls cooling fluid from base 152 via outlet 156 and a first tube 184 , and then pushes the fluid into radiator 182 via a second tube 184 .
- the fluid flows through radiator 182 and then back to inlet 155 of cooling pad 150 via a third tube 184 .
- Radiator 182 has fans 186 attached to push air through the radiator and cool off the fluid.
- Radiator 182 includes a fluid pathway and several fins that are warmed by the cooling fluid.
- Fans 186 blow ambient air through the radiator across the fins to transfer thermal energy from the fins to the ambient air. Cooling fluid is returned to base 152 via tube 184 to absorb more thermal energy from package 100 via pins 160 .
- thermal heat exchanger can be used instead of a radiator as illustrated.
- electrically powered Peltier coolers are used.
- One embodiment utilizes a refrigeration cycle to cool base 152 .
- the refrigeration cycle uses a refrigerant as the cooling fluid, and has a compressor, condenser, and expansion valve as part of the fluid circuit.
- Base 152 acts like an evaporator for the system and cools off pins 160 as part of the evaporation process.
- Base 152 may need a modified structure to properly act as an evaporator in the refrigeration cycle.
- Any type of heat exchangers can be used for radiator 182 and base 152 .
- Base 152 exchanges heat from package 100 to the cooling fluid.
- Radiator 182 exchanges heat from the cooling fluid to ambient air or another medium.
- FIG. 6 illustrates a pin 160 with a surface coating 200 on tip 163 of the pin.
- Pins 160 of cooling pad 150 optionally have surface coating 200 made of a damping material, such as silicone or polytetrafluoroethylene (PTFE).
- Surface coating 200 reduces friction and softens tip 163 , which reduces the likelihood of damage to the device being cooled and helps accommodate slight lateral movements of the device relative to the pins.
- FIG. 7 a is a top-down plan view while FIG. 7 b is a side view.
- pins 160 are close enough that adjacent pins are likely to physically contact each other during use.
- FIG. 7 c shows a coating 202 formed on the side surfaces all the way around pin 160 .
- Coating 202 can be formed from PTFE or another low-friction material that allows pins 160 to slide against each other.
- FIG. 7 d shows a pin 160 with coating 204 formed both on the side surfaces and also on tip 163 . Coating 204 provides the benefits of both coating 200 and coating 202 .
- coating 200 and coating 202 can be formed separately from the same or two different materials on pins 160 .
- FIGS. 8 a and 8 b illustrate different tip shapes for pins.
- FIG. 8 a shows pin 210 with a beveled tip 212 .
- a beveled surface 214 provides a transition from the side surface to the top surface.
- the edges of tip 212 can be rounded instead.
- FIG. 8 b illustrates a pin 220 with the entire tip 222 rounded. Rounded or beveled tips reduce the likelihood of damage from sharp tip corners and help the pins conform to angled surfaces.
- Pins can also be formed with a wide variety of profile shapes in plan view, as well as a variety of layouts within base 152 .
- FIG. 9 a shows round pins 160 oriented in a regular grid on base 152 .
- FIG. 9 b shows round pins 160 with rows of pins offset from each other. Rows being offset allows more round pins 160 to be placed in the same footprint area of base 152 .
- FIG. 9 c shows pins 230 with triangular profile shapes. The triangular pins can have all three side surfaces of each pin facing another adjacent pin so that nearly the entire surface of base 152 is covered in pins.
- Pins can have any desired profile shape in footprint view, e.g., rectangular, triangular, circular, etc. Multiple different shapes of pins can be used together on a single cooling pad, e.g., circular pins 160 and triangular pins 230 are used together in FIG. 9 d . Each circular pin 160 is surrounded by a triangular pin 230 on each cardinal direction from the circular pin. The size, footprint shape, tip shape, and layout of pins is not limited.
Abstract
Description
- The present application is a division of U.S. patent application Ser. No. 17/032,437, filed Sep. 25, 2020, which claims the benefit of priority of U.S. Provisional Application No. 63/001,213, filed Mar. 27, 2020, which applications are incorporated herein by reference.
- The present invention relates in general to semiconductor manufacturing and, more particularly, to a device and method for cooling double-sided system-in-package (SiP) devices during sputtering.
- Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
- Semiconductor devices are often susceptible to electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, or other inter-device interference, such as capacitive, inductive, or conductive coupling, also known as cross-talk, which can interfere with their operation. The high-speed switching of digital circuits also generates interference.
- Conductive layers can be formed over semiconductor packages to shield electronic parts within the package from EMI and other interference. Shielding layers absorb EMI before the signals can hit semiconductor die and discrete components within the package, which might otherwise cause malfunction of the device. Shielding layers are also formed over packages with components that are expected to generate EMI to protect nearby devices.
- The shielding layers are commonly formed by sputtering, which generates a significant amount of heat. Unfortunately, increasing the temperature of a package during sputtering can cause several problems, such as remelting of solder, extrusion, warpage, or material damage. Therefore, semiconductor packages are typically disposed on a cooling pad during sputtering to keep the package under 150-200 degrees Celsius (° C.). Staying below 200° C. is generally satisfactory, but staying below 150° C. is preferred.
-
FIG. 1 illustrates asemiconductor package 30 being sputtered to add a shielding layer.Package 30 includes apackage substrate 32. A semiconductor die 40,sub-package 50 withsemiconductor die 52, and other surface mount components are disposed onsubstrate 32 to provide the electrical functionality ofpackage 30. Solder 54 is used to physically and electrically couple semiconductor die 40 andsub-package 50 tosubstrate 32. Melting ofsolder 54 during sputtering could cause discontinuities in the electrical connections tosubstrate 32. - An encapsulant or molding compound 60 is deposited over
substrate 32, die 40, andsub-package 50. After encapsulation,package 30 is disposed oncooling pad 70 withinsputtering machine 72.Package 30 is bombarded withmetal molecules 74, e.g. copper, within sputteringmachine 72 to build up aconductive shielding layer 80. The temperature withinsputtering machine 72 stays around 400° C. during sputtering, and thermal energy is constantly added topackage 30 while sputtering is ongoing.Substrate 32 lies flat oncooling pad 70 for good thermal contact betweenpackage 30 and the cooling pad.Cooling pad 70 is made of a flexible material to tightly adhere to the bottom surface ofsubstrate 32.Cooling pad 70 withdraws thermal energy throughsubstrate 32 to keeppackage 30 below a desired target temperature. - Newer packaging types, such as system-in-package devices, commonly use surface mount components on both sides of a package substrate as shown with
package 100 inFIG. 2 .Substrate 101 ofpackage 100 haspassive components 102 andsemiconductor die 104 mounted on the bottom surface andpassive components 106 mounted on the top surface. Any combination of components can be disposed on any surface ofsubstrate 101. Encapsulant 108 is deposited oversubstrate 101 andcomponents 106. Aframe 110 holdspackage 100 insputtering machine 72 while the sputtering processdeposits shielding layer 120 overencapsulant 108. - As with
package 30 inFIG. 1 ,package 100 is disposed oncooling pad 70. However, due tocomponents substrate 101 does not directly contactcooling pad 70. Thermal energy can only be withdrawn fromcomponents 106 viasemiconductor die 104. Not having direct contact withsubstrate 101 reduces the rate of thermal energy being extracted from the top part ofpackage 100 and means that the temperature of the package is unlikely to remain satisfactory.Package 100 has a high likelihood of manufacturing defects being introduced during sputtering because of the elevated temperature. Therefore, a need exists for an improved cooling mechanism usable with double-sided SiP devices. -
FIG. 1 illustrates sputtering a semiconductor package; -
FIG. 2 illustrates sputtering a double-side system-in-package device; -
FIGS. 3a-3c illustrate a cooling pad having movable pins; -
FIG. 4 illustrates the double-sided system-in-package device in a sputtering machine with the cooling pad having movable pins; -
FIG. 5 illustrates a cooling circuit including the cooling pad having movable pins; -
FIG. 6 illustrates a coating formed on top of the movable pins; -
FIGS. 7a-7d illustrate movable pins disposed in physical contact with each other and a coating on the sides of the movable pins to reduce friction; -
FIGS. 8a and 8b illustrate different shapes for the tips of the movable pins; and -
FIGS. 9a-9d illustrate different shapes for the footprints of the movable pins. - The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
- Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.
- Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding compound is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
- Electromagnetic interference (EMI) shielding layers are commonly formed over semiconductor packages as part of back-end manufacturing. As explained above, sputtering machines used to form the shielding layers generate heat that can cause manufacturing defects.
FIG. 3a illustrates acooling pad 150 withmovable pins 160 that can be used in a sputtering machine to keep double-sided system-in-package (SiP) devices sufficiently cool.Cooling pad 150 has a base 152 with afluid pathway 154 running through the base. During use, a cooling fluid flows throughfluid pathway 154 to carry away thermal energy. The cooling fluid can be a chemical coolant, refrigerant, water, oil, gas, or any other suitable fluid. -
Pins 160 extend through openings in the top ofbase 152 so that the top of the pins are outside of the base and the bottoms of the pins are withinfluid pathway 154. The opening inbase 152 are just large enough to allowpins 160 to move in the openings without leaking fluid through the openings. In some embodiments, a gromet or other mechanism is used to seal the opening around pins 160.Pins 160 are formed from a metal, such as copper, aluminum, or gold, or a polymer having high thermal conductivity, or another material having suitable thermal conductivity. -
Pins 160 are spring-loaded withsprings 170 so that the pins can be pressed intofluid pathway 154 by a package to be cooled.Springs 170 are formed from any suitable material, such as those mentioned above forpins 160.Springs 170 can be made of a thermally conductive material to aid in thermal transfer to the cooling fluid. After the package is removed, pins 160 spring back out to the position shown inFIG. 3a . In some embodiments, an elastic material that stretches is used instead of coiled springs. Any suitable elastic mechanism can be used to returnpins 160 to their fully extended position. -
FIG. 3b shows apin 160 andspring 170 separated frombase 152.Pin 160 includes atop portion 162 with atip 163.Top portion 162 is the portion ofpin 160 that extends outside ofbase 152. A bottom portion 164 ofpin 160 is the portion that is disposed withinfluid pathway 154. Bottom portion 164 extends intospring 170 to keep the spring on the pin withinbase 152. In one embodiment,top portion 162 and bottom portion 164 are of a uniform cross-section when viewed fromtip 163. In other embodiments, bottom portion 164 is thinner, thicker, or differently shaped thantop portion 162 and may be simply a small bump on the bottom of the pin. In some embodiments,spring 170 extends into a groove on the bottom ofpin 160 rather than around a bump.Fluid pathway 154 optionally has bumps or other structures on the bottom of the fluid pathway for holding the opposite ends ofsprings 170. -
Pin 160 includes aflange 166 formed around the pin betweentop portion 162 and bottom portion 164.Flange 166 serves dual purposes, to both keeppin 160 withinbase 152 and to allow the pin to interact withspring 170. When a package to be cooled presses down ontip 163 ofpin 160, the pin moves downward intobase 152.Flange 166 presses against the top ofspring 170 aspin 160 moves downward, thereby compressing the spring. When the package is removed from coolingpad 150, springs 170 decompress and press againstflange 166 to move the pin back upward. Eventually,flange 166 hits the top offluid pathway 154 and springs 170 stop decompressing.Flange 166 keepsspring 170 from undesirably pushingpin 160 completely out ofbase 152. -
Flange 166 is a disk having a common center withtop portion 162 and bottom portion 164.Flange 166 has a circular shape with a circumference extending completely aroundpin 160. In other embodiments,flange 166 is simply two dowels or bumps extending in opposite directions from the pin. One dowel or bump on only one side ofpin 160 is used in other embodiments. Having aflange 166 that does not extend in all directions from the center ofpin 160 allows adjacent pins to be disposed closer together. Thediscrete flange 166 portions ofadjacent pins 160 can be positioned offset from each other so that the pins can be formed within the distance of a single flange width of each other, rather than having to be spaced by two flange widths. No flange is necessary in embodiments wherespring 170 extends into a groove on the bottom ofpin 160, or if the springs otherwise apply force to the bottom of the pins. A tab ofbase 152 can extend intopin 160 to keep the pins within the base, rather than relying onflange 166 hitting the top offluid pathway 154. -
FIG. 3c illustrates a top-down plan view ofcooling pad 150 withbase 152 cross-sectioned to showfluid pathway 154 with a serpentine shape. The footprint ofcooling pad 150 can be expanded to accommodate any sized semiconductor package, or a multi-device panel that will be singulated after sputtering. Cooling fluid flows back and forth across the entire width ofbase 152 multiple times to get fromfluid inlet 155 tofluid outlet 156. The serpentine shape offluid pathway 154 forces the cooling fluid to flow across eachpin 160 andspring 170 with substantially equal volume per unit time. In other embodiments,fluid pathway 154 is one large chamber, multiple parallel paths, or any other suitable shape. -
FIG. 4 showscooling pad 150 disposed in sputteringmachine 72 with double-sided SiP device 100 disposed on the cooling pad.SiP device 100 is pressed down ontopins 160.Tips 163 ofpins 160 press againstSiP device 100 as the SiP device is pressed downward. Eachpin 160 is pressed down a certain distance depending on what portion ofSiP device 100 is directly over the particular pin.Pins 160 directly underdie 104 are pressed down the most, such that springs 170 are fully or nearly fully compressed.Pins 160 that are directly underdiscrete components 102 are not pressed down as far as pins underdie 104 but still havetips 163 that are pressed against the discrete components bysprings 170. -
Pins 160 that are not under any components on the bottom ofsubstrate 101 havetips 163 pressing against the bottom surface of the substrate. Thepins 160 thatcontact substrate 101 still compressrespective springs 170 somewhat so that the pins apply some force against the substrate. In other embodiments,substrate 101 is positioned to rest in contact withpins 160 without compressingrespective springs 170. -
Pins 160 draw thermal energy fromSiP device 100 through physical contact. Because the heights ofpins 160 adjust based on the shape of the bottom of a package being sputtered, the pins provide physical contact of the cooling surface for a much larger surface area than prior art cooling pads.Pins 160 not only draw thermal energy fromdie 104, but also directly fromsubstrate 101 anddiscrete components 102. -
Pins 160 transfer thermal energy down to withinfluid pathway 154 where the thermal energy is further transferred to the cooling fluid and carried away by the flow. Thermal energy is also transferred frompins 160 tosprings 170, which helps present a larger surface area to the flow of cooling fluid due to the coiled shape. All pins contact the bottom ofpackage 100, which provides sufficient thermal capacity to keep the package under 150-200° C. In one embodiment,top portion 162 of each pin is made at least as long, fromflange 166 to tip 163, as the tallest expected device to be disposed on the bottom side of a package being sputtered so that in all expected cases pins 160 are able to physically contactsubstrate 101. -
FIG. 5 illustrates a full cooling loop withcooling pad 150, pump 180, andradiator 182 coupled in a fluid circuit viatubes 184.Pump 180 creates a pressure differential between an input and output of the pump to propel fluid through the system. In the illustrated configuration, pump 180 pulls cooling fluid frombase 152 viaoutlet 156 and afirst tube 184, and then pushes the fluid intoradiator 182 via asecond tube 184. The fluid flows throughradiator 182 and then back toinlet 155 ofcooling pad 150 via athird tube 184.Radiator 182 hasfans 186 attached to push air through the radiator and cool off the fluid.Radiator 182 includes a fluid pathway and several fins that are warmed by the cooling fluid.Fans 186 blow ambient air through the radiator across the fins to transfer thermal energy from the fins to the ambient air. Cooling fluid is returned tobase 152 viatube 184 to absorb more thermal energy frompackage 100 viapins 160. - Any type of thermal heat exchanger can be used instead of a radiator as illustrated. In some embodiments, electrically powered Peltier coolers are used. One embodiment utilizes a refrigeration cycle to
cool base 152. The refrigeration cycle uses a refrigerant as the cooling fluid, and has a compressor, condenser, and expansion valve as part of the fluid circuit.Base 152 acts like an evaporator for the system and cools offpins 160 as part of the evaporation process.Base 152 may need a modified structure to properly act as an evaporator in the refrigeration cycle. Any type of heat exchangers can be used forradiator 182 andbase 152.Base 152 exchanges heat frompackage 100 to the cooling fluid.Radiator 182 exchanges heat from the cooling fluid to ambient air or another medium. -
FIG. 6 illustrates apin 160 with asurface coating 200 ontip 163 of the pin.Pins 160 ofcooling pad 150 optionally havesurface coating 200 made of a damping material, such as silicone or polytetrafluoroethylene (PTFE).Surface coating 200 reduces friction and softenstip 163, which reduces the likelihood of damage to the device being cooled and helps accommodate slight lateral movements of the device relative to the pins. - In some embodiments, the gap between
adjacent pins 160 becomes nearly zero, as shown inFIGS. 7a and 7b .FIG. 7a is a top-down plan view whileFIG. 7b is a side view. For such embodiments, pins 160 are close enough that adjacent pins are likely to physically contact each other during use.FIG. 7c shows acoating 202 formed on the side surfaces all the way aroundpin 160. Coating 202 can be formed from PTFE or another low-friction material that allowspins 160 to slide against each other.FIG. 7d shows apin 160 withcoating 204 formed both on the side surfaces and also ontip 163. Coating 204 provides the benefits of bothcoating 200 andcoating 202. Alternatively, coating 200 andcoating 202 can be formed separately from the same or two different materials onpins 160. - Pins can be made with a wide variety of shapes.
FIGS. 8a and 8b illustrate different tip shapes for pins.FIG. 8a showspin 210 with abeveled tip 212. Abeveled surface 214 provides a transition from the side surface to the top surface. The edges oftip 212 can be rounded instead.FIG. 8b illustrates apin 220 with theentire tip 222 rounded. Rounded or beveled tips reduce the likelihood of damage from sharp tip corners and help the pins conform to angled surfaces. - Pins can also be formed with a wide variety of profile shapes in plan view, as well as a variety of layouts within
base 152.FIG. 9a shows round pins 160 oriented in a regular grid onbase 152.FIG. 9b shows round pins 160 with rows of pins offset from each other. Rows being offset allows moreround pins 160 to be placed in the same footprint area ofbase 152.FIG. 9c showspins 230 with triangular profile shapes. The triangular pins can have all three side surfaces of each pin facing another adjacent pin so that nearly the entire surface ofbase 152 is covered in pins. - Pins can have any desired profile shape in footprint view, e.g., rectangular, triangular, circular, etc. Multiple different shapes of pins can be used together on a single cooling pad, e.g.,
circular pins 160 andtriangular pins 230 are used together inFIG. 9d . Eachcircular pin 160 is surrounded by atriangular pin 230 on each cardinal direction from the circular pin. The size, footprint shape, tip shape, and layout of pins is not limited. - While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims. While the description is drafted in terms of cooling during sputtering, the described cooling pad with movable pins can be used to cool any device in any situation.
Claims (25)
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010028552A1 (en) * | 2000-04-10 | 2001-10-11 | Cit Alcatel | Securing heat sinks to electronic components |
US20170256398A1 (en) * | 2016-03-03 | 2017-09-07 | Tokyo Electron Limited | Substrate processing apparatus, substrate processing method, and storage medium |
US20170326665A1 (en) * | 2014-12-09 | 2017-11-16 | Pink Gmbh Thermosysteme | Heat transfer device for producing a soldered connection of electrical components |
US20190390911A1 (en) * | 2018-06-21 | 2019-12-26 | The Boeing Company | Heat transfer devices and methods of cooling heat sources |
US20200033075A1 (en) * | 2018-07-30 | 2020-01-30 | The Boeing Company | Heat transfer devices and methods of transfering heat |
US11452225B2 (en) * | 2019-04-29 | 2022-09-20 | Semiconductor Components Industries, Llc | Fin frame assemblies |
US20230163048A1 (en) * | 2021-11-19 | 2023-05-25 | Google Llc | Temperature Control Element Utilized in Device Die Packages |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3326721B2 (en) | 1992-08-04 | 2002-09-24 | 富士通株式会社 | Cooling device for ceramic substrate |
US6867976B2 (en) | 2002-02-12 | 2005-03-15 | Hewlett-Packard Development Company, L.P. | Pin retention for thermal transfer interfaces, and associated methods |
US7244311B2 (en) | 2004-10-13 | 2007-07-17 | Lam Research Corporation | Heat transfer system for improved semiconductor processing uniformity |
US7601009B2 (en) * | 2006-05-18 | 2009-10-13 | Centipede Systems, Inc. | Socket for an electronic device |
US7580261B2 (en) * | 2007-03-13 | 2009-08-25 | Gm Global Technology Operations, Inc. | Semiconductor cooling system for use in electric or hybrid vehicle |
US9210831B2 (en) * | 2013-04-15 | 2015-12-08 | International Business Machines Corporation | Separable and integrated heat sinks facilitating cooling multi-compnent electronic assembly |
KR101988336B1 (en) * | 2016-06-07 | 2019-06-12 | 주식회사 에스에프에이 | Inline sputtering apparatus |
JP2018010964A (en) * | 2016-07-13 | 2018-01-18 | 株式会社村田製作所 | Manufacturing method of circuit module and deposition device |
JP7000129B2 (en) * | 2017-11-15 | 2022-01-19 | 芝浦メカトロニクス株式会社 | Film forming equipment |
-
2020
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Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010028552A1 (en) * | 2000-04-10 | 2001-10-11 | Cit Alcatel | Securing heat sinks to electronic components |
US20170326665A1 (en) * | 2014-12-09 | 2017-11-16 | Pink Gmbh Thermosysteme | Heat transfer device for producing a soldered connection of electrical components |
US20170256398A1 (en) * | 2016-03-03 | 2017-09-07 | Tokyo Electron Limited | Substrate processing apparatus, substrate processing method, and storage medium |
US10679845B2 (en) * | 2016-03-03 | 2020-06-09 | Tokyo Electron Limited | Substrate processing apparatus having cooling member |
US20190390911A1 (en) * | 2018-06-21 | 2019-12-26 | The Boeing Company | Heat transfer devices and methods of cooling heat sources |
US20200033075A1 (en) * | 2018-07-30 | 2020-01-30 | The Boeing Company | Heat transfer devices and methods of transfering heat |
US11452225B2 (en) * | 2019-04-29 | 2022-09-20 | Semiconductor Components Industries, Llc | Fin frame assemblies |
US20230163048A1 (en) * | 2021-11-19 | 2023-05-25 | Google Llc | Temperature Control Element Utilized in Device Die Packages |
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