US20220357874A1 - Memory controller for resolving string to string shorts - Google Patents
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- 230000015654 memory Effects 0.000 title claims abstract description 162
- 230000007547 defect Effects 0.000 claims abstract description 50
- 230000004044 response Effects 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 46
- 230000002950 deficient Effects 0.000 claims description 37
- 238000001514 detection method Methods 0.000 claims 6
- 230000008569 process Effects 0.000 description 26
- 238000013500 data storage Methods 0.000 description 17
- 238000004891 communication Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000003491 array Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
- G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1202—Word line control
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1204—Bit line control
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
Definitions
- FIG. 2 is a diagram illustrating string to string shorts in a three-dimensional NAND memory device.
- a first string to string short 202 is between String 0 and String 1 and across the slit half etch (SHE) at row 5 .
- the first string to string short 202 is a short between a first memory hole MH 1 of the String 0 , a second memory hole MH 2 of the String 1 , a third memory hole MH 5 of the String 0 , and a fourth memory hole MH 6 of the String 1 .
- FIG. 4 is a table illustrating a second example string defect leakage check 400 to detect shorts between pairs of neighboring strings, in accordance with some embodiments of the disclosure.
- FIG. 4 is described with respect to the BiCS architecture 200 of FIG. 2 .
- the second example string defect leakage check 400 includes applying a high bias at even strings (e.g., String 0 , String 2 , and String 4 ) while applying a low bias at odd strings (e.g., String 1 and String 3 ).
- the controller 120 controls the defective string information 164 to store a different binary number in the bit register Bit- 0 when the string pair String 0 and String 1 does have leakage. For example, the controller 120 controls the defective string information 164 to store a one in bit register Bit- 0 when the string pair String 0 and String 1 does have leakage, e.g., the first string to string short 202 .
- the first example process 600 includes performing the string defect leakage check during a first programming operation of the block (at block 602 ).
- the controller 120 performs the string defect leakage check (e.g., the first example string defect leakage check 300 or the second example string defect leakage check 400 as described above in FIGS. 3 and 4 , respectively) on all of the strings in the block 107 A during an erase operation.
- the string defect leakage check e.g., the first example string defect leakage check 300 or the second example string defect leakage check 400 as described above in FIGS. 3 and 4 , respectively
- FIG. 7 is a flowchart illustrating a second example process 700 for resolving string to string shorts, in accordance with some embodiments of the disclosure.
- FIG. 7 is described with respect to FIGS. 1, 3, and 4 and being performed on a block-by-block basis. However, FIG. 7 is not limited to being performed on a block-by-block basis and may be performed on any other suitable basis (e.g., a page-by page basis).
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Abstract
Description
- This application is a continuation of U.S. Non-Provisional patent application Ser. No. 16/898,098, filed on Jun. 10, 2020, the entire contents of which is incorporated herein by reference.
- This application relates generally to memory devices and, more particularly, to a controller in a memory device that resolves string to string shorts.
- In certain memory architectures, large block size leads to select gate drain (SGD) to slit half etch (SHE) shorts that may impact string operations. The SGD to SHE shorts may be due to process related issues or lithographic issues in manufacturing three-dimensional memory architectures (e.g., a Bit Cost Scalable (BiCS) architecture or other three-dimensional memory architecture).
- The present disclosure includes devices, methods, and apparatuses that resolve the SGD to SHE shorts (referred to herein as “string to string shorts”). In some examples, the devices, methods, and apparatuses of the present disclosure also recover memory blocks from the impact of the string to string shorts. For example, the devices, methods, and apparatuses of the present disclosure may still partially use the memory blocks that are impacted by the string to string shorts.
- The disclosure provides a memory controller including, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory having a plurality of memory blocks. Each memory block having a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one memory block of the plurality of memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the one or more string to string shorts in response to determining that the one memory block has the one or more string to string shorts.
- The disclosure also provides a method. In one embodiment, the method includes performing, with a controller circuit, a string defect leakage check on one memory block of a memory during a first programming operation of the one memory block. The method includes determining, with the controller circuit, whether the one memory block has one or more string to string shorts based on the string defect leakage check. The method also includes resolving, with the controller circuit, the one or more string to string shorts in response to determining that the one memory block has the one or more string to string shorts.
- The disclosure also provides an apparatus including, in one embodiment, means for performing a string defect leakage check on one memory block during a first programming operation of the one memory block, means for determining whether the one memory block has one or more string to string shorts based on the string defect leakage check, and means for resolving the one or more string to string shorts in response to determining that the one memory block has the one or more string to string shorts.
- In this manner, various aspects of the disclosure provide for improvements in at least the technical fields of memory devices and their design and architecture. The disclosure can be embodied in various forms, including hardware or circuits controlled by computer-implemented methods, computer program products, computer systems and networks, user interfaces, and application programming interfaces; as well as hardware-implemented methods, signal processing circuits, memory arrays, application specific integrated circuits, field programmable gate arrays, and the like. The foregoing summary is intended solely to give a general idea of various aspects of the disclosure, and does not limit the scope of the disclosure in any way.
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FIG. 1 is a block diagram of a system including a data storage device that has a memory controller that resolves string to string shorts, in accordance with some embodiments of the disclosure. -
FIG. 2 is a diagram illustrating string to string shorts in a three-dimensional NAND memory device. -
FIG. 3 is a table illustrating a first example string defect leakage check to detect shorts between pairs of neighboring strings, in accordance with some embodiments of the disclosure. -
FIG. 4 is a table illustrating a second example string defect leakage check to detect shorts between pairs of neighboring strings, in accordance with some embodiments of the disclosure. -
FIG. 5 is a table illustrating example bit registers that registers shorts between pairs of neighboring strings, in accordance with some embodiments of the disclosure. -
FIG. 6 is a flowchart illustrating a first example for resolving string to string shorts, in accordance with some embodiments of the disclosure. -
FIG. 7 is a flowchart illustrating a second example for resolving string to string shorts, in accordance with some embodiments of the disclosure. - In the following description, numerous details are set forth, such as data storage device configurations, controller operations, and the like, in order to provide an understanding of one or more aspects of the present disclosure. It will be readily apparent to one skilled in the art that these specific details are merely exemplary and not intended to limit the scope of this application. In particular, the functions associated with the memory device may be performed by hardware (e.g., analog or digital circuits), a combination of hardware and software (e.g., program code or firmware stored in a non-transitory computer-readable medium that is executed by processing or control circuitry), or any other suitable means. The following description is intended solely to give a general idea of various aspects of the disclosure, and does not limit the scope of the disclosure in any way.
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FIG. 1 is block diagram of a system including a data storage device that has a memory controller that resolves string to string shorts, in accordance with some embodiments of the disclosure. In the example ofFIG. 1 , thesystem 100 includes adata storage device 102 and ahost device 150. Thedata storage device 102 includes acontroller 120 and a memory 104 (e.g., non-volatile memory) that is coupled to thecontroller 120. - The
data storage device 102 and thehost device 150 may be operationally coupled via a connection (e.g., a communication path 110), such as a bus or a wireless connection. In some examples, thedata storage device 102 may be embedded within thehost device 150. Alternatively, in other examples, thedata storage device 102 may be removable from the host device 150 (i.e., “removably” coupled to the host device 150). As an example, thedata storage device 102 may be removably coupled to thehost device 150 in accordance with a removable universal serial bus (USB) configuration. In some implementations, thedata storage device 102 may include or correspond to a solid state drive (SSD), which may be used as an embedded storage drive (e.g., a mobile embedded storage drive), an enterprise storage drive (ESD), a client storage device, or a cloud storage drive, or other suitable storage drives. - The
data storage device 102 may be configured to be coupled to thehost device 150 via thecommunication path 110, such as a wired communication path and/or a wireless communication path. For example, thedata storage device 102 may include an interface 108 (e.g., a host interface) that enables communication via thecommunication path 110 between thedata storage device 102 and thehost device 150, such as when theinterface 108 is communicatively coupled to thehost device 150. - The
host device 150 may include an electronic processor and a memory. The memory may be configured to store data and/or instructions that may be executable by the electronic processor. The memory may be a single memory or may include one or more memories, such as one or more non-volatile memories, one or more volatile memories, or a combination thereof. Thehost device 150 may issue one or more commands to thedata storage device 102, such as one or more requests to erase data at, read data from, or write data to thememory 104 of thedata storage device 102. For example, thehost device 150 may be configured to provide data, such asuser data 132, to be stored at thememory 104 or to request data to be read from thememory 104. Thehost device 150 may include a mobile smartphone, a music player, a video player, a gaming console, an electronic book reader, a personal digital assistant (PDA), a computer, such as a laptop computer or notebook computer, any combination thereof, or other suitable electronic device. - The
host device 150 communicates via a memory interface that enables reading from thememory 104 and writing to thememory 104. In some examples, thehost device 150 may operate in compliance with an industry specification, such as a Universal Flash Storage (UFS) Host Controller Interface specification. In other examples, thehost device 150 may operate in compliance with one or more other specifications, such as a Secure Digital (SD) Host Controller specification or other suitable industry specification. Thehost device 150 may also communicate with thememory 104 in accordance with any other suitable communication protocol. - The
memory 104 of thedata storage device 102 may include a non-volatile memory (e.g., NAND, BiCS family of memories, or other suitable memory). In some examples, thememory 104 may be any type of flash memory. For example, thememory 104 may be two-dimensional (2D) memory or three-dimensional (3D) flash memory. Thememory 104 may include one or more memory dies 103. Each of the one or more memory dies 103 may include one or more blocks (also referred to herein as “one or more memory blocks” or in the singular as “a memory block”). Each block may include one or more groups of storage elements, such as a representative group ofstorage elements 107A-107N. The group ofstorage elements 107A-107N may be configured as a word line. The group ofstorage elements 107A-107N may include multiple storage elements (e.g., memory cells that are referred to herein as a “string”), such as arepresentative storage elements - The
memory 104 may include support circuitry, such as read/writecircuitry 140, to support operation of the one or more memory dies 103. Although depicted as a single component, the read/write circuitry 140 may be divided into separate components of thememory 104, such as read circuitry and write circuitry. The read/write circuitry 140 may be external to the one or more memory dies 103 of thememory 104. Alternatively, one or more individual memory dies may include corresponding read/write circuitry that is operable to read from and/or write to storage elements within the individual memory die independent of any other read and/or write operations at any of the other memory dies. - The
data storage device 102 includes thecontroller 120 coupled to the memory 104 (e.g., the one or more memory dies 103) via abus 106, an interface (e.g., interface circuitry), another structure, or a combination thereof. For example, thebus 106 may include multiple distinct channels to enable thecontroller 120 to communicate with each of the one or more memory dies 103 in parallel with, and independently of, communication with the other memory dies 103. In some implementations, thememory 104 may be a flash memory. - The
controller 120 is configured to receive data and instructions from thehost device 150 and to send data to thehost device 150. For example, thecontroller 120 may send data to thehost device 150 via theinterface 108, and thecontroller 120 may receive data from thehost device 150 via theinterface 108. Thecontroller 120 is configured to send data and commands to thememory 104 and to receive data from thememory 104. For example, thecontroller 120 is configured to send data and a write command to cause thememory 104 to store data to a specified address of thememory 104. The write command may specify a physical address of a portion of the memory 104 (e.g., a physical address of a word line of the memory 104) that is to store the data. - The
controller 120 is configured to send a read command to thememory 104 to access data from a specified address of thememory 104. The read command may specify the physical address of a region of the memory 104 (e.g., a physical address of a word line of the memory 104). Thecontroller 120 may also be configured to send data and commands to thememory 104 associated with background scanning operations, garbage collection operations, and/or wear-leveling operations, or other suitable memory operations. For example, thecontroller 120 is configured to send data and commands to thememory 104 according to the examples processes as described inFIGS. 6 and 7 . - The
controller 120 may includeavailable memory regions 122, amemory 124, an error correction code (ECC)engine 126, and anelectronic processor 128. Theavailable memory regions 122 may indicate a pool of free regions of thememory 104, such as one or more regions available to store data as part of a write operation. For example, theavailable memory regions 122 may be organized as a table or other data structure that is configured to track free regions of thememory 104 that are available for write operations. - One example of the structural and functional features provided by the
controller 120 are illustrated inFIG. 1 . However, thecontroller 120 is not limited to the structural and functional features provided by thecontroller 120 inFIG. 1 . Thecontroller 120 may include fewer or additional structural and functional features that are not illustrated inFIG. 1 . - The
memory 124 may be configured to store data and/or instructions that may be executable by theelectronic processor 128. Thememory 124 may include string to stringresolution program data 160,metrics 162, anddefective string information 164. In some examples, thedefective string information 164 may be a lookup table of all the storage elements 109 of thememory 104. In these examples, the storage elements 109 in the lookup table may be tracked on a block-by-block basis with the bit registers described inFIG. 5 . However, the lookup table is not limited to a block-by-block basis. Instead, the storage elements 109 in the lookup table may also be tracked on a storage element-by-storage element basis, on a wordline-by-wordline basis, on a die-by-die basis, or other suitable basis. - The string to string
resolution program data 160 may be instructions that are executable by theelectronic processor 128. The string to stringresolution program data 160 is described in greater detail below with respect toFIGS. 6 and 7 . - The
metrics 162 may be tracked on a storage element-by-storage element basis, on a wordline-by-wordline basis, on a block-by-block basis, on a die-by-die basis, or other suitable basis. The one ormore metrics 162 may track a program/erase (P/E) count (PEC), a bit error rate (BER), a programming time, an erase time, a number of voltage pulses to program a storage element, a number of voltage pulses to erase a storage element, a combination thereof, or other suitable metrics corresponding to thememory 104. In some examples, themetrics 162 may also include thedefective string information 164. -
FIG. 2 is diagram illustrating string to string shorts in a three-dimensional NAND memory device architecture. In the example ofFIG. 2 , the three-dimensional NAND memory device architecture is anexample BiCS architecture 200. Theexample BiCS architecture 200 includes a plurality of string to string shorts 202-208 across respective slit half etches (SHEs). - However, the three-dimensional NAND memory device architecture of
FIG. 2 is not limited to theexample BiCS architecture 200. The three-dimensional NAND memory device architecture ofFIG. 2 may be any suitable three-dimensional NAND memory device architecture, and theexample BiCS architecture 200 is used for ease of understanding. - In the example of
FIG. 2 , theBiCS architecture 200 has twenty staggered memory holes (twenty-four physical memory holes) divided into five strings, i.e., String0, String1, String2, String3, and String4 that are between two source lines, VCELSRC. In this example, the memory holes associated with String0 and String4 are “outer” memory holes and the memory holes associated with String1-String3 are “inner” memory holes. - In other embodiments, more or less than twenty staggered memory holes (more or less than twenty-four physical memory holes) may be formed. The memory holes may be divided into more or less than five strings. Specifically, memory holes may be divided at least into two or more strings. In some examples, the
BiCS architecture 200 may also have a block size of thirty-four megabytes, and due to this block size, the plurality of string to string shorts 202-208 is an issue that impacts string operations in theBiCS architecture 200. In other embodiments, a three-dimensional NAND memory array may have a block size of more or less than thirty-four megabytes, and due to this block size, the plurality of string to string shorts 202-208 is an issue that impacts string operations in theBiCS architecture 200. - A first string to string short 202 is between String0 and String1 and across the slit half etch (SHE) at row 5. In the example of
FIG. 2 , the first string to string short 202 is a short between a first memory hole MH1 of the String0, a second memory hole MH2 of the String1, a third memory hole MH5 of the String0, and a fourth memory hole MH6 of the String1. - A second string to string short 204 is between String1 and String2 and across the SHE at row 10. In the example of
FIG. 2 , the second string to string short 204 is a short between a first memory hole MH1 of the String1, a second memory hole MH2 of the String2, a third memory hole MH5 of the String1, and a fourth memory hole MH6 of the String2. - A third string to string short 206 is between String2 and String3 and across the SHE at
row 15. In the example ofFIG. 2 , the third string to string short 206 is a short between a first memory hole MH1 of the String2, a second memory hole MH2 of the String3, a third memory hole MH5 of the String2, and a fourth memory hole MH6 of the String3. - A fourth string to string short 208 is between String3 and String4 and across the SHE at row 20. In the example of
FIG. 2 , the fourth string to string short 208 is a short between a first memory hole MH1 of the String3, a second memory hole MH2 of the String4, a third memory hole MH5 of the String3, and a fourth memory hole MH6 of the String4. -
FIG. 3 is a table illustrating a first example string detect leakage check 300 to detect shorts between pairs of neighboring strings, in accordance with some embodiments of the disclosure.FIG. 3 is described with respect to theBiCS architecture 200 ofFIG. 2 . - In the example of
FIG. 3 , the first example string detect leakage check 300 includes applying a high bias between String0 and String1 while applying a low bias between String1 and String2, a low bias between String2 and String3, and a low bias between String3 and String4. - The first example string detect leakage check 300 includes applying a high bias between String1 and String2 while applying a low bias between String0 and String1, a low bias between String2 and String3, and a low bias between String3 and String4.
- The first example string detect leakage check 300 includes applying a high bias between String2 and String3 while applying a low bias between String0 and String1, a low bias between String1 and String2, and a low bias between String3 and String4.
- The first example string detect leakage check 300 also includes applying a high bias between String3 and String4 while applying a low bias between String0 and String1, a low bias between String1 and String2, and a low bias between String2 and String3.
- By performing the first example string detect leakage check 300 (i.e., applying a high bias to one neighboring pair of strings at a time while applying a low bias to the other strings), the
controller 120 detects a leakage current between different pairs of neighboring strings. For example, thecontroller 120 detects a leakage current between the different pairs of neighboring strings, i.e., String0 and String1, String1 and String2, String2 and String3, and String3 and String4 ofFIG. 2 , which indicates the plurality of string to string shorts 202-208 as illustrated inFIG. 2 . -
FIG. 4 is a table illustrating a second example stringdefect leakage check 400 to detect shorts between pairs of neighboring strings, in accordance with some embodiments of the disclosure.FIG. 4 is described with respect to theBiCS architecture 200 ofFIG. 2 . - In the example of
FIG. 4 , the second example stringdefect leakage check 400 includes applying a high bias at even strings (e.g., String0, String2, and String4) while applying a low bias at odd strings (e.g., String1 and String3). - In the example of
FIG. 4 , the second example stringdefect leakage check 400 also includes applying a high bias at odd strings (e.g., String1 and String3) while applying a low bias at even strings (e.g., String0, String2, and String4). - By performing the second example string defect leakage check 400 (i.e., applying a high bias to even or odd strings while applying a low bias to the other strings), the
controller 120 detects a leakage current at the different strings. For example, by performing the second example stringdefect leakage check 400, thecontroller 120 detects a leakage current at String1, String2, String3, and String4 ofFIG. 2 , which indicates the plurality of string to string shorts 202-208 as illustrated inFIG. 2 . - The
controller 120 may also perform the second example string defect leakage check 400 faster than the first example string detect leakage check 300 because the second example stringdefect leakage check 400 has less operations than the first example string detectleakage check 300. Thus, the second example stringdefect leakage check 400 is computationally more efficient than the first example string detectleakage check 300. -
FIG. 5 is a table illustrating example bit registers that registers shorts between pairs of neighboring strings, in accordance with some embodiments of the disclosure.FIG. 5 is described with respect to thecontroller 120 and thedefective string information 164 ofFIG. 1 and theBiCS architecture 200 ofFIG. 2 . - As illustrated in
FIG. 5 , the example 500 includes three bit registers Bit-0, Bit-1, and Bit-2. Thecontroller 120 controls thedefective string information 164 to store the same binary number when the string pair does not have any leakage. For example, thecontroller 120 controls thedefective string information 164 to store a zero in bit registers Bit-0, Bit-1, and Bit-2 when the string pair does not have any leakage. - The
controller 120 controls thedefective string information 164 to store a different binary number in the bit register Bit-0 when the string pair String0 and String1 does have leakage. For example, thecontroller 120 controls thedefective string information 164 to store a one in bit register Bit-0 when the string pair String0 and String1 does have leakage, e.g., the first string to string short 202. - The
controller 120 controls thedefective string information 164 to store a different binary number in the bit register Bit-1 when the string pair String1 and String2 does have leakage. For example, thecontroller 120 controls thedefective string information 164 to store a one in bit register Bit-1 when the string pair String1 and String2 does have leakage, e.g., the two string to string short 204. - The
controller 120 controls thedefective string information 164 to store a different binary number in the bit registers Bit-0 and Bit-1 when the string pair String2 and String3 does have leakage. For example, thecontroller 120 controls thedefective string information 164 to store a one in bit registers Bit-0 and Bit-1 when the string pair String2 and String3 does have leakage, e.g., the third string to string short 206. - The
controller 120 controls thedefective string information 164 to store a different binary number in the bit register Bit-2 when the string pair String3 and String4 does have leakage. For example, thecontroller 120 controls thedefective string information 164 to store a one in bit register Bit-2 when the string pair String3 and String4 does have leakage, e.g., the fourth string to string short 208. -
FIG. 6 is a flowchart illustrating afirst example process 600 for resolving string to string shorts, in accordance with some embodiments of the disclosure.FIG. 6 is described with respect toFIGS. 1, 3, and 4 and being performed on a block-by-block basis. However,FIG. 6 is not limited to being performed on a block-by-block basis and may be performed on any other suitable basis (e.g., a page-by page basis). - As illustrated in
FIG. 6 , thefirst example process 600 includes performing the string defect leakage check during a first programming operation of the block (at block 602). For example, thecontroller 120 performs the string defect leakage check (e.g., the first example string defect leakage check 300 or the second example string defect leakage check 400 as described above inFIGS. 3 and 4 , respectively) on all of the strings in theblock 107A during an erase operation. - The
first example process 600 includes determining whether the strings pass or fail based on the string defect leakage check (at decision block 604). For example, thecontroller 120 determines whether some or all of the strings in theblock 107A pass or fail based on the string defect leakage check. - The
first example process 600 includes skipping or retiring the block (at block 606) in response to determining that one or more strings of the block fail the string defect leakage check (“Fail” at block decision 604). For example, thecontroller 120 skips or retires theblock 107A in response to determining that one or more strings of the block failed the string defect leakage check. In some examples, thecontroller 120 may retire theblock 107A from the programming operations by removing theblock 107A from theavailable memory regions 122. - The
first example process 600 includes performing regular operation on the block (at block 608) in response to determining that all strings of the block do not fail the string defect leakage check (“Pass” at decision block 604). For example, thecontroller 120 performs regular operations on theblock 107A in response to determining that all strings of theblock 107A did not fail the string defect leakage check. -
FIG. 7 is a flowchart illustrating asecond example process 700 for resolving string to string shorts, in accordance with some embodiments of the disclosure.FIG. 7 is described with respect toFIGS. 1, 3, and 4 and being performed on a block-by-block basis. However,FIG. 7 is not limited to being performed on a block-by-block basis and may be performed on any other suitable basis (e.g., a page-by page basis). - As illustrated in
FIG. 7 , thesecond example process 700 includes performing the string defect leakage check during a first programming operation of a block (at block 702). For example, thecontroller 120 performs the string defect leakage check (e.g., the first example string defect leakage check 300 or the second example string defect leakage check 400 as described above inFIGS. 3 and 4 , respectively) on all of the strings in theblock 107A during an erase operation. - The
second example process 700 includes determining whether the strings of the block pass or fail based on the string defect leakage check (at decision block 704). For example, thecontroller 120 determines whether some or all of the strings in theblock 107A pass or fail based on the string defect leakage check. - The
second example process 700 includes updating defective string information of the block (at block 706) in response to determining that one or more strings of the block fail the string defect leakage check (“Fail” at block decision 704). For example, thecontroller 120 checks thedefective string information 164 in response to determining that one or more strings of theblock 107A failed the string defect leakage check and updates thedefective string information 164 to indicate that the one or more strings of theblock 107A failed the string defect leakage check. In some examples, thedefective string information 164 includes a lookup table that stores defective string information for theblocks 107A-107N. - The
second example process 700 includes disabling any newly defective strings of the block during a second programming operation of the block (at block 708). For example, thecontroller 120, during the next programming operation of the block, retrieves thedefective string information 164 and disables the one or more strings of theblock 107A that failed the string defect leakage check. In some examples, thecontroller 120 disables the defective strings of theblock 107A by retrieving the string information of theblock 107A from a lookup table in thedefective string information 164, during the programming operation of theblock 107A, and removes the one or more strings of theblock 107A from theavailable memory regions 122 based on the string information of theblock 107A that is retrieved from the lookup table. - The
second example process 700 includes performing regular operation on the block (at block 710) in response to determining that all strings of the block did not fail the string defect leakage check (“Pass” at decision block 704). For example, thecontroller 120 performs regular operations on theblock 107A in response to determining that all strings of theblock 107A did not fail the string defect leakage check. - The
second example process 700 recovers theblock 107A because the defective strings are disabled, which leaves theblock 107A available for partial use. Thesecond example process 700 is advantageous over thefirst example process 600 because the total number of strings available in thememory 104 will greater with thesecond example process 700 than thefirst example process 600. For example, thefirst example process 600 may retire ten blocks, which add up to three-hundred and forty megabytes of memory space that is removed from theavailable memory regions 122. However, thesecond example process 700 does not retire the ten blocks, but rather, disables the defective neighboring pairs of strings, which may result in significantly less than the three-hundred and forty megabytes of memory space being removed from theavailable memory regions 122. The advance of thesecond example process 700 over thefirst example process 600 becomes more pronounced with any additional increases in block size. - With regard to the processes, systems, methods, heuristics, etc. described herein, it should be understood that, although the steps of such processes, etc. have been described as occurring according to a certain ordered sequence, such processes could be practiced with the described steps performed in an order other than the order described herein. It further should be understood that certain steps could be performed simultaneously, that other steps could be added, or that certain steps described herein could be omitted. In other words, the descriptions of processes herein are provided for the purpose of illustrating certain embodiments, and should in no way be construed so as to limit the claims.
- Accordingly, it is to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments and applications other than the examples provided would be apparent upon reading the above description. The scope should be determined, not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. It is anticipated and intended that future developments will occur in the technologies discussed herein, and that the disclosed devices, methods, and apparatuses will be incorporated into such future embodiments. In sum, it should be understood that the application is capable of modification and variation.
- All terms used in the claims are intended to be given their broadest reasonable constructions and their ordinary meanings as understood by those knowledgeable in the technologies described herein unless an explicit indication to the contrary in made herein. In particular, use of the singular articles such as “a,” “the,” “said,” etc. should be read to recite one or more of the indicated elements unless a claim recites an explicit limitation to the contrary.
- The Abstract is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.
Claims (20)
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US20240006010A1 (en) * | 2022-07-01 | 2024-01-04 | Western Digital Technologies, Inc. | Storage System and Method for Proactive Die Retirement by Fatal Wordline Leakage Detection |
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US20020145907A1 (en) * | 2001-04-10 | 2002-10-10 | Samsung Electronics Co., Ltd. | Non-volatile semiconductor memory device having word line defect check circuit |
US20180052732A1 (en) * | 2016-08-16 | 2018-02-22 | SK Hynix Inc. | Semiconductor device and semiconductor system |
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US20020145907A1 (en) * | 2001-04-10 | 2002-10-10 | Samsung Electronics Co., Ltd. | Non-volatile semiconductor memory device having word line defect check circuit |
US20180052732A1 (en) * | 2016-08-16 | 2018-02-22 | SK Hynix Inc. | Semiconductor device and semiconductor system |
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