US20220254934A1 - Electronic circuit - Google Patents
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- US20220254934A1 US20220254934A1 US17/731,637 US202217731637A US2022254934A1 US 20220254934 A1 US20220254934 A1 US 20220254934A1 US 202217731637 A US202217731637 A US 202217731637A US 2022254934 A1 US2022254934 A1 US 2022254934A1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Definitions
- This disclosure in general relates to an electronic circuit, in particular an electronic circuit that includes at least one transistor device and a level shifter.
- Various types of electronic circuits include a half-bridge circuit with a first transistor device and a second transistor device that have their load paths connected in series. Each of these two transistor devices switches on and off dependent on a respective drive signal received at a respective control node.
- the drive signal is a drive voltage received between a gate node, which forms the control node of the MOSFET, and a source node.
- a half-bridge circuit may receive control signals that govern switching on and switching off the two transistor devices from a control circuit, such as a microcontroller, or the like.
- the first transistor device directly receives the respective control signal or a drive circuit coupled to the first transistor device directly receives the respective control signal, while a drive circuit connected to the second transistor device receives the respective control signal via a level shifter from the control circuit.
- the electronic circuit includes a first transistor device integrated in an inner region of a first semiconductor body, and a first drive circuit integrated in a first drive circuit region of the semiconductor body, configured to be connected to a level shifter and configured to drive a second transistor device.
- the first drive circuit region is located in an edge region surrounding the inner region of the semiconductor body.
- FIG. 1 shows a circuit diagram of one example of an electronic circuit that includes a first transistor device, an optional level shifter and a drive circuit configured to drive a second transistor device
- FIG. 2A schematically illustrates a vertical cross-sectional view of one section of a semiconductor body in which the first transistor device, the optional level shifter and the drive circuit are integrated;
- FIG. 2B schematically illustrates a vertical cross-sectional view of one section of a semiconductor body in which the first transistor device, and the drive circuit are integrated;
- FIG. 3 schematically illustrates a top view of the semiconductor body
- FIG. 4 schematically illustrates the vertical cross-sectional view shown in FIG. 2 in greater detail
- FIG. 5 shows a horizontal cross-sectional view of several transistor cells of the transistor device according to one example
- FIG. 6 shows a horizontal cross-sectional view of several transistor cells of the transistor device according to another example
- FIG. 7 shows one example of the level shifter and the drive circuit in detail
- FIG. 8 shows an inverter of the drive circuit shown in FIG. 7 in detail
- FIG. 9 shows one example of a level shifter transistor integrated in a level shifter region of the semiconductor body
- FIG. 10 shows a horizontal cross-sectional view of two (2) level shifter transistors of the type shown in FIG. 9 ;
- FIG. 11 shows one example of an inverter of the drive circuit integrated in a drive circuit region of the semiconductor body
- FIGS. 12A and 12B shows another one example of an inverter of the drive circuit integrated in the drive circuit region of the semiconductor body
- FIG. 13 shows one example of an electronic circuit that is based on the electronic circuit shown in FIG. 1 and further includes an input circuit connected between an input and the level shifter and a further drive circuit coupled to the first transistor device;
- FIG. 14 shows examples of the input circuit and the further drive circuit
- FIG. 15 schematically illustrates a vertical cross-sectional view of one section of a semiconductor body in which the first transistor device, the level shifter, the drive circuit, the further drive circuit and the input circuit are integrated;
- FIG. 16 shows one example of an electronic circuit that further includes the second transistor device
- FIG. 17 illustrates one example of a module: that includes an electronic: circuit of the type shown in FIG. 16 ;
- FIG. 18 illustrates another example of the module.
- FIG. 1 shows a circuit diagram of an electronic circuit according to one example
- FIGS. 2A and 2B each schematically illustrates a vertical cross-sectional view of one section of a semiconductor body 100 in which the electronic circuit is integrated
- FIG. 3 schematically illustrates a top view of the semiconductor body 100
- the electronic circuit includes a first transistor device 2 and a drive circuit 4 .
- the drive circuit 4 is configured to be connected to a level shifter 3 and is configured to drive a second transistor device (not shown in FIG. 1 ).
- the level shifter 3 (that is illustrated in dashed lines in FIG. 1 ) is optional in the electronic circuit and, therefore, the semiconductor body 100 . That is, the level shifter 3 may be included in the electronic circuit and integrated in the semiconductor body 100 or may be an external circuit that is not integrated in the semiconductor body.
- FIG. 2A illustrates a vertical cross-sectional view of a semiconductor body 100 in which the level shifter is integrated
- FIG. 2B illustrates a vertical cross-sectional view of a semiconductor body 100 in which the level shifter is not integrated. Everything, except for the level shifter 3 , explained in the following with regard to the semiconductor body 100 shown in FIG. 2A applies to the semiconductor body shown in FIG. 2B accordingly.
- the semiconductor body 100 includes a first (main) surface 107 , a second (main) surface 108 opposite the first surface 107 , and a side surface 109 that extends between the first surface 107 and the second surface 108 .
- FIGS. 2A and 2B shows a vertical cross-sectional view of one section of the semiconductor body 100 in a vertical section plane A-A.
- This vertical section plane A-A is a plane perpendicular to each of the first and second surfaces 107 , 108 of the semiconductor body 100 .
- FIG. 3 shows a horizontal cross-sectional view of the semiconductor body 100 in a horizontal section plane B-B in order to illustrate a.
- the horizontal section plane B-B is a plane parallel to each of the first and second surfaces 107 , 108 .
- the edge region 101 of the semiconductor body 100 is arranged between the inner region 102 and the side surface 109 of the semiconductor body 100 and the edge region 101 surrounds the inner region 102 . In horizontal planes of the semiconductor body 100 .
- FIGS. 2A, 2B and 3 only schematically illustrate the semiconductor body 100 .
- angles between the side surface 109 and the first surface 107 and the second surface 108 are about 90°. This, however, is only an example.
- the side surface 109 is beveled relative to the first and second surfaces 107 , 108 .
- the semiconductor body 100 may include a conventional (monocrystalline) semiconductor material such as, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or the like.
- a conventional (monocrystalline) semiconductor material such as, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or the like.
- the first transistor device 2 is integrated in the inner region 102 of the semiconductor body 100 . This integration is only schematically illustrated in FIGS. 2A and 2B . A more detailed example is explained herein further below,
- the semiconductor body 100 further includes, in the edge region 101 of the semiconductor body 100 , a first drive circuit region 104 .
- the semiconductor body 100 further includes a level shifter region 103 in the edge region 101 of the semiconductor, wherein the level shifter region 103 is arranged closer to the inner region 10 : 2 than the first drive circuit region 104 . More specifically, in a horizontal direction of the semiconductor body 100 , the level shifter region 103 is arranged between the first drive circuit region 104 and the inner region 102 and the first drive circuit region 104 is arranged between the level shifter region 103 and the first side surface 109 of the semiconductor body 100 .
- the “horizontal direction” is a direction parallel to the first and second surfaces 107 , 108 of the semiconductor body 100 .
- the level shifter 3 is integrated in the level shifter region 103 and the drive circuit 4 is integrated in the first drive circuit region 104 . This, however, is only schematically illustrated in FIGS. 2A and 23 . Examples are explained herein further below.
- each of the first transistor device 2 being integrated in the inner region 102
- the optional level shifter 3 being integrated in the level shifter region 103
- the drive circuit 4 being integrated in the first drive circuit region 104
- “integrated” means that each of the first transistor device 2 , the level shifter 3 and the drive circuit 4 includes several doped semiconductor regions that are located in the inner region 102 , the level shifter region 103 , and the first drive circuit region 104 , respectively, of the semiconductor body 100 .
- each of the first transistor device 2 the level shifter 3 and the drive circuit 4 may include conductors, electrodes, or the like formed on top of the first and/or the second surface 107 , 108 of the semiconductor body 100 .
- the first transistor device 2 includes a control node G, a load path D-S between a first load node S and a second load node D and is configured to switch on or off dependent on a drive voltage V GS received at a drive input.
- the load path D-S is connected between a first output node 11 and a second output node 12 of the electronic circuit, wherein these first and second output nodes are also referred to as first load output node 11 and a second load output node 12 in the following.
- the first transistor device 2 is a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor).
- MOSFET Metal Oxide Semiconductor Field-Effect Transistor
- IGFET insulated gate electrode
- the circuit symbol of the first transistor device 2 shown in FIG. 1 represents n-type enhancement MOSFET. This, however, is just for illustration purposes.
- MOSFET any other type of MOSFET such as a p-type enhancement MOSFET, a p-type depletion MOSFET, an n-type depletion MOSFET, or any other type of field-effect transistor such as an IGBT (Insulated Gate Bipolar Transistor) or a JFET (Junction Field-Effect Transistor) may be used as well.
- IGBT Insulated Gate Bipolar Transistor
- JFET Joint Field-Effect Transistor
- the control node G is also referred to as gate node
- the first load node S is also referred to as source node
- the second load node D is also referred to as drain node
- the drive voltage V GS is also referred to as gate-source voltage.
- the first transistor device 2 shown in FIG. 1 is not restricted to be implemented as a MOSFET, the terms gate node 0 , source node S and drain node D will be used in the following to denote the control node, the first load node and the second load node, respectively.
- the drive input receiving the drive voltage V GS formed by the gate node G and the source node S this is only an example.
- the drive input is formed by the gate node and an auxiliary source node that is different from the source node.
- the drive input is formed by the gate node and by a circuit node that is connected to the source node S via a (current measurement) resistor.
- the first transistor device 2 switches on or off dependent on the drive voltage V GS .
- this drive voltage V GS is dependent on a first input signal Sin 1 received at a first input 13 of the electronic circuit so that the first transistor device 2 switches on or off dependent on the first input signal Sin 1 . Examples of how the drive voltage V GS may be generated based on the first input signal Sin 1 are explained herein further below.
- the drive circuit 4 is configured to generate an output signal Sout at a further output 16 of the electronic circuit based on a level shifter signal S 3 received from the level shifter 3 .
- the level shifter 3 may be part of the electronic circuit and integrated in the semiconductor body 100 , or may be an external circuit. This further output 16 is also referred to as drive output in the following.
- the level shifter 3 is configured to generate the level shifter signal S 3 based on a second input signal Sin 2 , wherein the second input signal Sin 2 is received at a second input 14 of the electronic circuit when the level shifter 3 is part of the electronic circuit.
- the electronic circuit receives the level shifter signal S 3 instead of the second input signal Sin 2 .
- the output signal Sout at the further output 16 is generated based on the second input signal Sin 2 .
- the output signal Sout is a voltage at the drive output 16 that is referenced to the first load output node 11 .
- FIG. 4 shows a vertical cross-sectional view of the semiconductor body 100 in the section plane A-A explained above and illustrates one example of how the first transistor device 2 may be implemented in the inner region 102 .
- the first transistor device 2 is a MOSFET that includes a plurality of transistor cells 20 .
- Each of these transistor cells 20 includes a drift region 21 of a first doping type (conductivity type), a source region 22 of the first doping type and a body region 23 of a second doping type (conductivity type) complementary to the first doping type, wherein the body region 23 is arranged between the drift region 21 and the source region 22 .
- each transistor cell 20 includes a gate electrode 26 adjacent the body region 23 and dielectrically insulated from the body region 23 by a gate dielectric 27 .
- the gate electrodes 26 of the individual transistor cells 20 are connected to the gate node G or form the gate node G of the first transistor device 2 .
- the source and body regions 22 , 23 of the individual transistor cells 20 are connected to a source electrode 28 .
- This source electrode 28 forms the source node S or is connected to a source node S of the first transistor device 1 .
- Each transistor cell 20 further includes a drain region 24 of the first doping type, wherein the drain region 24 is separated from the body region 23 by the drift region 21 .
- the first transistor device 2 is a vertical transistor device.
- the transistor cells 20 of this vertical transistor device can be referred to as vertical transistor cells.
- the source region 22 is spaced apart from the drain region 24 in a vertical direction of the semiconductor body 100 , wherein the “vertical direction” is a direction perpendicular to the first surface 107 and the second surface 108 .
- a current in the drift region 21 essentially flows in the vertical direction of the semiconductor body 100 .
- the first transistor device 1 switches on or off dependent on the drive voltage V GS received between the gate node E1 and the source node 5 , wherein the gate electrode 26 dependent on this drive voltage V GS controls a conducting channel in the body region 23 between the source region 22 and the drift region 21 .
- the gate electrode 26 is a planar gate electrode arranged on top of the first surface 107 of the semiconductor body 100 . This, however, is only an example. According to another example (not shown) the gate electrode 26 is a trench electrode arranged in a trench extending from the first surface 107 into the semiconductor body 100 .
- a drain electrode 29 formed on the second surface 108 is connected to the drain region 24 .
- This drain electrode 22 is connected to the drain node D or forms the drain node D of the transistor device 2 .
- the drain electrode is arranged on top of the first surface 107 between the side surface 109 and the drive circuit region 104 and is connected to the drain region 24 via a semiconductor region of the same doping type as the drain region and extends in a vertical direction from the drain region 24 to the drain electrode.
- the drain region can be arranged on an electrically insulation carrier or on a semiconductor substrate of a doping type complementary to the doping type of the drain region 24 .
- the transistor cells 20 are connected in parallel in that the gate electrodes 26 of the individual transistor cells 20 are connected to the gate node G, the source and body region 22 , 23 of the transistor cells 20 are connected to the source node S, and the drain regions 24 are connected to the drain node D.
- the drain regions 24 of the individual transistor cells 20 are formed by one doped region 110 that adjoins the second surface 108 and is formed in the inner region 102 and the edge region 101 of the semiconductor body 100 .
- This doped region 110 may be formed by a semiconductor substrate, wherein the other doped regions explained above may be formed in an epitaxial layer formed on the substrate.
- the first transistor device 2 may be implemented as an n-type transistor device or as a p-type transistor device.
- the regions of the first doping type are n-type (n-doped) semiconductor regions and the regions of the second doping type are p-type (p-doped) regions.
- the regions of the first doping type are p-type regions and the region of the second doping type are n-type regions.
- the transistor device can be implemented as an enhancement device or as a depletion device.
- the body region 23 of the second doping type adjoins the gate dielectric 27 .
- each of the transistor cells : 20 further includes a channel region (not shown in the drawings) in the body region 23 , wherein the channel region is of the first doping type, adjoins the gate dielectric 27 and extends from the source region 22 to the drift region 21 .
- An enhancement device is in the on-state when the drive V GS is such that the gate electrode 26 generates an inversion channel in the body region 23 along the gate dielectric 27 and is in the off-state when the inversion channel is interrupted.
- a depletion device is in the on-state when the channel region of the first doping type along the gate dielectric is not depleted by the gate electrode 26 and is in the off-state when the gate electrode 26 depletes the channel region.
- the transistor device conducts a current when operated in the on-state and when a drain-source voltage different from zero is applied between the drain node D and the source node S.
- the first transistor device 2 is implemented as a superjunction device.
- each transistor cell 20 further includes a compensation region 25 of the second doping type, wherein the compensation region 25 adjoins the drift region 21 in a direction perpendicular to the current flow direction (that is, in a horizontal direction in the example shown in FIG. 4 ).
- the compensation region 25 is electrically connected to the source node S. In the example shown in FIG. 4 this is achieved in that the compensation region 25 adjoins the body region 23 .
- the compensation region 25 has a depth in the vertical direction of the semiconductor body 100 that is at least 50% or at least 70% of a distance between the body region 23 and the drain region 24 in the vertical direction.
- the distance between the body regions 23 and the drain region 24 is between 10 micrometers and 100 micrometers, in particular between 20 micrometers and 60 micrometers.
- This distance affects the voltage blocking capability of the transistor device.
- the “voltage blocking capability” is given by the maximum drain-source voltage the transistor device 2 can withstand in the off-state without a voltage breakdown (avalanche breakdown) occurring. Basically, the voltage blocking capability increases as the distance between the body regions 23 and the drain region 24 increases. In a transistor device with a voltage blocking capability of 600 volts (V), for example, this distance is between 40 micrometers ( ⁇ m) and 50 micrometers.
- FIG. 5 shows a horizontal cross-sectional view of one section of the inner region 10:2 in order to illustrate one example of how the transistor cells may be implemented in the horizontal plane.
- the transistor cells 20 are elongated transistor cells.
- the source and body regions 22 , 23 are elongated semiconductor regions with a length I in a first horizontal direction and a width w in a second horizontal direction perpendicular to the first horizontal direction, wherein the length is significantly greater than the width.
- a ratio 1:w between the length and the width is at least 10:1 or at least 100:1.
- the body regions 23 have a polygonal shape.
- the polygonal shape can be rectangular. This, however, is only an example.
- the body regions 23 may be implemented with any other type of polygonal shape as well.
- the gate electrodes 26 (which are out of view in FIG. 5 ) can be elongated electrodes formed above the first surface 107 .
- the gate electrodes 26 (which are out of view in FIG. 5 ) of the individual transistor cells 20 can be formed by one grid-shaped electrode formed above the first surface 107 .
- the semiconductor body 100 includes a doped region 120 of the first doping type in the edge region 101 .
- This semiconductor region 120 which is referred to as first region 120 in the following, is connected to the drain node D.
- the first semiconductor region 120 can be connected to the drain node D in that it adjoins the drain region 24 .
- a (maximum) doping concentration of the first region 120 may be equal to the (maximum) doping concentration of the drift regions 21 or may be higher.
- the semiconductor body 100 includes a second region 130 of the second doping type.
- This second region 130 is arranged in the edge region 101 , is spaced apart from the side surface 109 , forms a pn-junction with the first region 120 and is connected to the source node S.
- the second region 130 adjoins the body region 23 and the optional compensation region 25 of an outermost transistor cell.
- the “outermost transistor cell” is the transistor cell that is closest to the edge region 101 .
- the second region 130 may extend in the direction of the drain region 24 as far as the optional compensation regions 25 .
- the second region 130 may extend less in the direction of the drain region 24 than the optional compensation regions 25 .
- a maximum doping concentration of the second region 130 is lower than the maximum doping concentration of the drift region 21 .
- a doping concentration of the second regions 130 is less than 1E16 cm ⁇ 3 ,
- a lateral dimension of the second region 130 is less than a vertical dimension.
- the “lateral dimension” is the (shortest) dimension in a direction from the side surface 109 towards the inner region 102 .
- the “vertical dimension” is the (shortest) dimension in the vertical direction.
- the first region 120 is coupled to the drain node D and the second region 130 is coupled to the source node.
- the pn-junction between the first region 120 and the second region 130 may become reverse biased when the transistor device 2 is in the off-state.
- the doping concentrations of the first region 120 and the second region 130 are adapted to one another such that a voltage blocking capability of the pn-junction formed between the first region 120 and the second region 130 is greater than the voltage blocking capability of the transistor cells 20 in the inner region 102 .
- the breakdown occurs in the inner region 102 .
- this may be achieved by implementing the first and second regions 120 , 130 with a lower doping concentration than the drift region 21 .
- the doping concentration of the first region 120 may be selected such that the first region 120 cannot be completely depleted of charge carriers when the pn-junction between the first region 120 and the second region 130 is reverse biased.
- a space charge region (depletion region) that occurs when the pn-junction is reverse biased mainly expands in the second region 130 .
- the first drive circuit region 104 is embedded in the first semiconductor region 120 .
- the optional level shifter region 103 is embedded in the second region 130 .
- FIG. 7 shows an example of the optional level shifter 3 and the drive circuit 4 in greater detail.
- the level shifter 3 includes a first level shifter transistor 3 1 and a second level shifter transistor 3 2 each having a load path and a control node.
- the circuit symbols of the level shifter transistors 3 1 , 3 2 shown in FIG. 7 represent n-type MOSFETs.
- the load path of the first level shifter transistor 3 1 is connected between an input IN 1 of a first inverter 41 1 of the drive circuit 4 and the second load output 12 and the load path of the second level shifter transistor 3 2 is connected between an input IN 2 of a second inverter 41 2 of the drive circuit 4 and the second load output 12 .
- the second input 14 of the electronic circuit is a differential input with a first input node 14 1 and a second input node 14 2 .
- the first input node 14 1 is connected to the control node of the first level shifter transistor 3 1 and the second input node 142 is connected to the control node of the second level shifter transistor 3 2 .
- the first and second inverter 41 1 , 41 2 of the drive circuit 4 are cross-coupled. That is, an output OUT 1 of the first inverter 41 1 is connected to the input IN 2 of the second inverter 412 and an output OUT, of the second inverter 41 2 is connected to the input IN 1 of the first inverter 41 1 .
- Each of these first and second inverters 41 1 , 41 2 has a first supply input and a second supply input.
- the first supply input is connected to a first supply input 15 of the electronic circuit and the second. supply input is connected to the second load output 11 of the electronic circuit.
- the drive circuit 4 is configured to generate the output signal Sout at the drive output 16 as a voltage that is referenced to the first load output 11 .
- the drive circuit 4 further includes a comparator 42 having a first input connected to the output OUT 1 of the first inverter 41 1 and a second input connected to the output OUT 2 of the second inverter 41 2 .
- a driver 43 receives an output signal S 42 from the comparator 42 and generates the output signal Sout based on the comparator output signal S 42 .
- the driver 43 includes an inverter with a low-side transistor 43 L and a high-side transistor 4311 .
- Each of these transistors 43 H, 43 L has a load path and a control node. The load paths of these transistors 43 L, 43 H are connected in series between the supply node 15 and the first load output node 11 .
- the control nodes of these transistors 43 H, 43 L are connected with each other and connected to the output of the comparator 42 .
- the drive output 16 is formed by a circuit node common to the load nodes of the transistors 43 L, 43 H of the driver 43 .
- the low-side transistor 4311 and the high-side transistor 43 H are complementary transistors.
- the circuit symbol of the low-side transistor 43 L shown in FIG. 7 represents a n-type transistor and the circuit symbol of the high-side transistor 43 H shown in FIG. 7 represents a p-type transistor.
- the second input 14 is configured to receive complementary input signals Sin 2 1 , Sin 2 2 at the first and second input nodes 14 1 , 14 2 .
- each of these input signals Sin 2 1 , Sin 2 2 is a voltage referenced to the second load output 12 .
- “Complementary” means that, at the same time, one of these input signals Sin 2 1 , Sin 2 2 switches on the respective level shifter transistor 3 1 , 3 2 and the other one of these input signals Sin 2 1 , Sin 2 2 switches off the respective level shifter transistors 3 1 , 3 2 .
- the level shifter output signal S 3 shown in FIG. 1 is given by electrical potentials generated by the level shifter transistors 3 1 , 3 2 at the inputs IN 2 of the first and second inverters 411 , 412 .
- the output signal Sout generated by the drive circuit 4 has one of two different signal levels dependent on which of the first and second level shifter transistors 31 , 32 is in the on-state and which is in the off-state one. This is explained in the following.
- the output signal Sout has a first signal level when the comparator output signal S 42 switches on the high-side switch 43 H and switches off the low-side switch 43 L of the driver 43 , and the output Sout has a second signal level when the comparator output signal S 42 switches off the high-side switch 43 H and switches on the low-side switch 43 L.
- the first signal level essentially equals a voltage level of a supply voltage V SUP2 received by the electronic circuit between the first supply input 15 and the first load output node 11 . An example of generating this supply voltage V SUP2 is explained herein further below.
- the second signal level of the output signal Sout is essentially zero in this example.
- the comparator output signal S 42 can have two different signal levels, a first signal level that switches on the high-side switch 43 H and switches off the low-side switch 43 L of the driver 43 and a second signal level that switches off the high-side switch 43 H and switches on the low-side switch 43 L.
- a signal level of the comparator output signal S 42 is dependent on signal levels of signals V OUT1 , V OUT2 at the outputs OUT 1 , OUT 2 of the inverters 41 1 , 41 2 .
- these output signals V OUT1 , V OUT2 are voltages referenced to the first load output 11 and each can have two different signal level, a first signal level that essentially equals the voltage level of the supply voltage V SUP2 and a second signal level that essentially equals zero. Due to the cross-coupling of the inverters 41 1 , 41 2 , at the same time, the output signal V OUT1 , V OUT2 of one of the two inverters 41 1 , 41 2 has the first signal level and the output voltage V OUT1 , V OUT2 of the other one of the two inverters 41 1 , 41 2 has the second signal level.
- the signal level of the comparator output signal S 42 is dependent on which of the inverter output signals V OUT1 , V OUT2 has the first signal level and which has the second signal level.
- the signal levels of the inverter output signals V OUT1 , V OUT2 are dependent on the switching state of the level shifter transistors 3 1 , 3 2 .
- the first level shifter transistor 3 1 is in the on-state and the second level shifter transistor 3 2 is in the off-state the output signal V OUT1 of the first inverter 41 1 has the first signal level and the output signal V OUT2 of the second inverter 41 2 has the second signal level.
- the cross-coupled inverters 411 , 412 form a bistable circuit that changes its state when one of the two (2) level shifter transistors 3 1 , 3 2 switches on and maintains the state after the one of the two level shifter transistors 3 1 , 3 2 has been switched off until the other one of the two level shifter transistors 3 1 , 3 2 switches on. That is, the two level shifter transistors 3 1 , 3 2 just trigger the change of the state of the bistable circuit.
- FIG. 8 shows one example of how the first and second inverters 41 1 , 41 2 may be implemented.
- reference number 41 i represents an arbitrary one of the first and second inverters 41 1 , 41 2
- IN 1 denotes the input of the inverter 41 1
- OUT i denotes the output of the inverter 41 i .
- the inverter 41 includes two complementary transistors, a high-side transistor 41 H and a low-side transistor 41 L, that each have a load path and a control node.
- the load paths of these transistors 41 H, 41 L are connected in series between the supply node 15 and the first load output 11 .
- the output OUT i is formed by a circuit node that is common to the load paths of the two transistors 41 L, 41 H.
- the control nodes of the transistors 41 L, 41 H are connected with each other and form the input IN i of the inverter 41 1 .
- each of the level shifter transistors 31 , 32 forms a voltage. divider with the transistors of that inverter to the output of which it is connected.
- the first level shifter transistor 3 1 forms a voltage divider with the high-side transistor of the second inverter 412
- the second level shifter transistor 32 forms a voltage divider with the high-side transistor of the first inverter 41 1 .
- the low side transistors of the inverters 41 1 , 41 2 prevent the potentials at the inputs IN 1 , IN 2 from dropping below the potential at the first load output node 11 .
- the level shifter transistors 3 1 , 3 2 are implemented as lateral transistor devices in the level shifter region 103 .
- FIG. 9 shows a vertical cross-sectional view of one section of the semiconductor body 100 that includes the level shifter region 103 .
- FIG. 9 shows a vertical cross-sectional view of one of the level shifter transistors 3 1 , 3 2 (reference character 3 i denotes an arbitrary one of the two level shifter transistors 3 1 , 3 2 ).
- reference character 3 i denotes an arbitrary one of the two level shifter transistors 3 1 , 3 2 .
- the level shifter transistor 31 is a transistor of the first doping type and includes a source region 32 and a drain region 34 that are spaced apart from each other in a horizontal direction of the semiconductor body 100 .
- the source region 32 and the drain region 34 are arranged such that the source region 32 is closer to the inner region (not shown in FIG. 9 ) than the drain region 34 .
- the drain 34 is closer to the edge surface (not shown) than the source region 32 .
- the drain region 32 is embedded in a drift region 31 of the first doping type.
- the drift region 31 has a lower doping concentration than the drain region 34 and essentially defines the voltage blocking capability of the level shifter transistor 3 .
- the voltage blocking capability is the voltage the level shifter transistor 3 i can withstand in the off-state.
- the level shifter transistor 3 further includes a body region 33 of the second doping type between the source region 32 and the drift region 31 .
- This body region 33 may have the same doping concentration as the second region 130 , in which the source regions 32 and the drift region 31 are embedded, or may have a doping concentration different from the second region 130 .
- a gate electrode 35 is adjacent the body region 33 and dielectrically insulated from the body region 33 by a gate dielectric 36 .
- each of the level shifter transistors 3 1 , 3 2 has its load path connected between the second load output node 12 (that is connected to the source node S of the first transistor device 2 ) and the input of a corresponding inverter 41 i , 41 2 .
- the drain region 34 can be connected to the input (represented by IN i in FIG. 9 ) of the corresponding inverter and the source region 32 can be connected to the second load output node 12 .
- Wiring arrangements that connect the drain region 34 to the input of the corresponding inverter and that connect the source region 32 to the second load output node 12 and the source node S of the first transistor device can be formed on top of the first surface 107 and may include conductors embedded in or formed On top of at least one insulation layer 91 .
- the conductor connecting the drain region 34 to the input IN i of the corresponding inverter may include a first contact electrode 37 connected to the drain region 34 and the conductor connecting the source region 32 to the second load output 12 and the source node S may include a second contact electrode 38 connected to the source region 32 .
- the second contact electrode 38 extends into the semiconductor 100 and is connected to the second region 130 .
- a contact region 39 of the second doping type that is doped higher than the second region 103 is formed between the second contact electrode 38 and the second region 130 .
- this second contact electrode 38 forms the contact explained with reference to FIG. 4 between the source node S and the second region 130 .
- FIG. 10 shows a horizontal cross-sectional view in a section plane D-D of the level shifter region 103 shown in FIG. 9 and shows the two level shifter transistors 3 1 , 3 2 , wherein each of these level shifter transistors is implemented in accordance with the example shown in FIG. 9 .
- the features of the level shifter transistors 3 1 , 3 2 shown in FIG. 10 are labelled with the same reference characters used in FIG. 9 , wherein a subscript index “1” has been added to the reference numbers of the first level shifter transistor 3 1 and a subscript index “2” has been added to the reference numbers of the second level shifter transistor 3 2 . Referring to FIG.
- the drift regions 31 1 , 31 2 and the source regions 32 1 , 32 of the two level shifter transistors 3 1 , 3 2 can be separated from each other by sections of the second region 130 so that a junction isolation is formed. Between the drift region 31 1 , 31 2 .
- the source regions 32 1 , 32 2 can be formed by two separate regions separated by a section of the first region 120 . According to another example (illustrated in dashed and dotted lines in FIG. 10 ), the source regions 32 1 , 32 2 are formed by one continuous semiconductor region.
- the drive circuit 4 is integrated in the first drive circuit region 104 of the semiconductor body 100 .
- FIG. 11 illustrates one example of implementing one of the two inverters 41 1 , 41 2 (reference number 41 i represents an arbitrary one of these inverters 41 1 , 41 2 ). It should be noted that the other one of the two inverters as well as the inverter of the driver 43 can be implemented in the same way.
- doped regions of the second doping type are drawn as grey regions and doped regions of the first doping type are drawn as white regions in the example shown in FIG. 11 .
- the inverter 41 includes a doped region 410 of the second doping type, which is referred to as first well in the following.
- the active device regions of the high-side transistor 41 H and the low-side transistor 41 L are embedded in this first well 410 .
- the low-side transistor 41 L includes a source region 411 and a drain region 412 of the first doping type and spaced apart from each other in a horizontal direction.
- a body region of the low-side transistor 41 L may be formed by a section of the first well 410 .
- the body region is a region with a doping concentration different from the doping concentration of the first well 410 .
- a gate electrode 413 of the low-side transistor 41 L is adjacent the body region and dielectrically insulated from the body region by a gate dielectric 414 .
- the source region 411 is connected to the first load output node 11 via a conductor that may formed in or on top of an insulator 92 and may include a source electrode 415 .
- the first well 410 (forming the body region of the low-side transistor 411 ) may be connected to the first load output 11 via a contact electrode 418 and a contact region 417 of the second. doping type,
- the high-side transistor 41 H includes a second well 420 of the first doping type in the first well 410 of the first doping type. Further, the high-side transistor 41 H includes a source region 421 and a drain region 422 of the second doping type in the second well 420 and spaced apart from each other in a horizontal direction of the semiconductor body 100 .
- a body region of the high-side transistor 41 H may be formed by a section of the second well 420 . Optionally, the body region is a region with a doping concentration different from the doping concentration of the second well 420 .
- a gate electrode 423 of the high-side transistor 41 H is adjacent the body region and dielectrically insulated from the body region by a gate dielectric 424 .
- the source region 421 of the high-side transistor 41 H is connected to the second supply input 15 via a conductor that may include a source electrode 425 . Further, the second supply input 15 may be connected to the second well 420 via a contact electrode 428 and a higher doped contact region 427 of the first doping type.
- the drain region 422 of the high-side transistor 4111 is connected to the drain region 412 of the low-side transistor 411 , via a conductor.
- This conductor may include a first drain electrode 416 connected to the drain region 412 of the low-side transistor 41 L and a drain electrode 426 connected to the drain region 422 of the high-side transistor 41 H.
- the potential at the first supply input 15 may become higher than the potential at the drain node D of the first transistor device 2 .
- a pn-junction between the first well 410 and the second well 420 absorbs the voltage that may occur between the first supply input 15 and the first region 120 (which is connected to the drain node Di and, therefore, prevents a current flow from the first supply input to the drain region 24 of the transistor device 2 .
- the first drive circuit region 104 may include several first wells of the type. illustrated in FIG. 11 that are spaced apart from each other so that a junction isolation is formed between these first wells. In each of these first wells, one inverter can be implemented. Further, the comparator 42 may include transistor of the first doping type and/or the second doping type. These transistors can be implemented in the same way as the transistors 41 L, 41 H illustrated in FIG. 11 .
- FIGS. 12A and 12B illustrate another implementation of the inverter 41 i .
- FIG. 12A shows a vertical cross-sectional view
- FIG. 12B shows a horizontal cross-sectional view of the first drive circuit region 104 .
- source regions 411 , 421 and body regions 418 , 428 of the low-side and the high-side transistor 411 , 41 H are ring-shaped regions.
- source regions 412 , 422 of these transistors 41 L, 41 H are ring-shaped regions that surround the body regions 418 , 428 .
- the source region 422 of the high-side transistor 41 H is embedded in the first well 410 , and the body region of the high-side transistor 41 H may be formed by a section of the first well 410 (or by a region having a doping concentration different from the doping concentration of the first well 410 ). Further, the source, body and drain regions 411 , 418 , 412 of the low-side transistor 41 L are embedded in a further well 419 of the first doping type that is embedded in the first well 410 . The source region 412 of the low-side transistor 41 L is embedded in this further well 419 .
- the body region of the low-side transistor 41 L may be formed by a section of this further well 419 or by another region of the first doping type having a doping concentration different from the doping concentration of the further well 419 .
- the further well 419 is embedded in the first well 410 .
- the pn-junction formed between first well 410 and the second well 420 absorbs a voltage between the first supply node 15 and the drain node D (drain region 24 ) of the transistor device 2 .
- a further region 431 of the first doping type surrounding the first well 410 and a further region 432 of the second doping type surrounding the further region 431 of the first doping type and adjoining the first region 120 form two pn-junctions between the first well 410 and the first region 120 and, therefore, prevent a current flow from the first supply input 15 to the drain node D (the drain region 24 ) of the transistor device 2 .
- the further region 431 of the first doping type is connected to the first supply input 15 and the further region 432 of the second doping type is connected to the first load output node 11 .
- Transistors 41 L, 41 H of the type shown in FIG. 11 may be implemented using a CMOS process, and transistors of the type shown in FIGS. 12A and 12B may be implemented using a DMOS process.
- the drive voltage V GS of the first transistor device 2 is generated based on the first input signal Sin 1 received at the first input 13 .
- the first input signal Sin 1 is a voltage referenced to the source node S of the first transistor device 2 and is directly used to drive the first transistor device 2 . That is, the first transistor device 2 receives the first input signal Sin 1 as the drive: voltage V GS .
- the signal received at the input IN of the inverter 41 i from the level shifter 3 is an internal signal when the level shifter 3 is integrated in the semiconductor body 100 or an external signal when the level shifter 3 is an external circuit that is not integrated in the semiconductor body 100 .
- the electronic circuit 1 includes a further drive circuit 6 that receives the first input signal Sin 1 and generates the drive voltage VGs based on the first input signal Sin 1 .
- the further drive circuit 6 receives a supply voltage V SUP1 via a further supply input 17 .
- this further supply voltage V SUP1 is a voltage referenced to the source node S and the second load output 12 .
- the level shifter 3 is a differential level shifter with two level shifter transistors 31 , 32 and receives two input signals Sin 2 i, Sin 22 .
- These input signals Sin 21 , Sin 2 can be received from an external control circuit such as, for example, a microcontroller.
- the electronic circuit 1 receives one second input signal Sin 2 , which can be a voltage referenced to the second load output 12 , in this example, the electronic circuit. 1 includes an input circuit 5 , that receives the second input signal Sin 2 and is configured to generate the two input signals Sin 2 1 , Sin 2 2 of the level shifter 3 based on the second input signal Sin 2 .
- the input circuit 5 includes an inverter with a low-side transistor 5 L and a high-side transistor 51 -I that receives the second input signal Sin 2 at an input.
- the second level shifter input signal Sin 2 2 received by the second level shifter transistor 32 is available.
- the first level shifter input signal Sin 2 1 equals the second input signal Sin 2 in this example.
- Each of the low-side transistor 5 L and the high-side transistor 5 H has a load path and a control node. The load paths are connected in series between the second supply input 17 and the second load output 12 and the control nodes are connected with each other and form the input of the inverter 5 L, 5 H.
- the second drive circuit 6 may include a first inverter 61 and a second inverter 62 each including a low-side transistor 61 L, 62 L and a high-side 61 H, 62 H.
- Each of the low-side transistors 61 L, 62 L and the high-side transistors 61 H, 62 H has a load path and a control node.
- the load paths of the high-side transistor 61 H, 62 H and the low side transistor 61 L, 62 L of each inverter 61 , 62 are connected in series between the second supply input 17 and the second load output 12 . Further, the control nodes are connected with each other and form an input of the respective inverter 61 , 62 .
- each inverter 61 , 62 is formed by a circuit node common to the load paths of the high-side transistor 61 H, 62 H and the low side transistor 61 L, 62 L of the respective inverter 61 , 62 .
- the first inverter 61 receives the first input signal Sin 1 at the input, and the input of the second inverter 62 is connected to the output of the first inverter 61 .
- the drive voltage V GS is available between the output of the second inverter 62 and the second load output node 12 .
- the second drive circuit 6 and the input circuit 5 are integrated in a second drive circuit region 105 .
- This second drive circuit region 105 is schematically illustrated in FIG. 15 that shows a vertical cross-sectional view of the semiconductor body 100 in the section plane A-A explained above.
- the second drive circuit region 105 is arranged between the level shifter region 103 and the inner region 102 and is embedded in the second region 130 .
- each of the input circuit 5 and the second drive circuit 6 includes at least one inverter. These inverters can be implemented in the second drive circuit region 105 in accordance with the examples explained with reference to FIGS. 11 and 12A-12B .
- the first well 410 shown in FIG. 11 and the further region 432 of the second doping type shown in FIGS. 12A and 12B may be formed by the second region 130 .
- the drive circuit 4 that generates the output signal Sout based on the second input signal Sin 2 is configured to drive a second transistor device.
- a second transistor device One example of an electronic circuit that includes the first transistor device 2 and the second transistor device 7 is illustrated in FIG. 16 .
- the second transistor device 7 is of the same transistor type as the first transistor device 2 . That is, in this example, the second transistor device 7 is a n-type enhancement MOSFET.
- the second transistor device 7 includes a control node (gate node) G 7 and a load path between a drain node D 7 and a source node S 7 .
- the load path D 7 -S 7 of the second transistor device 7 is connected in series with the load path D-S of the first transistor device 2 so that the first transistor device 2 and the second transistor device 7 form a half-bridge circuit.
- the second transistor device 7 is driven by the output signal Sout, which, in this example, is a voltage between the drive output 16 and the first load output 11 to which the source node S 7 of the second transistor device 7 is connected.
- the (first) supply voltage V SUP1 received between the second supply node 17 and the second load Output 12 can be generated by an external voltage source 81 connected between the second supply input 17 and the second load output node 12 of the electronic circuit.
- the (second) supply voltage V SUP2 received by the electronic circuit between the first supply input 15 and the first load output node 11 can be generated by a bootstrap circuit based on the first supply voltage V SUP1 .
- this bootstrap circuit may include a capacitor 82 connected between the first supply input 15 and the first load output node 11 , and a diode 83 connected between the voltage source 81 and the capacitor 82 .
- the capacitor 82 is charged each time the first transistor device 2 switches on. When the first transistor device 2 switches off the charge stored in the capacitor 82 can be used by the drive circuit 4 to generate the output signal Sout and drive the second transistor device 7 .
- the second transistor device 7 is integrated in a second semiconductor body 200 . According to one example, only the second transistor device 7 is integrated in the second semiconductor body 200 while the first transistor device 2 , the level shifter 3 and the drive circuit 4 are integrated in the first semiconductor body 100 .
- the first and second semiconductor bodies 100 , 200 are arranged in a common housing (package).
- a common housing Package
- FIG. 17 shows a top view of the arrangement, wherein the housing 301 is illustrated in dashed and dotted lines.
- the arrangement includes a first carrier 310 onto which the first semiconductor body 100 is mounted such that the drain node D is electrically connected to the first carrier 310 .
- the first carrier 310 includes a pin 311 that protrudes from the housing 301 and forms the first load output node 11 of the electronic circuit.
- the second transistor device 7 integrated in this second semiconductor body 200 can be a vertical transistor device implemented in the same way as the first transistor device 2 . In this case a drain node of the second transistor device is formed by a second surface of the second semiconductor body 200 . This second surface of the second semiconductor body 200 is mounted on a second carrier 320 . This second carrier 320 is mounted on the first carrier 310 but is electrically insulated from the first carrier 310 .
- the second carrier 320 is electrically connected to a further output pin 318 that forms a further output node 18 shown in FIG. 16 of the electronic circuit.
- the second carrier 320 is connected to the further output pin 318 by a bond wire. This, however, is only an example.
- a flat conductor, or the like, may be used as well.
- the second semiconductor body 200 includes a source pad 228 that is connected to the source node S 7 of the second transistor device 7 , and a gate pad 226 connected to the gate node ( 37 of the second transistor device 7 .
- the first semiconductor body 100 includes a source pad 128 that is connected to the source electrode 28 of the first transistor device 2 .
- a first and second input pad 113 , 114 and a first and second supply pad 115 , 117 are formed on top of the first surface 107 of the first semiconductor body 100 .
- the first input pad 113 is connected to a first input pin 313
- the second input pad 114 is connected to a second input pin 314 .
- the first input pins 313 forms the first input 13 and the second put pin 314 forms the second input 14 of the electronic circuit.
- the first supply pad 115 is connected to a first supply pin 315 and the second supply 117 is connected to a second supply pin 317 .
- the first supply pin 315 forms the first supply input 15 and the second supply pin 317 forms the second supply input 17 .
- an output pad 116 on top of the first semiconductor body 100 forms the drive output 16 and is connected to the gate pad 226 of the second transistor device 7 inside the housing 301 .
- the source pad 128 on top of the first semiconductor body 100 is connected to a second output pin 312 that forms the second load output 12 of the electronic circuit. Further, the source pad 228 on top of the second semiconductor body 200 is connected to the first output pin 311 .
- electrical connections between pads on top of the semiconductor bodies 100 , 200 and input or output pins include bond wires in the example shown in FIG. 17 . This, however, is only an example. These connections can be implemented using flat conductors, or any other type of electrical connections as well.
- the second transistor device integrated in the second semiconductor body 200 is a drain-down transistor, that is, the drain node of the second transistor device is formed by a surface of the semiconductor body 200 connected to the second carrier.
- the second transistor device is a source-down transistor, in which the drain electrode and the gate electrode are accessible at the same side of the semiconductor body 200 and the source electrode is accessible at the opposite side.
- the second carrier 320 can be omitted; the second semiconductor body 200 can be mounted on the first carrier 310 such that the source electrode is connected to the first carrier 310 (and, in this way, to the drain node of the first transistor device 2 integrated in the first semiconductor body 100 ); and the drain electrode can be connected to the further output pin 318 via a connector, such as a bond wire, a flat conductor, or the like.
- FIG. 18 shows a modification of the module shown in FIG. 17 .
- the module according to FIG. 18 is different from the module according to FIG. 17 in that the first carrier 310 and the second carrier 320 are spaced apart from each other in a lateral direction and, thereby, electrically insulated from each other.
- the further output pin 18 can be formed by a part of the second carrier 320 . Everything else explained with reference to the module shown in FIG. 17 applies to the module shown in FIG. 18 accordingly.
- Example 1 An electronic circuit, including: a first transistor device integrated in an inner region of a first semiconductor body; a level shifter integrated in a level shifter region of the first semiconductor body; and a first drive circuit connected to the level shifter, integrated in a first drive circuit region of the semiconductor body, and configured to drive a second transistor device, wherein each of the level shifter region and the first drive circuit region is located in an edge region surrounding the inner region of the semiconductor body, and wherein the level shifter region is arranged closer to the inner region than the first drive circuit region.
- Example 2 The electronic circuit of example 1, further including: a second drive circuit integrated in a second drive circuit region in the edge region of the first semiconductor body, wherein the second drive circuit is configured to receive a first input signal from a first input and drive the first transistor device based on the first input signal, and wherein the second drive circuit region is arranged closer to the inner region than the level shifter region.
- Example 3 The electronic circuit of any combination of examples 1 to 2, further including: an input circuit integrated in the second drive circuit region and coupled between a second input and the level shifter.
- Example 4 The electronic circuit of any combination of examples 1 to 3, wherein the first transistor device includes a plurality of transistor cells, each including: a drift region of a first doping type; a source region of the first doping type connected to a source node; a body region of a second doping type complementary to the first doping type; a drain region of the first doping type separated from the body region by the drift region and connected to a drain node; and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric.
- Example 5 The electronic circuit of any combination of examples 1 to 4, wherein each of the plurality of transistor cells further includes: a compensation region adjoining the drift region.
- Example 6 The electronic circuit of any combination of examples 1 to 5, further including: a first region of the first doping type and a second region of the second doping type in the edge region, wherein a pn-junction is formed between the first region and the second region, wherein the first region is connected to the drain node and the second region is connected to the source node, and wherein the level shifter region is embedded in the second region and the first drive circuit region is embedded in the first region.
- Example 7 The electronic circuit of any combination of examples 1 to 6, wherein the second drive circuit region is embedded in the second region.
- Example 8 The electronic circuit of any combination of examples 1 to 7, wherein a maximum doping concentration of each of the first region is higher than a maximum doping concentration of the drift region.
- Example 9 The electronic circuit of any one of any combination of examples 1 to 8, wherein a maximum doping concentration of the second region is less than a maximum doping concentration of the drift region.
- Example 9 The electronic circuit of any one of any combination of examples 1 to 8, wherein a maximum doping concentration of the second region is less than 1E16 cm ⁇ 1 .
- Example 11 The electronic circuit of any one of the preceding claims, wherein the level shifter includes at least one lateral transistor device,
- Example 12 The electronic circuit of any combination of examples 1 to 11, wherein the first drive circuit includes at least one inverter.
- Example 13 The electronic circuit of any combination of examples 1 to 12, wherein the second drive circuit includes at least one inverter.
- Example 14 The electronic circuit of any combination of examples 1 to 13, further including the second transistor device, wherein a load path of the second transistor device is connected in series with a load path of the first transistor device.
- Example 15 The electronic circuit of any combination of examples 1 to 14, wherein the second transistor device is integrated in a further semiconductor body.
- Example 16 The electronic circuit of any combination of examples 1 to 15, wherein the first semiconductor body and the second semiconductor body are arranged in a common housing.
- Example 17 The electronic circuit of any combination of examples 1 to 16, wherein the first semiconductor body is mounted on a first carrier and the second semiconductor body is mounted on a second carrier that is electrically insulated from the first carrier.
- Example 18 The electronic circuit of any combination of examples 1 to 17, wherein the first semiconductor body and the second semiconductor body are mounted on the same carrier.
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Abstract
An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; a level shifter integrated in a level shifter region of the first semiconductor body, the level shifter region located in an edge region surrounding the inner region of the semiconductor body; and a drive circuit integrated in a drive circuit region in the edge region of the first semiconductor body, the drive circuit configured to receive a first input signal from a first input and drive the first transistor device based on the first input the drive circuit region arranged closer to the inner region than the level shifter region.
Description
- This disclosure in general relates to an electronic circuit, in particular an electronic circuit that includes at least one transistor device and a level shifter.
- Various types of electronic circuits include a half-bridge circuit with a first transistor device and a second transistor device that have their load paths connected in series. Each of these two transistor devices switches on and off dependent on a respective drive signal received at a respective control node. In a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), for example, the drive signal is a drive voltage received between a gate node, which forms the control node of the MOSFET, and a source node.
- A half-bridge circuit may receive control signals that govern switching on and switching off the two transistor devices from a control circuit, such as a microcontroller, or the like. In some types of half-bridge circuits, the first transistor device directly receives the respective control signal or a drive circuit coupled to the first transistor device directly receives the respective control signal, while a drive circuit connected to the second transistor device receives the respective control signal via a level shifter from the control circuit.
- There is a need to implement the first transistor device, the level shifter and the drive circuit configured to drive the second transistor device in a space saving fashion.
- One example relates to an electronic circuit. The electronic circuit includes a first transistor device integrated in an inner region of a first semiconductor body, and a first drive circuit integrated in a first drive circuit region of the semiconductor body, configured to be connected to a level shifter and configured to drive a second transistor device. The first drive circuit region is located in an edge region surrounding the inner region of the semiconductor body.
- Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
- Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like features.
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FIG. 1 shows a circuit diagram of one example of an electronic circuit that includes a first transistor device, an optional level shifter and a drive circuit configured to drive a second transistor device -
FIG. 2A schematically illustrates a vertical cross-sectional view of one section of a semiconductor body in which the first transistor device, the optional level shifter and the drive circuit are integrated; -
FIG. 2B schematically illustrates a vertical cross-sectional view of one section of a semiconductor body in which the first transistor device, and the drive circuit are integrated; -
FIG. 3 schematically illustrates a top view of the semiconductor body; -
FIG. 4 schematically illustrates the vertical cross-sectional view shown inFIG. 2 in greater detail; -
FIG. 5 shows a horizontal cross-sectional view of several transistor cells of the transistor device according to one example; -
FIG. 6 shows a horizontal cross-sectional view of several transistor cells of the transistor device according to another example; -
FIG. 7 shows one example of the level shifter and the drive circuit in detail; -
FIG. 8 shows an inverter of the drive circuit shown inFIG. 7 in detail; -
FIG. 9 shows one example of a level shifter transistor integrated in a level shifter region of the semiconductor body; -
FIG. 10 shows a horizontal cross-sectional view of two (2) level shifter transistors of the type shown inFIG. 9 ; -
FIG. 11 shows one example of an inverter of the drive circuit integrated in a drive circuit region of the semiconductor body; -
FIGS. 12A and 12B shows another one example of an inverter of the drive circuit integrated in the drive circuit region of the semiconductor body; -
FIG. 13 shows one example of an electronic circuit that is based on the electronic circuit shown inFIG. 1 and further includes an input circuit connected between an input and the level shifter and a further drive circuit coupled to the first transistor device; -
FIG. 14 shows examples of the input circuit and the further drive circuit; -
FIG. 15 schematically illustrates a vertical cross-sectional view of one section of a semiconductor body in which the first transistor device, the level shifter, the drive circuit, the further drive circuit and the input circuit are integrated; -
FIG. 16 shows one example of an electronic circuit that further includes the second transistor device; -
FIG. 17 illustrates one example of a module: that includes an electronic: circuit of the type shown inFIG. 16 ; and -
FIG. 18 illustrates another example of the module. - In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and for the purpose of illustration show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
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FIG. 1 shows a circuit diagram of an electronic circuit according to one example,FIGS. 2A and 2B each schematically illustrates a vertical cross-sectional view of one section of asemiconductor body 100 in which the electronic circuit is integrated, andFIG. 3 schematically illustrates a top view of thesemiconductor body 100. Referring toFIG. 1 , the electronic circuit includes afirst transistor device 2 and adrive circuit 4. Thedrive circuit 4 is configured to be connected to alevel shifter 3 and is configured to drive a second transistor device (not shown inFIG. 1 ). - The level shifter 3 (that is illustrated in dashed lines in
FIG. 1 ) is optional in the electronic circuit and, therefore, thesemiconductor body 100. That is, thelevel shifter 3 may be included in the electronic circuit and integrated in thesemiconductor body 100 or may be an external circuit that is not integrated in the semiconductor body.FIG. 2A illustrates a vertical cross-sectional view of asemiconductor body 100 in which the level shifter is integrated, andFIG. 2B illustrates a vertical cross-sectional view of asemiconductor body 100 in which the level shifter is not integrated. Everything, except for thelevel shifter 3, explained in the following with regard to thesemiconductor body 100 shown inFIG. 2A applies to the semiconductor body shown inFIG. 2B accordingly. - Referring to
FIGS. 2A and 2B , thesemiconductor body 100 includes a first (main)surface 107, a second (main)surface 108 opposite thefirst surface 107, and aside surface 109 that extends between thefirst surface 107 and thesecond surface 108. Each ofFIGS. 2A and 2B shows a vertical cross-sectional view of one section of thesemiconductor body 100 in a vertical section plane A-A. This vertical section plane A-A is a plane perpendicular to each of the first andsecond surfaces semiconductor body 100.FIG. 3 shows a horizontal cross-sectional view of thesemiconductor body 100 in a horizontal section plane B-B in order to illustrate a. position of aninner region 102 and anedge region 101 in thesemiconductor body 100. The horizontal section plane B-B is a plane parallel to each of the first andsecond surfaces FIGS. 2A, 2B and 3 , theedge region 101 of thesemiconductor body 100 is arranged between theinner region 102 and theside surface 109 of thesemiconductor body 100 and theedge region 101 surrounds theinner region 102. In horizontal planes of thesemiconductor body 100. - It should be noted that
FIGS. 2A, 2B and 3 only schematically illustrate thesemiconductor body 100. This means that conducting layers or passivation layers that may be formed on thefirst surface 107 and/or thesecond surface 108 are not shown in these figures. Further, in the example illustrated inFIG. 2 , angles between theside surface 109 and thefirst surface 107 and thesecond surface 108 are about 90°. This, however, is only an example. According to another example (not shown) theside surface 109 is beveled relative to the first andsecond surfaces - The
semiconductor body 100 may include a conventional (monocrystalline) semiconductor material such as, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or the like. - Referring to
FIGS. 2A and 2B , thefirst transistor device 2 is integrated in theinner region 102 of thesemiconductor body 100. This integration is only schematically illustrated inFIGS. 2A and 2B . A more detailed example is explained herein further below, - Referring to
FIGS. 2A and 2B , thesemiconductor body 100 further includes, in theedge region 101 of thesemiconductor body 100, a firstdrive circuit region 104. Optionally, referring toFIG. 2B thesemiconductor body 100 further includes alevel shifter region 103 in theedge region 101 of the semiconductor, wherein thelevel shifter region 103 is arranged closer to the inner region 10:2 than the firstdrive circuit region 104. More specifically, in a horizontal direction of thesemiconductor body 100, thelevel shifter region 103 is arranged between the firstdrive circuit region 104 and theinner region 102 and the firstdrive circuit region 104 is arranged between thelevel shifter region 103 and thefirst side surface 109 of thesemiconductor body 100. The “horizontal direction” is a direction parallel to the first andsecond surfaces semiconductor body 100. Thelevel shifter 3 is integrated in thelevel shifter region 103 and thedrive circuit 4 is integrated in the firstdrive circuit region 104. This, however, is only schematically illustrated inFIGS. 2A and 23 . Examples are explained herein further below. - With regard to the
first transistor device 2 being integrated in theinner region 102, theoptional level shifter 3 being integrated in thelevel shifter region 103, and thedrive circuit 4 being integrated in the firstdrive circuit region 104, “integrated” means that each of thefirst transistor device 2, thelevel shifter 3 and thedrive circuit 4 includes several doped semiconductor regions that are located in theinner region 102, thelevel shifter region 103, and the firstdrive circuit region 104, respectively, of thesemiconductor body 100. In addition to these doped semiconductor regions each of thefirst transistor device 2, thelevel shifter 3 and thedrive circuit 4 may include conductors, electrodes, or the like formed on top of the first and/or thesecond surface semiconductor body 100. - Referring to
FIG. 1 , thefirst transistor device 2 includes a control node G, a load path D-S between a first load node S and a second load node D and is configured to switch on or off dependent on a drive voltage VGS received at a drive input. According to one example, the load path D-S is connected between afirst output node 11 and asecond output node 12 of the electronic circuit, wherein these first and second output nodes are also referred to as firstload output node 11 and a secondload output node 12 in the following. - According to one example, the
first transistor device 2 is a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor). It should be noted that the term MOSFET as used herein denotes any type of field-effect transistor with an insulated gate electrode (often referred to as IGFET) irrespective of whether the gate electrode includes a metal or another type of electrically conducting material, and irrespective of whether the gate dielectric includes an oxide or another type of dielectrically insulating material. The circuit symbol of thefirst transistor device 2 shown inFIG. 1 represents n-type enhancement MOSFET. This, however, is just for illustration purposes. Any other type of MOSFET such as a p-type enhancement MOSFET, a p-type depletion MOSFET, an n-type depletion MOSFET, or any other type of field-effect transistor such as an IGBT (Insulated Gate Bipolar Transistor) or a JFET (Junction Field-Effect Transistor) may be used as well. - In a MOSFET, the control node G is also referred to as gate node, the first load node S is also referred to as source node, the second load node D is also referred to as drain node, and the drive voltage VGS is also referred to as gate-source voltage. Although the
first transistor device 2 shown inFIG. 1 is not restricted to be implemented as a MOSFET, theterms gate node 0, source node S and drain node D will be used in the following to denote the control node, the first load node and the second load node, respectively. Further, although in the MOSFET illustrated inFIG. 1 the drive input receiving the drive voltage VGS formed by the gate node G and the source node S, this is only an example. According to a further example (not illustrated), the drive input is formed by the gate node and an auxiliary source node that is different from the source node. According to yet another example, the drive input is formed by the gate node and by a circuit node that is connected to the source node S via a (current measurement) resistor. - Referring to the above, the
first transistor device 2 switches on or off dependent on the drive voltage VGS. According to one example, this drive voltage VGS is dependent on a first input signal Sin1 received at afirst input 13 of the electronic circuit so that thefirst transistor device 2 switches on or off dependent on the first input signal Sin1. Examples of how the drive voltage VGS may be generated based on the first input signal Sin1 are explained herein further below. - The
drive circuit 4 is configured to generate an output signal Sout at afurther output 16 of the electronic circuit based on a level shifter signal S3 received from thelevel shifter 3. Referring to the above, thelevel shifter 3 may be part of the electronic circuit and integrated in thesemiconductor body 100, or may be an external circuit. Thisfurther output 16 is also referred to as drive output in the following. According to one example, thelevel shifter 3 is configured to generate the level shifter signal S3 based on a second input signal Sin2, wherein the second input signal Sin2 is received at asecond input 14 of the electronic circuit when thelevel shifter 3 is part of the electronic circuit. When thelevel shifter 3 is an external circuit, the electronic circuit receives the level shifter signal S3 instead of the second input signal Sin2. In each case, the output signal Sout at thefurther output 16 is generated based on the second input signal Sin2. According to one example, the output signal Sout is a voltage at thedrive output 16 that is referenced to the firstload output node 11. -
FIG. 4 shows a vertical cross-sectional view of thesemiconductor body 100 in the section plane A-A explained above and illustrates one example of how thefirst transistor device 2 may be implemented in theinner region 102. In this example, thefirst transistor device 2 is a MOSFET that includes a plurality oftransistor cells 20. Each of thesetransistor cells 20 includes adrift region 21 of a first doping type (conductivity type), asource region 22 of the first doping type and abody region 23 of a second doping type (conductivity type) complementary to the first doping type, wherein thebody region 23 is arranged between thedrift region 21 and thesource region 22. Further, eachtransistor cell 20 includes agate electrode 26 adjacent thebody region 23 and dielectrically insulated from thebody region 23 by agate dielectric 27. Thegate electrodes 26 of theindividual transistor cells 20 are connected to the gate node G or form the gate node G of thefirst transistor device 2. Further, the source andbody regions individual transistor cells 20 are connected to asource electrode 28. This source electrode 28 forms the source node S or is connected to a source node S of thefirst transistor device 1. Eachtransistor cell 20 further includes adrain region 24 of the first doping type, wherein thedrain region 24 is separated from thebody region 23 by thedrift region 21. - In the example shown in
FIG. 4 , thefirst transistor device 2 is a vertical transistor device. Thetransistor cells 20 of this vertical transistor device can be referred to as vertical transistor cells. In this type of transistor cells, thesource region 22 is spaced apart from thedrain region 24 in a vertical direction of thesemiconductor body 100, wherein the “vertical direction” is a direction perpendicular to thefirst surface 107 and thesecond surface 108. In an on-state, (switched-on state) of the transistor device, a current in thedrift region 21 essentially flows in the vertical direction of thesemiconductor body 100. Thefirst transistor device 1 switches on or off dependent on the drive voltage VGS received between the gate node E1 and thesource node 5, wherein thegate electrode 26 dependent on this drive voltage VGS controls a conducting channel in thebody region 23 between thesource region 22 and thedrift region 21. In the example shown inFIG. 4 , thegate electrode 26 is a planar gate electrode arranged on top of thefirst surface 107 of thesemiconductor body 100. This, however, is only an example. According to another example (not shown) thegate electrode 26 is a trench electrode arranged in a trench extending from thefirst surface 107 into thesemiconductor body 100. - Referring to
FIG. 4 , adrain electrode 29 formed on thesecond surface 108 is connected to thedrain region 24. Thisdrain electrode 22 is connected to the drain node D or forms the drain node D of thetransistor device 2. According to another example (not shown) the drain electrode is arranged on top of thefirst surface 107 between theside surface 109 and thedrive circuit region 104 and is connected to thedrain region 24 via a semiconductor region of the same doping type as the drain region and extends in a vertical direction from thedrain region 24 to the drain electrode. In this example, the drain region can be arranged on an electrically insulation carrier or on a semiconductor substrate of a doping type complementary to the doping type of thedrain region 24. - In the first transistor device shown in
FIG. 4 , thetransistor cells 20 are connected in parallel in that thegate electrodes 26 of theindividual transistor cells 20 are connected to the gate node G, the source andbody region transistor cells 20 are connected to the source node S, and thedrain regions 24 are connected to the drain node D. In the example shown inFIG. 4 , thedrain regions 24 of theindividual transistor cells 20 are formed by one dopedregion 110 that adjoins thesecond surface 108 and is formed in theinner region 102 and theedge region 101 of thesemiconductor body 100. Thisdoped region 110 may be formed by a semiconductor substrate, wherein the other doped regions explained above may be formed in an epitaxial layer formed on the substrate. - The
first transistor device 2 may be implemented as an n-type transistor device or as a p-type transistor device. In a n-type transistor device, the regions of the first doping type are n-type (n-doped) semiconductor regions and the regions of the second doping type are p-type (p-doped) regions. In a p-type transistor device, the regions of the first doping type are p-type regions and the region of the second doping type are n-type regions. Further, the transistor device can be implemented as an enhancement device or as a depletion device. In an enhancement device, thebody region 23 of the second doping type adjoins thegate dielectric 27. In a depletion device, each of the transistor cells :20 further includes a channel region (not shown in the drawings) in thebody region 23, wherein the channel region is of the first doping type, adjoins thegate dielectric 27 and extends from thesource region 22 to thedrift region 21. An enhancement device is in the on-state when the drive VGS is such that thegate electrode 26 generates an inversion channel in thebody region 23 along thegate dielectric 27 and is in the off-state when the inversion channel is interrupted. A depletion device is in the on-state when the channel region of the first doping type along the gate dielectric is not depleted by thegate electrode 26 and is in the off-state when thegate electrode 26 depletes the channel region. The transistor device conducts a current when operated in the on-state and when a drain-source voltage different from zero is applied between the drain node D and the source node S. - According to one example, the
first transistor device 2 is implemented as a superjunction device. In this example, eachtransistor cell 20 further includes acompensation region 25 of the second doping type, wherein thecompensation region 25 adjoins thedrift region 21 in a direction perpendicular to the current flow direction (that is, in a horizontal direction in the example shown inFIG. 4 ). Further, thecompensation region 25 is electrically connected to the source node S. In the example shown inFIG. 4 this is achieved in that thecompensation region 25 adjoins thebody region 23. According to one example, thecompensation region 25 has a depth in the vertical direction of thesemiconductor body 100 that is at least 50% or at least 70% of a distance between thebody region 23 and thedrain region 24 in the vertical direction. - According to one example, the distance between the
body regions 23 and thedrain region 24 is between 10 micrometers and 100 micrometers, in particular between 20 micrometers and 60 micrometers. This distance, inter alia, affects the voltage blocking capability of the transistor device. The “voltage blocking capability” is given by the maximum drain-source voltage thetransistor device 2 can withstand in the off-state without a voltage breakdown (avalanche breakdown) occurring. Basically, the voltage blocking capability increases as the distance between thebody regions 23 and thedrain region 24 increases. In a transistor device with a voltage blocking capability of 600 volts (V), for example, this distance is between 40 micrometers (μm) and 50 micrometers. - According to one example, doping concentrations of the
drift regions 21 and thecompensation regions 25 are selected from a range of between 1E16 (=1·1016) cm−3 and 5E17 cm−3, a doping concentration of thesource regions 22 is higher than 1E19 cm−3, a doping concentration of thedrain regions 24 is higher than 1E19 cm−3, and a doping concentration of thebody regions 23 is selected from a range of between 1E17 cm−3 and 1E18 cm−3. -
FIG. 5 shows a horizontal cross-sectional view of one section of the inner region 10:2 in order to illustrate one example of how the transistor cells may be implemented in the horizontal plane. In this example, thetransistor cells 20 are elongated transistor cells. In this case, the source andbody regions - According to another example, the
body regions 23 have a polygonal shape. Referring toFIG. 6 , the polygonal shape can be rectangular. This, however, is only an example. Thebody regions 23 may be implemented with any other type of polygonal shape as well. - In
elongated transistor cells 20 of the type illustrated inFIG. 5 , the gate electrodes 26 (which are out of view inFIG. 5 ) can be elongated electrodes formed above thefirst surface 107. In polygonal transistor cells of the type shown inFIG. 6 , the gate electrodes 26 (which are out of view inFIG. 5 ) of theindividual transistor cells 20 can be formed by one grid-shaped electrode formed above thefirst surface 107. - Referring to
FIG. 4 , thesemiconductor body 100 includes a dopedregion 120 of the first doping type in theedge region 101. Thissemiconductor region 120, which is referred to asfirst region 120 in the following, is connected to the drain node D. Referring toFIG. 4 , thefirst semiconductor region 120 can be connected to the drain node D in that it adjoins thedrain region 24. A (maximum) doping concentration of thefirst region 120 may be equal to the (maximum) doping concentration of thedrift regions 21 or may be higher. According to one example, the doping concentration of thefirst region 120 is at least 1E1 (=101) times, at least 1E2 times, or even at least 1E3 times the doping concentration of thedrift region 21. - Further, in the example illustrated in
FIG. 4 , thesemiconductor body 100 includes asecond region 130 of the second doping type. Thissecond region 130 is arranged in theedge region 101, is spaced apart from theside surface 109, forms a pn-junction with thefirst region 120 and is connected to the source node S. According to one example, thesecond region 130 adjoins thebody region 23 and theoptional compensation region 25 of an outermost transistor cell. The “outermost transistor cell” is the transistor cell that is closest to theedge region 101. In the vertical direction (the direction perpendicular to the first surface 107) thesecond region 130 may extend in the direction of thedrain region 24 as far as theoptional compensation regions 25. According to another example, as illustrated inFIG. 4 , thesecond region 130 may extend less in the direction of thedrain region 24 than theoptional compensation regions 25. - According to one example, a maximum doping concentration of the
second region 130 is lower than the maximum doping concentration of thedrift region 21. According to one example, the doping concentration of thesecond region 130 is less than 1E-1 (=10 −1) times, less than 1E-2 times, or even less than 1E-3 times the maximum doping concentration of thedrift region 21. According to one example, a doping concentration of thesecond regions 130 is less than 1E16 cm−3, - According to one example, a lateral dimension of the
second region 130 is less than a vertical dimension. The “lateral dimension” is the (shortest) dimension in a direction from theside surface 109 towards theinner region 102. The “vertical dimension” is the (shortest) dimension in the vertical direction. - Referring to the above, the
first region 120 is coupled to the drain node D and thesecond region 130 is coupled to the source node. Thus, the pn-junction between thefirst region 120 and thesecond region 130 may become reverse biased when thetransistor device 2 is in the off-state. According to one example, the doping concentrations of thefirst region 120 and thesecond region 130 are adapted to one another such that a voltage blocking capability of the pn-junction formed between thefirst region 120 and thesecond region 130 is greater than the voltage blocking capability of thetransistor cells 20 in theinner region 102. Thus, when an overvoltage scenario occurs that causes thetransistor device 2 to breakdown, the breakdown occurs in theinner region 102. For example, this may be achieved by implementing the first andsecond regions drift region 21. Further, the doping concentration of thefirst region 120 may be selected such that thefirst region 120 cannot be completely depleted of charge carriers when the pn-junction between thefirst region 120 and thesecond region 130 is reverse biased. In this case a space charge region (depletion region) that occurs when the pn-junction is reverse biased mainly expands in thesecond region 130. Further, even when the pn-junction is reverse biased, there are sections of thefirst region 120 along the first surface that have the electrical potential of thedrain region 24. - According to one example, the first
drive circuit region 104 is embedded in thefirst semiconductor region 120. The optionallevel shifter region 103 is embedded in thesecond region 130. -
FIG. 7 shows an example of theoptional level shifter 3 and thedrive circuit 4 in greater detail. In this example, thelevel shifter 3 includes a firstlevel shifter transistor 3 1 and a secondlevel shifter transistor 3 2 each having a load path and a control node. Just for the purpose of illustration, the circuit symbols of thelevel shifter transistors FIG. 7 represent n-type MOSFETs. The load path of the firstlevel shifter transistor 3 1 is connected between an input IN1 of afirst inverter 41 1 of thedrive circuit 4 and thesecond load output 12 and the load path of the secondlevel shifter transistor 3 2 is connected between an input IN2 of asecond inverter 41 2 of thedrive circuit 4 and thesecond load output 12. In this example, thesecond input 14 of the electronic circuit is a differential input with afirst input node 14 1 and asecond input node 14 2. Thefirst input node 14 1 is connected to the control node of the firstlevel shifter transistor 3 1 and thesecond input node 142 is connected to the control node of the secondlevel shifter transistor 3 2. - Referring to
FIG. 7 , the first andsecond inverter drive circuit 4 are cross-coupled. That is, an output OUT1 of thefirst inverter 41 1 is connected to the input IN2 of thesecond inverter 412 and an output OUT, of thesecond inverter 41 2 is connected to the input IN1 of thefirst inverter 41 1. Each of these first andsecond inverters first supply input 15 of the electronic circuit and the second. supply input is connected to thesecond load output 11 of the electronic circuit. In this example, thedrive circuit 4 is configured to generate the output signal Sout at thedrive output 16 as a voltage that is referenced to thefirst load output 11. - Referring to
FIG. 7 , thedrive circuit 4 further includes acomparator 42 having a first input connected to the output OUT1 of thefirst inverter 41 1 and a second input connected to the output OUT2 of thesecond inverter 41 2. Adriver 43 receives an output signal S42 from thecomparator 42 and generates the output signal Sout based on the comparator output signal S42. In the example illustrated inFIG. 7 , thedriver 43 includes an inverter with a low-side transistor 43L and a high-side transistor 4311. Each of thesetransistors 43H, 43L, has a load path and a control node. The load paths of thesetransistors 43L, 43H are connected in series between thesupply node 15 and the firstload output node 11. Further, the control nodes of thesetransistors 43H, 43L, are connected with each other and connected to the output of thecomparator 42. Thedrive output 16 is formed by a circuit node common to the load nodes of thetransistors 43L, 43H of thedriver 43. According to one example, the low-side transistor 4311 and the high-side transistor 43H are complementary transistors. Just for the purpose of illustration, the circuit symbol of the low-side transistor 43L shown inFIG. 7 represents a n-type transistor and the circuit symbol of the high-side transistor 43H shown inFIG. 7 represents a p-type transistor. - In the example shown in
FIG. 7 , thesecond input 14 is configured to receive complementary input signals Sin2 1, Sin2 2 at the first andsecond input nodes second load output 12. “Complementary” means that, at the same time, one of these input signals Sin2 1, Sin2 2 switches on the respectivelevel shifter transistor level shifter transistors FIG. 7 , the level shifter output signal S3 shown inFIG. 1 is given by electrical potentials generated by thelevel shifter transistors second inverters - The output signal Sout generated by the
drive circuit 4 has one of two different signal levels dependent on which of the first and secondlevel shifter transistors side switch 43H and switches off the low-side switch 43L of thedriver 43, and the output Sout has a second signal level when the comparator output signal S42 switches off the high-side switch 43H and switches on the low-side switch 43L. In the example illustrated inFIG. 7 , the first signal level essentially equals a voltage level of a supply voltage VSUP2 received by the electronic circuit between thefirst supply input 15 and the firstload output node 11. An example of generating this supply voltage VSUP2 is explained herein further below. The second signal level of the output signal Sout is essentially zero in this example. - The comparator output signal S42 can have two different signal levels, a first signal level that switches on the high-
side switch 43H and switches off the low-side switch 43L of thedriver 43 and a second signal level that switches off the high-side switch 43H and switches on the low-side switch 43L. A signal level of the comparator output signal S42 is dependent on signal levels of signals VOUT1, VOUT2 at the outputs OUT1, OUT2 of theinverters first load output 11 and each can have two different signal level, a first signal level that essentially equals the voltage level of the supply voltage VSUP2 and a second signal level that essentially equals zero. Due to the cross-coupling of theinverters inverters inverters level shifter transistors level shifter transistor 3 1 is in the on-state and the secondlevel shifter transistor 3 2 is in the off-state the output signal VOUT1 of thefirst inverter 41 1 has the first signal level and the output signal VOUT2 of thesecond inverter 41 2 has the second signal level. - In the circuit according to
FIG. 7 , thecross-coupled inverters level shifter transistors level shifter transistors level shifter transistors level shifter transistors -
FIG. 8 shows one example of how the first andsecond inverters FIG. 8 ,reference number 41i represents an arbitrary one of the first andsecond inverters inverter 41 1 and OUTi denotes the output of theinverter 41 i. In this example, theinverter 41 includes two complementary transistors, a high-side transistor 41H and a low-side transistor 41L, that each have a load path and a control node. The load paths of thesetransistors supply node 15 and thefirst load output 11. The output OUTi is formed by a circuit node that is common to the load paths of the twotransistors transistors inverter 41 1. - If the inverters in the circuit according to
FIG. 7 are implemented in accordance with.FIG. 8 , each of thelevel shifter transistors level shifter transistor 3 1 forms a voltage divider with the high-side transistor of thesecond inverter 412, and the secondlevel shifter transistor 32 forms a voltage divider with the high-side transistor of thefirst inverter 41 1. The low side transistors of theinverters load output node 11. - According to one example, the
level shifter transistors level shifter region 103. One example of how thelevel shifter transistors FIG. 9 .FIG. 9 shows a vertical cross-sectional view of one section of thesemiconductor body 100 that includes thelevel shifter region 103.FIG. 9 shows a vertical cross-sectional view of one of thelevel shifter transistors 3 1, 3 2 (reference character 3i denotes an arbitrary one of the twolevel shifter transistors 3 1, 3 2). In the example illustrated inFIG. 9 , thelevel shifter transistor 31 is a transistor of the first doping type and includes asource region 32 and adrain region 34 that are spaced apart from each other in a horizontal direction of thesemiconductor body 100. According to one example, thesource region 32 and thedrain region 34 are arranged such that thesource region 32 is closer to the inner region (not shown inFIG. 9 ) than thedrain region 34. In other words, thedrain 34 is closer to the edge surface (not shown) than thesource region 32. Thedrain region 32 is embedded in adrift region 31 of the first doping type. Thedrift region 31 has a lower doping concentration than thedrain region 34 and essentially defines the voltage blocking capability of thelevel shifter transistor 3. The voltage blocking capability is the voltage thelevel shifter transistor 3i can withstand in the off-state. - Referring to
FIG. 9 , thelevel shifter transistor 3; further includes abody region 33 of the second doping type between thesource region 32 and thedrift region 31. Thisbody region 33 may have the same doping concentration as thesecond region 130, in which thesource regions 32 and thedrift region 31 are embedded, or may have a doping concentration different from thesecond region 130. Further, agate electrode 35 is adjacent thebody region 33 and dielectrically insulated from thebody region 33 by agate dielectric 36. - Referring to
FIG. 7 , each of thelevel shifter transistors inverter - Referring to
FIG. 9 , thedrain region 34 can be connected to the input (represented by INi inFIG. 9 ) of the corresponding inverter and thesource region 32 can be connected to the secondload output node 12. Wiring arrangements that connect thedrain region 34 to the input of the corresponding inverter and that connect thesource region 32 to the secondload output node 12 and the source node S of the first transistor device can be formed on top of thefirst surface 107 and may include conductors embedded in or formed On top of at least oneinsulation layer 91. The conductor connecting thedrain region 34 to the input INi of the corresponding inverter may include afirst contact electrode 37 connected to thedrain region 34 and the conductor connecting thesource region 32 to thesecond load output 12 and the source node S may include asecond contact electrode 38 connected to thesource region 32. According to one example, thesecond contact electrode 38 extends into thesemiconductor 100 and is connected to thesecond region 130. Optionally, acontact region 39 of the second doping type that is doped higher than thesecond region 103 is formed between thesecond contact electrode 38 and thesecond region 130. According to one example, thissecond contact electrode 38 forms the contact explained with reference toFIG. 4 between the source node S and thesecond region 130. -
FIG. 10 shows a horizontal cross-sectional view in a section plane D-D of thelevel shifter region 103 shown inFIG. 9 and shows the twolevel shifter transistors FIG. 9 . The features of thelevel shifter transistors FIG. 10 are labelled with the same reference characters used inFIG. 9 , wherein a subscript index “1” has been added to the reference numbers of the firstlevel shifter transistor 3 1 and a subscript index “2” has been added to the reference numbers of the secondlevel shifter transistor 3 2. Referring toFIG. 10 , thedrift regions source regions level shifter transistors second region 130 so that a junction isolation is formed. between thedrift region source regions first region 120. According to another example (illustrated in dashed and dotted lines inFIG. 10 ), thesource regions - Referring to the above, the
drive circuit 4 is integrated in the firstdrive circuit region 104 of thesemiconductor body 100. One example of how thedrive circuit 4 may be implemented is illustrated inFIG. 11 .FIG. 11 illustrates one example of implementing one of the twoinverters 41 1, 41 2 (reference number 41 i represents an arbitrary one of theseinverters 41 1, 41 2). It should be noted that the other one of the two inverters as well as the inverter of thedriver 43 can be implemented in the same way. For the ease of understanding, doped regions of the second doping type are drawn as grey regions and doped regions of the first doping type are drawn as white regions in the example shown inFIG. 11 . - Referring to
FIG. 11 , theinverter 41, includes a dopedregion 410 of the second doping type, which is referred to as first well in the following. The active device regions of the high-side transistor 41H and the low-side transistor 41L are embedded in thisfirst well 410. - Referring to
FIG. 11 , the low-side transistor 41L includes asource region 411 and adrain region 412 of the first doping type and spaced apart from each other in a horizontal direction. A body region of the low-side transistor 41L may be formed by a section of thefirst well 410. Optionally, the body region is a region with a doping concentration different from the doping concentration of thefirst well 410. Agate electrode 413 of the low-side transistor 41L is adjacent the body region and dielectrically insulated from the body region by agate dielectric 414. Thesource region 411 is connected to the firstload output node 11 via a conductor that may formed in or on top of aninsulator 92 and may include asource electrode 415. Further, the first well 410 (forming the body region of the low-side transistor 411) may be connected to thefirst load output 11 via acontact electrode 418 and acontact region 417 of the second. doping type, - Referring to
FIG. 11 , the high-side transistor 41H includes asecond well 420 of the first doping type in the first well 410 of the first doping type. Further, the high-side transistor 41H includes asource region 421 and adrain region 422 of the second doping type in thesecond well 420 and spaced apart from each other in a horizontal direction of thesemiconductor body 100. A body region of the high-side transistor 41H may be formed by a section of thesecond well 420. Optionally, the body region is a region with a doping concentration different from the doping concentration of thesecond well 420. Agate electrode 423 of the high-side transistor 41H is adjacent the body region and dielectrically insulated from the body region by agate dielectric 424. Thesource region 421 of the high-side transistor 41H is connected to thesecond supply input 15 via a conductor that may include asource electrode 425. Further, thesecond supply input 15 may be connected to the second well 420 via acontact electrode 428 and a higherdoped contact region 427 of the first doping type. - Referring to
FIG. 11 , thedrain region 422 of the high-side transistor 4111 is connected to thedrain region 412 of the low-side transistor 411, via a conductor. This conductor may include afirst drain electrode 416 connected to thedrain region 412 of the low-side transistor 41L and adrain electrode 426 connected to thedrain region 422 of the high-side transistor 41H. - As can be seen from
FIG. 7 , for example, the potential at thefirst supply input 15 may become higher than the potential at the drain node D of thefirst transistor device 2. In theinverter 41, according toFIG. 11 , a pn-junction between thefirst well 410 and thesecond well 420 absorbs the voltage that may occur between thefirst supply input 15 and the first region 120 (which is connected to the drain node Di and, therefore, prevents a current flow from the first supply input to thedrain region 24 of thetransistor device 2. - The first
drive circuit region 104 may include several first wells of the type. illustrated inFIG. 11 that are spaced apart from each other so that a junction isolation is formed between these first wells. In each of these first wells, one inverter can be implemented. Further, thecomparator 42 may include transistor of the first doping type and/or the second doping type. These transistors can be implemented in the same way as thetransistors FIG. 11 . -
FIGS. 12A and 12B illustrate another implementation of theinverter 41 i.FIG. 12A shows a vertical cross-sectional view andFIG. 12B shows a horizontal cross-sectional view of the firstdrive circuit region 104. In the example shown inFIGS. 12A and 12B ,source regions body regions side transistor source regions transistors body regions source region 422 of the high-side transistor 41H is embedded in thefirst well 410, and the body region of the high-side transistor 41H may be formed by a section of the first well 410 (or by a region having a doping concentration different from the doping concentration of the first well 410). Further, the source, body and drainregions side transistor 41L are embedded in a further well 419 of the first doping type that is embedded in thefirst well 410. Thesource region 412 of the low-side transistor 41L is embedded in this further well 419. The body region of the low-side transistor 41L may be formed by a section of this further well 419 or by another region of the first doping type having a doping concentration different from the doping concentration of thefurther well 419. Thefurther well 419 is embedded in thefirst well 410. - In the example shown in
FIG. 11 , in which thesource region 421 and thedrain region 422 of the high-side transistor 41H are embedded in thesecond well 420, the pn-junction formed between first well 410 and thesecond well 420 absorbs a voltage between thefirst supply node 15 and the drain node D (drain region 24) of thetransistor device 2. In the example shown inFIGS. 12A and 12B , in which the source region 42:2 is embedded in thefirst well 410 and in which the potential of thesource region 422 essentially equals the potential at thesupply input 15 when the high-side transistor 41H is in the on-state, afurther region 431 of the first doping type surrounding thefirst well 410 and afurther region 432 of the second doping type surrounding thefurther region 431 of the first doping type and adjoining thefirst region 120 form two pn-junctions between thefirst well 410 and thefirst region 120 and, therefore, prevent a current flow from thefirst supply input 15 to the drain node D (the drain region 24) of thetransistor device 2. According to one example, thefurther region 431 of the first doping type is connected to thefirst supply input 15 and thefurther region 432 of the second doping type is connected to the firstload output node 11. -
Transistors FIG. 11 may be implemented using a CMOS process, and transistors of the type shown inFIGS. 12A and 12B may be implemented using a DMOS process. - Referring to the above, the drive voltage VGS of the
first transistor device 2 is generated based on the first input signal Sin1 received at thefirst input 13. According to one example, the first input signal Sin1 is a voltage referenced to the source node S of thefirst transistor device 2 and is directly used to drive thefirst transistor device 2. That is, thefirst transistor device 2 receives the first input signal Sin1 as the drive: voltage VGS. - In each of the examples illustrated in
FIGS. 11, 12A and 12B the signal received at the input IN of theinverter 41i from thelevel shifter 3 is an internal signal when thelevel shifter 3 is integrated in thesemiconductor body 100 or an external signal when thelevel shifter 3 is an external circuit that is not integrated in thesemiconductor body 100. - According to another example shown in
FIG. 13 theelectronic circuit 1 includes afurther drive circuit 6 that receives the first input signal Sin1 and generates the drive voltage VGs based on the first input signal Sin1. In this example, thefurther drive circuit 6 receives a supply voltage VSUP1 via afurther supply input 17. According to one example, this further supply voltage VSUP1 is a voltage referenced to the source node S and thesecond load output 12. - In the example illustrated in
FIG. 7 , thelevel shifter 3 is a differential level shifter with twolevel shifter transistors FIG. 13 , theelectronic circuit 1 receives one second input signal Sin2, which can be a voltage referenced to thesecond load output 12, in this example, the electronic circuit. 1 includes aninput circuit 5, that receives the second input signal Sin2 and is configured to generate the two input signals Sin2 1, Sin2 2 of thelevel shifter 3 based on the second input signal Sin2. - Examples of the
input circuit 5 and thesecond drive circuit 6 are illustrated inFIG. 14 . In this example, theinput circuit 5 includes an inverter with a low-side transistor 5L and a high-side transistor 51-I that receives the second input signal Sin2 at an input. At the output of the inverter the second level shifter input signal Sin2 2 received by the secondlevel shifter transistor 32 is available. The first level shifter input signal Sin2 1 equals the second input signal Sin2 in this example. Each of the low-side transistor 5L and the high-side transistor 5H has a load path and a control node. The load paths are connected in series between thesecond supply input 17 and thesecond load output 12 and the control nodes are connected with each other and form the input of theinverter - Referring to
FIG. 14 , thesecond drive circuit 6 may include afirst inverter 61 and asecond inverter 62 each including a low-side transistor side side transistors side transistors side transistor low side transistor inverter second supply input 17 and thesecond load output 12. Further, the control nodes are connected with each other and form an input of therespective inverter inverter side transistor low side transistor respective inverter first inverter 61 receives the first input signal Sin1 at the input, and the input of thesecond inverter 62 is connected to the output of thefirst inverter 61. The drive voltage VGS is available between the output of thesecond inverter 62 and the secondload output node 12. - According to one example, the
second drive circuit 6 and theinput circuit 5 are integrated in a seconddrive circuit region 105. This seconddrive circuit region 105 is schematically illustrated inFIG. 15 that shows a vertical cross-sectional view of thesemiconductor body 100 in the section plane A-A explained above. Referring toFIG. 15 , the seconddrive circuit region 105 is arranged between thelevel shifter region 103 and theinner region 102 and is embedded in thesecond region 130. Referring toFIG. 14 , each of theinput circuit 5 and thesecond drive circuit 6 includes at least one inverter. These inverters can be implemented in the seconddrive circuit region 105 in accordance with the examples explained with reference toFIGS. 11 and 12A-12B . According to one example, in this case, the first well 410 shown inFIG. 11 and thefurther region 432 of the second doping type shown inFIGS. 12A and 12B may be formed by thesecond region 130. - Referring to the above, the
drive circuit 4 that generates the output signal Sout based on the second input signal Sin2 is configured to drive a second transistor device. One example of an electronic circuit that includes thefirst transistor device 2 and thesecond transistor device 7 is illustrated inFIG. 16 . In this example, thesecond transistor device 7 is of the same transistor type as thefirst transistor device 2. That is, in this example, thesecond transistor device 7 is a n-type enhancement MOSFET. Thesecond transistor device 7 includes a control node (gate node) G7 and a load path between a drain node D7 and a source node S7. Further, the load path D7-S7 of thesecond transistor device 7 is connected in series with the load path D-S of thefirst transistor device 2 so that thefirst transistor device 2 and thesecond transistor device 7 form a half-bridge circuit. Thesecond transistor device 7 is driven by the output signal Sout, which, in this example, is a voltage between thedrive output 16 and thefirst load output 11 to which the source node S7 of thesecond transistor device 7 is connected. - Referring to
FIG. 16 , the (first) supply voltage VSUP1 received between thesecond supply node 17 and thesecond load Output 12 can be generated by anexternal voltage source 81 connected between thesecond supply input 17 and the secondload output node 12 of the electronic circuit. The (second) supply voltage VSUP2 received by the electronic circuit between thefirst supply input 15 and the firstload output node 11 can be generated by a bootstrap circuit based on the first supply voltage VSUP1. Referring toFIG. 16 , this bootstrap circuit may include acapacitor 82 connected between thefirst supply input 15 and the firstload output node 11, and adiode 83 connected between thevoltage source 81 and thecapacitor 82. In this electronic circuit, thecapacitor 82 is charged each time thefirst transistor device 2 switches on. When thefirst transistor device 2 switches off the charge stored in thecapacitor 82 can be used by thedrive circuit 4 to generate the output signal Sout and drive thesecond transistor device 7. - According to one example, the
second transistor device 7 is integrated in asecond semiconductor body 200. According to one example, only thesecond transistor device 7 is integrated in thesecond semiconductor body 200 while thefirst transistor device 2, thelevel shifter 3 and thedrive circuit 4 are integrated in thefirst semiconductor body 100. - According to one example, the first and
second semiconductor bodies second semiconductor bodies 100. 200 arranged in a common housing is illustrated inFIG. 17 .FIG. 17 shows a top view of the arrangement, wherein thehousing 301 is illustrated in dashed and dotted lines. - In the example shown in
FIG. 17 the arrangement includes afirst carrier 310 onto which thefirst semiconductor body 100 is mounted such that the drain node D is electrically connected to thefirst carrier 310. Thefirst carrier 310 includes apin 311 that protrudes from thehousing 301 and forms the firstload output node 11 of the electronic circuit. Thesecond transistor device 7 integrated in thissecond semiconductor body 200 can be a vertical transistor device implemented in the same way as thefirst transistor device 2. In this case a drain node of the second transistor device is formed by a second surface of thesecond semiconductor body 200. This second surface of thesecond semiconductor body 200 is mounted on asecond carrier 320. Thissecond carrier 320 is mounted on thefirst carrier 310 but is electrically insulated from thefirst carrier 310. Thesecond carrier 320 is electrically connected to afurther output pin 318 that forms a further output node 18 shown inFIG. 16 of the electronic circuit. According to one example, thesecond carrier 320 is connected to thefurther output pin 318 by a bond wire. This, however, is only an example. A flat conductor, or the like, may be used as well. - On top of a first surface, the
second semiconductor body 200 includes asource pad 228 that is connected to the source node S7 of thesecond transistor device 7, and agate pad 226 connected to the gate node (37 of thesecond transistor device 7. On top of the first surface, thefirst semiconductor body 100 includes asource pad 128 that is connected to thesource electrode 28 of thefirst transistor device 2. Further, on top of thefirst surface 107 of the first semiconductor body 100 a first andsecond input pad second supply pad first input pad 113 is connected to afirst input pin 313, and thesecond input pad 114 is connected to asecond input pin 314. The first input pins 313 forms thefirst input 13 and thesecond put pin 314 forms thesecond input 14 of the electronic circuit. Thefirst supply pad 115 is connected to afirst supply pin 315 and thesecond supply 117 is connected to asecond supply pin 317. Thefirst supply pin 315 forms thefirst supply input 15 and thesecond supply pin 317 forms thesecond supply input 17. Further anoutput pad 116 on top of thefirst semiconductor body 100 forms thedrive output 16 and is connected to thegate pad 226 of thesecond transistor device 7 inside thehousing 301. - The
source pad 128 on top of thefirst semiconductor body 100 is connected to asecond output pin 312 that forms thesecond load output 12 of the electronic circuit. Further, thesource pad 228 on top of thesecond semiconductor body 200 is connected to thefirst output pin 311. Just for the purpose of illustration, electrical connections between pads on top of thesemiconductor bodies FIG. 17 . This, however, is only an example. These connections can be implemented using flat conductors, or any other type of electrical connections as well. - in the example illustrated in
FIG. 17 , the second transistor device integrated in thesecond semiconductor body 200 is a drain-down transistor, that is, the drain node of the second transistor device is formed by a surface of thesemiconductor body 200 connected to the second carrier. According to another example (not shown) the second transistor device is a source-down transistor, in which the drain electrode and the gate electrode are accessible at the same side of thesemiconductor body 200 and the source electrode is accessible at the opposite side. In this example, thesecond carrier 320 can be omitted; thesecond semiconductor body 200 can be mounted on thefirst carrier 310 such that the source electrode is connected to the first carrier 310 (and, in this way, to the drain node of thefirst transistor device 2 integrated in the first semiconductor body 100); and the drain electrode can be connected to thefurther output pin 318 via a connector, such as a bond wire, a flat conductor, or the like. -
FIG. 18 shows a modification of the module shown inFIG. 17 . The module according toFIG. 18 is different from the module according toFIG. 17 in that thefirst carrier 310 and thesecond carrier 320 are spaced apart from each other in a lateral direction and, thereby, electrically insulated from each other. In this example, the further output pin 18 can be formed by a part of thesecond carrier 320. Everything else explained with reference to the module shown inFIG. 17 applies to the module shown inFIG. 18 accordingly. - Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the disclosure.
- Example 1. An electronic circuit, including: a first transistor device integrated in an inner region of a first semiconductor body; a level shifter integrated in a level shifter region of the first semiconductor body; and a first drive circuit connected to the level shifter, integrated in a first drive circuit region of the semiconductor body, and configured to drive a second transistor device, wherein each of the level shifter region and the first drive circuit region is located in an edge region surrounding the inner region of the semiconductor body, and wherein the level shifter region is arranged closer to the inner region than the first drive circuit region.
- Example 2. The electronic circuit of example 1, further including: a second drive circuit integrated in a second drive circuit region in the edge region of the first semiconductor body, wherein the second drive circuit is configured to receive a first input signal from a first input and drive the first transistor device based on the first input signal, and wherein the second drive circuit region is arranged closer to the inner region than the level shifter region.
- Example 3. The electronic circuit of any combination of examples 1 to 2, further including: an input circuit integrated in the second drive circuit region and coupled between a second input and the level shifter.
- Example 4. The electronic circuit of any combination of examples 1 to 3, wherein the first transistor device includes a plurality of transistor cells, each including: a drift region of a first doping type; a source region of the first doping type connected to a source node; a body region of a second doping type complementary to the first doping type; a drain region of the first doping type separated from the body region by the drift region and connected to a drain node; and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric.
- Example 5. The electronic circuit of any combination of examples 1 to 4, wherein each of the plurality of transistor cells further includes: a compensation region adjoining the drift region.
- Example 6. The electronic circuit of any combination of examples 1 to 5, further including: a first region of the first doping type and a second region of the second doping type in the edge region, wherein a pn-junction is formed between the first region and the second region, wherein the first region is connected to the drain node and the second region is connected to the source node, and wherein the level shifter region is embedded in the second region and the first drive circuit region is embedded in the first region.
- Example 7. The electronic circuit of any combination of examples 1 to 6, wherein the second drive circuit region is embedded in the second region.
- Example 8. The electronic circuit of any combination of examples 1 to 7, wherein a maximum doping concentration of each of the first region is higher than a maximum doping concentration of the drift region.
- Example 9. The electronic circuit of any one of any combination of examples 1 to 8, wherein a maximum doping concentration of the second region is less than a maximum doping concentration of the drift region.
- Example 9. The electronic circuit of any one of any combination of examples 1 to 8, wherein a maximum doping concentration of the second region is less than 1E16 cm−1.
- Example 11. The electronic circuit of any one of the preceding claims, wherein the level shifter includes at least one lateral transistor device,
- Example 12. The electronic circuit of any combination of examples 1 to 11, wherein the first drive circuit includes at least one inverter.
- Example 13. The electronic circuit of any combination of examples 1 to 12, wherein the second drive circuit includes at least one inverter.
- Example 14. The electronic circuit of any combination of examples 1 to 13, further including the second transistor device, wherein a load path of the second transistor device is connected in series with a load path of the first transistor device.
- Example 15. The electronic circuit of any combination of examples 1 to 14, wherein the second transistor device is integrated in a further semiconductor body.
- Example 16. The electronic circuit of any combination of examples 1 to 15, wherein the first semiconductor body and the second semiconductor body are arranged in a common housing.
- Example 17. The electronic circuit of any combination of examples 1 to 16, wherein the first semiconductor body is mounted on a first carrier and the second semiconductor body is mounted on a second carrier that is electrically insulated from the first carrier.
- Example 18. The electronic circuit of any combination of examples 1 to 17, wherein the first semiconductor body and the second semiconductor body are mounted on the same carrier.
- While the invention has been described with reference to illustrative examples, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative examples, as well as other examples of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or examples.
Claims (25)
1. An electronic circuit, comprising:
a first transistor device integrated in an inner region of a first semiconductor body;
a level shifter integrated in a level shifter region of the first semiconductor body, wherein the level shifter region is located in an edge region surrounding the inner region of the semiconductor body; and
a drive circuit integrated in a drive circuit region in the edge region of the first semiconductor body, wherein the drive circuit is configured to receive a first input signal from a first input and drive the first transistor device based on the first input. signal, and wherein the drive: circuit region is arranged closer to the inner region than the level shifter region.
2. The electronic circuit of claim 1 , further comprising:
an input circuit integrated in the drive circuit region and coupled be a second input and the level shifter.
3. The electronic circuit of claim 1 , wherein the drive circuit comprises at least one inverter.
4. The electronic circuit of claim 1 , wherein the first transistor device comprises a plurality of transistor cells, each comprising:
a drift region of a first doping type;
a source region of the first doping type connected to a source node;
a body region of a second doping type complementary to the first doping type;
a drain region of the first doping type separated from the body region by the drift region and connected to a drain node; and.
a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric.
5. The electronic circuit of claim 4 , wherein each of the plurality of transistor cells further comprises:
a compensation region adjoining the drift region.
6. The electronic circuit of claim 4 , further comprising:
a first region of the first doping type and a second region of the second doping type in the edge region,
wherein a pn-junction is formed between the first region and the second region,
wherein the first region is connected to the drain node and the second region is connected to the source node, and
wherein the level shifter region is embedded in the second region.
7. The electronic circuit of claim 6 , wherein the drive circuit region is embedded in the second region.
8. The electronic circuit of claim 7 , wherein the drive circuit comprises at east one inverter.
9. The electronic circuit of claim 6 , wherein a maximum doping concentration of the first region is higher than a maximum doping concentration of the drift region.
10. The electronic circuit of claim 6 , wherein a maximum doping concentration of the second region is less than a maximum doping concentration of the drift region.
11. The electronic circuit of claim 6 , wherein a maximum doping concentration of the second region is less than 1E16 cm−3.
12. The electronic circuit of claim1, wherein the level shifter comprises at least one lateral transistor device.
13. The electronic circuit of claim 1 , further comprising:
a second transistor device,
wherein a load path of the second transistor device is connected in series with load path of the first transistor device.
14. The electronic circuit of claim 13 , wherein the second transistor device is integrated in a second semiconductor body.
15. The electronic circuit of claim 14 , wherein the first semiconductor body and the second semiconductor body are arranged in a common housing.
16. The electronic circuit of claim 15 , wherein the first semiconductor body is mounted on a first carrier and the second semiconductor body is mounted on a second carrier that is electrically insulated from the first carrier.
17. The electronic circuit of claim 15 , wherein the first semiconductor body and the second semiconductor body are mounted on the same carrier.
18. An electronic circuit, comprising.
a first transistor device integrated in an inner region of a first semiconductor body; and
a level shifter and a drive circuit integrated in an edge region surrounding the inner region of the semiconductor body,
wherein the drive circuit is configured to receive a first input signal from a first input and drive the first transistor device based on the first input signal,
wherein the drive circuit is arranged closer to the inner region than the level shifter,
wherein the first transistor device comprises a plurality of transistor cells, each comprising:
a drift region of a first doping type;
a source region of the first doping type connected to a source node;
a body region of a second doping type complementary to the first doping type;
a drain region of be first doping type separated from the body region by the drift region and connected to a drain node; and
a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric.
19. The electronic circuit of claim 18 , wherein each of the plurality of transistor cells further comprises:
a compensation region adjoining the drift region.
20. The electronic circuit of claim 18 , further comprising:
a first region of the first doping type and a second region of the second doping type in the edge region,
wherein a pn-junction is formed between the first region and the second region,
wherein the first region is connected to the drain node and the second region is connected to the source node, and
wherein the level shifter is embedded in the second region.
21. The electronic circuit of claim 20 , wherein the drive circuit region is embedded in the second region.
22. The electronic circuit of claim 21 , wherein the drive circuit comprises at least one inverter.
23. The electronic circuit of claim 20 , wherein a maximum doping concentration of the first region is higher than a maximum doping concentration of the drift region.
4. The electronic circuit of claim 20 , therein a maximum doping concentration of the second region is less than a maximum doping concentration of the drift region.
25. The electronic circuit of claim 20 , wherein a maximum doping concentration of the second region is less than 1E16 cm−3.
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US17/731,637 US20220254934A1 (en) | 2018-08-06 | 2022-04-28 | Electronic circuit |
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DE102018119098.0 | 2018-08-06 | ||
DE102018119098.0A DE102018119098B4 (en) | 2018-08-06 | 2018-08-06 | ELECTRONIC CIRCUIT WITH A TRANSISTOR COMPONENT AND A LEVEL CONVERTER |
US16/531,460 US11183598B2 (en) | 2018-08-06 | 2019-08-05 | Electronic circuit with a transistor device and a level shifter |
US17/506,272 US11342467B2 (en) | 2018-08-06 | 2021-10-20 | Electronic circuit with a transistor device, a level shifter and a drive circuit |
US17/731,637 US20220254934A1 (en) | 2018-08-06 | 2022-04-28 | Electronic circuit |
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US17/506,272 Continuation US11342467B2 (en) | 2018-08-06 | 2021-10-20 | Electronic circuit with a transistor device, a level shifter and a drive circuit |
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US17/506,272 Active US11342467B2 (en) | 2018-08-06 | 2021-10-20 | Electronic circuit with a transistor device, a level shifter and a drive circuit |
US17/731,637 Pending US20220254934A1 (en) | 2018-08-06 | 2022-04-28 | Electronic circuit |
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US17/506,272 Active US11342467B2 (en) | 2018-08-06 | 2021-10-20 | Electronic circuit with a transistor device, a level shifter and a drive circuit |
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DE19710487A1 (en) * | 1996-03-13 | 1997-09-18 | Toshiba Kawasaki Kk | Semiconductor module with vertical semiconductor component |
JP4067967B2 (en) * | 2001-02-06 | 2008-03-26 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Integrated field effect transistor and driver |
US8310007B2 (en) * | 2009-07-13 | 2012-11-13 | Maxpower Semiconductor Inc. | Integrated power supplies and combined high-side plus low-side switches |
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US9859274B2 (en) * | 2012-07-11 | 2018-01-02 | Infineon Technologies Dresden Gmbh | Integrated circuit with at least two switches |
JP5754558B2 (en) | 2012-09-13 | 2015-07-29 | 富士電機株式会社 | Semiconductor integrated circuit device |
US9704580B2 (en) * | 2012-10-22 | 2017-07-11 | Conversant Intellectual Property Management Inc. | Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices |
JP6134219B2 (en) * | 2013-07-08 | 2017-05-24 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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CN105874597B (en) | 2014-07-02 | 2019-03-08 | 富士电机株式会社 | Conductor integrated circuit device |
US10141845B2 (en) * | 2016-04-13 | 2018-11-27 | Texas Instruments Incorporated | DC-DC converter and control circuit with low-power clocked comparator referenced to switching node for zero voltage switching |
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