US20220109379A1

US20220109379A1 - Soft-switching voltage-edge-rate-limiting power inverter

Info

Publication number: US20220109379A1
Application number: US17/551,071
Authority: US
Inventors: Oleg Wasynczuk; Minyu Cai
Original assignee: Purdue Research Foundation
Current assignee: Purdue Research Foundation
Priority date: 2019-06-23
Filing date: 2021-12-14
Publication date: 2022-04-07
Also published as: US20210408940A1; US11201562B1

Abstract

An auxiliary resonant soft-edge pole inverter circuit is provided. The power inverter circuitry may include a first pair of capacitors in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch and a diode in parallel and sharing a common central node with the first pair of capacitors. The power inverter circuit may further include a first pair of auxiliary switches connected in series with a first pair of inductors, respectively, to generate resonant current from a DC power source, the first pair of inductors also sharing the common central node. The power inverter circuitry may further include a second pair of auxiliary switches connected in series with a second pair of capacitors, respectively, the second pair of auxiliary switches also sharing the common central node, the circuit producing an alternating current output at the common central node.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 16/887,013 filed May 29, 2021, which claims the benefit of U.S. Provisional Application No. 62/865,292 filed Jun. 23, 2019, the entireties of which is hereby incorporated by reference.

STATEMENT REGARDING GOVERNMENT FUNDING

This invention was made with government support under DE-EE0005568 awarded by the Department of Energy. The government has certain rights in the invention.

TECHNICAL FIELD

The present application relates to DC-to-AC power inverters, and more specifically, to soft-switching inverters.

BACKGROUND

Switch-mode DC-to-AC inverters are widely used in variable-speed motor drive systems and other applications. To increase switching frequency and reduce switching loss, power switches have been made faster in the past decades. The switching times of insulated-gate bipolar transistors (IGBTs) have reduced to tens of nanoseconds, while those of wide-bandgap (WBG) devices, such as Silicon Carbide and Gallium Nitride devices, have reduced to several nanoseconds.
As switches are made faster, the inverter output voltage edge rate (dv/dt) becomes larger. Various deleterious effects have been experienced and documented since the introduction of IGBTs. These problems include overvoltages at the motor/inverter terminals, electromagnetic interference, large common-mode currents, and the failure of motor bearings due to induced micro-arcs. To reduce the occurrence of problems resulting from high dv/dt, some standards have been established that limit the dv/dt going into motor drives, among which the US National Electrical Manufacturers Association (NEMA) MG1 Part 31 is commonly observed in the US.
Conventional dv/dt-limiting methods include increasing the external gate resistance or Miller capacitance of the switches, and adding a dv/dt filter between the inverter and the motor. All of these methods, especially the dv/dt filter, can effectively reduce the dv/dt but will introduce extra losses, size and weight of the system.
Soft-switching inverters that are originally developed to reduce switching loss can also limit the dv/dt in the circuits. They can possibly replace the dv/dt filter which may result in reduction in total loss and size/weight. Among various soft-switching inverter topologies, the auxiliary resonant commutated pole (ARCP) inverter and its variants are suitable for variable-speed motor drive systems because they have full pulse width modulation (PWM) control capabilities. The original ARCP inverter can realize zero-voltage switching (ZVS) and zero-current switching (ZCS) in its main and auxiliary switches, respectively. However, it has several drawbacks. First, the necessary mid-voltage point requires extra balancing circuits. Secondly, a boost current needs to be generated, which requires accurate current sensing and/or switch triggering, and results in complicated control. Thirdly, the reverse-recovery current of the auxiliary diodes will induce a large voltage across the auxiliary switches. Therefore, snubbers or voltage-clamping circuits are required, which generate extra losses. To eliminate these drawbacks, some variants of the ARCP were proposed over the past decades.
One approach to improve the ARCP is to use a transformer or coupled inductor. A topology described in J. D. Herbst, F. D. Engelkemeir, and A. L. Gattozzi, “High power density and high effciency converter topologies for electric ships,” in Proc. IEEE Electric Ship Technol. Symp. (ESTS), April 2013, pp. 360-365 uses a 1:1 transformer to create a virtual mid-voltage point, and the auxiliary switches only conduct half of the resonant current. However, the transformer needs to be reset after each switching cycle by extra circuits. A transformer-assisted resonant pole inverter is proposed in X. Yuan and I. Barbi, “Analysis, designing, and experimentation of a transformer-assisted pwm zero-voltage switching pole inverter,” IEEE Trans. Power Electron., vol. 15, no. 1, pp. 72-82, January 2000. Its transformer has a turns ratio different from one so the boost current is not required, which makes control simpler. The transformer current can be properly reset. However, the transformer is bulky and its leakage inductance is part of the resonant inductor which makes parameter design more challenging.
The other approach to improve the ARCP is represented by the auxiliary resonant pole (ARP). The ARP connects the resonant inductor to the upper or lower DC bus through auxiliary switches so it does not need a mid-voltage point. Due to this configuration, the boost current is not required, and the auxiliary switch turn-on and the main switch turn-off can be triggered at the same time, which makes control simpler. In addition, the transient voltage across auxiliary switches is clamped to the DC-bus voltage by auxiliary diodes. However, there are still some drawbacks with the ARP inverter. The auxiliary switches have lossy hard-switched turn-off. In addition, there may be a circulating current in the auxiliary circuits when a main switch module is conducting continuously, which again generates loss. A circuit proposed in W. Yu, J. S. Lai, and S. Y. Park, “An improved zero-voltage switching inverter using two coupled magnetics in one resonant pole,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 952-961, April 2010 uses two coupled magnetics as resonant inductors so the circulating current can be prevented. However, the turn-off transients of the auxiliary switches are not perfect ZCS because of the remaining magnetizing current. Therefore, improvements are needed in the field.
The active auxiliary edge resonant pole (AAERP) (see M. Nakamura, T. Yamazaki, Y. Fujii, T. Ahmed, and M. Nakaoka, “A novel prototype of auxiliary edge resonant bridge leg link snubber-assisted soft-switching sine-wave PWM inverter,” Elect. Eng. Jpn., vol. 155, no. 4, pp. 64-76, 2006) and the double ARCP (DARCP) (see E. Chu, X. Zhang, and L. Huang, “Research on a novel modulation strategy for double auxiliary resonant commutated pole soft-switching inverter with the shunt dead time,” IEEE Trans. Power Electron., vol. 31, no. 10, pp. 6855-6869, October 2016.) improve upon ARP by adding a second pair of capacitors to realize ZVS turn off in the auxiliary switches. However, the second pair of capacitors may not be precharged to the DC-bus voltage, so the output dv/dt may sometimes be large.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following description and drawings, identical reference numerals have been used, where possible, to designate identical features that are common to the drawings.

FIG. 1 is a schematic and timing diagram illustrating an auxiliary resonant soft-edge pole inverter circuit according to various aspects.

FIG. 2A is a schematic and timing diagram illustrating operation of a power inverter in a diode-to-switch (D2S) commutation during time Interval A according to various aspects.

FIG. 2B is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval B according to various aspects.

FIG. 2C is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval C according to various aspects.

FIG. 2D is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval D according to various aspects.

FIG. 2E is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval E according to various aspects.

FIG. 2F is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval F according to various aspects.

FIG. 2G is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval G according to various aspects.

FIG. 2H is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval H according to various aspects.

FIG. 3A is a schematic and timing diagram illustrating operation of a power inverter in a switch-to-diode (S2D) commutation during time Interval H according to various aspects.

FIG. 3B is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval I according to various aspects.

FIG. 3C is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval J according to various aspects.

FIG. 3D is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval K according to various aspects.

FIG. 3E is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval L according to various aspects.

FIG. 4 is a schematic and timing diagram illustrating operation of a power inverter circuit in a D2S commutation during time Interval C₂according to various aspects.

FIG. 5A-B are state-plane plots of ARSEP and AAERP according to various aspects.

FIG. 6 is a schematic illustrating an auxiliary resonant soft-edge pole inverter circuit with metal-oxide-semiconductor field-effect transistors (MOSFETs) according to various aspects.

The attached drawings are for purposes of illustration and are not necessarily to scale.

DETAILED DESCRIPTION

In the following description, some aspects will be described in terms that would ordinarily be implemented as software programs. Those skilled in the art will readily recognize that the equivalent of such software can also be constructed in hardware, firmware, or micro-code. Because data-manipulation algorithms and systems are well known, the present description will be directed in particular to algorithms and systems forming part of, or cooperating more directly with, systems and methods described herein. Other aspects of such algorithms and systems, and hardware or software for producing and otherwise processing the signals involved therewith, not specifically shown or described herein, are selected from such systems, algorithms, components, and elements known in the art. Given the systems and methods as described herein, software not specifically shown, suggested, or described herein that is useful for implementation of any aspect is conventional and within the ordinary skill in such arts.
The present disclosure provides a soft-switching circuit to control an inverter output dv/dt with less loss, size and weight than prior-art dv/dt limiting methods, while eliminating the drawbacks of prior-art soft-switching circuits. A circuit topology is provided, referred to herein as an auxiliary resonant soft-edge pole (ARSEP) inverter that realizes soft-switching in all of the main and auxiliary switches and ensures that the inverter dv/dt is limited by circuit parameters. The second pair of resonant capacitors will always be fully pre-charged so the inverter dv/dt can be well-controlled.
One embodiment of a single-phase ARSEP inverter is shown in FIG. 1, in which auxiliary circuits are illustrated using a dashed box. Capacitors C₁and C₂are connected in parallel with the main switch modules S₁/D₁and S₂/D₂. Auxiliary switches S₃and S₄are connected in series with inductors L₁and L₂to generate resonant current.
It is notable that S₃and S₄are unidirectional to prevent circulating current. Capacitors C₃and C₄have two roles. When S₅(S₆) is on, C₃(C₄) facilitates soft-switching of the main switches; when S₅(S₆) is off, C₃(C₄) and D₃(D₄) serve as the turn-off snubber of S₃(S₄). Diodes D₅and D₆enable pre-charging of C₃and C₄, which prepares them for the next resonant process so that the dv/dt is well-controlled by circuit parameters. Diodes D₇and D₈direct residue energy in L₁and L₂back to the power source. It is assumed that C₁=C₂=C_a, C₃=C₄=C_b, and L₁=L₂=L. The “+” signs in FIG. 1 define the ports where positive current goes into the devices.
Output Current I_omay be constant during commutation. Since inverter operation is symmetric for positive and negative output current I_o, without losing generality, the circuit operation with a positive output current (I_o>0) will be explained in the following subsections. The output current is generally constant during the commutation because the commutation time is relatively short.
A. Diode-to-Switch Commutation
A commutation in which the output current I_ocommutes from a diode to a switch is called a diode-to-switch (D2S) commutation.
Interval A (t<t₀): Initially, S₂is ON while D₂actually conducts I_o(FIG. 2A). Voltages ν_C1=E, ν_C2=0, and ν_C3=E due to the presence of D₅. In order to demonstrate the basic operation of the circuit, it is assumed that C₄is initially pre-charged, i.e., ν_C4,0=E. The situation where ν_C4.0<E will be discussed further below.
Interval B (t₀≤t<t₁): At t₀, a D₂S commutation is commanded. Switch S₂is turned off while S₃and S₅are turned on (FIG. 2B). Since D₂is conducting, S₂is turned off with zero-voltage-zero-current switching (ZVZCS). Since i_L1(t₀)=0, S₃is turned on with ZCS. Since ν_C3(t₀)=E, S₅is turned on with ZVZCS. Current i_L1increases substantially linearly.
Interval C (t₁≤t<t₂): At t₁, i_L1increases to I_owhereupon D₂stops conducting and L₁starts to resonate with C₁, C₂, and C₃(FIG. 2C). Voltage ν_oincreases while ν_C4stays at E since S₆is OFF.
Interval D (t₂≤t<t₃): At 12, ν_oreaches E and the resonance stops (FIG. 2D). Current i_L1supplies I_o. Since i_L1>I_o, the extra current circulates in the circuit shown in FIG. 2D. Based on simulation and experiment, the extra current circulates in the L₁-D₁-S₃and L₁-S₅-D₃loops. The current in the L₁-D₆-D₈-S₃loop is negligible because there are two diodes in this loop. Ideally, i_L1is constant and is actually at its peak value
$\begin{matrix} I_{{L 1}_{p}} = \frac{E}{Z} + I_{o} & (1) \\ where \\ Z_{1} = \sqrt{\frac{L}{2 C_{a} + C_{b}}} & (2) \end{matrix}$
Interval E (t₃≤t<t₄): At t₃, S₁is turned on while S₃and S₅are turned off so i_L1starts to charge C₃(FIG. 2E). Since D₁is conducting, S₁is turned on with ZVZCS. Since ν_C3(t₃)=0, S₃and S₅are turned off with ZVS. The energy in L₁at t₃is
W _L1=½L ₁ L _L1p ²>½C _b E ²+½LI _o ² (3)
Therefore, L₁has enough energy to charge C₃to E.
Interval F (t₄≤t<t₅): At t₄, C₃is charged to E whereupon D₇starts to conduct (FIG. 2F). The energy transferred to C₃is ½C_bE², so the energy remains in L₁is still higher than ½LI_o ²according to (3). Therefore, i_L1(t₄)>I_o, so D₁still conducts current. Current i_L1will decrease linearly, and the energy will flow back to the DC source.
Interval G (t≤t<t₆): At t₅, i_L1decreases to I_owhile D₁stops conducting and S₁starts to conduct (FIG. 2G). Current i_L1decreases linearly to zero at t₆, which ends the D2S commutation.
B. Switch-to-Diode Commutation
A commutation in which the output current commutes from a switch to a diode is called a switch-to-diode (S2D) commutation.
Interval H (t₆≤t<t₇): Prior to an S2D commutation, the circuit is in Interval H where S₁is conducting (FIG. 3A).
Interval I (t₇≤t<t₈): At t₇, an S2D commutation is commanded so S₁is turned off while S₄and S₆are turned on. Inductor L₂starts to resonate with C₁, C₂, and C₄(FIG. 3B). Since ν_C1(t₇)=0, S₁is turned off with ZVS. Since i_L2(t₇)=0, S₄is turned on with ZCS. Since ν_C4(t₇)=E, S₆is turned on with ZVZCS. Voltage ν_odecreases and ν_C3stays at E since S₅is OFF.
Interval J (t₈≤t<t₉): At t₈, ν_odecreases to zero and i_L2starts to circulate in the circuit (FIG. 3C). According to the simulation and experiment, i_L2circulates in the L₂-S₄-D₂and L₂-D₄-S₆loops. The current in the L₂-S₄-D₇-D₅loop is negligible. Ideally, i_L2is constant and is at its peak value
$\begin{matrix} I_{L 2 p} = \sqrt{{I_{o}}^{2} + {(\frac{E}{Z_{1}})}^{2}} - I_{o} & (4) \end{matrix}$
Interval K (t₉≤t<t₁₀): At t₉, S₂is turned on while S₄and S₆are turned off. Current i_L2starts to charge C₄(FIG. 3D). Since D₂is conducting, S₂is turned on with ZVZCS. Since ν_C4(t₉)=0, S₄and S₆are turned off with ZVS. Unlike the D2S commutation, L₂may not have sufficient energy to charge C₄up to E. Here, it is assumed that L₂has sufficient energy so ν_C4reaches E.
Interval L (t₁₀≤t<t₁₁): At t₁₀, ν_C4reaches E and D₈starts to conduct. Current i_L2decreases linearly to zero at t₁₁, which completes an S2D commutation.
C. Alternative Mode of Operation
According to (4), I_L2pdecreases when I_oincreases. The energy in L₂in Interval J is
W _L2=½LI _L2p ² (5)
It may be less than ½C_bE², especially when I_ois large or C_ais much smaller than C_b. Therefore, C₄may not be charged to E even absorbing all energy in L₂. In this case, Interval K ends at t′₁₀when i_L2decreases to zero. The circuit operation will then skip Interval L and goes directly to Interval A. Then, the initial voltage of C₄for the next D₂S commutation ν_C4,0is less than E. In the next D₂S commutation, C₄stays at ν_C4,0in Interval B. Interval C will actually have two subintervals denoted by Intervals C₁and C₂.
Interval C₁(t₁≤t<t_1.5): This interval is similar to Interval C (FIG. 2C) except that ν_C4stays at ν_C4,0.
Interval C₂(t_1.5≤t<t₂): At t_1.5, ν_oincreases to ν_C4,0and D₆starts to conduct current (FIG. 4). Inductor L₁starts to resonate with C_1-4. When ν_oincreases to E, i_L1increases to its peak value
$\begin{matrix} L_{L 1 p}^{'} = \sqrt{{(\frac{E - v_{C 4, 0}}{Z_{3}})}^{2} (1 - \frac{Z_{3}^{2}}{Z_{1}^{2}}) + {(\frac{E}{Z_{1}})}^{2}} + I_{o} & (6) \\ where \\ Z_{3} = \sqrt{\frac{L}{2 C_{a} + C_{b}}} & (7) \end{matrix}$
Since Z₃<Z₁and I_L1P′>I_L1p, according to (3), L₁has enough energy to charge C₃up to E, and the remaining i_L1is still greater than I_o. This interval ends at t₂when ν_oincreases to E. Voltage ν_C4increases to E at t₂, which prepares for the next S2D commutation. This pre-charging feature is not available in AAERP or DARCP, so they may result in high dv/dt.
D. Summary of Circuit Operation
The gating signals of the ARSEP inverter can be generated based on the PWM signal and a time delay t_d, as shown in FIG. 3. The requirement on t_dis
$\begin{matrix} t_{d} > t_{B} + t_{C} = \frac{I_{o} L}{E} + t_{C} & (8) \\ where \\ \frac{π}{2 ω_{1}} \leq t_{C} < \frac{π}{2 ω_{3}} & (9) \\ ω_{1} = \frac{1}{\sqrt{L (2 C_{a} + C_{b})}} & (10) \\ ω_{3} = \frac{1}{\sqrt{L (2 C_{a} + 2 C_{b})}} & (11) \end{matrix}$
From (8), t_dis a function of I_o. The first term depends on circuit parameters, and the second term is mainly determined by allowable dv/dt. Therefore, it is possible to reduce t_dthrough the parameter design to cater to high switching frequencies.
If t_dis constant, all gating signals can be generated without any sensing. Then, t_dshould be longer than the maximum possible voltage commutation time
$\begin{matrix} t_{c, \max} = {(t_{B} + t_{C})}_{\max} = \frac{I_{p} L}{E} + \frac{π}{2 ω_{3}} & (12) \end{matrix}$
where I_pis the peak output current. If I_ois measured by a current sensor, a lookup table can be used to determine the required t_d. Then, the duration of Intervals D and J as well as the associated losses can be reduced without affecting the dv/dt performance.
The circuit operation can be represented in a more concise way using a state-plane plot as shown in FIG. 5A. The two normalized states for the state-plane plot are defined as:
$\begin{matrix} \overline{i} = \frac{{iZ}_{1}}{E}, \overline{v} = \frac{v}{E} & (13) \end{matrix}$
The moving directions of the state are indicated by arrows. From t₁to t_1.5, the state follows a circular arc about the center (1, Ī_o) with a rotational speed of ω₁. Similarly, from t₇to t₈, the state follows another circular arc about the center (0, Ī_o) with the same speed ω₁. If ν_C4,0=E, from Point P, the state will keep following the solid circular arc to Point Q. If ν_C4,0<E, from Point P, the state follows the dashed curve and goes to Point R.
The state-plane plot of AAERP is shown in FIG. 5B. When C₃and C₄are fully charged, the state follows the solid line to Point Q. However, when C₃or C₄is lightly charged (which is likely when I_ois large), the state moves from the origin to Point P and then to Point R, during which high dv/dt will occur. DARCP suffers a similar problem. ARSEP solves the problem by pre-charging C₃(C₄) through diode D₅(D₆) so that dv/dt can be well controlled by circuit parameters.
E. Voltage and Current Characteristics
The peak inductor current, di/dt, and dv/dt in the ARSEP inverter can be derived as:
$\begin{matrix} I_{L, \max} = \frac{E}{Z_{3}} + I_{p} = (\frac{1}{{\overline{Z}}_{3}} + 1) I_{p} & (14) \\ \frac{{di}_{L}}{{dt}_{\max}} = \frac{E}{L} & (15) \\ \frac{{dv}_{o}}{{dt}_{\max}} = \frac{0.8 {E ω}_{1}}{{Δθ}_{T 2 D} ({\overline{Z}}_{1})} & (16) \\ where \\ {Δθ}_{S2D} ({\overline{Z}}_{1}) = \cos^{- 1} \frac{0.1}{\sqrt{{\overline{Z}}_{1}^{2} + 1}} - \cos^{- 1} \frac{0.9}{\sqrt{{\overline{Z}}_{1}^{2} + 1}} & (17) \end{matrix}$
is the angle being swept when ν _odecreases from 0.9 to 0.1, as shown in FIG. 5A, because dv/dt defined by the NEMA MG-1 standard is the average voltage-change rate when the voltage changes between 10% and 90%. The normalized impedance is defined as
$\begin{matrix} \overline{Z} = \frac{I_{p} Z}{E} & (18) \end{matrix}$
F. Example

TABLE 1

ARSEP Inverter Design Specification (Example)

	Item	Value

DC-bus voltage, E	200	V
Peak output current, I_p	20	A
Maximum voltage edge rate, dv/dt_limit	200	V/μs
Maximum current edge rate, di/dt_limit	50	A/μs
Maximum inductor current, I_{L, limit}	50	A
Switching frequency, f _sw	10	kHz
Maximum commutation time	5	μs

By way of example, given the specifications in Table 1, an ARSEP inverter may be designed as follows. Referring to (14)
$\begin{matrix} {\overline{Z}}_{3} > \frac{I_{p}}{I_{L, limit} - I_{p}} = 0.67 & (19) \end{matrix}$
It is selected that Z ₃=1 to limit the maximum inductor current. Based on (2) and (7), it can be concluded that Z₁>Z₃, so it is selected that Z ₁=1.1. Subsequently, according to (16) and (17)
$\begin{matrix} {Δθ}_{S2D} = 0.583 rad & (20) \\ ω_{1} = \frac{\frac{dv}{{dt}_{limit}} {Δθ}_{S2D}}{0.8 E} = 0.729 rad/μs & (21) \end{matrix}$
Based on Z ₁, Z ₃, and ω₁, the values of the resonant components are calculated to be L=15 μH, C_a=50 nF, and C_b=25 nF. In order to maximize the benefit of soft switching, C_bshould be large enough so that S₃and S₄are over-snubbed. With this design, according to (12) and (14)-(16), t_cmax=3.9 μs, I_Lmax=40 A, di_L/dt_max=13.3 A/μs, and dv_o/dt_max=200 V/μs, which satisfy NEMA standards.
FIG. 6 illustrates an example of the circuit. The switches may be include metal-oxide-semiconductor field-effect transistors (MOSFETs) (as shown in FIG. 6), an insulated-gate bipolar junction transistor (IGBT), or other suitable transistor. When the switches labelled S₃and S₄are MOSFET devices, there are diodes in series with the MOSFET “switch” (labeled D₉and D₁₀in FIG. 6), since the unidirectional switches S₃and S₄should conduct current in one direction only.
The presently disclosed ARSEP circuit may be implemented to control power inverters in hybrid and electric vehicles, aircraft actuators, ship propulsion, and grid integration of renewable energy sources, or other applications.
In various aspects and examples, the auxiliary resonant soft-edge pole inverter circuit may include a first pair of capacitors (C₁and C₂) in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch (S₁/S₂) and a diode (D₁/D₂) in parallel and sharing a common central node with the first pair of capacitors.
The auxiliary resonant soft-edge pole inverter circuit may further include a first pair of auxiliary switches (S₃and S₄) connected in series with a first pair of inductors (L₁and L₂) to generate resonant current from a DC power source (E), the first pair of inductors also sharing the common central node.
The auxiliary resonant soft-edge pole inverter circuit may further include a second pair of auxiliary switches (S₅and S₆) connected in series with a second pair of capacitors (C₃and C₄). The second pair of auxiliary switches (S₅and S₆) also sharing the common central node, the circuit producing an alternating current output at the common central node.
The auxiliary resonant soft-edge pole inverter circuit may further include a second pair of diodes (D₃and D₄) connected between the second pair of auxiliary switches (S₅and S₆) and the inductors (L₁and L₂).
The auxiliary resonant soft-edge pole inverter circuit may further include a third pair of diodes (D₅and D₆) connected in parallel with the second set of auxiliary switches (S₅and S₆) and sharing the common central node.
The auxiliary resonant soft-edge pole inverter circuit may further include a fourth pair of diodes (D₇and D₉) connected between the second pair of auxiliary switches (S₃and S₄) and the DC power source (E).
The auxiliary resonant soft-edge pole inverter circuit may further include a fifth pair of diodes (D₉and D₁₀) respectively connected in series with the second pair of auxiliary switches (S3 and S4).
In various aspects and examples, the power inverter may include a plurality of capacitors comprising a first capacitor C₁, a second capacitor C₂, a third capacitor C₃, and a fourth capacitor C₄. The power inverter may further include a plurality of switches. The switches may include a first switch S₁, a second switch S₂, a third switch S₃, a fourth switch S₄, a fifth switch S₅, and a sixth switch S₆. The power inverter may include a plurality of inductors. The inductors may include a first inductor L₁and a second inductor L₂. The power inverter may further include a plurality of diodes comprising a first diode D₁and a second diode D₂.
The first switch S₁may be connected in parallel with the first capacitor C₁and the first diode D₁. The second switch S₂may be connected in parallel with a second capacitor C₂and a second diode D₂.
The third switch S₃may be connected in series with the first inductor L₁. The fourth switch S₄may be connected in series with the second inductor L₂.
The fifth switch S₅may be connected in series with the third capacitor C₃and the sixth switch S₆may be connected in series with the fourth capacitor C₄.
The first switch S₁, the second switch S₂, the first diode D₁, the second diode D₂, the first capacitor C₁, the second capacitor C₂, the first inductor L₁, the second inductor L₂, and the fifth switch S₅and the sixth switch S₆may share a common node.
In some examples, the diodes further comprise third diode D₃and fourth diode D₄. The third diode D₃may be connected between the third switch S₃and the first inductor L₁. The fourth diode D₄may be connected between the second inductor L₂and the fourth switch S₄.
In some examples, the diodes may further include a fifth diode D₅and sixth diode D₆. The fifth diode D₅may be connected in parallel with the fifth switch S₅and the sixth diode D₆may be connected in parallel with the sixth switch S₆. Further, the fifth diode D₅and the sixth diode D₆may both connect to the common node.
In some examples, the diodes may include a seventh diode D₇and an eight diode d₈. The seventh diode D₇may be connected between the fourth switch S₄and a DC power source E. The eight diode D₈may be connected between the third switch S₃and the DC power source E.
In some examples, the third switch S₃and the fourth switch S₄may include MOSFETs. In such examples, the diodes may further include a diode D₉and a diode D₁₀. The diode D₉may be connected in series with the third switch in S₃. The diode D₁₀may be connected in series with the fourth switch in S₄. Alternatively or in addition, the power inverter may include switch circuitry (identified as 602 and 604 in FIG. 6). The switch circuitry may include a series connection of a diode and a MOSFET.
The invention is inclusive of combinations of the aspects described herein. References to “a particular aspect” and the like refer to features that are present in at least one aspect of the invention. Separate references to “an aspect” (or “embodiment”) or “particular aspects” or the like do not necessarily refer to the same aspect or aspects; however, such aspects are not mutually exclusive, unless so indicated or as are readily apparent to one of skill in the art. The use of singular or plural in referring to “method” or “methods” and the like is not limiting. The word “or” is used in this disclosure in a non-exclusive sense, unless otherwise explicitly noted.
The invention has been described in detail with particular reference to certain preferred aspects thereof, but it will be understood that variations, combinations, and modifications can be effected by a person of ordinary skill in the art within the spirit and scope of the invention.

Claims

1. An auxiliary resonant soft-edge pole inverter circuit, comprising:

a first pair of capacitors in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch and a diode in parallel and sharing a common central node with the first pair of capacitors;

a first pair of auxiliary switches connected in series with a first pair of inductors, respectively, to generate resonant current from a DC power source, the first pair of inductors also sharing the common central node; and

a second pair of auxiliary switches connected in series with a second pair of capacitors, respectively, the second pair of auxiliary switches also sharing the common central node, the circuit producing an alternating current output at the common central node.

2. The circuit of claim 1, further comprising a second pair of diodes respectively connected in series with the first pair of auxiliary switches.

3. The circuit of claim 1, further comprising a second pair of diodes connected between the second pair of auxiliary switches and the inductors, respectively.

4. The circuit of claim 3, further comprising a third pair of diodes connected in parallel with the second set of auxiliary switches and sharing the common central node.

5. The circuit of claim 4, further comprising a fourth pair of diodes connected between the second pair of auxiliary switches and the DC power source.

6. The circuit of claim 1, wherein at least one of the switches comprises insulated-gate bipolar transistor.

7. The circuit of claim 1, wherein at least one of the switches comprise a metal-oxide-semiconductor field-effect transistor (MOSFET).

8. A power inverter circuit, comprising:

a plurality of capacitors comprising a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

a plurality of switches comprising a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch;

a plurality of inductors comprising a first inductor and a second inductor; and

a plurality of diodes comprising a first diode, a second diode,

wherein the first switch is connected in parallel with the first capacitor and the first diode, and the second switch is connected in parallel with a second capacitor and a second diode,

wherein the third switch is connected in series with the first inductor and the fourth switch is connected in series with the second inductor,

wherein the fifth switch is connected in series with the third capacitor and the sixth switch is connected in series with the fourth capacitor, and

wherein the first and second switch, the first and second diode, the first and second capacitor, the first and second inductor, and the fifth and sixth switch share a common node.

9. The power inverter of claim 8, wherein the third and fourth switches comprise metal-oxide-semiconductor field-effect switches (MOSFET), and the diodes further comprise third and fourth diode, the third diode connected in series with the third switch, and the fourth diode connected in series with the fourth switch.

10. The power inverter of claim 8, wherein the diodes further comprise third and fourth diode, the third diode is between the third switch and the first inductor, and the fourth diode is connected between the second inductor and the fourth switch.

11. The power inverter of claim 10, wherein the diodes further comprise a fifth and sixth diode, wherein the fifth diode is connected in parallel with the fifth switch and the sixth diode connected in parallel with the sixth switch, the fifth and sixth diode both connected to the common node.

12. The power inverter of claim 11, further comprising a seventh and eighth diode, wherein the seventh diode is connected between the fourth switch and a DC power source, and the eighth diode is connected between the third switch and the DC power source.

13. The power inverter of claim 8, wherein at least one of the switches comprises insulated-gate bipolar switches.

14. The power inverter of claim 8, wherein at least one of the switches comprise a metal-oxide-semiconductor field-effect transistor (MOSFET).