US20220045127A1

US20220045127A1 - Selector devices

Info

Publication number: US20220045127A1
Application number: US17/506,716
Authority: US
Inventors: Abhishek A. Sharma; Ravi Pillarisetty; Van H. Le; Gilbert W. Dewey; Willy Rachmady
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2017-08-29
Filing date: 2021-10-21
Publication date: 2022-02-10
Also published as: US11222921B2; WO2019045682A1; US20200185457A1

Abstract

Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation (and claims benefit of priority under 35 U.S.C. § 120) of U.S. application Ser. No. 16/635,111, filed Jan. 29, 2020, entitled “SELECTOR DEVICES,” which is a national stage application under 35 U.S.C. § 371 of PCT Application No. PCT/US2017/048988, filed Aug. 29, 2017, and entitled “SELECTOR DEVICES.” The disclosure of each prior application is considered part of and is incorporated by reference in the disclosure of this application.

BACKGROUND

A selector device is a two-terminal device exhibiting a volatile change in resistance. In an off state, a selector device may exhibit high resistance; in an on state, a selector device may exhibit low resistance.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

FIG. 1A is a perspective view of a portion of a memory array including a selector device, in accordance with various embodiments.

FIG. 1B is a schematic illustration of a memory cell of the memory array of FIG. 1A, in accordance with various embodiments.

FIG. 1C is a plot depicting example characteristic voltages of the selector device and the storage element of the memory cell of FIGS. 1A and 1B, in accordance with various embodiments.

FIG. 2 is a cross-sectional view of an example selector device, in accordance with various embodiments.

FIG. 3 is a schematic illustration of a memory device including selector devices, in accordance with various embodiments.

FIG. 4 is a flow diagram of an illustrative method of manufacturing a selector device, in accordance with various embodiments.

FIG. 5 depicts top views of a wafer and dies that may include any of the selector devices or memory cells disclosed herein.

FIG. 6 is a cross-sectional side view of a device assembly that may include any of the selector devices or memory cells disclosed herein.

FIG. 7 is a block diagram of an example computing device that may include any of the selector devices or memory cells disclosed herein, in accordance with various embodiments.

DETAILED DESCRIPTION

Disclosed herein are selector devices, and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C). As used herein, a “dopant” refers to an impurity material that is included in another material to alter the electrical properties of the other material.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The disclosure may use the singular term “layer,” but the term “layer” should be understood to refer to assemblies that may include multiple different material layers. The accompanying drawings are not necessarily drawn to scale.
FIG. 1A is a perspective view of a portion of a memory array 100 including a selector device 130, in accordance with various embodiments. The memory array 100 may be a cross-point array including memory cells 102 located at the intersections of conductive lines 104 and conductive lines 106. In some embodiments, the conductive lines 104 may be word lines and the conductive lines 106 may be bit lines, for example; for ease of discussion, this terminology may be used herein to refer to the conductive lines 104 and the conductive lines 106. In the embodiment illustrated in FIG. 1A, the word lines 104 may be parallel to each other and may be arranged perpendicularly to the bit lines 106 (which themselves may be parallel to each other), but any other suitable arrangement may be used. The word lines 104 and/or the bit lines 106 may be formed of any suitable conductive material, such as a metal (e.g., tungsten, copper, titanium, or aluminum). In some embodiments, the memory array 100 depicted in FIG. 1A may be a portion (e.g., a level) of a three-dimensional array in which other memory arrays like the memory array 100 of FIG. 1A are located at different levels (e.g., above or below the memory array 100).
Each memory cell 102 may include a storage element 120 coupled in series with an associated selector device 130. Generally, a storage element 120 may be programmed to a target data state (e.g., corresponding to a particular resistance state) by applying an electric field or energy (e.g., positive or negative voltage or current pulses) to the storage element 120 for a particular duration. In some embodiments, a storage element 120 may include a memory material 110 disposed between a pair of electrodes 108 and 112. The storage element 120 may be, for example, a resistive storage element (also referred to herein as a “resistive switch”) that, during operation, switches between two different non-volatile states: a high resistance state (HRS) and a low resistance state (LRS). The state of a resistive storage element may be used to represent a data bit (e.g., a “1” for HRS and a “0” for LRS, or vice versa). A resistive storage element may have a voltage threshold beyond which the resistive storage element is in the LRS; driving a resistive storage element into the LRS may be referred to as SET (with an associated SET threshold voltage). Similarly, a resistive storage element may have a voltage threshold beyond which the resistive storage element is in the HRS; driving a resistive storage element into the HRS may be referred to as RESET (with an associated RESET threshold voltage).
The storage element 120 may be, for example, a resistive random access memory (RRAM) device; in such embodiments, the memory material 110 may include an oxygen exchange layer (e.g., hafnium) and an oxide layer, as known in the art. The storage element 120 may be, for example, a metal filament memory device (e.g., a conductive bridging random access memory (CBRAM) device); in such embodiments, the memory material 110 may include a solid electrolyte, one of the electrodes 108 and 112 may be an electrochemically active material (e.g., silver or copper), and the other of the electrodes 108 and 112 may be an inert material (e.g., an inert metal), as known in the art. A chemical barrier layer (e.g., tantalum, tantalum nitride, or tungsten) may be disposed between the electrochemically active electrode and the solid electrolyte to mitigate diffusion of the electrochemically active material into the solid electrolyte, in some such embodiments. In some embodiments, the storage element 120 may be a phase change memory (PCM) device; in such embodiments, the memory material 110 may include a chalcogenide or other phase change memory material. In some embodiments, the storage element 120 may be a magnetoresistive random access memory (MRAM) device; in such embodiments, the electrodes 108 and 112 may be magnetic (e.g., ferromagnetic), and the memory material 110 may be a thin tunnel barrier material. As known in the art, MRAM devices may operate on the principle of tunnel magnetoresistance between two magnetic layers (the electrodes 108 and 112) separated by a tunnel junction (the memory material 110). An MRAM device may have two stable states: when the magnetic moments of the two magnetic layers are aligned parallel to each other, an MRAM device may be in the LRS, and when aligned antiparallel, an MRAM device may be in the HRS.
The selector device 130 may be a two-terminal device that may act as a bipolar switch, controlling the flow of current through the storage element 120. In some embodiments, the selector device 130 may include a selector material 114 disposed between a pair of electrodes 112 and 116. Note that, in the embodiment illustrated in FIG. 1A, the electrode 112 of the selector device 130 is “shared” with the storage element 120 in that the electrode 112 acts as an electrode for the selector device 130 and for the storage element 120. In other embodiments of the memory cell 102, the selector device 130 may not share any electrodes with the storage element 120. During manufacture of the memory cell 102, the selector device 130 may be fabricated before or after the storage element 120 is fabricated. Various embodiments of the selector device 130 are discussed in detail below.
As illustrated in the schematic view in FIG. 1B of the memory cell 102, when the selector device 130 is in a conductive (i.e., low resistance) state, the “switch” may be closed; when the selector device 130 is in a non-conductive (i.e., high resistance) state, the “switch” may be open. The state of the selector device 130 may change in response to the voltage applied across the selector device 130. FIG. 1C illustrates example electrical characteristics of an example selector device 130 and an example storage element 120 when positive voltages are applied. The I-V characteristic 140 represents behavior of an example selector device 130, and the I-V characteristic 142 represents behavior of an example storage element 120.
As illustrated in FIG. 1C, the selector device 130 may be in a high resistance state (an “off state”) when the voltage across the selector device 130 increases from zero to the threshold voltage Von. When the voltage across the selector device 130 reaches and exceeds the threshold voltage Von (and an associated on stage current Ion), the selector device 130 may enter a low resistance state (an “on state”) and may conduct current of a positive polarity. When the voltage across the selector device 130 is decreased from the threshold voltage Von, the selector device 130 may remain in the on stage until a holding voltage Vhold (and an associated holding current Ihold) is reached. When the voltage across the selector device decreases to and beyond the holding voltage Vhold, the selector device 130 may enter the off state again. In some embodiments, the selector devices 130 disclosed herein may have a threshold voltage Von between 0.4 volts and 2.5 volts, or 1 volt or less. In some embodiments, the selector devices 130 disclosed herein may have an on stage current Ion that is greater than or equal to 0.5 megaamperes per square centimeter. In some embodiments, the selector devices 130 disclosed herein may have a holding voltage Vhold between 0.1 volts and 2.5 volts (e.g., between 0.1 volts and 1 volt for embedded applications, and between 0.5 volts and 2 volts for standalone applications).
Note that the holding voltage Vhold may be less than the threshold voltage Von, as illustrated in FIG. 1C. In some embodiments, it may be desirable for the holding voltage Vhold to be approximately the same as, or close to, the threshold voltage Von. In other embodiments, it may be desirable for the holding voltage Vhold to be less than the threshold voltage Von. For example, when the holding voltage Vhold is less than the threshold voltage Von, the voltage across an “on” selector device 130 may be decreased from the threshold voltage Von and the selector device 130 may remain in the on state; this may reduce the power required to keep the selector device 130 on (e.g., during a read operation of the associated storage element 120), and thus may improve power efficiency.
As noted above, FIG. 1C also depicts an example I-V characteristic 142 for a storage element 120 (e.g., an RRAM device) with a SET threshold voltage Vset. The SET threshold voltage Vset may be greater than the threshold voltage Von for the selector device 130.
Disclosed herein are selector devices 130 having selector material 114 that may include a conductive dopant in a dielectric material. Some of these selector devices 130 may advantageously exhibit decreased threshold voltages Von relative to conventional selector devices, resulting in improved performance and decreased power consumption. A selector device 130 with a lower threshold voltage Von may be turned on and off with lower applied voltages, and thus may enable new low power applications (e.g., embedded electronics, or integrated circuits in other low power environments). Additionally, some of the selector devices 130 disclosed herein may exhibit higher on state currents Ion than conventional selector devices.
Further, some of the embodiments disclosed herein may not require the application of a large initial formation voltage, as may be required by some conventional selector devices. In particular, some conventional selector devices require the application of an initial formation voltage Vform that is larger than the threshold voltage Von when the selector device is first used; FIG. 1C includes a curve 141 illustrating an example initial formation phase. This initial formation phase (sometimes referred to as “first fire”) may “break down” the selector material 114 (e.g., by introducing some of the material of the electrodes 112 and 116 into the selector material 114, or creating regions of inhomogeneous material composition in the selector material 114) so as to allow subsequent on/off behavior as described above. Applying a large initial breakdown voltage (and associated current) to a selector device 130 may have undesirable consequences for the memory array 100; for example, overdriving the storage element 120 may result in permanent damage and/or a reduced lifetime for the storage element 120. The conductive dopants in the selector material 114 disclosed herein may provide sites at which the insulator-to-metal transition of the selector material 114 may readily occur (when the selector device 130 switches from the off state to the on state), and thus no initial formation phase may be required.
The selector devices 130 disclosed herein, and the associated memory cells 102, may take any of a number of forms. For example, FIG. 2 is a cross-sectional view of a selector device 130, in accordance with various embodiments. The selector device 130 of FIG. 2 may include an electrode 116, an electrode 112, and a selector material 114 between the electrodes 116 and 112. FIG. 2 also illustrates a getter layer 115 between the selector material 114 and the electrode 116. The getter layer 115 is optional; in some embodiments, the selector device 130 may not include a getter layer 115. Additionally, the location of the getter layer 115 in FIG. 2 is simply illustrative, and in other embodiments that include a getter layer 115, the getter layer 115 may be located between the selector material 114 and the electrode 112 (instead of between the selector material 114 and the electrode 116). In some embodiments, the getter layer 115 may be adjacent to the electrode of the selector device 130 that is at a more positive potential than the other electrode; this “more positive” electrode of the electrodes 112/116 may be referred to as the “injecting” electrode.
The electrodes 112 and 116 may be composed of any suitable material. In some embodiments, the electrodes 112 and 116 may be composed of tantalum, platinum, hafnium, cobalt, indium, iridium, copper, tungsten, ruthenium, palladium, and/or carbon. The electrodes 112 and 116 may be composed of pure forms of these elements, combinations of these elements, or combinations of these elements and other elements, in some embodiments. For example, in some embodiments, the electrode 112 and/or the electrode 116 may include a conductive nitride (e.g., tantalum nitride or titanium nitride). In some embodiments, the material compositions of the electrodes 112 and 116 may be the same, while in other embodiments, the material compositions of the electrodes 112 and 116 may be different.
In some embodiments of the selector devices 130 disclosed herein, the geometries of the electrodes 112 and 116 may be the same, or may differ. For example, the electrodes 112 and 116 may have the same or different surface areas. In some embodiments, the cross-sectional width 143 of the electrode 112, the selector material 114, and/or the electrode 116 may be between 5 nanometers and 50 nanometers.
The selector material 114 may include a dielectric material and a conductive dopant. The presence of the conductive dopant in the selector material 114 may reduce the internal bulk electric field of the selector device 130 (and thus reducing the threshold voltage Von), while also increasing the local dielectric field (and thus eliminating or mitigating the need for an initial breakdown voltage). The presence of the conductive dopant in the selector material 114 may also increase the number of carriers available in the on state of the selector material 114 (in addition to the injected carriers), increasing the on state current Ion relative to selector materials that do not include a conductive dopant. In some embodiments, a selector device 130 with the selector material 114 may replace a transistor in some memory cells, and may provide improved current sourcing relative to the limited current sourcing of some transistors.
In some embodiments, the dielectric material may include niobium, tantalum, vanadium, titanium, or hafnium. For example, the dielectric material may be an oxide material (e.g., niobium oxide, tantalum oxide, vanadium oxide, titanium oxide, or hafnium oxide) that may be capable of undergoing an insulator-to-metal transition in response to an applied voltage or resistance. For example, the dielectric material may be TaO_0.5-1.7(e.g., TaO_1.5). In some embodiments, the dielectric material may be a non-oxide material. For example, the dielectric material may be a chalcogenide material, a multi-component material including group IV or group VI elements, such as silicon and tellurium. Examples of chalcogenides that may serve as the dielectric material in the selector material 114 may include germanium silicon selenium, germanium silicon tellurium, and silicon tellurium arsenic germanium, among others.
In some embodiments, the conductive dopant of the selector material 114 may include carbon, platinum, silver, gold, tantalum, copper, cobalt, or tungsten. The selector material 114 may be composed of pure forms of these materials, combinations of these materials, or combinations of these materials and other elements, in some embodiments. In some embodiments, the conductive dopant may be a material having an ion migration velocity that is less than the ion migration velocity of the dielectric material. For example, in some embodiments, the ion migration velocity of the dielectric material may be greater than the ion migration velocity of the conductive dopant by a factor of 10 or more. In some embodiments, the conductive dopant may be a material having a work function that is less than 4.5 electron volts (e.g., tantalum, titanium, or carbon).
The threshold voltage Von of the selector device 130 may be based at least in part on the amount of conductive dopant in the selector material 114. In particular, greater concentrations of the conductive dopant may result in lower threshold voltages Von. The amount of conductive dopant in the selector material 114 may be selected to achieve a desired threshold voltage Von and/or other desired characteristics. In some embodiments, the conductive dopant may be present in the selector material 114 at a concentration between 0.0001 atomic-percent and 10 atomic-percent (e.g., between 0.001 atomic-percent and 10 atomic-percent).
As noted above, some selector devices 130 may include a getter layer 115 between the selector material 114 and one of the electrodes 112/116. In some embodiments, the getter layer 115 may include tantalum (e.g., tantalum nitride), titanium (e.g., titanium nitride), or chromium. In some embodiments, no getter layer 115 may be included.
The thicknesses of the materials included in the selector device 130 of FIG. 2 may take any suitable values. For example, in some embodiments, the electrode 112 may have a thickness 132 between 1 nanometer and 100 nanometers, the selector material 114 may have a thickness 134 between 2 nanometers and 80 nanometers, the getter layer 115 may have a thickness 135 between 0.5 nanometers and 2 nanometers, and the electrode 116 may have a thickness 136 between 1 nanometer and 100 nanometers.
A memory array 100 including a selector device 130 may be controlled in any suitable manner. For example, FIG. 3 is a schematic illustration of a memory device 200 including a memory array 100 having memory cells 102 with storage elements 120 and selector devices 130, in accordance with various embodiments. As discussed above, each memory cell 102 may include a storage element 120 connected in series with any of the embodiments of the selector devices 130 disclosed herein. The memory device 200 of FIG. 3 may be a bidirectional cross-point array in which each column is associated with a bit line 106 driven by column select circuitry 210. Each row may be associated with a word line 104 driven by row select circuitry 206. During operation, read/write control circuitry 208 may receive memory access requests (e.g., from one or more processing devices or communication chips of a computing device, such as the computing device 2000 discussed below), and may respond by generating an appropriate control signal (e.g., read, write 0, or write 1), as known in the art. The read/write control circuitry 208 may control the row select circuitry 206 and the column select circuitry 210 to select the desired memory cell(s) 102. Voltage supplies 204 and 212 may be controlled to provide the voltage(s) necessary to bias the memory array 100 to facilitate the requested action on one or more memory cells 102. Row select circuitry 206 and column select circuitry 210 may apply appropriate voltages across the memory array 100 to access the selected memory cells 102 (e.g., by providing appropriate voltages to the memory cells 102 to allow the desired selector devices 130 to conduct). Row select circuitry 206, column select circuitry 210, and read/write control circuitry 208 may be implemented using any devices and techniques known in the art.
Any suitable techniques may be used to manufacture the selector devices 130 and memory cells 102 disclosed herein. FIG. 4 is a flow diagram of an illustrative method 1000 of manufacturing a selector device, in accordance with various embodiments. Although the operations discussed below with reference to the method 1000 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 1000 may be illustrated with reference to one or more of the embodiments discussed above, but the method 1000 may be used to manufacture any suitable selector device (including any suitable ones of the embodiments disclosed herein).
At 1002, a first electrode may be formed (e.g., by physical vapor deposition (PVD), such as sputtering). For example, the electrode 112 may be formed on memory material 110 of a storage element 120. The first electrode may take any of the forms disclosed herein.
At 1004, a selector material may be formed on the first electrode. The selector material may include a dielectric material and a conductive dopant. For example, the selector material 114 may be formed on the electrode 112. The selector material may take any of the forms disclosed herein.
Any suitable technique may be used to form the selector material at 1004. In some embodiments, a PVD technique may be used to form the selector material. For example, the conductive dopant and the dielectric material of the selector material may be co-sputtered onto the first electrode. In another example, the conductive dopant and the dielectric material of the selector material may be formed on the first electrode by reactive sputtering. In another example, the conductive dopant and the dielectric material of the selector material may be formed by sputtering with an alloy target (e.g., to form hafnium oxide doped with tantalum). In some embodiments, an atomic layer deposition (ALD) technique may be used to form the selector material. For example, one or more cycles of ALD of the dielectric material may be performed, then one or more cycles of ALD of the conductive dopant may be performed, and this process repeated as desired. The PVD or ALD technique may be followed by an annealing operation.
At 1006, a second electrode may be formed on the selector material. For example, the electrode 116 may be formed on the selector material 114. The second electrode may take any of the forms disclosed herein.
The selector devices 130 and memory cells 102 disclosed herein may be included in any suitable electronic device. FIG. 5 depicts top views of a wafer 450 and dies 452 that may be formed from the wafer 450; the dies 452 may include any of the selector devices 130 or memory cells 102 disclosed herein. The wafer 450 may include semiconductor material and may include one or more dies 452 having integrated circuit elements (e.g., selector devices 130 and storage elements 120) formed on a surface of the wafer 450. Each of the dies 452 may be a repeating unit of a semiconductor product that includes any suitable device (e.g., the memory device 200). After the fabrication of the semiconductor product is complete, the wafer 450 may undergo a singulation process in which the dies 452 are separated from one another to provide discrete “chips” of the semiconductor product. A die 452 may include one or more selector devices 130 or memory cells 102 and/or supporting circuitry to route electrical signals to the selector devices 130 or memory cells 102 (e.g., interconnects including conductive lines 104 and 106), as well as any other integrated circuit (IC) components. In some embodiments, the wafer 450 or the die 452 may include other memory devices, logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 452. For example, a memory device formed by multiple memory arrays (e.g., multiple memory arrays 100) may be formed on a same die 452 as a processing device (e.g., the processing device 2002 of FIG. 7) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
FIG. 6 is a cross-sectional side view of a device assembly 400 that may include any of the selector devices 130 or memory cells 102 disclosed herein in one or more packages. A “package” may refer to an electronic component that includes one or more IC devices that are structured for coupling to other components; for example, a package may include a die coupled to a package substrate that provides electrical routing and mechanical stability to the die. The device assembly 400 includes a number of components disposed on a circuit board 402. The device assembly 400 may include components disposed on a first face 440 of the circuit board 402 and an opposing second face 442 of the circuit board 402; generally, components may be disposed on one or both faces 440 and 442.
In some embodiments, the circuit board 402 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 402. In other embodiments, the circuit board 402 may be a package substrate or flexible board.
The device assembly 400 illustrated in FIG. 6 includes a package-on-interposer structure 436 coupled to the first face 440 of the circuit board 402 by coupling components 416. The coupling components 416 may electrically and mechanically couple the package-on-interposer structure 436 to the circuit board 402, and may include solder balls, male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
The package-on-interposer structure 436 may include a package 420 coupled to an interposer 404 by coupling components 418. The coupling components 418 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 416. Although a single package 420 is shown in FIG. 6, multiple packages may be coupled to the interposer 404; indeed, additional interposers may be coupled to the interposer 404. The interposer 404 may provide an intervening substrate used to bridge the circuit board 402 and the package 420. The package 420 may include one or more selector devices 130 or memory cells 102, for example. Generally, the interposer 404 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 404 may couple the package 420 (e.g., a die) to a ball grid array (BGA) of the coupling components 416 for coupling to the circuit board 402. In the embodiment illustrated in FIG. 6, the package 420 and the circuit board 402 are attached to opposing sides of the interposer 404; in other embodiments, the package 420 and the circuit board 402 may be attached to a same side of the interposer 404. In some embodiments, three or more components may be interconnected by way of the interposer 404.
The interposer 404 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 404 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 404 may include metal interconnects 408 and vias 410, including but not limited to through-silicon vias (TSVs) 406. The interposer 404 may further include embedded devices 414, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices (e.g., the selector devices 130 or memory cells 102). More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 404. The package-on-interposer structure 436 may take the form of any of the package-on-interposer structures known in the art.
The device assembly 400 may include a package 424 coupled to the first face 440 of the circuit board 402 by coupling components 422. The coupling components 422 may take the form of any of the embodiments discussed above with reference to the coupling components 416, and the package 424 may take the form of any of the embodiments discussed above with reference to the package 420. The package 424 may include one or more selector devices 130 or memory cells 102, for example.
The device assembly 400 illustrated in FIG. 6 includes a package-on-package structure 434 coupled to the second face 442 of the circuit board 402 by coupling components 428. The package-on-package structure 434 may include a package 426 and a package 432 coupled together by coupling components 430 such that the package 426 is disposed between the circuit board 402 and the package 432. The coupling components 428 and 430 may take the form of any of the embodiments of the coupling components 416 discussed above, and the packages 426 and 432 may take the form of any of the embodiments of the package 420 discussed above. Each of the packages 426 and 432 may include one or more selector devices 130 or memory cells 102, for example.
FIG. 7 is a block diagram of an example computing device 2000 that may include any of the selector devices 130 or memory cells 102 disclosed herein. A number of components are illustrated in FIG. 7 as included in the computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 2000 may be attached to one or more PCBs (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the computing device 2000 may not include one or more of the components illustrated in FIG. 7, but the computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the computing device 2000 may not include an audio input device 2024 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2024 or audio output device 2008 may be coupled.
The computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may interface with one or more of the other components of the computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner. The processing device 2002 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
The computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. The memory 2004 may include one or more selector devices 130 or memory cells 102 or memory arrays 100 or memory devices 200, as disclosed herein. In some embodiments, the memory 2004 may include memory that shares a die with the processing device 2002. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, the computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the computing device 2000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.
The computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2000 to an energy source separate from the computing device 2000 (e.g., AC line power).
The computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above). The audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The computing device 2000 may include a GPS device 2018 (or corresponding interface circuitry, as discussed above). The GPS device 2018 may be in communication with a satellite-based system and may receive a location of the computing device 2000, as known in the art.
The computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 is a selector device, including: a first electrode; a second electrode; and a selector material between the first electrode and the second electrode, wherein the selector material includes a dielectric material and a conductive dopant.
Example 2 may include the subject matter of Example 1, and may further specify that the dielectric material includes hafnium, tantalum, niobium, vanadium, or titanium.
Example 3 may include the subject matter of Example 2, and may further specify that the dielectric material is an oxide.
Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the dielectric material includes a chalcogenide.
Example 5 may include the subject matter of any of Examples 1-4, and may further specify that the conductive dopant includes platinum, silver, gold, tantalum, copper, cobalt, tungsten, ruthenium, palladium, or carbon.
Example 6 may include the subject matter of any of Examples 1-5, and may further specify that the conductive dopant has a work function less than 4.5 electron volts.
Example 7 may include the subject matter of any of Examples 1-6, and may further specify that the conductive dopant has a first ion migration velocity, the dielectric material has a second ion migration velocity, and the second ion migration velocity is greater than the first ion migration velocity by a factor of at least 10.
Example 8 may include the subject matter of any of Examples 1-7, and may further specify that the conductive dopant is present in the selector material at a concentration between 0.0001 atomic-percent and 10 atomic-percent.
Example 9 may include the subject matter of any of Examples 1-8, and may further specify that the selector device has a threshold voltage between 0.4 volts and 2.5 volts.
Example 10 may include the subject matter of any of Examples 1-9, and may further specify that the selector device has a holding voltage between 0.1 volts and 2.5 volts.
Example 11 may include the subject matter of Example 10, and may further specify that the holding voltage is between 0.1 volts and 1 volt.
Example 12 may include the subject matter of Example 10, and may further specify that the holding voltage is between 0.5 volts and 2 volts.
Example 13 may include the subject matter of any of Examples 1-12, and may further specify that the selector device has an on current that is at least 0.5 megaamperes per square centimeter.
Example 14 may include the subject matter of any of Examples 1-13, and may further specify that the selector material has a thickness between 2 nanometers and 80 nanometers.
Example 15 may include the subject matter of any of Examples 1-14, and may further specify that the first electrode or the second electrode includes tantalum, platinum, hafnium, cobalt, indium, iridium, copper, or tungsten.
Example 16 is a memory cell, including: a storage element; and a selector device coupled to the storage element, wherein the selector device includes a selector material, and the selector material includes a dielectric material and a conductive dopant.
Example 17 may include the subject matter of Example 16, and may further specify that the selector device includes a first electrode and a second electrode, the selector material is between the first electrode and the second electrode, and the first electrode or the second electrode is also an electrode of the storage element.
Example 18 may include the subject matter of any of Examples 16-17, and may further specify that the selector device includes a first electrode and a second electrode, the selector material is between the first electrode and the second electrode, and the selector device further includes a getter layer between the first electrode and the selector material.
Example 19 may include the subject matter of Example 18, and may further specify that the getter layer includes tantalum, titanium, or chromium.
Example 20 may include the subject matter of any of Examples 16-19, and may further specify that the storage element is a resistive random access memory (RRAM) device, a phase change memory (PCM) device, a metal filament memory device, or a magnetoresistive random access memory (MRAM) device.
Example 21 may include the subject matter of any of Examples 16-20, and may further specify that the memory cell includes a first terminal coupled to a bit line, and the memory cell includes a second terminal coupled to a word line.
Example 22 is a method of manufacturing a selector device, including: forming a first electrode; forming a selector material on the first electrode, wherein the selector material includes a dielectric material and a conductive dopant; and forming a second electrode on the selector material.
Example 23 may include the subject matter of Example 22, and may further specify that forming the selector material includes physical vapor deposition of the dielectric material and the conductive dopant.
Example 24 may include the subject matter of any of Examples 22-23, and may further specify that forming the selector material includes reactive sputtering of the dielectric material and the conductive dopant.
Example 25 may include the subject matter of Example 23, and may further specify that forming the selector material includes atomic layer deposition of the dielectric material and the conductive dopant.
Example 26 may include the subject matter of any of Examples 22-25, and may further include forming a storage element in series with the selector device.
Example 27 may include the subject matter of Example 26, and may further specify that the first electrode is shared with the storage element.
Example 28 may include the subject matter of Example 26, and may further specify that the second electrode is shared with the storage element.
Example 29 is a computing device, including: a circuit board; a processing device coupled to the circuit board; and a memory array coupled to the processing device, wherein the memory array includes a memory cell having a storage element coupled in series with a selector device, the selector device includes a selector material, and the selector material includes a dielectric material and a conductive dopant.
Example 30 may include the subject matter of Example 29, and may further include a wireless communications device coupled to the circuit board.
Example 31 may include the subject matter of any of Examples 29-30, and may further specify that the storage element includes a resistive switch.
Example 32 may include the subject matter of any of Examples 29-31, and may further specify that the storage element includes a resistive random access memory (RRAM) device, a phase change memory (PCM) device, a metal filament memory device, or a magnetoresistive random access memory (MRAM) device.

Claims

1. A selector device, comprising:

a first electrode;

a second electrode; and

a selector material between the first electrode and the second electrode, wherein the selector material comprises a dielectric material and a conductive dopant, wherein the dielectric material comprises a chalcogenide.

2. The selector device of claim 1, wherein the chalcogenide comprises at least one of silicon and tellurium.

3. The selector device of claim 2, wherein the chalcogenide comprises germanium.

4. The selector device of claim 1, wherein the chalcogenide comprises a group IV or group VI element.

5. The selector device of claim 1, wherein the conductive dopant includes platinum, silver, gold, tantalum, copper, cobalt, tungsten, ruthenium, palladium, or carbon.

6. The selector device of claim 1, wherein the conductive dopant has a work function less than 4.5 electron volts.

7. The selector device of claim 1, wherein the conductive dopant has a first ion migration velocity, the dielectric material has a second ion migration velocity, and the second ion migration velocity is greater than the first ion migration velocity by a factor of at least 10.

8. The selector device of claim 1, wherein the selector device has a threshold voltage between 0.4 volts and 2.5 volts, and the selector device has a holding voltage between 0.1 volts and 2.5 volts.

9. The selector device of claim 1, further comprising a getter layer between the first electrode and the selector material.

10. A memory cell, comprising:

a storage element; and

a selector device coupled to the storage element, wherein the selector device comprises a selector material, the selector material comprises a dielectric material and a conductive dopant, and the dielectric material comprises a chalcogenide.

11. The memory cell of claim 10, wherein the selector device comprises a first electrode and a second electrode, the selector material is between the first electrode and the second electrode, and the first electrode or the second electrode is also an electrode of the storage element.

12. The memory cell of claim 10, wherein the selector device comprises a first electrode and a second electrode, the selector material is between the first electrode and the second electrode, and the selector device further comprises a getter layer between the first electrode and the selector material.

13. The memory cell of claim 12, wherein the getter layer comprises at least one of tantalum, titanium, and chromium.

14. The memory cell of claim 10, wherein the storage element is a resistive random access memory (RRAM) device, a phase change memory (PCM) device, a metal filament memory device, or a magnetoresistive random access memory (MRAM) device.

15. The memory cell of claim 10, wherein the chalcogenide comprises at least one of silicon and tellurium.

16. The memory cell of claim 15, wherein the chalcogenide comprises germanium.

17. A computing device, comprising:

a circuit board;

a processing device coupled to the circuit board; and

a memory array coupled to the processing device, wherein the memory array comprises a memory cell having a storage element coupled in series with a selector device, the selector device comprises a selector material, the selector material comprises a dielectric material and a conductive dopant, and the dielectric material comprises a chalcogenide.

18. The computing device of claim 17, further comprising a wireless communications device coupled to the circuit board.

19. The computing device of claim 17, wherein the storage element includes a resistive switch.

20. The computing device of claim 17, wherein the chalcogenide comprises at least one of silicon, tellurium, and germanium.