US20220020627A1 - Processing tape and method of fabricating a semiconductor device using the same - Google Patents

Processing tape and method of fabricating a semiconductor device using the same Download PDF

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Publication number
US20220020627A1
US20220020627A1 US17/191,163 US202117191163A US2022020627A1 US 20220020627 A1 US20220020627 A1 US 20220020627A1 US 202117191163 A US202117191163 A US 202117191163A US 2022020627 A1 US2022020627 A1 US 2022020627A1
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layer
release
release film
release layer
carbon atoms
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US17/191,163
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US12040213B2 (en
Inventor
Hwail Jin
Seon Ho Lee
Yeongseok Kim
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JIN, HWAIL, KIM, YEONGSEOK, LEE, SEON HO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
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    • C09J7/00—Adhesives in the form of films or foils
    • C09J7/20—Adhesives in the form of films or foils characterised by their carriers
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G77/00—Macromolecular compounds obtained by reactions forming a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon in the main chain of the macromolecule
    • C08G77/04—Polysiloxanes
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G77/00—Macromolecular compounds obtained by reactions forming a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon in the main chain of the macromolecule
    • C08G77/04—Polysiloxanes
    • C08G77/20—Polysiloxanes containing silicon bound to unsaturated aliphatic groups
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08J—WORKING-UP; GENERAL PROCESSES OF COMPOUNDING; AFTER-TREATMENT NOT COVERED BY SUBCLASSES C08B, C08C, C08F, C08G or C08H
    • C08J7/00—Chemical treatment or coating of shaped articles made of macromolecular substances
    • C08J7/04—Coating
    • C08J7/042—Coating with two or more layers, where at least one layer of a composition contains a polymer binder
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    • C09J133/00—Adhesives based on homopolymers or copolymers of compounds having one or more unsaturated aliphatic radicals, each having only one carbon-to-carbon double bond, and at least one being terminated by only one carboxyl radical, or of salts, anhydrides, esters, amides, imides, or nitriles thereof; Adhesives based on derivatives of such polymers
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    • C09J7/381—Pressure-sensitive adhesives [PSA] based on macromolecular compounds obtained by reactions involving only carbon-to-carbon unsaturated bonds
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • C09J2203/00—Applications of adhesives in processes or use of adhesives in the form of films or foils
    • C09J2203/326—Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/14—Layer or component removable to expose adhesive
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/14—Layer or component removable to expose adhesive
    • Y10T428/1452—Polymer derived only from ethylenically unsaturated monomer
    • Y10T428/1457—Silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/14—Layer or component removable to expose adhesive
    • Y10T428/1476—Release layer

Definitions

  • the present disclosure relates to a processing tape, and in particular, to a processing tape which is used in a process of fabricating a semiconductor device.
  • the electronic product includes a semiconductor device, which is fabricated using a wafer-level substrate. A plurality of semiconductor chips are formed by dicing the substrate. A processing tape, such as a dicing tape, is used in the process of dicing the substrate.
  • An embodiment of the inventive concept provides a processing tape with improved adhesive strength and a method of fabricating a semiconductor device using the same.
  • An embodiment of the inventive concept provides a processing tape with improved releasing property and a method of fabricating a semiconductor device using the same.
  • a processing tape may include a base layer, an adhesive layer disposed on the base layer, a protection release film on the adhesive layer, and a first release layer interposed between the adhesive layer and the protection release film.
  • the first release layer may include a silicone-based material and may be non-photo-curable.
  • a method of fabricating a semiconductor device may include preparing a processing tape including an adhesive layer, a first release layer, and a protection release film stacked on a base layer, removing the protection release film while leaving at least a portion of the first release layer, which is used as a first release film, on the adhesive layer, attaching a substrate structure to the first release film, performing a processing process on the substrate structure to form a processed substrate structure, and detaching the processed substrate structure from the first release film.
  • the first release film may be non-photo-curable.
  • a processing tape may include a base layer including a polymer, a pressure sensing adhesive layer disposed on the base layer, a protection release film on the pressure sensing adhesive layer, a first release layer interposed between the pressure sensing adhesive layer and the protection release film, and a second release layer interposed between the first release layer and the protection release film, the second release layer including silicone acrylate.
  • the first release layer may be non-photo-curable, and the pressure sensing adhesive layer may include a photo-curable material.
  • the first release layer may be 0.01 phr to 30 phr of the pressure sensing adhesive layer, and a thickness of the first release layer ranges from 0.01 ⁇ m to 10 ⁇ m.
  • the first release layer may include a material represented by chemical formula 1.
  • R 1 and R 2 may each independently include one selected from a hydrogen, an alkyl group having 1 to 5 carbon atoms, an alkyl substituted silyl group having 1 to 5 carbon atoms, —NH 2 , an amino alkyl group having 1 to 5 carbon atoms, an alkyl amino group having 1 to 5 carbon atoms, a hydroxyl group (—OH), a hydroxy alkyl group having 1 to 5 carbon atoms, an isocyanate group (NCO), an alkyl group having 1 to 5 carbon atoms substituted with isocyanate, R 3 each independently includes one selected from an alkyl group having 1 to 3 carbon atoms and an alkyl group having 1 to 5 carbon atoms substituted with epoxy group, and n is from 1 to 410.
  • FIG. 1 is a sectional view illustrating a processing tape according to an embodiment of the inventive concept.
  • FIG. 2 is a sectional view illustrating a processing tape according to an embodiment of the inventive concept.
  • FIGS. 3A to 3C are sectional views illustrating a method of fabricating a processing tape, according to an embodiment of the inventive concept.
  • FIGS. 4A to 4F are sectional views illustrating a method of fabricating a semiconductor device, using a processing tape according to an embodiment of the inventive concept.
  • FIG. 5A is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • FIG. 5B is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept
  • FIG. 1 is a sectional view illustrating a processing tape according to an embodiment of the inventive concept.
  • a processing tape 10 may include a base layer 110 , an adhesive layer 120 , a first release layer 130 , a second release layer 140 , and a protection release film 150 .
  • the processing tape 10 may be a dicing tape.
  • the processing tape 10 may be used in a process of dicing a wafer-level substrate.
  • the base layer 110 may include at least one of organic materials (e.g., polymeric materials).
  • the base layer 110 may include at least one of poly ethyleneterephthalate (PET), poly olefin (PO), poly (vinyl alcohol) (PVA), poly(l-naphthylamine) (PNA), poly ether ketone (PEEK), and/or mixtures thereof.
  • the base layer 110 may include homopolymers or blend polymers.
  • the base layer 110 may be a single layer or a multiple layer.
  • the adhesive layer 120 may be disposed on the base layer 110 .
  • the adhesive layer 120 may be, for example, a pressure sensitive adhesive (PSA) layer.
  • PSA pressure sensitive adhesive
  • the adhesive layer 120 may contain a photo-curable material which is in an uncured state.
  • the photo-curable material may contain polymer, which contains an alkyne group and an alcohol (—OH) group.
  • the adhesive layer 120 may include an acrylate-based material (e.g., acrylate polymer).
  • the adhesive layer 120 may further include at least one of a cross-linking agent, a photocuring agent, or an additive agent.
  • the additive agent may further include at least one of a UV absorbing agent and a coating leveling agent.
  • the UV absorbing agent may be formed of or include a material having an aromatic ring or a conjugate structure.
  • the UV absorbing agent may include benzophenone and/or derivatives thereof.
  • the coating leveling agent may include a silicone-based surfactant.
  • a thickness T 1 of the adhesive layer 120 may range from 5 ⁇ m to 50 ⁇ m.
  • the first release layer 130 may be disposed on the adhesive layer 120 .
  • the first release layer 130 may be interposed between the adhesive layer 120 and the protection release film 150 .
  • the first release layer 130 may be in direct or physical contact with the adhesive layer 120 .
  • the first release layer 130 may be attached to the base layer 110 by the adhesive layer 120 .
  • the first release layer 130 may include a non-photosensitive material.
  • the non-photosensitive material may mean a material that is not cured by light.
  • the first release layer 130 may include a non-photo-curable material.
  • the non-photo-curable material may have unintentional or negligible changes under UV light.
  • the non-photo-curable material may have substantially no cross linking occur under UV light.
  • the molecular weight of the non-photo-curable material may undergo substantially no change when exposed to light, or the molecular weight of the non-photo-curable material may change less than 1% under UV light.
  • the first release layer 130 may include a thermosetting material or a non-reactive material.
  • the non-reactive property may mean a non-thermosetting property, a non-photo-curable property, and a chemically non-reactive property.
  • the chemically non-reactive property may mean that the material does not participate in chemical reaction with other materials.
  • the first release layer 130 may include a silicone-based material.
  • the first release layer 130 may include a silicone-based material represented by the following chemical formula 1.
  • a weight average molecular weight (Mw) of the silicone-based material may range from 100 g/mol to 30,000 g/mol.
  • R 1 and R 2 may each independently include one selected from a hydrogen, an alkyl group having 1 to 5 carbon atoms, an alkyl substituted silyl group having 1 to 5 carbon atoms, —NH 2 , an amino alkyl group having 1 to 5 carbon atoms, an alkyl amino group having 1 to 5 carbon atoms, a hydroxyl group (—OH), a hydroxy alkyl group having 1 to 5 carbon atoms, an isocyanate group (NCO), an alkyl group having 1 to 5 carbon atoms substituted with isocyanate, R 3 may each independently include one selected from an alkyl group having 1 to 3 carbon atoms (e.g. a methyl, ethyl or propyl group) and an alkyl group having 1 to 5 carbon atoms substituted with epoxy group, and n is from 1 to 410.
  • R 3 may each independently include one selected from an alkyl group having 1 to 3 carbon atoms (e.g. a methyl, ethy
  • the first release layer 130 may exhibit a non-reactive property, and in the chemical formula 1, R 1 and R 2 may be each independently a hydrogen, an alkyl group having 1 to 5 carbon atoms, or an alkyl substituted silyl group having 1 to 5 carbon atoms.
  • the first release layer 130 may exhibit a thermosetting property, and in the chemical formula 1, R 1 and R 2 may each independently include any one selected from —NH 2 , an amino alkyl group having 1 to 5 carbon atoms, an alkyl amino group having 1 to 5 carbon atoms, —OH, a hydroxy alkyl group having 1 to 5 carbon atoms, an isocyanate group (NCO), an alkyl group having 1 to 5 carbon atoms substituted with isocyanate, and an alkyl group having 1 to 5 carbon atoms substituted with epoxy group.
  • the first release layer 130 may have a thermosetting property and may be chemically bonded with the adhesive layer 120 . A chemical bond may be provided between a bottom surface of the first release layer 130 and a top surface of the adhesive layer 120 . In this case, the first release layer 130 may be more strongly fastened to the adhesive layer 120 .
  • the first release layer 130 may be 0.01 phr (parts per hundred rubber) to 30 phr of the adhesive layer 120 .
  • a thickness T 2 of the first release layer 130 may range from 0.01 ⁇ m to 10 ⁇ m.
  • the first release layer 130 may have a hydrophobic property.
  • the second release layer 140 may be disposed on the first release layer 130 .
  • the second release layer 140 may be interposed between the first release layer 130 and the protection release film 150 .
  • the second release layer 140 may include a different material from the first release layer 130 and may have physical and chemical characteristics different from the first release layer 130 .
  • the second release layer 140 may include a photo-curable material.
  • the second release layer 140 may be in a photo-cured state.
  • the second release layer 140 may include a silicone acrylate-based material.
  • the second release layer 140 may include a material, which is represented by the following chemical formula 2, and/or derivatives thereof.
  • a weight average molecular weight of the material represented by the chemical formula 2 may range from 100 g/mol to 30,000 g/mol.
  • the material represented by the chemical formula 2 may be silicone acrylate.
  • R 4 each independently includes one selected from an alkyl group having 1 to 3 carbon atom (e.g. a methyl, ethyl or propyl group), and m is from 0 to 520.
  • the second release layer 140 may be 0.00001 phr to 30 phr of the adhesive layer 120 .
  • the protection release film 150 may be disposed on the second release layer 140 .
  • the protection release film 150 may include an organic material (e.g., polymer).
  • the protection release film 150 may be formed of or include at least one of poly ethyleneterephthalate (PET), poly olefin (PO), poly (vinyl alcohol) (PVA), poly(l-naphthylamine) (PNA), poly ether ketone (PEEK), and/or mixtures thereof.
  • PET poly ethyleneterephthalate
  • PO poly olefin
  • PVA poly (vinyl alcohol)
  • PNA poly(l-naphthylamine)
  • PEEK poly ether ketone
  • the protection release film 150 may protect the second release layer 140 , the first release layer 130 , or the adhesive layer 120 from a physical stress.
  • the physical stress may be an external impact but is not limited thereto.
  • the protection release film 150 may be removed before using the processing tape 10 . An example, in which the
  • FIG. 2 is a sectional view illustrating a processing tape according to an embodiment of the inventive concept.
  • a previously described element may be identified by the same reference number without repeating an overlapping description thereof.
  • the processing tape 10 A may be a dicing tape.
  • the processing tape 10 may include the base layer 110 , the adhesive layer 120 , the first release layer 130 , and the protection release film 150 .
  • the base layer 110 , the adhesive layer 120 , the first release layer 130 , and the protection release film 150 may be substantially the same as those described with reference to FIG. 1 .
  • the thickness T 1 of the adhesive layer 120 and the thickness T 2 of the first release layer 130 may be the same as those described with reference to FIG. 1 .
  • the processing tape 10 may not include the second release layer 140 of FIG. 1 and the first release layer 130 may be in direct or physical contact with the adhesive layer 120 and the protection release film 150 .
  • the layers illustrated in FIGS. 1 and 2 may be directly provided adjacent each other as illustrated, or one or more intervening layers (to aid with strength, adhesion, separation etc) may also be provided between the illustrated layers.
  • FIGS. 3A to 3C are sectional views illustrating a method of fabricating a processing tape, according to an embodiment of the inventive concept.
  • a previously described element may be identified by the same reference number without repeating an overlapping description thereof.
  • the second release layer 140 may be formed on the protection release film 150 .
  • the formation of the second release layer 140 may include coating a photo-curable material on the protection release film 150 .
  • the photo-curable material may include a silicone acrylate-based material.
  • the formation of the second release layer 140 may further include irradiating light to the coated layer.
  • the light may be an ultraviolet (UV) light.
  • the second release layer 140 may be photo-cured by the irradiation of the light.
  • the second release layer 140 may include a photo-cured silicone acrylate-based material.
  • the photo curing may mean an ultraviolet light (UV) curing.
  • the first release layer 130 may be formed on the second release layer 140 .
  • the first release layer 130 may be formed by coating the material, which is represented by the chemical formula 1, on the second release layer 140 .
  • the first release layer 130 may be coated on the second release layer 140 , before the irradiation of the light described with reference to FIG. 3A . Thereafter, the light may be irradiated to the first release layer 130 . As a result of the irradiation of the light, the second release layer 140 may be photo-cured. Since the first release layer 130 includes a non-photo-curable material, the first release layer 130 may not be affected by the light. For example, the first release layer 130 may not be photo-cured.
  • the base layer 110 and the adhesive layer 120 may be prepared.
  • the adhesive layer 120 may be provided on the base layer 110 .
  • a photo-curable acrylate-based polymer may be coated on the base layer 110 to form the adhesive layer 120 .
  • the protection release film 150 , the second release layer 140 , and the first release layer 130 which are formed by the method of FIGS. 3A and 3B , may be prepared.
  • the structure including the protection release film 150 , the second release layer 140 , and the first release layer 130 may be inverted and then may be placed on the adhesive layer 120 such that the first release layer 130 faces the adhesive layer 120 .
  • the first release layer 130 may be attached to the adhesive layer 120 such that the first release layer 130 is in physical contact with the adhesive layer 120 .
  • the attaching of the first release layer 130 may be performed by a laminating process.
  • the processing tape 10 may be fabricated by the afore-described process.
  • the protection release film 150 and the second release layer 140 may be prepared, and then the first release layer 130 may be coated not on the second release layer 140 but on the adhesive layer 120 .
  • the second release layer 140 may be disposed on the first release layer 130 such that the second release layer 140 and the first release layer 130 are spaced apart from each other and face each other.
  • the processing tape 10 may be formed by attaching the second release layer 140 to the first release layer 130 through a laminating process.
  • the process of forming the second release layer 140 may be omitted.
  • the first release layer 130 may be directly coated on the protection release film 150 or the adhesive layer 120 .
  • a stacking process may be performed to form the base layer 110 , the adhesive layer 120 , the first release layer 130 , and the protection release film 150 , which are sequentially stacked.
  • the first release layer 130 may be in contact with the adhesive layer 120 and the protection release film 150 .
  • the processing tape 10 A may be fabricated to have the structure of FIG. 2 .
  • FIGS. 4A to 4F are sectional views illustrating a method of fabricating a semiconductor device, using a processing tape according to an embodiment of the inventive concept.
  • a previously described element may be identified by the same reference number without repeating an overlapping description thereof.
  • the processing tape 10 may be prepared.
  • the processing tape 10 may be substantially the same as that described with reference to FIG. 1 .
  • the processing tape 10 may include the base layer 110 , the adhesive layer 120 , the first release layer 130 , the second release layer 140 , and the protection release film 150 .
  • the second release layer 140 may be omitted and the first release layer 130 may be in direct contact with the adhesive layer 120 and the protection release film 150 .
  • the protection release film 150 may be removed.
  • the second release layer 140 may also be removed, along with the protection release film 150 .
  • the removal of the protection release film 150 and the second release layer 140 may be achieved by a physical method or a mechanical method.
  • the removal of the protection release film 150 may be performed by a user or by a machine operated by a user, and the protection release film 150 may prevent the second release layer 140 , the first release layer 130 , or the adhesive layer 120 from being damaged during a process of transferring and storing the processing tape 10 .
  • the first release film 130 ′ left on the adhesive layer 120 may be 10 wt % to 50 wt % of the first release layer 130 prior to removing the protection release film 150 .
  • the remaining portion of the first release layer 130 may be removed along with the second release layer 140 .
  • a processing release tape 11 may be formed.
  • the processing release tape 11 may include the base layer 110 , the adhesive layer 120 , and the first release film 130 ′.
  • a magnitude of the interaction may be represented as an adhesive strength or a bonding strength.
  • the second release layer 140 may be interposed between the first release layer 130 and the protection release film 150 .
  • An adhesive strength between the second release layer 140 and the first release layer 130 may be relatively weak. Accordingly, at least a portion of the first release layer 130 (i.e., the first release film 130 ′) may be left on the adhesive layer 120 , after the removal of the protection release film 150 and the second release layer 140 .
  • the second release layer 140 may not be provided, as shown in the processing tape 10 A of FIG. 2 .
  • a substrate may be prepared.
  • the substrate may be a substrate structure 20 .
  • the substrate structure 20 may include a semiconductor substrate 210 , a circuit layer 220 , and penetration structures 230 .
  • the substrate structure 20 may further include solder bumps 240 .
  • the substrate structure 20 may have a first surface 20 a and a second surface 20 b , which are opposite to each other.
  • the first surface 20 a of the substrate structure 20 may correspond to a top surface of the circuit layer 220
  • the second surface 20 b of the substrate structure 20 may correspond to a bottom surface of the semiconductor substrate 210 .
  • a redistribution layer may be further provided on the bottom surface of the semiconductor substrate 210 .
  • the second surface 20 b of the substrate structure 20 may correspond to an exposed surface of the redistribution layer.
  • the substrate structure 20 may be disposed on the processing release tape 11 .
  • the second surface 20 b of the substrate structure 20 may face a top surface of the first release layer 130 .
  • the substrate structure 20 may be attached to the first release layer 130 such that the semiconductor substrate 210 is in physical contact with the first release layer 130 .
  • the substrate structure 20 may be a wafer-level substrate.
  • the semiconductor substrate 210 may be a semiconductor wafer.
  • the semiconductor substrate 210 may be formed of or include a semiconductor material, such as silicon, germanium, or silicon-germanium.
  • the wafer can be formed of a non-semiconductor material, and can be a glass, quartz, sapphire or other wafer.
  • the semiconductor substrate 210 may include a bottom surface and a top surface 210 a , which are opposite to each other.
  • the bottom surface of the semiconductor substrate 210 may be a rear surface.
  • the top surface 210 a of the semiconductor substrate 210 may be a front surface.
  • the circuit layer 220 may be provided on the top surface 210 a of the semiconductor substrate 210 .
  • the circuit layer 220 may include integrated circuits (not shown), an insulating layer 221 , an interconnection structure 223 , and chip pads 225 .
  • the integrated circuits may be provided on the top surface 210 a of the semiconductor substrate 210 and may include transistors.
  • the insulating layer 221 may be disposed on the top surface 210 a of the semiconductor substrate 210 to cover the integrated circuits.
  • the insulating layer 221 may include a plurality of stacked layers.
  • the insulating layer 221 may be formed of or include at least one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the interconnection structure 223 may be disposed in the insulating layer 221 .
  • the interconnection structure 223 may be electrically connected to the integrated circuits.
  • the interconnection structure 223 may be formed of or include at least one of conductive materials (e.g., copper and/or tungsten).
  • conductive materials e.g., copper and/or tungsten.
  • the expression “electrically connected or coupled” may mean that relevant elements are directly connected/coupled to each other or are indirectly connected or coupled to each other through another conductive element.
  • the chip pads 225 On a top surface of the insulating layer 221 , the chip pads 225 may be exposed to the outside. At least one of the chip pads 225 may be electrically connected to the interconnection structure 223 .
  • the chip pads 225 may be formed of or include at least one of conductive materials (e.g., aluminum, gold, and/or copper).
  • the penetration structure 230 may be provided in the circuit layer 220 and the semiconductor substrate 210 .
  • the penetration structure 230 may be provided to penetrate the semiconductor substrate 210 .
  • the penetration structure 230 may be provided to penetrate at least a portion of the circuit layer 220 .
  • the penetration structure 230 may be electrically connected to at least one of the chip pads 225 or the integrated circuits through the interconnection structure 223 .
  • the penetration structure 230 may be formed of or include at least one of conductive materials (e.g., copper, titanium, or tungsten). In an embodiment, a plurality of the penetration structures 230 may be provided.
  • the solder bumps 240 may be provided on the circuit layer 220 and may be coupled to the chip pads 225 , respectively.
  • the solder bumps 240 may include solder balls, solder bumps, pillars, or combinations thereof.
  • the solder bumps 240 may be formed of or include at least one of conductive materials (e.g., tin, lead, silver, and alloys thereof).
  • the solder bumps 240 may be connected to the integrated circuits or the penetration structures 230 through the interconnection structure 223 .
  • the substrate structure 20 may include a plurality of preliminary semiconductor chips 200 P.
  • the preliminary semiconductor chips 200 P may be connected to each other, without any interface therebetween.
  • the preliminary semiconductor chips 200 P may be separated from each other to form semiconductor chips 200 , as will be described with reference to FIG. 4D .
  • Each of the preliminary semiconductor chips 200 P may include a portion corresponding to the semiconductor substrate 210 , a portion corresponding to the circuit layer 220 , the penetration structures 230 , and the solder bumps 240 .
  • a processing process may be performed on the first surface 20 a of the substrate structure 20 .
  • the processing process may be a dicing process.
  • the dicing process may include cutting the substrate structure 20 using a cutting wheel or a laser beam. Accordingly, the processed substrate structure 20 may be formed.
  • the processed substrate structure 20 may mean a diced substrate.
  • grooves 290 may be formed in the substrate structure 20 .
  • Each of the grooves 290 may penetrate the substrate structure 20 from the first surface 20 a to the second surface 20 b .
  • the preliminary semiconductor chips 200 P of FIG. 4C may be separated from each other by the grooves 290 to form the semiconductor chips 200 .
  • the semiconductor chips 200 may be horizontally spaced apart from each other.
  • Each of the semiconductor chips 200 may include the diced semiconductor substrate 210 , the diced circuit layer 220 , the penetration structures 230 , and the solder bumps 240 .
  • Each of the semiconductor chips 200 may correspond to a portion of the diced substrate structure 20 .
  • a portion of the processing release tape 11 may be diced along with the substrate structure 20 , and thus, the grooves 290 may be extended into the processing release tape 11 .
  • the grooves 290 may be formed to penetrate at least one of the first release layer 130 and the adhesive layer 120 . However, the grooves 290 may not completely penetrate the processing release tape 11 .
  • an adhesive strength between the first release layer 130 and the substrate structure 20 may be relatively strong.
  • an adhesive strength between the first release film 130 ′ and the semiconductor substrate 210 may range from 0.5 N/inch to 5 N/inch. Accordingly, during the dicing process, the processing release tape 11 may be effectively used to fasten or support the substrate structure 20 .
  • the substrate structure 20 may be stably fastened to the adhesive layer 120 and the base layer 110 by the first release layer 130 .
  • the adhesive strength between the first release layer 130 and the substrate structure 20 may correspond to the adhesive strength between the first release film 130 ′ and the semiconductor substrate 210 , but the inventive concept is not limited to this example.
  • the processing release tape 11 may be formed by removing the protection release film 150 , the second release layer 140 , and the portion of the first release layer 130 from the processing tape 10 as described with reference to FIG. 4A . If, in the processing tape 10 , the content of the first release layer 130 is greater than 30 phr of the adhesive layer 120 or the thickness T 2 of the first release layer 130 is thicker than 10 ⁇ m, the adhesive strength between the substrate structure 20 and the first release film 130 ′ of the processing release tape 11 may be deteriorated. In this case, it may be difficult to stably fasten the substrate structure 20 to the processing release tape 11 , during the processing process. However, according to an embodiment of the inventive concept, in the processing tapes 10 and 10 A of FIGS.
  • the first release layer 130 may be 0.01 phr to 30 phr of the adhesive layer 120 .
  • the thickness T 2 of the first release layer 130 may range from 0.01 ⁇ m to 10 ⁇ m. Accordingly, the substrate structure 20 may be stably fastened to the adhesive layer 120 and the base layer 110 through the first release film 130 ′.
  • light may be irradiated to the processing release tape 11 and the processed substrate structure 20 .
  • the light may be an ultraviolet light.
  • the light may be irradiated to the adhesive layer 120 and the first release film 130 ′.
  • the adhesive layer 120 may be photo-cured.
  • the adhesive strength between the first release film 130 ′ and the semiconductor substrate 210 may be lowered.
  • the adhesive strength between the first release film 130 ′ and the semiconductor substrate 210 after the irradiation of the light may be smaller than the adhesive strength between the first release film 130 ′ and the semiconductor substrate 210 before the irradiation of the light.
  • the adhesive strength between the first release film 130 ′ and the semiconductor substrate 210 after the irradiation of the light may range from 0.01 N/inch (1.02 gf/inch) to 0.05 N/inch (5.10 gf/inch).
  • the diced substrate structure 20 may be detached from the first release film 130 ′.
  • the semiconductor substrate 210 of each semiconductor chip 200 may be detached from the first release film 130 ′ by picking up each of the semiconductor chips 200 .
  • the substrate structure 20 may be in direct contact with the adhesive layer 120 .
  • the semiconductor chips 200 may be hardly detached from the adhesive layer 120 or residues of the adhesive layer 120 may be left on the picked-up semiconductor chips 200 .
  • the substrate structure 20 may be in contact with the first release layer 130 and may be spaced apart from the adhesive layer 120 . Since the adhesive strength between the first release film 130 ′ and the substrate structure 20 is weak, it may be possible to prevent the residues of the first release film 130 ′ from being left on the semiconductor chips 200 . Accordingly, it may be possible to improve the reliability in the process of fabricating the semiconductor chips 200 .
  • a bonding strength between the first release film 130 ′ and the adhesive layer 120 may be very strong.
  • the bonding strength between the first release film 130 ′ and the adhesive layer 120 may be stronger than a bonding strength between the first release film 130 ′ and the semiconductor substrate 210 . Accordingly, the substrate structure 20 may be more easily detached from the first release film 130 ′.
  • the semiconductor device may be fabricated by the method described above.
  • the semiconductor device may be a semiconductor chip.
  • a second release layer was formed by coating silicone acrylate represented by the chemical formula 2 on a protection release film.
  • a base layer containing poly olefin was prepared.
  • An adhesive layer was formed by coating an acrylate-based photo-curable polymer on the base layer.
  • a processing tape was formed by attaching the adhesive layer to the second release layer.
  • a delamination process on the protection release film and the second release layer was performed to expose the adhesive layer.
  • a substrate was attached to the exposed adhesive layer. A weight of 2 kg was exerted on the substrate, the adhesive layer, and the base layer, and then, a first adhesive strength between the adhesive layer and the substrate was measured.
  • An ultraviolet light was irradiated to the processing tape, and then, a second adhesive strength between the second release layer and the substrate was measured.
  • the measurements of the first and second adhesive strengths were conducted on a stainless steel (SUS) substrate and a bare wafer substrate, respectively.
  • SUS stainless steel
  • a second release layer was formed by coating silicone acrylate represented by the chemical formula 2 on a protection release film.
  • a first release layer was formed by coating a silicone-based material represented by the chemical formula 1 on the second release layer.
  • a base layer containing poly olefin was prepared.
  • An adhesive layer was formed by coating an acrylate-based photo-curable polymer on the base layer.
  • a processing tape was formed by attaching the adhesive layer to the first release layer.
  • a processing release tape was formed by performing a delamination process on the protection release film and the second release layer. Here, 30 wt % of the first release layer was left on the adhesive layer. The remaining portion of the first release layer will be referred to as a first release film.
  • the processing release tape was composed of the base layer, the adhesive layer, and the first release film.
  • a substrate was attached to the first release film.
  • a weight of 2 kg was exerted on the substrate and the processing release tape, and then, a first adhesive strength between the first release film and the substrate was measured.
  • An ultraviolet light was irradiated to the processing release tape, and then, a second adhesive strength between the first release layer and the substrate was measured.
  • the measurements of the first and second adhesive strengths were conducted on a stainless steel (SUS) substrate and a bare wafer substrate, respectively.
  • SUS stainless steel
  • a processing release tape was fabricated by substantially the same method as in the experimental example 1, and then, the first and second adhesive strengths were measured.
  • the measurements of the first and second adhesive strengths were conducted on a stainless steel (SUS) substrate and a bare wafer substrate, respectively.
  • SUS stainless steel
  • 10 wt % of the first release layer was left on the adhesive layer to form the first release film.
  • Table 1 summarizes the first and second adhesive strengths measured on the stainless steel substrate in the experimental examples 1 and 2 and the comparative example.
  • the first adhesive strength is an adhesive strength measured before the UV irradiation
  • the second adhesive strength is an adhesive strength measured after the UV irradiation.
  • Each of the first and second adhesive strengths was measured three times, and a value written in Table 1 is an average value.
  • Table 2 summarizes the first and second adhesive strengths measured on the bare wafer substrate in the experimental examples 1 and 2 and the comparative example.
  • the first adhesive strength is an adhesive strength measured before the UV irradiation
  • the second adhesive strength is an adhesive strength measured after the UV irradiation.
  • Each of the first and second adhesive strengths was measured three times, and a value written in Table 2 is an average value.
  • the processing release tape did not include the first release film.
  • the second adhesive strength was much smaller than the first adhesive strength.
  • the adhesive strength between the first release film and the substrate was significantly reduced after the UV irradiation.
  • a reduction ratio of the second adhesive strength to the first adhesive strengths in the experimental examples 1 and 2 was greater than a reduction ratio of the second adhesive strength to the first adhesive strength in the comparative example.
  • the first adhesive strengths in the experimental examples 1 and 2 were smaller than the first adhesive strength in the comparative example.
  • the first adhesive strengths in the experimental examples 1 and 2 were about 0.5 to about 0.9 times the first adhesive strength in the comparative example.
  • the first adhesive strengths in the experimental examples 1 and 2 can generally be from 0.3 to 0.9 times the first adhesive strength in the comparative example.
  • the second adhesive strengths in the experimental examples 1 and 2 were smaller than the second adhesive strength in the comparative example.
  • the second adhesive strengths in the experimental examples 1 and 2 were 0.4 to 0.8 times the second adhesive strength in the comparative example.
  • the second adhesive strengths in the experimental examples 1 and 2 can generally be from 0.3 to 0.9 times the second adhesive strength in the comparative example.
  • an adhesive strength between the first release film 130 ′ and the substrate structure 20 after the irradiation of the light was smaller than an adhesive strength between the first release film 130 ′ and the substrate structure 20 before the irradiation of the light.
  • the adhesive strength between the first release film 130 ′ and the semiconductor substrate 210 before the irradiation of the light may be from 0.5 N/inch to 5 N/inch, and the adhesive strength between the first release film 130 ′ and the semiconductor substrate 210 after the irradiation of the light may be from 0.01 N/inch to 0.05 N/inch.
  • the semiconductor substrate 210 may be a bare wafer substrate, such as a bare silicon wafer. Other conductive elements or circuits on a surface of the bare wafer substrate may not be exposed.
  • the semiconductor substrate 210 according to an embodiment of the inventive concept is not limited to the bare wafer.
  • FIG. 5A is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • a previously described element may be identified by the same reference number without repeating an overlapping description thereof.
  • a semiconductor package may include a package substrate 900 , an outer terminal 950 , an interposer bump 840 , an interposer substrate 800 , a semiconductor device 400 , and a first semiconductor chip 200 Z.
  • the semiconductor package may further include at least one of a second semiconductor chip 300 , a mold layer 500 , a first under-fill layer 510 , a second under-fill layers 520 , or a heat-dissipation structure 700 .
  • the package substrate 900 may include an insulating base layer 910 , a substrate pad 920 , and an internal interconnection line 930 .
  • the insulating base layer 910 may include a plurality of stacked layers.
  • the substrate pad 920 may be exposed on a top surface of the package substrate 900 .
  • the internal interconnection line 930 may be disposed in the insulating base layer 910 and may be electrically connected to the substrate pad 920 .
  • the expression “two elements are electrically connected or coupled to each other” may mean that the elements are directly connected or coupled to each other or are indirectly connected or coupled to each other through other conductive elements.
  • an element is electrically connected to the package substrate 900 may mean that the element is electrically connected to the internal interconnection line 930 .
  • the substrate pad 920 and the internal interconnection line 930 may be formed of or include at least one of metallic materials (e.g., copper, aluminum, tungsten, and/or titanium).
  • the package substrate 900 may be a printed circuit board (PCB).
  • PCB printed circuit board
  • a redistribution layer may be used as the package substrate 900 .
  • the outer terminal 950 may be provided on a bottom surface of the package substrate 900 and may be coupled to the internal interconnection line 930 .
  • the outer terminal 950 may include a solder ball.
  • the outer terminal 950 may be formed of or include at least one of solder materials.
  • the solder materials may include tin (Sn), silver (Ag), zinc (Zn), and/or alloys thereof.
  • the interposer substrate 800 may be disposed on the package substrate 900 .
  • the interposer substrate 800 may include a metal pad 820 and a metal line 830 .
  • the metal pad 820 may be exposed on a top surface of the interposer substrate 800 .
  • the metal line 830 may be provided in the interposer substrate 800 and may be coupled to the metal pad 820 .
  • the expression “an element is electrically connected to the interposer substrate 800 ” may mean that the element is electrically connected to the metal line 830 .
  • the metal pad 820 and the metal line 830 may be formed of or include at least one of metallic materials (e.g., copper, aluminum, tungsten, and/or titanium).
  • the interposer bump 840 may be interposed between the package substrate 900 and the interposer substrate 800 and may be coupled to the package substrate 900 and the interposer substrate 800 .
  • the interposer bump 840 may include a solder material.
  • the semiconductor device 400 may be disposed on the top surface of the interposer substrate 800 .
  • the semiconductor device 400 may include a semiconductor chip (e.g., a logic chip, a buffer chip, or a system-on-chip (SOC)).
  • the semiconductor device 400 may include, for example, an application specific integrated circuit (ASIC) chip or an application processor (AP) chip.
  • ASIC application specific integrated circuit
  • AP application processor
  • the semiconductor device 400 may be a semiconductor chip including at least one of a central processing unit (CPU) or a graphic processing unit (GPU).
  • a bump terminal 440 may be interposed between the interposer substrate 800 and the semiconductor device 400 and may be electrically connected to the interposer substrate 800 and the semiconductor device 400 .
  • the bump terminal 440 may include a solder material.
  • the first under-fill layer 510 may be provided in a gap region between the interposer substrate 800 and the semiconductor device 400 to encapsulate or seal the bump terminal 440 .
  • the first under-fill layer 510 may be formed of or include an insulating polymer (e.g., epoxy-based polymers).
  • the first semiconductor chip 200 Z may be disposed on the top surface of the interposer substrate 800 to be horizontally spaced apart from the semiconductor device 400 .
  • the semiconductor package may include a plurality of the first semiconductor chips 200 Z, which are stacked on the top surface of the interposer substrate 800 .
  • the first semiconductor chips 200 Z may be semiconductor chips that are of a kind different from the semiconductor device 400 .
  • the first semiconductor chips 200 Z may include high bandwidth memory (HBM) chips.
  • the first semiconductor chips 200 Z may include DRAM chips.
  • the lowermost of the first semiconductor chips 200 Z may be a logic chip and may have a different function from the semiconductor device 400 .
  • a width of the lowermost of the first semiconductor chips 200 Z may be different from a width of the others of the first semiconductor chips 200 Z, but the inventive concept is not limited to this example.
  • Each of the first semiconductor chips 200 Z may include the first solder bumps 240 Z, a first circuit layer 220 Z, a first semiconductor substrate 210 Z, and the first penetration structures 230 Z.
  • the first solder bumps 240 Z, the first circuit layer 220 Z, the first semiconductor substrate 210 Z, and the first penetration structures 230 Z may be substantially the same as the solder bumps 240 Z, the circuit layer 220 , the semiconductor substrate 210 , and the penetration structures 230 , respectively, which were described with reference to FIGS. 4C to 4F .
  • the first semiconductor chips 200 Z may include a lower semiconductor chip and an upper semiconductor chip, which are adjacent to each other. The upper semiconductor chip may be disposed on the lower semiconductor chip.
  • the first solder bumps 240 Z of the upper semiconductor chip may be electrically connected to the first penetration structures 230 Z, respectively, of the lower semiconductor chip.
  • the expression “an element is electrically connected to the semiconductor chip” may mean that the element is electrically connected to the integrated circuits in the semiconductor chip.
  • At least one of the first semiconductor chips 200 Z may be formed by the process of dicing the substrate structure 20 using the processing tape 10 , described with reference to FIGS. 4A to 4F . Any residue of the first release layer 130 may not be left on the top surfaces of the first semiconductor chips 200 Z. This may make it possible to realize reliable electric connection between the first semiconductor chips 200 Z.
  • the second semiconductor chip 300 may be disposed on the uppermost one of the first semiconductor chips 200 Z.
  • the second semiconductor chip 300 may include a high bandwidth memory chip.
  • the second semiconductor chip 300 may include a second semiconductor substrate 310 , a second circuit layer 320 , and second solder bumps 340 , but may not include any penetration structure.
  • the second solder bumps 340 may be respectively coupled to the first penetration structures 230 Z of the uppermost one of the first semiconductor chips 200 Z.
  • the second semiconductor substrate 310 , the second circuit layer 320 , and the second solder bumps 340 may be substantially the same as the semiconductor substrate 210 , the circuit layer 220 , and the solder bumps 240 Z, respectively, described with reference to FIGS. 4C to 4F .
  • the second semiconductor chip 300 may be omitted.
  • the second under-fill layers 520 may be respectively provided in first gap regions between the first semiconductor chips 200 Z to seal corresponding ones of the first solder bumps 240 Z.
  • the second under-fill layers 520 may be further provided in a second gap region between the substrate structure 20 and the lowermost of the first semiconductor chips 200 Z and a third gap region between the uppermost one of the first semiconductor chips 200 Z and the second semiconductor chip 300 .
  • the second under-fill layers 520 may be formed of or include an insulating polymer (e.g., epoxy-based polymers).
  • the mold layer 500 may be provided on the package substrate 900 to cover the semiconductor device 400 , the first semiconductor chips 200 Z, and the second semiconductor chip 300 .
  • the mold layer 500 may be formed to expose the top surface of the semiconductor device 400 and the top surface of the second semiconductor chip 300 , but the inventive concept is not limited to this example.
  • the mold layer 500 may be formed of or include an insulating polymer (e.g., epoxy-based polymers).
  • the heat-dissipation structure 700 may be disposed on at least one of the top surface of the semiconductor device 400 and the top surface of the second semiconductor chip 300 .
  • the heat-dissipation structure 700 may further cover the top surface of the mold layer 500 .
  • the heat-dissipation structure 700 may be further extended to cover the side surface of the mold layer 500 .
  • the heat-dissipation structure 700 may include a heat slug or a heat sink.
  • the heat-dissipation structure 700 may be formed of or include materials (e.g., metals) having high thermal conductivity.
  • FIG. 5B is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • a previously described element may be identified by the same reference number without repeating an overlapping description thereof.
  • the semiconductor package may include the package substrate 900 , the outer terminal 950 , the first semiconductor chip 200 Z, and the second semiconductor chip 300 .
  • the semiconductor package may further include the mold layer 500 , a first under-fill pattern 511 , second under-fill patterns 521 , and the heat-dissipation structure 700 .
  • the package substrate 900 and the outer terminal 950 may be substantially the same as those described with reference to FIG. 5A .
  • the first semiconductor chip 200 Z may be mounted on the package substrate 900 .
  • the first semiconductor chip 200 Z may be one of the semiconductor chips 200 , which are formed by a process of dicing the substrate structure 20 using the processing tape 10 , described with reference to FIGS. 4A to 4F .
  • Each of the first semiconductor chips 200 Z may include the first solder bumps 240 Z, the first circuit layer 220 Z, the first semiconductor substrate 210 Z, and the first penetration structures 230 Z.
  • the first solder bumps 240 Z may be coupled to a plurality of substrate pads 920 , respectively.
  • the first semiconductor chip 200 Z may be a logic chip.
  • the second semiconductor chip 300 may be disposed on the first semiconductor chip 200 Z.
  • the second semiconductor chip 300 may be configured to have features similar to the second semiconductor chip 300 described with reference to FIG. 5A .
  • the second semiconductor chip 300 may include the second solder bumps 340 , the second circuit layer 320 , and the second semiconductor substrate 310 , but may not include any penetration structure.
  • the second semiconductor chip 300 may be a memory chip (e.g., an SRAM chip).
  • the second solder bumps 340 may be electrically connected to the first penetration structures 230 Z, respectively.
  • the second semiconductor chip 300 may be electrically connected to the first semiconductor chip 200 Z or the outer terminal 950 .
  • a plurality of the second semiconductor chips 300 may be provided and may be horizontally spaced apart from each other.
  • the first under-fill pattern 511 may be provided in a first gap region between the package substrate 900 and the first semiconductor chip 200 Z to seal the first solder bumps 240 Z.
  • the second under-fill patterns 521 may be respectively disposed in second gap regions between the first semiconductor chip 200 Z and the second semiconductor chips 300 . Each of the second under-fill patterns 521 may seal corresponding ones of the second solder bumps 340 .
  • the first under-fill pattern 511 and the second under-fill patterns 521 may be formed of or include an insulating polymer (e.g., epoxy-based polymers).
  • the mold layer 500 may be disposed on the top surface of the first semiconductor chip 200 Z to cover the second semiconductor chips 300 .
  • the mold layer 500 may be provided to expose the top surfaces of the second semiconductor chips 300 .
  • the heat-dissipation structure 700 may be disposed on the top surfaces of the second semiconductor chips 300 and the top surface of the mold layer 500 .
  • the heat-dissipation structure 700 may be extended to cover the side surface of the mold layer 500 .
  • a processing release tape may include a first release layer.
  • a substrate structure may be attached to the first release layer, and then, a process of processing the substrate structure may be performed.
  • An adhesive strength between the first release layer and the substrate structure may be high enough to allow the first release layer to stably fasten the substrate structure during the processing process.
  • light may be irradiated to the processing release tape.
  • the adhesive strength between the first release layer and the substrate structure may be sufficiently lowered. Accordingly, the substrate structure may be easily detached from the first release layer. There may be no residue of the first release layer on the detached substrate structure.

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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • Adhesives Or Adhesive Processes (AREA)

Abstract

A processing tape may include a base layer, an adhesive layer disposed on the base layer, a protection release film on the adhesive layer, and a first release layer interposed between the adhesive layer and the protection release film. The first release layer may include a silicone-based material and may be non-photo-curable.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0086874, filed on Jul. 14, 2020, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
    • BACKGROUND OF THE INVENTION
  • The present disclosure relates to a processing tape, and in particular, to a processing tape which is used in a process of fabricating a semiconductor device.
  • With the development of the electronics industry, it becomes possible to cost-effectively manufacture light, small, fast, and high-performance electronic products. The electronic product includes a semiconductor device, which is fabricated using a wafer-level substrate. A plurality of semiconductor chips are formed by dicing the substrate. A processing tape, such as a dicing tape, is used in the process of dicing the substrate.
    • SUMMARY
  • An embodiment of the inventive concept provides a processing tape with improved adhesive strength and a method of fabricating a semiconductor device using the same.
  • An embodiment of the inventive concept provides a processing tape with improved releasing property and a method of fabricating a semiconductor device using the same.
  • According to an embodiment of the inventive concept, a processing tape may include a base layer, an adhesive layer disposed on the base layer, a protection release film on the adhesive layer, and a first release layer interposed between the adhesive layer and the protection release film. The first release layer may include a silicone-based material and may be non-photo-curable.
  • According to an embodiment of the inventive concept, a method of fabricating a semiconductor device may include preparing a processing tape including an adhesive layer, a first release layer, and a protection release film stacked on a base layer, removing the protection release film while leaving at least a portion of the first release layer, which is used as a first release film, on the adhesive layer, attaching a substrate structure to the first release film, performing a processing process on the substrate structure to form a processed substrate structure, and detaching the processed substrate structure from the first release film. The first release film may be non-photo-curable.
  • According to an embodiment of the inventive concept, a processing tape may include a base layer including a polymer, a pressure sensing adhesive layer disposed on the base layer, a protection release film on the pressure sensing adhesive layer, a first release layer interposed between the pressure sensing adhesive layer and the protection release film, and a second release layer interposed between the first release layer and the protection release film, the second release layer including silicone acrylate. The first release layer may be non-photo-curable, and the pressure sensing adhesive layer may include a photo-curable material. The first release layer may be 0.01 phr to 30 phr of the pressure sensing adhesive layer, and a thickness of the first release layer ranges from 0.01 μm to 10 μm. The first release layer may include a material represented by chemical formula 1.
  • Figure US20220020627A1-20220120-C00001
  • where R1 and R2 may each independently include one selected from a hydrogen, an alkyl group having 1 to 5 carbon atoms, an alkyl substituted silyl group having 1 to 5 carbon atoms, —NH2, an amino alkyl group having 1 to 5 carbon atoms, an alkyl amino group having 1 to 5 carbon atoms, a hydroxyl group (—OH), a hydroxy alkyl group having 1 to 5 carbon atoms, an isocyanate group (NCO), an alkyl group having 1 to 5 carbon atoms substituted with isocyanate, R3 each independently includes one selected from an alkyl group having 1 to 3 carbon atoms and an alkyl group having 1 to 5 carbon atoms substituted with epoxy group, and n is from 1 to 410.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein.
  • FIG. 1 is a sectional view illustrating a processing tape according to an embodiment of the inventive concept.
  • FIG. 2 is a sectional view illustrating a processing tape according to an embodiment of the inventive concept.
  • FIGS. 3A to 3C are sectional views illustrating a method of fabricating a processing tape, according to an embodiment of the inventive concept.
  • FIGS. 4A to 4F are sectional views illustrating a method of fabricating a semiconductor device, using a processing tape according to an embodiment of the inventive concept.
  • FIG. 5A is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • FIG. 5B is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept
    •  DETAILED DESCRIPTION
  • Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.
  • FIG. 1 is a sectional view illustrating a processing tape according to an embodiment of the inventive concept.
  • Referring to FIG. 1, a processing tape 10 may include a base layer 110, an adhesive layer 120, a first release layer 130, a second release layer 140, and a protection release film 150. The processing tape 10 may be a dicing tape. For example, the processing tape 10 may be used in a process of dicing a wafer-level substrate.
  • The base layer 110 may include at least one of organic materials (e.g., polymeric materials). For example, the base layer 110 may include at least one of poly ethyleneterephthalate (PET), poly olefin (PO), poly (vinyl alcohol) (PVA), poly(l-naphthylamine) (PNA), poly ether ketone (PEEK), and/or mixtures thereof. For example, the base layer 110 may include homopolymers or blend polymers. The base layer 110 may be a single layer or a multiple layer.
  • The adhesive layer 120 may be disposed on the base layer 110. The adhesive layer 120 may be, for example, a pressure sensitive adhesive (PSA) layer. The adhesive layer 120 may contain a photo-curable material which is in an uncured state. The photo-curable material may contain polymer, which contains an alkyne group and an alcohol (—OH) group. For example, the adhesive layer 120 may include an acrylate-based material (e.g., acrylate polymer). The adhesive layer 120 may further include at least one of a cross-linking agent, a photocuring agent, or an additive agent. The additive agent may further include at least one of a UV absorbing agent and a coating leveling agent. The UV absorbing agent may be formed of or include a material having an aromatic ring or a conjugate structure. For example, the UV absorbing agent may include benzophenone and/or derivatives thereof. The coating leveling agent may include a silicone-based surfactant. A thickness T1 of the adhesive layer 120 may range from 5 μm to 50 μm.
  • The first release layer 130 may be disposed on the adhesive layer 120. For example, the first release layer 130 may be interposed between the adhesive layer 120 and the protection release film 150. The first release layer 130 may be in direct or physical contact with the adhesive layer 120. The first release layer 130 may be attached to the base layer 110 by the adhesive layer 120. The first release layer 130 may include a non-photosensitive material. The non-photosensitive material may mean a material that is not cured by light. In other words, the first release layer 130 may include a non-photo-curable material. The non-photo-curable material may have unintentional or negligible changes under UV light. For example, the non-photo-curable material may have substantially no cross linking occur under UV light. The molecular weight of the non-photo-curable material may undergo substantially no change when exposed to light, or the molecular weight of the non-photo-curable material may change less than 1% under UV light. The first release layer 130 may include a thermosetting material or a non-reactive material. In the present specification, the non-reactive property may mean a non-thermosetting property, a non-photo-curable property, and a chemically non-reactive property. The chemically non-reactive property may mean that the material does not participate in chemical reaction with other materials. The first release layer 130 may include a silicone-based material. For example, the first release layer 130 may include a silicone-based material represented by the following chemical formula 1. A weight average molecular weight (Mw) of the silicone-based material may range from 100 g/mol to 30,000 g/mol.
  • Figure US20220020627A1-20220120-C00002
  • In the chemical formula 1, R1 and R2 may each independently include one selected from a hydrogen, an alkyl group having 1 to 5 carbon atoms, an alkyl substituted silyl group having 1 to 5 carbon atoms, —NH2, an amino alkyl group having 1 to 5 carbon atoms, an alkyl amino group having 1 to 5 carbon atoms, a hydroxyl group (—OH), a hydroxy alkyl group having 1 to 5 carbon atoms, an isocyanate group (NCO), an alkyl group having 1 to 5 carbon atoms substituted with isocyanate, R3 may each independently include one selected from an alkyl group having 1 to 3 carbon atoms (e.g. a methyl, ethyl or propyl group) and an alkyl group having 1 to 5 carbon atoms substituted with epoxy group, and n is from 1 to 410.
  • As an example, the first release layer 130 may exhibit a non-reactive property, and in the chemical formula 1, R1 and R2 may be each independently a hydrogen, an alkyl group having 1 to 5 carbon atoms, or an alkyl substituted silyl group having 1 to 5 carbon atoms.
  • As another example, the first release layer 130 may exhibit a thermosetting property, and in the chemical formula 1, R1 and R2 may each independently include any one selected from —NH2, an amino alkyl group having 1 to 5 carbon atoms, an alkyl amino group having 1 to 5 carbon atoms, —OH, a hydroxy alkyl group having 1 to 5 carbon atoms, an isocyanate group (NCO), an alkyl group having 1 to 5 carbon atoms substituted with isocyanate, and an alkyl group having 1 to 5 carbon atoms substituted with epoxy group. In an embodiment, the first release layer 130 may have a thermosetting property and may be chemically bonded with the adhesive layer 120. A chemical bond may be provided between a bottom surface of the first release layer 130 and a top surface of the adhesive layer 120. In this case, the first release layer 130 may be more strongly fastened to the adhesive layer 120.
  • The first release layer 130 may be 0.01 phr (parts per hundred rubber) to 30 phr of the adhesive layer 120. A thickness T2 of the first release layer 130 may range from 0.01 μm to 10 μm. The first release layer 130 may have a hydrophobic property.
  • The second release layer 140 may be disposed on the first release layer 130. For example, the second release layer 140 may be interposed between the first release layer 130 and the protection release film 150. The second release layer 140 may include a different material from the first release layer 130 and may have physical and chemical characteristics different from the first release layer 130. The second release layer 140 may include a photo-curable material. The second release layer 140 may be in a photo-cured state. The second release layer 140 may include a silicone acrylate-based material. In an embodiment, the second release layer 140 may include a material, which is represented by the following chemical formula 2, and/or derivatives thereof. A weight average molecular weight of the material represented by the chemical formula 2 may range from 100 g/mol to 30,000 g/mol. The material represented by the chemical formula 2 may be silicone acrylate.
  • Figure US20220020627A1-20220120-C00003
  • In the chemical formula 2, R4 each independently includes one selected from an alkyl group having 1 to 3 carbon atom (e.g. a methyl, ethyl or propyl group), and m is from 0 to 520.
  • The second release layer 140 may be 0.00001 phr to 30 phr of the adhesive layer 120.
  • The protection release film 150 may be disposed on the second release layer 140. The protection release film 150 may include an organic material (e.g., polymer). For example, the protection release film 150 may be formed of or include at least one of poly ethyleneterephthalate (PET), poly olefin (PO), poly (vinyl alcohol) (PVA), poly(l-naphthylamine) (PNA), poly ether ketone (PEEK), and/or mixtures thereof. The protection release film 150 may protect the second release layer 140, the first release layer 130, or the adhesive layer 120 from a physical stress. The physical stress may be an external impact but is not limited thereto. The protection release film 150 may be removed before using the processing tape 10. An example, in which the processing tape 10 is used, will be described with reference to FIGS. 4A to 4F.
  • FIG. 2 is a sectional view illustrating a processing tape according to an embodiment of the inventive concept. For concise description, a previously described element may be identified by the same reference number without repeating an overlapping description thereof.
  • Referring to FIG. 2, the processing tape 10A may be a dicing tape. The processing tape 10 may include the base layer 110, the adhesive layer 120, the first release layer 130, and the protection release film 150. The base layer 110, the adhesive layer 120, the first release layer 130, and the protection release film 150 may be substantially the same as those described with reference to FIG. 1. For example, the thickness T1 of the adhesive layer 120 and the thickness T2 of the first release layer 130 may be the same as those described with reference to FIG. 1. However, the processing tape 10 may not include the second release layer 140 of FIG. 1 and the first release layer 130 may be in direct or physical contact with the adhesive layer 120 and the protection release film 150. The layers illustrated in FIGS. 1 and 2 may be directly provided adjacent each other as illustrated, or one or more intervening layers (to aid with strength, adhesion, separation etc) may also be provided between the illustrated layers.
  • FIGS. 3A to 3C are sectional views illustrating a method of fabricating a processing tape, according to an embodiment of the inventive concept. For concise description, a previously described element may be identified by the same reference number without repeating an overlapping description thereof.
  • Referring to FIG. 3A, the second release layer 140 may be formed on the protection release film 150. In an embodiment, the formation of the second release layer 140 may include coating a photo-curable material on the protection release film 150. The photo-curable material may include a silicone acrylate-based material. The formation of the second release layer 140 may further include irradiating light to the coated layer. The light may be an ultraviolet (UV) light. The second release layer 140 may be photo-cured by the irradiation of the light. Accordingly, the second release layer 140 may include a photo-cured silicone acrylate-based material. The photo curing may mean an ultraviolet light (UV) curing.
  • Referring to FIG. 3B, the first release layer 130 may be formed on the second release layer 140. The first release layer 130 may be formed by coating the material, which is represented by the chemical formula 1, on the second release layer 140.
  • Unlike that shown in the figure, the first release layer 130 may be coated on the second release layer 140, before the irradiation of the light described with reference to FIG. 3A. Thereafter, the light may be irradiated to the first release layer 130. As a result of the irradiation of the light, the second release layer 140 may be photo-cured. Since the first release layer 130 includes a non-photo-curable material, the first release layer 130 may not be affected by the light. For example, the first release layer 130 may not be photo-cured.
  • Referring to FIG. 3C, the base layer 110 and the adhesive layer 120 may be prepared. The adhesive layer 120 may be provided on the base layer 110. As an example, a photo-curable acrylate-based polymer may be coated on the base layer 110 to form the adhesive layer 120.
  • The protection release film 150, the second release layer 140, and the first release layer 130, which are formed by the method of FIGS. 3A and 3B, may be prepared. The structure including the protection release film 150, the second release layer 140, and the first release layer 130 may be inverted and then may be placed on the adhesive layer 120 such that the first release layer 130 faces the adhesive layer 120.
  • Referring to FIGS. 3C and 1, the first release layer 130 may be attached to the adhesive layer 120 such that the first release layer 130 is in physical contact with the adhesive layer 120. The attaching of the first release layer 130 may be performed by a laminating process. The processing tape 10 may be fabricated by the afore-described process.
  • Alternatively, the protection release film 150 and the second release layer 140 may be prepared, and then the first release layer 130 may be coated not on the second release layer 140 but on the adhesive layer 120. In this case, the second release layer 140 may be disposed on the first release layer 130 such that the second release layer 140 and the first release layer 130 are spaced apart from each other and face each other. Next, the processing tape 10 may be formed by attaching the second release layer 140 to the first release layer 130 through a laminating process.
  • Unlike that shown in the figure, the process of forming the second release layer 140 may be omitted. In this case, the first release layer 130 may be directly coated on the protection release film 150 or the adhesive layer 120. Thereafter, a stacking process may be performed to form the base layer 110, the adhesive layer 120, the first release layer 130, and the protection release film 150, which are sequentially stacked. The first release layer 130 may be in contact with the adhesive layer 120 and the protection release film 150. In this case, the processing tape 10A may be fabricated to have the structure of FIG. 2.
  • FIGS. 4A to 4F are sectional views illustrating a method of fabricating a semiconductor device, using a processing tape according to an embodiment of the inventive concept. For concise description, a previously described element may be identified by the same reference number without repeating an overlapping description thereof.
  • Referring to FIG. 4A, the processing tape 10 may be prepared. The processing tape 10 may be substantially the same as that described with reference to FIG. 1. For example, the processing tape 10 may include the base layer 110, the adhesive layer 120, the first release layer 130, the second release layer 140, and the protection release film 150. Alternatively, as described with reference to FIG. 2, the second release layer 140 may be omitted and the first release layer 130 may be in direct contact with the adhesive layer 120 and the protection release film 150.
  • Referring to FIGS. 4A and 4B, the protection release film 150 may be removed. Here, the second release layer 140 may also be removed, along with the protection release film 150. The removal of the protection release film 150 and the second release layer 140 may be achieved by a physical method or a mechanical method. The removal of the protection release film 150 may be performed by a user or by a machine operated by a user, and the protection release film 150 may prevent the second release layer 140, the first release layer 130, or the adhesive layer 120 from being damaged during a process of transferring and storing the processing tape 10.
  • After the process of removing the protection release film 150, at least a portion of the first release layer 130 may be left to form a first release film 130′ on the adhesive layer 120. The first release film 130′ left on the adhesive layer 120 may be 10 wt % to 50 wt % of the first release layer 130 prior to removing the protection release film 150. The remaining portion of the first release layer 130 may be removed along with the second release layer 140. As a result of the removal of the protection release film 150 and the second release layer 140, a processing release tape 11 may be formed. The processing release tape 11 may include the base layer 110, the adhesive layer 120, and the first release film 130′.
  • In the case where an interaction between the protection release film 150 and the first release layer 130 is strong, it may be difficult to detach the first release layer 130 from the protection release film 150. A magnitude of the interaction may be represented as an adhesive strength or a bonding strength. In an embodiment, the second release layer 140 may be interposed between the first release layer 130 and the protection release film 150. An adhesive strength between the second release layer 140 and the first release layer 130 may be relatively weak. Accordingly, at least a portion of the first release layer 130 (i.e., the first release film 130′) may be left on the adhesive layer 120, after the removal of the protection release film 150 and the second release layer 140. Alternatively, in the case where an adhesive strength between the protection release film 150 and the first release layer 130 is relatively weak, the second release layer 140 may not be provided, as shown in the processing tape 10A of FIG. 2.
  • Referring to FIG. 4C, a substrate may be prepared. The substrate may be a substrate structure 20. The substrate structure 20 may include a semiconductor substrate 210, a circuit layer 220, and penetration structures 230. The substrate structure 20 may further include solder bumps 240. The substrate structure 20 may have a first surface 20 a and a second surface 20 b, which are opposite to each other. The first surface 20 a of the substrate structure 20 may correspond to a top surface of the circuit layer 220, and the second surface 20 b of the substrate structure 20 may correspond to a bottom surface of the semiconductor substrate 210. Although not shown, a redistribution layer may be further provided on the bottom surface of the semiconductor substrate 210. In this case, the second surface 20 b of the substrate structure 20 may correspond to an exposed surface of the redistribution layer.
  • The substrate structure 20 may be disposed on the processing release tape 11. Here, the second surface 20 b of the substrate structure 20 may face a top surface of the first release layer 130. The substrate structure 20 may be attached to the first release layer 130 such that the semiconductor substrate 210 is in physical contact with the first release layer 130.
  • The substrate structure 20 may be a wafer-level substrate. The semiconductor substrate 210 may be a semiconductor wafer. For example, the semiconductor substrate 210 may be formed of or include a semiconductor material, such as silicon, germanium, or silicon-germanium. Alternatively the wafer can be formed of a non-semiconductor material, and can be a glass, quartz, sapphire or other wafer. The semiconductor substrate 210 may include a bottom surface and a top surface 210 a, which are opposite to each other. The bottom surface of the semiconductor substrate 210 may be a rear surface. The top surface 210 a of the semiconductor substrate 210 may be a front surface. The circuit layer 220 may be provided on the top surface 210 a of the semiconductor substrate 210. The circuit layer 220 may include integrated circuits (not shown), an insulating layer 221, an interconnection structure 223, and chip pads 225. The integrated circuits may be provided on the top surface 210 a of the semiconductor substrate 210 and may include transistors. The insulating layer 221 may be disposed on the top surface 210 a of the semiconductor substrate 210 to cover the integrated circuits. The insulating layer 221 may include a plurality of stacked layers. The insulating layer 221 may be formed of or include at least one of silicon oxide, silicon nitride, or silicon oxynitride. The interconnection structure 223 may be disposed in the insulating layer 221. The interconnection structure 223 may be electrically connected to the integrated circuits. The interconnection structure 223 may be formed of or include at least one of conductive materials (e.g., copper and/or tungsten). In the present specification, the expression “electrically connected or coupled” may mean that relevant elements are directly connected/coupled to each other or are indirectly connected or coupled to each other through another conductive element. On a top surface of the insulating layer 221, the chip pads 225 may be exposed to the outside. At least one of the chip pads 225 may be electrically connected to the interconnection structure 223. The chip pads 225 may be formed of or include at least one of conductive materials (e.g., aluminum, gold, and/or copper).
  • The penetration structure 230 may be provided in the circuit layer 220 and the semiconductor substrate 210. For example, the penetration structure 230 may be provided to penetrate the semiconductor substrate 210. In an embodiment, the penetration structure 230 may be provided to penetrate at least a portion of the circuit layer 220. The penetration structure 230 may be electrically connected to at least one of the chip pads 225 or the integrated circuits through the interconnection structure 223. The penetration structure 230 may be formed of or include at least one of conductive materials (e.g., copper, titanium, or tungsten). In an embodiment, a plurality of the penetration structures 230 may be provided.
  • The solder bumps 240 may be provided on the circuit layer 220 and may be coupled to the chip pads 225, respectively. The solder bumps 240 may include solder balls, solder bumps, pillars, or combinations thereof. The solder bumps 240 may be formed of or include at least one of conductive materials (e.g., tin, lead, silver, and alloys thereof). The solder bumps 240 may be connected to the integrated circuits or the penetration structures 230 through the interconnection structure 223.
  • The substrate structure 20 may include a plurality of preliminary semiconductor chips 200P. The preliminary semiconductor chips 200P may be connected to each other, without any interface therebetween. The preliminary semiconductor chips 200P may be separated from each other to form semiconductor chips 200, as will be described with reference to FIG. 4D. Each of the preliminary semiconductor chips 200P may include a portion corresponding to the semiconductor substrate 210, a portion corresponding to the circuit layer 220, the penetration structures 230, and the solder bumps 240.
  • Referring to FIG. 4D, a processing process may be performed on the first surface 20 a of the substrate structure 20. The processing process may be a dicing process. The dicing process may include cutting the substrate structure 20 using a cutting wheel or a laser beam. Accordingly, the processed substrate structure 20 may be formed. The processed substrate structure 20 may mean a diced substrate.
  • As a result of the dicing process, grooves 290 may be formed in the substrate structure 20. Each of the grooves 290 may penetrate the substrate structure 20 from the first surface 20 a to the second surface 20 b. The preliminary semiconductor chips 200P of FIG. 4C may be separated from each other by the grooves 290 to form the semiconductor chips 200. The semiconductor chips 200 may be horizontally spaced apart from each other. Each of the semiconductor chips 200 may include the diced semiconductor substrate 210, the diced circuit layer 220, the penetration structures 230, and the solder bumps 240. Each of the semiconductor chips 200 may correspond to a portion of the diced substrate structure 20.
  • A portion of the processing release tape 11 may be diced along with the substrate structure 20, and thus, the grooves 290 may be extended into the processing release tape 11. For example, the grooves 290 may be formed to penetrate at least one of the first release layer 130 and the adhesive layer 120. However, the grooves 290 may not completely penetrate the processing release tape 11.
  • In an embodiment, an adhesive strength between the first release layer 130 and the substrate structure 20 may be relatively strong. For example, an adhesive strength between the first release film 130′ and the semiconductor substrate 210 may range from 0.5 N/inch to 5 N/inch. Accordingly, during the dicing process, the processing release tape 11 may be effectively used to fasten or support the substrate structure 20. For example, the substrate structure 20 may be stably fastened to the adhesive layer 120 and the base layer 110 by the first release layer 130. The adhesive strength between the first release layer 130 and the substrate structure 20 may correspond to the adhesive strength between the first release film 130′ and the semiconductor substrate 210, but the inventive concept is not limited to this example.
  • The processing release tape 11 may be formed by removing the protection release film 150, the second release layer 140, and the portion of the first release layer 130 from the processing tape 10 as described with reference to FIG. 4A. If, in the processing tape 10, the content of the first release layer 130 is greater than 30 phr of the adhesive layer 120 or the thickness T2 of the first release layer 130 is thicker than 10 μm, the adhesive strength between the substrate structure 20 and the first release film 130′ of the processing release tape 11 may be deteriorated. In this case, it may be difficult to stably fasten the substrate structure 20 to the processing release tape 11, during the processing process. However, according to an embodiment of the inventive concept, in the processing tapes 10 and 10A of FIGS. 1 and 2, the first release layer 130 may be 0.01 phr to 30 phr of the adhesive layer 120. The thickness T2 of the first release layer 130 may range from 0.01 μm to 10 μm. Accordingly, the substrate structure 20 may be stably fastened to the adhesive layer 120 and the base layer 110 through the first release film 130′.
  • Referring to FIG. 4E, light may be irradiated to the processing release tape 11 and the processed substrate structure 20. The light may be an ultraviolet light. For example, the light may be irradiated to the adhesive layer 120 and the first release film 130′. As a result of the irradiation of the light, the adhesive layer 120 may be photo-cured. As a result of the irradiation of the light, the adhesive strength between the first release film 130′ and the semiconductor substrate 210 may be lowered. The adhesive strength between the first release film 130′ and the semiconductor substrate 210 after the irradiation of the light may be smaller than the adhesive strength between the first release film 130′ and the semiconductor substrate 210 before the irradiation of the light. For example, the adhesive strength between the first release film 130′ and the semiconductor substrate 210 after the irradiation of the light may range from 0.01 N/inch (1.02 gf/inch) to 0.05 N/inch (5.10 gf/inch).
  • Referring to FIG. 4F, the diced substrate structure 20 may be detached from the first release film 130′. For example, the semiconductor substrate 210 of each semiconductor chip 200 may be detached from the first release film 130′ by picking up each of the semiconductor chips 200.
  • In the case where the first release layer 130 is omitted, the substrate structure 20 may be in direct contact with the adhesive layer 120. In this case, the semiconductor chips 200 may be hardly detached from the adhesive layer 120 or residues of the adhesive layer 120 may be left on the picked-up semiconductor chips 200. However, according to an embodiment of the inventive concept, the substrate structure 20 may be in contact with the first release layer 130 and may be spaced apart from the adhesive layer 120. Since the adhesive strength between the first release film 130′ and the substrate structure 20 is weak, it may be possible to prevent the residues of the first release film 130′ from being left on the semiconductor chips 200. Accordingly, it may be possible to improve the reliability in the process of fabricating the semiconductor chips 200.
  • As an example, in the case where the first release film 130′ is chemically bonded to the adhesive layer 120, a bonding strength between the first release film 130′ and the adhesive layer 120 may be very strong. The bonding strength between the first release film 130′ and the adhesive layer 120 may be stronger than a bonding strength between the first release film 130′ and the semiconductor substrate 210. Accordingly, the substrate structure 20 may be more easily detached from the first release film 130′.
  • Since the first release film 130′ has the hydrophobic property, it may be possible to more effectively prevent the residues of the first release film 130′ from being left on the semiconductor chips 200. The semiconductor device may be fabricated by the method described above. The semiconductor device may be a semiconductor chip.
  • Hereinafter, physical characteristics of processing tapes, which were fabricated in experimental and comparative examples, will be described in more detail below.
    • Comparative Example
  • A second release layer was formed by coating silicone acrylate represented by the chemical formula 2 on a protection release film. A base layer containing poly olefin was prepared. An adhesive layer was formed by coating an acrylate-based photo-curable polymer on the base layer. A processing tape was formed by attaching the adhesive layer to the second release layer. A delamination process on the protection release film and the second release layer was performed to expose the adhesive layer. A substrate was attached to the exposed adhesive layer. A weight of 2 kg was exerted on the substrate, the adhesive layer, and the base layer, and then, a first adhesive strength between the adhesive layer and the substrate was measured. An ultraviolet light was irradiated to the processing tape, and then, a second adhesive strength between the second release layer and the substrate was measured. The measurements of the first and second adhesive strengths were conducted on a stainless steel (SUS) substrate and a bare wafer substrate, respectively.
    • Experimental Example 1
  • A second release layer was formed by coating silicone acrylate represented by the chemical formula 2 on a protection release film. A first release layer was formed by coating a silicone-based material represented by the chemical formula 1 on the second release layer.
  • A base layer containing poly olefin was prepared. An adhesive layer was formed by coating an acrylate-based photo-curable polymer on the base layer. A processing tape was formed by attaching the adhesive layer to the first release layer. A processing release tape was formed by performing a delamination process on the protection release film and the second release layer. Here, 30 wt % of the first release layer was left on the adhesive layer. The remaining portion of the first release layer will be referred to as a first release film. The processing release tape was composed of the base layer, the adhesive layer, and the first release film.
  • A substrate was attached to the first release film. A weight of 2 kg was exerted on the substrate and the processing release tape, and then, a first adhesive strength between the first release film and the substrate was measured. An ultraviolet light was irradiated to the processing release tape, and then, a second adhesive strength between the first release layer and the substrate was measured. The measurements of the first and second adhesive strengths were conducted on a stainless steel (SUS) substrate and a bare wafer substrate, respectively.
    • Experimental Example 2
  • A processing release tape was fabricated by substantially the same method as in the experimental example 1, and then, the first and second adhesive strengths were measured. The measurements of the first and second adhesive strengths were conducted on a stainless steel (SUS) substrate and a bare wafer substrate, respectively. However, in the case of the experimental example 2, after the delamination process on the protection release film and the second release layer, 10 wt % of the first release layer was left on the adhesive layer to form the first release film.
  • Table 1 summarizes the first and second adhesive strengths measured on the stainless steel substrate in the experimental examples 1 and 2 and the comparative example. In Table 1, the first adhesive strength is an adhesive strength measured before the UV irradiation, and the second adhesive strength is an adhesive strength measured after the UV irradiation. Each of the first and second adhesive strengths was measured three times, and a value written in Table 1 is an average value.
  • TABLE 1
    Ratio of first release First adhesive Second adhesive
    film to first release strength strength
    layer (wt %) (gf/inch) (gf/inch)
    Experimental 30 471 29.2
    Example 1
    Experimental 10 537 48.9
    Example 2
    Comparative — 604 61.1
    Example
  • Table 2 summarizes the first and second adhesive strengths measured on the bare wafer substrate in the experimental examples 1 and 2 and the comparative example. In Table 2, the first adhesive strength is an adhesive strength measured before the UV irradiation, and the second adhesive strength is an adhesive strength measured after the UV irradiation. Each of the first and second adhesive strengths was measured three times, and a value written in Table 2 is an average value.
  • TABLE 2
    Ratio of first release First adhesive Second adhesive
    film to first release strength strength
    layer (wt %) (gf/inch) (gf/inch)
    Experimental 30 95.9 2.96
    Example 1
    Experimental 10 127.6 4.29
    Example 2
    Comparative — 175.5 7.45
    Example
  • Referring to Tables 1 and 2, in the case of the comparative example, the processing release tape did not include the first release film. In the cases of the experimental examples 1 and 2, the second adhesive strength was much smaller than the first adhesive strength. In the cases of the experimental examples 1 and 2, the adhesive strength between the first release film and the substrate was significantly reduced after the UV irradiation. A reduction ratio of the second adhesive strength to the first adhesive strengths in the experimental examples 1 and 2 was greater than a reduction ratio of the second adhesive strength to the first adhesive strength in the comparative example.
  • The first adhesive strengths in the experimental examples 1 and 2 were smaller than the first adhesive strength in the comparative example. The first adhesive strengths in the experimental examples 1 and 2 were about 0.5 to about 0.9 times the first adhesive strength in the comparative example. Depending upon the materials and thicknesses selected for the adhesive and release layers, the first adhesive strengths in the experimental examples 1 and 2 can generally be from 0.3 to 0.9 times the first adhesive strength in the comparative example. The second adhesive strengths in the experimental examples 1 and 2 were smaller than the second adhesive strength in the comparative example. The second adhesive strengths in the experimental examples 1 and 2 were 0.4 to 0.8 times the second adhesive strength in the comparative example. Depending upon the materials and thicknesses selected for the adhesive and release layers, the second adhesive strengths in the experimental examples 1 and 2 can generally be from 0.3 to 0.9 times the second adhesive strength in the comparative example.
  • Referring to FIGS. 4E and 4F and Table 2, an adhesive strength between the first release film 130′ and the substrate structure 20 after the irradiation of the light was smaller than an adhesive strength between the first release film 130′ and the substrate structure 20 before the irradiation of the light. For example, the adhesive strength between the first release film 130′ and the semiconductor substrate 210 before the irradiation of the light may be from 0.5 N/inch to 5 N/inch, and the adhesive strength between the first release film 130′ and the semiconductor substrate 210 after the irradiation of the light may be from 0.01 N/inch to 0.05 N/inch. 0.5 N/inch to 5 N/inch correspond to 51 gf/inch to 510 gf/inch, and 0.01 N/inch to 0.05 N/inch correspond to 1.02 gf/inch to 5.1 gf/inch. Unlike that shown in the figure, the semiconductor substrate 210 may be a bare wafer substrate, such as a bare silicon wafer. Other conductive elements or circuits on a surface of the bare wafer substrate may not be exposed. However, the semiconductor substrate 210 according to an embodiment of the inventive concept is not limited to the bare wafer.
  • FIG. 5A is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. For concise description, a previously described element may be identified by the same reference number without repeating an overlapping description thereof.
  • Referring to FIG. 5A, a semiconductor package may include a package substrate 900, an outer terminal 950, an interposer bump 840, an interposer substrate 800, a semiconductor device 400, and a first semiconductor chip 200Z. The semiconductor package may further include at least one of a second semiconductor chip 300, a mold layer 500, a first under-fill layer 510, a second under-fill layers 520, or a heat-dissipation structure 700.
  • The package substrate 900 may include an insulating base layer 910, a substrate pad 920, and an internal interconnection line 930. The insulating base layer 910 may include a plurality of stacked layers. The substrate pad 920 may be exposed on a top surface of the package substrate 900. The internal interconnection line 930 may be disposed in the insulating base layer 910 and may be electrically connected to the substrate pad 920. In the present specification, the expression “two elements are electrically connected or coupled to each other” may mean that the elements are directly connected or coupled to each other or are indirectly connected or coupled to each other through other conductive elements. The expression “an element is electrically connected to the package substrate 900” may mean that the element is electrically connected to the internal interconnection line 930. The substrate pad 920 and the internal interconnection line 930 may be formed of or include at least one of metallic materials (e.g., copper, aluminum, tungsten, and/or titanium). As an example, the package substrate 900 may be a printed circuit board (PCB). As another example, a redistribution layer may be used as the package substrate 900.
  • The outer terminal 950 may be provided on a bottom surface of the package substrate 900 and may be coupled to the internal interconnection line 930. The outer terminal 950 may include a solder ball. The outer terminal 950 may be formed of or include at least one of solder materials. The solder materials may include tin (Sn), silver (Ag), zinc (Zn), and/or alloys thereof.
  • The interposer substrate 800 may be disposed on the package substrate 900. The interposer substrate 800 may include a metal pad 820 and a metal line 830. The metal pad 820 may be exposed on a top surface of the interposer substrate 800. The metal line 830 may be provided in the interposer substrate 800 and may be coupled to the metal pad 820. In the present specification, the expression “an element is electrically connected to the interposer substrate 800” may mean that the element is electrically connected to the metal line 830. The metal pad 820 and the metal line 830 may be formed of or include at least one of metallic materials (e.g., copper, aluminum, tungsten, and/or titanium).
  • The interposer bump 840 may be interposed between the package substrate 900 and the interposer substrate 800 and may be coupled to the package substrate 900 and the interposer substrate 800. The interposer bump 840 may include a solder material.
  • The semiconductor device 400 may be disposed on the top surface of the interposer substrate 800. The semiconductor device 400 may include a semiconductor chip (e.g., a logic chip, a buffer chip, or a system-on-chip (SOC)). The semiconductor device 400 may include, for example, an application specific integrated circuit (ASIC) chip or an application processor (AP) chip. The semiconductor device 400 may be a semiconductor chip including at least one of a central processing unit (CPU) or a graphic processing unit (GPU).
  • A bump terminal 440 may be interposed between the interposer substrate 800 and the semiconductor device 400 and may be electrically connected to the interposer substrate 800 and the semiconductor device 400. For example, the bump terminal 440 may include a solder material. The first under-fill layer 510 may be provided in a gap region between the interposer substrate 800 and the semiconductor device 400 to encapsulate or seal the bump terminal 440. The first under-fill layer 510 may be formed of or include an insulating polymer (e.g., epoxy-based polymers).
  • The first semiconductor chip 200Z may be disposed on the top surface of the interposer substrate 800 to be horizontally spaced apart from the semiconductor device 400. In an embodiment, the semiconductor package may include a plurality of the first semiconductor chips 200Z, which are stacked on the top surface of the interposer substrate 800. The first semiconductor chips 200Z may be semiconductor chips that are of a kind different from the semiconductor device 400. The first semiconductor chips 200Z may include high bandwidth memory (HBM) chips. The first semiconductor chips 200Z may include DRAM chips. However, the lowermost of the first semiconductor chips 200Z may be a logic chip and may have a different function from the semiconductor device 400. A width of the lowermost of the first semiconductor chips 200Z may be different from a width of the others of the first semiconductor chips 200Z, but the inventive concept is not limited to this example.
  • Each of the first semiconductor chips 200Z may include the first solder bumps 240Z, a first circuit layer 220Z, a first semiconductor substrate 210Z, and the first penetration structures 230Z. The first solder bumps 240Z, the first circuit layer 220Z, the first semiconductor substrate 210Z, and the first penetration structures 230Z may be substantially the same as the solder bumps 240Z, the circuit layer 220, the semiconductor substrate 210, and the penetration structures 230, respectively, which were described with reference to FIGS. 4C to 4F. The first semiconductor chips 200Z may include a lower semiconductor chip and an upper semiconductor chip, which are adjacent to each other. The upper semiconductor chip may be disposed on the lower semiconductor chip. The first solder bumps 240Z of the upper semiconductor chip may be electrically connected to the first penetration structures 230Z, respectively, of the lower semiconductor chip. In the present specification, the expression “an element is electrically connected to the semiconductor chip” may mean that the element is electrically connected to the integrated circuits in the semiconductor chip. At least one of the first semiconductor chips 200Z may be formed by the process of dicing the substrate structure 20 using the processing tape 10, described with reference to FIGS. 4A to 4F. Any residue of the first release layer 130 may not be left on the top surfaces of the first semiconductor chips 200Z. This may make it possible to realize reliable electric connection between the first semiconductor chips 200Z.
  • The second semiconductor chip 300 may be disposed on the uppermost one of the first semiconductor chips 200Z. The second semiconductor chip 300 may include a high bandwidth memory chip. The second semiconductor chip 300 may include a second semiconductor substrate 310, a second circuit layer 320, and second solder bumps 340, but may not include any penetration structure. The second solder bumps 340 may be respectively coupled to the first penetration structures 230Z of the uppermost one of the first semiconductor chips 200Z. The second semiconductor substrate 310, the second circuit layer 320, and the second solder bumps 340 may be substantially the same as the semiconductor substrate 210, the circuit layer 220, and the solder bumps 240Z, respectively, described with reference to FIGS. 4C to 4F. In an embodiment, the second semiconductor chip 300 may be omitted.
  • The second under-fill layers 520 may be respectively provided in first gap regions between the first semiconductor chips 200Z to seal corresponding ones of the first solder bumps 240Z. The second under-fill layers 520 may be further provided in a second gap region between the substrate structure 20 and the lowermost of the first semiconductor chips 200Z and a third gap region between the uppermost one of the first semiconductor chips 200Z and the second semiconductor chip 300. The second under-fill layers 520 may be formed of or include an insulating polymer (e.g., epoxy-based polymers).
  • The mold layer 500 may be provided on the package substrate 900 to cover the semiconductor device 400, the first semiconductor chips 200Z, and the second semiconductor chip 300. The mold layer 500 may be formed to expose the top surface of the semiconductor device 400 and the top surface of the second semiconductor chip 300, but the inventive concept is not limited to this example. The mold layer 500 may be formed of or include an insulating polymer (e.g., epoxy-based polymers).
  • The heat-dissipation structure 700 may be disposed on at least one of the top surface of the semiconductor device 400 and the top surface of the second semiconductor chip 300. The heat-dissipation structure 700 may further cover the top surface of the mold layer 500. The heat-dissipation structure 700 may be further extended to cover the side surface of the mold layer 500. The heat-dissipation structure 700 may include a heat slug or a heat sink. The heat-dissipation structure 700 may be formed of or include materials (e.g., metals) having high thermal conductivity.
  • FIG. 5B is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. For concise description, a previously described element may be identified by the same reference number without repeating an overlapping description thereof.
  • Referring to FIG. 5B, the semiconductor package may include the package substrate 900, the outer terminal 950, the first semiconductor chip 200Z, and the second semiconductor chip 300. The semiconductor package may further include the mold layer 500, a first under-fill pattern 511, second under-fill patterns 521, and the heat-dissipation structure 700. The package substrate 900 and the outer terminal 950 may be substantially the same as those described with reference to FIG. 5A.
  • The first semiconductor chip 200Z may be mounted on the package substrate 900. The first semiconductor chip 200Z may be one of the semiconductor chips 200, which are formed by a process of dicing the substrate structure 20 using the processing tape 10, described with reference to FIGS. 4A to 4F. Each of the first semiconductor chips 200Z may include the first solder bumps 240Z, the first circuit layer 220Z, the first semiconductor substrate 210Z, and the first penetration structures 230Z. The first solder bumps 240Z may be coupled to a plurality of substrate pads 920, respectively. The first semiconductor chip 200Z may be a logic chip.
  • The second semiconductor chip 300 may be disposed on the first semiconductor chip 200Z. The second semiconductor chip 300 may be configured to have features similar to the second semiconductor chip 300 described with reference to FIG. 5A. For example, the second semiconductor chip 300 may include the second solder bumps 340, the second circuit layer 320, and the second semiconductor substrate 310, but may not include any penetration structure. The second semiconductor chip 300 may be a memory chip (e.g., an SRAM chip). The second solder bumps 340 may be electrically connected to the first penetration structures 230Z, respectively. Accordingly, the second semiconductor chip 300 may be electrically connected to the first semiconductor chip 200Z or the outer terminal 950. In an embodiment, a plurality of the second semiconductor chips 300 may be provided and may be horizontally spaced apart from each other.
  • The first under-fill pattern 511 may be provided in a first gap region between the package substrate 900 and the first semiconductor chip 200Z to seal the first solder bumps 240Z. The second under-fill patterns 521 may be respectively disposed in second gap regions between the first semiconductor chip 200Z and the second semiconductor chips 300. Each of the second under-fill patterns 521 may seal corresponding ones of the second solder bumps 340. The first under-fill pattern 511 and the second under-fill patterns 521 may be formed of or include an insulating polymer (e.g., epoxy-based polymers).
  • The mold layer 500 may be disposed on the top surface of the first semiconductor chip 200Z to cover the second semiconductor chips 300. The mold layer 500 may be provided to expose the top surfaces of the second semiconductor chips 300. The heat-dissipation structure 700 may be disposed on the top surfaces of the second semiconductor chips 300 and the top surface of the mold layer 500. The heat-dissipation structure 700 may be extended to cover the side surface of the mold layer 500.
  • According to an embodiment of the inventive concept, a processing release tape may include a first release layer. A substrate structure may be attached to the first release layer, and then, a process of processing the substrate structure may be performed. An adhesive strength between the first release layer and the substrate structure may be high enough to allow the first release layer to stably fasten the substrate structure during the processing process. After the processing process, light may be irradiated to the processing release tape. In this case, the adhesive strength between the first release layer and the substrate structure may be sufficiently lowered. Accordingly, the substrate structure may be easily detached from the first release layer. There may be no residue of the first release layer on the detached substrate structure.
  • While example embodiments of the inventive concept have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.

Claims (21)

1. A processing tape, comprising:
a base layer;
an adhesive layer disposed on the base layer;
a protection release film on the adhesive layer; and
a first release layer interposed between the adhesive layer and the protection release film,
wherein the first release layer comprises a silicone-based material and is non-photo-curable.
2. The processing tape of claim 1, wherein the adhesive layer comprises an acrylate-based material and is photo-curable.
3. The processing tape of claim 1, further comprising a second release layer interposed between the first release layer and the protection release film,
wherein the second release layer comprises a silicone acrylate-based material.
4. The processing tape of claim 1, wherein the silicone-based material of the first release layer is represented by Chemical Formula 1:
Figure US20220020627A1-20220120-C00004
where R1 and R2 each independently includes one selected from a hydrogen, an alkyl group having 1 to 5 carbon atoms, an alkyl substituted silyl group having 1 to 5 carbon atoms, —NH2, an amino alkyl group having 1 to 5 carbon atoms, an alkyl amino group having 1 to 5 carbon atoms, a hydroxyl group (—OH), a hydroxy alkyl group having 1 to 5 carbon atoms, an isocyanate group (NCO), an alkyl group having 1 to 5 carbon atoms substituted with isocyanate, and an alkyl group having 1 to 5 carbon atoms substituted with epoxy group, R3 each independently includes one selected from an alkyl group having 1 to 3 carbon atoms and n is 1 to 410.
5. The processing tape of claim 4, wherein the first release layer has a thermosetting property, and
in the Chemical Formula 1, R1 and R2 is each independently any one selected from —NH2, an amino alkyl group having 1 to 5 carbon atoms, an alkyl amino group having 1 to 5 carbon atoms, —OH, a hydroxy alkyl group having 1 to 5 carbon atoms, an isocyanate group (NCO), an alkyl group having 1 to 5 carbon atoms substituted with isocyanate, and an alkyl group having 1 to 5 carbon atoms substituted with epoxy group.
6. The processing tape of claim 4, wherein the first release layer has a non-thermosetting property, and
in the Chemical Formula 1, R1 and R2 are hydrogen.
7. The processing tape of claim 1, wherein the first release layer is 0.01 phr (parts per hundred rubber) to 30 phr of the adhesive layer.
8. The processing tape of claim 1, wherein a thickness of the first release layer ranges from 0.01 μm to 10 μm.
9. The processing tape of claim 1, wherein the first release layer is chemically bonded to the adhesive layer.
10. The processing tape of claim 1, wherein the adhesive layer comprises a pressure sensing adhesive layer and a thickness of the adhesive layer ranges from 5 μm to 50 μm.
11. A method of fabricating a semiconductor device, comprising:
preparing a processing tape including an adhesive layer, a first release layer, and a protection release film stacked on a base layer;
removing the protection release film while leaving at least a portion of the first release layer, which is used as a first release film, on the adhesive layer;
attaching a substrate structure to the first release film;
performing a processing process on the substrate structure to form a processed substrate structure; and
detaching the processed substrate structure from the first release film,
wherein the first release film is non-photo-curable.
12. The method of claim 11, wherein the adhesive layer comprises a photo-curable material,
the method further comprises irradiating a light to the adhesive layer and the first release film, before the detaching of the processed substrate structure.
13. The method of claim 12, wherein an adhesive strength between the first release film and the substrate structure after the irradiation of the light is smaller than an adhesive strength between the first release film and the substrate structure before the irradiation of the light.
14. The method of claim 13, wherein the adhesive strength between the first release film and the substrate structure before the irradiation of the light ranges from 0.5 N/inch to 5 N/inch, and
the adhesive strength between the first release film and the substrate structure after the irradiation of the light ranges from 0.01 N/inch to 0.05 N/inch.
15. The method of claim 11, wherein the performing of the processing process on the substrate structure comprises dicing the substrate structure to form a plurality of semiconductor chips.
16. The method of claim 11, wherein the first release film is 10 wt % to 50 wt % of the first release layer.
17. The method of claim 11, wherein the processing tape further comprises a second release layer interposed between the first release layer and the protection release film,
the second release layer comprises silicone acrylate whose weight average molecular weight ranges from 100 g/mol to 30,000 g/mol, and
during the removing of the protection release film, the second release layer is removed along with the protection release film.
18. A processing tape, comprising:
a base layer including a polymer;
a pressure sensing adhesive layer disposed on the base layer;
a protection release film on the pressure sensing adhesive layer;
a first release layer interposed between the pressure sensing adhesive layer and the protection release film; and
a second release layer interposed between the first release layer and the protection release film, the second release layer comprising silicone acrylate,
wherein the first release layer is non-photo-curable,
the pressure sensing adhesive layer comprises a photo-curable material,
the first release layer is 0.01 phr to 30 phr of the pressure sensing adhesive layer,
a thickness of the first release layer ranges from 0.01 μm to 10 μm, and
the first release layer comprising a material represented by Chemical Formula 1,
Figure US20220020627A1-20220120-C00005
where R1 and R2 each independently includes one selected from a hydrogen, an alkyl group having 1 to 5 carbon atoms, an alkyl substituted silyl group having 1 to 5 carbon atoms, —NH2, an amino alkyl group having 1 to 5 carbon atoms, an alkyl amino group having 1 to 5 carbon atoms, a hydroxyl group (—OH), a hydroxy alkyl group having 1 to 5 carbon atoms, an isocyanate group (NCO), an alkyl group having 1 to 5 carbon atoms substituted with isocyanate, and an alkyl group having 1 to 5 carbon atoms substituted with epoxy group, R3 each independently includes one selected from an alkyl group having 1 to 3 carbon atoms, and n is 1 to 410.
19. The processing tape of claim 18, wherein the pressure sensing adhesive layer comprise polymer, which contains an alkyne group and an alcohol group, and
a thickness of the pressure sensing adhesive layer ranges from 5 μm to 50 μm.
20. The processing tape of claim 18, wherein the base layer comprises at least one of poly ethyleneterephthalate (PET), poly olefin (PO), poly (vinyl alcohol) (PVA), poly(l-naphthylamine) (PNA), poly ether ether ketone (PEEK), and/or mixtures thereof, and
the protection release film comprises at least one of PET, PO, PVA, PNA, PEEK, and/or mixtures thereof.
21-30: (canceled)
US17/191,163 2020-07-14 2021-03-03 Processing tape and method of fabricating a semiconductor device using the same Active 2042-07-11 US12040213B2 (en)

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Citations (5)

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US20080166513A1 (en) * 2007-01-10 2008-07-10 Nitto Denko Corporation Heat-activated adhesive sheet
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Publication number Priority date Publication date Assignee Title
US4977006A (en) * 1988-07-20 1990-12-11 Revolutionary Adhesive Materials, Ltd. Adhesive labels and methods for their manufacture
US20080057251A1 (en) * 2006-09-01 2008-03-06 General Electric Company Laminates utilizing pressure sensitive adhesive composition and conventional silicon liners
US20080166513A1 (en) * 2007-01-10 2008-07-10 Nitto Denko Corporation Heat-activated adhesive sheet
US9006081B2 (en) * 2011-06-22 2015-04-14 Samsung Electronics Co., Ltd. Methods of processing substrates
WO2015020413A1 (en) * 2013-08-05 2015-02-12 주식회사 엘지화학 Adhesive composition, adhesive film, and method for preparing organic electronic device by using same
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