US20220005697A1 - Replacement metal gate device structure and method of manufacturing same - Google Patents
Replacement metal gate device structure and method of manufacturing same Download PDFInfo
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- US20220005697A1 US20220005697A1 US17/165,078 US202117165078A US2022005697A1 US 20220005697 A1 US20220005697 A1 US 20220005697A1 US 202117165078 A US202117165078 A US 202117165078A US 2022005697 A1 US2022005697 A1 US 2022005697A1
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- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052751 metal Inorganic materials 0.000 title description 71
- 239000002184 metal Substances 0.000 title description 71
- 239000004065 semiconductor Substances 0.000 claims abstract description 174
- 239000000463 material Substances 0.000 claims abstract description 92
- 239000002019 doping agent Substances 0.000 claims abstract description 68
- 239000010410 layer Substances 0.000 claims description 264
- 238000000034 method Methods 0.000 claims description 63
- 239000000758 substrate Substances 0.000 claims description 34
- 238000000151 deposition Methods 0.000 claims description 25
- 125000006850 spacer group Chemical group 0.000 claims description 25
- 239000004215 Carbon black (E152) Substances 0.000 claims description 22
- 229930195733 hydrocarbon Natural products 0.000 claims description 22
- 150000002430 hydrocarbons Chemical class 0.000 claims description 22
- 239000006227 byproduct Substances 0.000 claims description 19
- 239000012535 impurity Substances 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 11
- 229910052799 carbon Inorganic materials 0.000 claims description 11
- 239000002243 precursor Substances 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 9
- -1 fluorine ions Chemical class 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 8
- 239000011737 fluorine Substances 0.000 claims description 7
- 229910052731 fluorine Inorganic materials 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical compound [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 229910021324 titanium aluminide Inorganic materials 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052787 antimony Inorganic materials 0.000 claims description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052797 bismuth Inorganic materials 0.000 claims description 3
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 description 25
- 239000003989 dielectric material Substances 0.000 description 20
- 238000005229 chemical vapour deposition Methods 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 13
- 230000009969 flowable effect Effects 0.000 description 13
- 150000004820 halides Chemical class 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 230000008021 deposition Effects 0.000 description 11
- 238000005137 deposition process Methods 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000000137 annealing Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 6
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000011068 loading method Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- WEAMLHXSIBDPGN-UHFFFAOYSA-N (4-hydroxy-3-methylphenyl) thiocyanate Chemical compound CC1=CC(SC#N)=CC=C1O WEAMLHXSIBDPGN-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- KPGXUAIFQMJJFB-UHFFFAOYSA-H tungsten hexachloride Chemical compound Cl[W](Cl)(Cl)(Cl)(Cl)Cl KPGXUAIFQMJJFB-UHFFFAOYSA-H 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 229910021355 zirconium silicide Inorganic materials 0.000 description 2
- 229910000951 Aluminide Inorganic materials 0.000 description 1
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910003091 WCl6 Inorganic materials 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- KMTYGNUPYSXKGJ-UHFFFAOYSA-N [Si+4].[Si+4].[Ni++] Chemical compound [Si+4].[Si+4].[Ni++] KMTYGNUPYSXKGJ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- RVSGESPTHDDNTH-UHFFFAOYSA-N alumane;tantalum Chemical compound [AlH3].[Ta] RVSGESPTHDDNTH-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- MANYRMJQFFSZKJ-UHFFFAOYSA-N bis($l^{2}-silanylidene)tantalum Chemical compound [Si]=[Ta]=[Si] MANYRMJQFFSZKJ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- PWYYWQHXAPXYMF-UHFFFAOYSA-N strontium(2+) Chemical compound [Sr+2] PWYYWQHXAPXYMF-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Definitions
- a three-dimensional device architecture such as a fin-type field effect transistor (FinFET) and the use of a metal gate structure with a high-k gate dielectric material.
- FinFET fin-type field effect transistor
- metal gates are manufactured using a replacement metal gate process.
- FIG. 1 is a flowchart of a method of fabricating a semiconductor device, in accordance with some embodiments.
- FIG. 2 is a cross-sectional view of a semiconductor device after forming a semiconductor fin, isolation structures, and a dummy gate structure over the semiconductor fin, in accordance with some embodiments.
- FIG. 3 is a cross-sectional view of the semiconductor device of FIG. 2 after forming source/drain regions in the semiconductor fin on opposite sides of a dummy gate stack in the dummy gate structure, in accordance with some embodiments.
- FIG. 4 is a cross-sectional view of the semiconductor device of FIG. 3 after depositing an inter-layer dielectric (ILD) layer over the source/drain regions and the isolation structures, in accordance with some embodiments.
- ILD inter-layer dielectric
- FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4 after removing the dummy gate stack to forming an opening, in accordance with some embodiments.
- FIG. 6 is a cross-sectional view of the semiconductor device of FIG. 5 after depositing a gate dielectric layer along sidewalls and bottom of the opening and above the ILD layer, in accordance with some embodiments.
- FIG. 7 is a cross-sectional view of the semiconductor device of FIG. 6 after depositing a work function material layer over the gate dielectric layer, in accordance with some embodiments.
- FIG. 8 is a cross-sectional view of the semiconductor device of FIG. 7 after depositing a gate electrode layer over the work function material layer, in accordance with some embodiments.
- FIG. 9 is a cross-sectional view of the semiconductor device of FIG. 8 after removing excess portions of the gate dielectric layer, the work function material layer, and the gate electrode layer above the ILD layer, in accordance with some embodiments.
- FIG. 10 is a perspective view of a FinFET, in accordance with some embodiments.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- a dummy gate stack is formed over a semiconductor fin as a placeholder for a functional gate stack. Then, gate spacers are formed surrounding the dummy gate stack. After source/drain regions are formed adjacent to the gate spacer, the dummy gate stack is removed, leaving an opening surrounded by the spacer. Finally, a metal gate is formed in the opening.
- the metal gate includes a high-k gate dielectric layer, a work function metal layer, and a metal gate electrode layer.
- Low resistance metals such as tungsten are often used as the metal gate electrode material.
- Processes for depositing bulk tungsten layers involve hydrogen reduction of tungsten-containing precursors in chemical vapor deposition (CVD) processes.
- CVD chemical vapor deposition
- a halide by-product such as fluoride or chloride
- WF 6 tungsten hexafluoride
- WCl 6 tungsten hexachloride
- dopants are introduced into the work function metal layer.
- a dopant is a species added into a lattice structure of a material that is different from the main components of the material.
- the dopants occupy locations in a lattice structure of the work function metal, which would otherwise enable the halide by-product to diffuse into the underlying gate dielectric layer, thereby blocking the available diffusion routes through which the halide by-product is diffused.
- the introduction of the dopants in the work function metal layer thus helps to prevent the halide by-product from diffusing to the underlying gate dielectric layer.
- FIG. 1 is a flowchart illustrating a method 100 of fabricating a semiconductor device 200 comprising a metal gate structure, in accordance with some embodiments of the present disclosure.
- FIGS. 2 through 9 are cross-sectional views of the semiconductor device 200 in various stages of a manufacturing process, in accordance with some embodiments.
- the method 100 is discussed in detail below, with reference to the semiconductor device 200 , in FIGS. 2-9 .
- additional operations are performed before, during, and/or after the method 100 , or some of the operations described are replaced, and/or eliminated.
- additional features are added to the semiconductor device 200 .
- some of the features described below are replaced or eliminated.
- the semiconductor device 200 includes a FinFET.
- the method 100 comprises an operation 102 , in which an initial structure of a semiconductor device 200 is formed on a substrate 202 .
- the initial structure of the semiconductor device 200 includes a semiconductor fin 204 extending upwardly from the substrate 202 , a plurality of isolation structures over the substrate 202 and surrounding a bottom portion of the semiconductor fin 204 , and a dummy gate structure 210 over a portion of the semiconductor fin 204 .
- FIG. 2 shows a single semiconductor fin 204 , one of ordinary skill in the art would understand that some embodiments include multiple semiconductor fins formed over the substrate 202 .
- FIG. 2 shows a single semiconductor fin 204 , one of ordinary skill in the art would understand that some embodiments include multiple semiconductor fins formed over the substrate 202 .
- FIG. 1 shows a single semiconductor fin 204 , one of ordinary skill in the art would understand that some embodiments include multiple semiconductor fins formed over the substrate 202 .
- FIG. 2 shows a single dummy gate structure 210
- one of ordinary skill in the art would understand that some embodiments include additional dummy gate structure(s) similar to and parallel to the dummy gate structure 210 .
- One of ordinary skill in the art would further understand that in some embodiments a single dummy gate structure will extend across multiple semiconductor fins.
- the semiconductor fin 204 is formed by first providing a semiconductor substrate 202 .
- the semiconductor substrate is a bulk semiconductor substrate.
- a “bulk” semiconductor substrate refers to a substrate that is entirely composed of at least one semiconductor material.
- the bulk semiconductor substrate includes a semiconductor material or a stack of semiconductor materials such as, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon doped silicon (Si:C), silicon germanium carbon (SiGeC), or an III-V compound semiconductor such as, for example, gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (AlGaAs), gall
- the bulk semiconductor substrate includes a single crystalline semiconductor material such as, for example, single crystalline silicon. In some embodiments, the bulk semiconductor substrate is doped depending on design requirements. In some embodiments, the bulk semiconductor substrate is doped with p-type dopants or n-type dopants.
- p-type refers to the addition of impurities that creates deficiencies of valence electrons to an intrinsic semiconductor. Exemplary p-type dopants, i.e., p-type impurities, include, but are not limited to, boron, aluminum, gallium, and indium.
- N-type refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor.
- n-type dopants include, but are not limited to, antimony, arsenic, and phosphorous.
- the semiconductor substrate is a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer formed on an insulator layer (not shown).
- the top semiconductor layer includes the above-mentioned semiconductor material such as, for example, Si, Ge, SiGe, Si:C, SiGeC, or an III-V compound semiconductor including GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, or GaInASP.
- the insulator layer is, for example, a silicon oxide layer, or the like.
- the insulator layer is provided over a substrate, typically a silicon or glass substrate.
- the semiconductor substrate 202 is then patterned to form trenches therein.
- the trenches define the semiconductor fin 204 in the upper portion of the semiconductor substrate, while the substrate 202 represents a remaining portion of the semiconductor substrate.
- the semiconductor substrate is patterned using suitable lithography and etching processes. For example, a mask layer (not shown) is applied over a topmost surface of the semiconductor substrate and lithographically patterned to define a set of areas covered by a patterned mask layer.
- the mask layer is a photoresist layer.
- the mask layer is a photoresist layer in conjunction with hardmask layer(s).
- the semiconductor substrate is then patterned by an anisotropic etch using the patterned mask layer as an etch mask.
- a dry etch such as, for example, a reactive ion etch (RIE) or a plasma etch is used.
- RIE reactive ion etch
- a wet etch using a chemical etchant is used.
- a combination of dry etch and wet etch is used.
- the patterned mask layer is removed, for example, by oxygen plasma or ashing.
- the semiconductor fin 204 is formed utilizing a sidewall image transfer (SIT) process.
- SIT sidewall image transfer
- spacers are formed on a mandrel. The mandrel is removed and the remaining spacers are used as a hard mask to etch the semiconductor substrate. The spacers are then removed after semiconductor fins are formed.
- sequential SIT processes are utilized to form semiconductor fins with highly scaled fin width and pitches.
- the isolation structures are formed within trenches so that the semiconductor fin 204 protrudes from between neighboring isolation structures.
- the isolation structures surround a bottom portion of the semiconductor fin 204 to electrically isolate the semiconductor fin 204 from neighboring semiconductor fins (not shown).
- the isolation structures surround a plurality of fins 204 .
- the isolation structures include silicon oxide, silicon nitride, silicon oxynitride, and/or other suitable insulating material.
- the isolation structures include a multi-layer structure, for example, having one or more thermal oxide liner layers disposed on the bottom portion of the semiconductor fin 204 and the substrate 202 .
- the isolation structure are shallow trench isolation (STI) structures. Other isolation structures such as filed oxide, local oxidation of silicon (LOCOS), and/or other suitable structures are possible.
- the isolation structures are formed by filling trenches with an insulating material using suitable deposition processes.
- the deposition of the insulating material is performed, for example, by CVD, plasma enhance chemical vapor deposition (PECVD), or spin coating.
- the isolation structures include silicon oxide formed by a flowable CVD process (FCVD) during which a flowable oxide is deposited and a post-deposition anneal is then performed to convert the flowable oxide into silicon oxide.
- FCVD flowable CVD process
- Excess deposited insulating material is subsequently removed from above the top surface of the semiconductor fin 204 , for example, by a chemical mechanical planarization (CMP) process.
- CMP chemical mechanical planarization
- the top surfaces of the isolation structures are coplanar with the top surface of the semiconductor fin 204 .
- the isolation structures are recessed relative to the top surface of the semiconductor fin 204 .
- an etch back process that is selective to the semiconductor material of the semiconductor fin 204 is performed to recess the isolation structures.
- a wet etch employing dilute hydrofluoric acid is performed to recess the isolation structures. The top portion of the semiconductor fin 204 is thus physically exposed.
- the dummy gate structure 210 is formed traversing the semiconductor fin 204 .
- the dummy gate structure 210 includes a dummy gate stack ( 212 , 214 , 216 ) wrapping around a portion of the semiconductor fin 204 that becomes a channel region 204 C of the resulting FinFET.
- the term “dummy gate stack” is used throughout the present disclosure to denote a material stack that serves as a placeholder for a functional gate stack to be subsequently formed.
- functional gate stack refers to a permanent gate stack used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical fields.
- the dummy gate stack ( 212 , 214 , 216 ) include one or more material layers, such as, a dummy gate dielectric layer 212 , a dummy gate electrode layer 214 , a dummy gate cap layer 216 , or other suitable layers.
- the dummy gate dielectric layer 212 is over the semiconductor fin 204 .
- the dummy gate dielectric layer 212 includes a dielectric material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride.
- the dummy gate dielectric layer 212 is formed utilizing a deposition process such as, for example, CVD, PECVD, atomic layer deposition (ALD), or physical vapor deposition (PVD).
- the dummy gate dielectric layer 212 is formed by conversion of a surface portion of the semiconductor fin utilizing chemical oxidation, thermal oxidation, or nitridation.
- the dummy gate electrode layer 214 is over the dummy gate dielectric layer 212 .
- the dummy gate electrode layer 214 includes a semiconductor material such as polysilicon or a silicon-containing semiconductor alloy such as SiGe.
- the dummy gate electrode layer 214 is formed by a suitable deposition process such as, for example, CVD, PECVD, ALD, or PVD.
- the dummy gate cap layer 216 is over the dummy gate electrode layer 214 .
- the dummy gate cap layer 216 includes a dielectric material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride.
- the dummy gate cap layer 216 is formed utilizing a deposition process such as, for example, CVD, PECVD, ALD, PVD.
- the various layers in the dummy gate stack ( 212 , 214 , 216 ) are deposited as blanket layers. Then the blanket layers are patterned using lithography and etching processes to remove portions of the blanket layers. The remaining portions of the blanket layers over the channel region 204 C of semiconductor fin 204 constitute the dummy gate stack ( 212 , 314 , 216 ).
- the lithography process includes forming a photoresist layer (resist) overlying the topmost surface of the blanket layers, exposing the resist to a pattern, performing post-exposure baking, and developing the resist to form a patterned photoresist layer.
- the pattern in the photoresist layer is sequentially transferred into the blanket layers by at least one anisotropic etch.
- the anisotropic etch is a dry etch such as, for example, RIE.
- the patterned photoresist layer is removed, for example, by wet stripping or plasma ashing.
- the dummy gate structure 210 further includes gate spacers 218 along sidewalls of the dummy gate stack ( 212 , 214 , 216 ).
- the gate spacers 218 include a material different from the material(s) for the dummy gate stack ( 212 , 214 , 216 ).
- the gate spacers 218 include a dielectric material such as, for example, silicon nitride, silicon carbonitride, silicon oxynitride, or silicon carbon oxynitride.
- the gate spacers 218 include a single layer. In some embodiments, the gate spacers 218 include multiple layers of dielectric materials.
- the gate spacers 218 are formed by conformally depositing spacer material(s) over the semiconductor fin 204 , the isolation structures and the dummy gate stack ( 212 , 214 , 216 ) using a conformal deposition process such as, for example, CVD or ALD. Thereafter, an anisotropic etch is performed to remove horizontal portions of the deposited spacer material(s) to form the gate spacers 218 .
- the anisotropic etch includes a dry etch such as, for example, RIE.
- the method 100 proceeds to operation 104 , in which a source/drain region and a drain region (collectively referred to source/drain regions 220 ) are formed in portions of the semiconductor fin 204 on opposite sides of the dummy gate stack ( 212 , 214 , 216 ), in accordance with some embodiments.
- the names “source” and “drain” are interchangeable based on the voltage that is applied to those terminals when the resulting FinFET is operated.
- the source/drain regions 220 are doped semiconductor regions.
- the source/drain regions 220 include p-type dopants such as, for example, boron for a p-type FinFET.
- the source/drain regions 220 include n-type dopants such as, for example, arsenic or phosphorus for an n-type FinFET.
- the source/drain regions 220 includes an epitaxial semiconductor material that is able to apply a stress on the channel region 204 C of the semiconductor fin 204 to improve carrier mobility.
- the source/drain regions 220 include SiGe that exerts a compressive stress towards the channel region 204 C of the semiconductor fin 204 .
- the source/drain regions 220 include silicon phosphorous (SiP) or Si:C that exerts a tensile stress towards the channel region 204 C of the semiconductor fin 204 .
- the source/drain regions 220 are formed by implanting dopants into portions of the semiconductor fin 204 that are not covered by the dummy gate stack ( 212 , 214 , 216 ) using, for example, ion implantation. In some embodiments, the source/drain regions 220 are formed by epitaxial growing a semiconductor material on portions of the semiconductor fin 204 that are not covered by the dummy gate stack ( 212 , 214 , 216 ). In still some further embodiments, the source/drain regions 220 are formed by etching recesses in the semiconductor fin 204 followed by performing an epitaxy to grow a semiconductor material in the recesses ( FIG. 3 ).
- the recesses are formed in the semiconductor fin 204 , for example, by an anisotropic etch, an isotropic etch, or a combination thereof.
- a dry etch such as, for example, RIE, is performed to remove the semiconductor material of the semiconductor fin 204 selective to the dielectric materials of the dummy gate cap layer 216 , gate spacers 218 , and the isolation structures, thereby forming the recesses.
- a timed wet etch using an etchant solution of tetramethylammonium hydroxide (TMAH) or carbon tetrafluoride (CF 4 ) is performed to form the recesses.
- the recesses are formed to have faceted surfaces.
- the recesses have a substantially trapezoidal shape or a diamond shape. Alternatively, the recesses have other shapes, such as rectangular, rounded or elliptical shapes. In some embodiments, the recesses are formed to extend under the gate spacer 218 . In some embodiments, the recesses extend under the gate spacer 218 by a distance substantially equal to the width of the gate spacers 218 . The edges of the recesses are thus aligned with inner sidewalls of the gate spacer 218 .
- a semiconductor material is deposited in recesses to provide the source/drain regions 220 .
- a selective epitaxial growth process is performed to deposit the semiconductor material in the recesses.
- the term “epitaxial growth and/or deposition” means the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same (or nearly the same) crystalline characteristics as the semiconductor material of the deposition surface.
- the deposited semiconductor material grows only on exposed semiconductor surfaces, i.e., surfaces of the recesses in the semiconductor fin 204 and does not grow on dielectric surfaces, such as surfaces of the isolation structures, the dummy gate cap layer 216 and the gate spacers 218 .
- a mask (not shown) is used to prevent the semiconductor material from growing in unwanted regions of the semiconductor fin 204 .
- the epitaxial growth process includes metalorganic chemical vapor deposition (MOCVD), molecular beam deposition (MBE), low pressure chemical vapor deposition (LPCVD), or other suitable deposition processes.
- MOCVD metalorganic chemical vapor deposition
- MBE molecular beam deposition
- LPCVD low pressure chemical vapor deposition
- the epitaxial growth process continues until top surfaces of the source/drain regions 220 above the top surface of the semiconductor fin 204 .
- the epitaxial growth process is continued until the top surfaces of the source/drain regions 220 are coplanar with the top surface of the semiconductor fin 204 .
- the source/drain regions 220 are in-situ doped with dopants of p-type or n-type during the epitaxial growth process.
- the source/drain regions 220 are undoped during the epitaxial growth process, and are doped during a subsequent doping process.
- the subsequent doping process is achieved by an ion implantation, plasma immersion ion implantation, gas and/or solid source diffusion, other suitable processes, and/or combinations thereof.
- source/drain regions 220 are further exposed to an annealing process to active the dopants in the source/drain regions 220 after forming the source/drain regions 220 and/or after the subsequent doping process.
- the dopants in the source/drain regions 220 are activated by a thermal annealing process including a rapid thermal annealing process, a laser annealing process, or a furnace annealing process.
- the method 100 proceeds to operation 106 , in which an inter-layer dielectric (ILD) layer 230 is deposited over the source/drain regions 220 and the isolation structures.
- ILD inter-layer dielectric
- the ILD layer 230 fills the gap between the dummy gate structure 210 and adjacent dummy gate structures (not shown).
- one or more etching processes are performed to remove various components of the dummy gate stack ( 212 , 214 , 216 ) selective to the semiconductor material of the semiconductor fin 204 and the dielectric materials of the gate spacers 218 , the isolation structures, and the ILD layer 230 .
- the etching processes include a wet etch, a dry etch, or a combination thereof.
- a dry etch using chlorine-containing gases or fluorine-containing gases is performed.
- a wet etch using an etchant solution of TMAH or diluted hydrofluoric acid is performed
- the gate dielectric layer 244 includes a high-k dielectric material having a dielectric constant greater than 3.9.
- Exemplary high-k dielectric materials include, but are not limited to, hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), strontium titanium oxide (SrTiO 3 ), lanthanum Aluminum oxide (LaAlO 3 ), and yttrium oxide (Y 2 O 3 ).
- the gate dielectric layer 244 is deposited as a conformal layer using a suitable deposition process including, for example, CVD, PECVD, PVD, or ALD.
- a work function metal layer 246 is deposited over the gate dielectric layer 244 .
- the work function metal layer 246 includes a metal having a work function suitable to turn the work function of the resulting FinFET.
- the work function metal layer 246 includes a high work function metal having a work function value of about 4.7 eV or more for a p-type FinFET.
- a thickness of the work function metal layer 246 ranges from about 3 nanometers (nm) to about 9 nm.
- the work function metal layer 246 includes a low work function metal having a work function value of about 4.5 eV or less for an n-type FinFET.
- n-type work function metals include tantalum (Ta), titanium aluminide (TiAl), tantalum aluminide (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), other suitable n-type work function materials, or combinations thereof.
- the work function metal layer 246 includes TiAl for an n-type FinFET.
- the dopants occupy locations in a lattice structure of the work function metal which would otherwise enable the halide by-product generated during the deposition process used for formation of the gate electrode layer 248 ( FIG. 8 ) to diffuse through the work function metal layer 246 into the gate dielectric layer 244 .
- the dopants help to block a number of available diffusion routes through which the halide by-product is able to diffuse into the gate dielectric layer 244 .
- the amount of dopants in the work function metal layer 246 is adjusted to provide a suitable level of blocking effect. In some embodiments, the concentration of dopants in the work function metal layer 246 is from about 0.5% to about 5% by weight.
- the concentration of dopants depends on a size of the dopant species and a material of the work function metal layer 246 . For example, as a size of the dopant species increases the concentration of the dopant is in the lower portion of the above range in some instances. In some embodiments, the dopants are distributed uniformly throughout the work function metal layer 246 . In some embodiments, the dopants forms a dopant gradient within the work function metal layer 246 .
- the work function metal layer 246 has a dopant concentration which increase to a maximum as the distance from gate dielectric layer 244 increases and decreases from the maximum as the distance from the gate dielectric layer 244 continues to increase.
- the maximum dopant concentration is at about 2 nm to about 5 nm from an interface between the work function metal layer 246 and the gate dielectric layer 244 .
- the location of the maximum dopant concentration from the interface between the work function metal layer 246 and the gate dielectric layer 244 ranges from about 20% to about 70% of a total thickness of the work function metal layer 246 .
- the in-situ doping process includes introducing a dopant precursor into the deposition chamber during the formation of the work function metal layer 246 .
- the work function metal layer 246 includes TiAl and is formed while in-situ doped using a combination of titanium chloride (TiCl4), TEAL (Al 2 (C 2 H 5 ) 6 ) and other impurities.
- the impurities include a hydrocarbon, chlorine, an organosilicon material or another suitable material.
- an amount of impurities is less than 10% but greater than 0% of a total flow of material into the deposition chamber during formation of the work function metal layer 246 .
- an amount of impurities is less than 5% but greater than 0% of a total flow of material into the deposition chamber during formation of the work function metal layer 246 . In some embodiments, an amount of impurities is less than 1% but greater than 0% of a total flow of material into the deposition chamber during formation of the work function metal layer 246 . As an amount of impurities decreases, a cost of materials for the production process increases. If an amount of impurities is too high, the ability of the impurities will negatively impact the formation of the work function metal layer 246 in some instances.
- the method 100 proceeds to operation 114 , in which a gate electrode layer 248 is deposited over the work function metal layer 246 .
- the gate electrode layer 248 fills the remaining volume of the opening 232 .
- the gate electrode layer 248 includes a low resistance metal such as, for example, tungsten, copper, cobalt and/or other suitable materials.
- the gate electrode layer 248 is deposited by CVD, PVD, plating, and/or other suitable processes.
- the gate electrode layer 248 includes tungsten and is formed by reducing a tungsten-containing precursor such as WF 6 in a reduction gas, such as a diborane (B 2 H 6 ) gas or hydrogen gas (H 2 ).
- a reduction gas such as a diborane (B 2 H 6 ) gas or hydrogen gas (H 2 ).
- the reaction between the tungsten-containing precursor produces metallic tungsten to form the gate electrode layer 248 .
- the reaction also produces by-products such as fluorine ions (F ⁇ ) as well as hydrofluoric acid (HF).
- the gate electrode layer 248 is formed by reducing WF6, for example by WF 6 +3H 2 ⁇ W+HF+5H + +5F ⁇ .
- the dopants in work function metal layer 246 help to prevent these by-products from migrating from the deposited gate electrode layer 248 through the work function metal layer 246 and into the gate dielectric layer 244 .
- the gate dielectric layer 244 is less likely to be damaged and the FinFET is more likely to function as designed.
- the reaction chemistry associated with the formation of the gate electrode layer 248 generates a halide by-product (e.g., fluoride or chloride).
- the halide by-product diffuses through the work function metal layer 246 into the gate dielectric layer 244 , causing the degradation of the gate dielectric material.
- the dopants in the work function metal layer 246 help to block the halide by-product from diffusing into the gate dielectric layer 244 , thereby helps to prevent the degradation of the high-k dielectric material in the underlying gate dielectric layer 244 . Accordingly, the performance and the reliability of the resulting FinFET are improved.
- the method 100 proceeds to operation 116 , in which the excess portions of the gate dielectric layer 244 , the work function metal layer 246 , and the gate electrode layer 248 are removed.
- a planarization process such as, a CMP process is performed to remove portions of the gate dielectric layer 244 , the work function metal layer 246 , and the gate electrode layer 248 from the top surface of the ILD layer 230 .
- the resulting remaining portions of the gate dielectric layer 244 , the work function metal layer 246 and the gate electrode layer 248 in the opening 232 form a functional gate stack 240 over the channel region 204 C of the resulting FinFET.
- each of the remaining portions of the gate dielectric layer 244 , the work function metal layer 246 , and the gate electrode layer 248 includes a bottom portion, and sidewall portions over and connected to the bottom portion.
- FIG. 10 is a perspective view of a FinFET 1000 , in accordance with some embodiments.
- a FinFET 1000 normally includes multiple semiconductor fins 1010 above a semiconductor substrate 1002 , and a gate structure 1020 over the semiconductor substrate 1002 and straddling the semiconductor fins 1010 .
- Shallow trench isolation (STI) structures 1030 are between the semiconductor fins 1010 to electrically insulate the semiconductor fins 1010 .
- FinFETs having different fin numbers are formed in different regions of a semiconductor substrate.
- a manufacturing technique that is employed in manufacturing FinFETs with different fin numbers is to initially form trenches in a semiconductor substrate to define an array of uniformly spaced semiconductor fins across the entire substrate, followed by removing some dummy fins to define active semiconductor fins in device regions.
- STI structures are then formed to separate and isolate the active and dummy semiconductor fins from each other.
- fabricating the STI structures involves deposition of a dielectric material to fill spaces between the active and dummy semiconductor fins.
- Flowable dielectric materials are thus introduced to provide scalable, defect-free, high yield dielectric fill between semiconductor fins, in some instances.
- a flowable dielectric material is deposited to fill gaps between semiconductor fins using a flowable chemical vapor deposition (FCVD) process.
- FCVD flowable chemical vapor deposition
- the flowable dielectric film is cured and then annealed to form a dielectric layer, e.g., silicon dioxide.
- the flowable dielectric film is usually annealed at a high temperature, e.g., greater than 1000° C. to densify the film so as to obtain the desired mechanical property.
- the high temperature annealing consumes silicon atoms in the active semiconductor fins due to the reaction of silicon atoms and the water vapor in the processing chamber, which in turn causes shrinkage of fin critical dimensions (CDs).
- Active semiconductor fins in the different device regions having different fin numbers experience different flowable dielectric loading effects, i.e., the fin CD losses in different device regions are different.
- a larger volume of flowable dielectric between adjacent fins has a more significant impact on the fin CDs than a smaller volume of flowable dielectric.
- the final CDs of active semiconductor fins in different device regions vary based on fin density.
- the fin CD variation in different device regions affects the consistency of device performance.
- the STI structures are formed before the removal of nonfunctional dummy fins such that all the semiconductor fins on the semiconductor substrate experience the same dielectric loading environment during the high temperature annealing of the flowable dielectric material for formation of the STI structures.
- the fin CD shrinkage differences caused by the different flowable dielectric loading effects in different device regions are avoided.
- the more uniform fin CDs help to produce FinFETs with more consistent device performance.
- the semiconductor device includes a semiconductor fin, and a gate stack over the semiconductor fin.
- the gate stack includes a gate dielectric layer over a channel region of the semiconductor fin, a work function material layer over the gate dielectric layer, wherein the work function material layer includes dopants, and a gate electrode layer over the work function material layer.
- the gate dielectric layer is free of the dopants.
- the dopants comprise boron, nitrogen, aluminum, silicon, phosphorus, gallium, germanium, arsenic, indium, tin, antimony, titanium, lead, bismuth, carbon, or a mixture of carbon and a hydrocarbon species, or carbon, a hydrocarbon species and oxygen.
- the dopants includes a hydrocarbon species comprising at least one of CH, CH 2 , or CH 3 .
- the work function material layer has a dopant concentration ranging from about 0.5% to about 5% by weight.
- the work function material layer has a gradient dopant concentration with a maximum dopant concentration at about 5 nm from an interface between the gate dielectric layer and the work function material layer.
- a position of a maximum dopant concentration in the work function material layer from the interface between the work function material layer and the gate dielectric layer ranges from about 20% to about 70% of a total thickness of the work function material layer.
- the gate electrode includes fluorine ions.
- a thickness of the work function material layer ranges from about 3 nanometers (nm) to about 9 nm.
- the work function material layer includes titanium nitride or titanium aluminide.
- the gate electrode layer includes tungsten, cobalt, or copper.
- the semiconductor device includes a semiconductor fin protruding from a substrate, and a gate stack over the semiconductor fin.
- the gate stack includes a gate dielectric layer over a channel region of the semiconductor fin, a work function material layer over the gate dielectric layer, wherein the work function material layer includes a hydrocarbon-containing dopant, and a gate electrode layer over the work function material layer.
- the hydrocarbon species includes at least one of CH, CH 2 , and CH 3 .
- the work function material layer has a concentration of the hydrocarbon-containing dopant ranging from about 0.5% to about 5% by weight. In some embodiments, a concentration of the hydrocarbon-containing dopant varies within the work function material layer.
- the work function material layer has a maximum concentration of the hydrocarbon-containing dopant at about 5 nm from an interface between the gate dielectric layer and the work function material layer.
- Still another aspect of this description relates to a method of fabricating a semiconductor device.
- the method includes forming a dummy gate structure over a semiconductor fin.
- the dummy gate structure includes a dummy gate stack and gate spacers along sidewalls of the dummy gate stack.
- the method further includes forming an inter-layer dielectric (ILD) layer surrounding the dummy gate structure, removing the dummy gate stack to provide an opening exposing a channel region of the semiconductor fin, depositing a gate dielectric layer over bottom and sidewalls of the opening and over the ILD layer, forming a doped work function material layer over the gate dielectric layer using an in-situ doping process, and depositing a gate electrode layer over the doped work function material layer.
- ILD inter-layer dielectric
- forming the doped work function material layer comprises forming the doped work function material layer using a precursor gas mixture having less than 10% impurities. In some embodiments, depositing the gate electrode layer comprises forming by-products in the gate electrode layer. In some embodiments, forming by-products in the gate electrode layer comprises forming fluorine ions in the gate electrode layer. In some embodiments, forming the doped work function material layer includes using the precursor gas mixture includes WF 6 and hydrogen gas.
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Abstract
Description
- As demands to reduce the dimensions of transistor devices continue, challenges from both fabrication and design issues have resulted in the development of a three-dimensional device architecture, such as a fin-type field effect transistor (FinFET) and the use of a metal gate structure with a high-k gate dielectric material. In some instances, metal gates are manufactured using a replacement metal gate process.
- The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not necessarily to scale. On the contrary, the dimensions and spatial relationship(s) of the various features may be arbitrarily enlarged or reduced for clarity. Like reference numerals denote like features throughout specification and drawings.
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FIG. 1 is a flowchart of a method of fabricating a semiconductor device, in accordance with some embodiments. -
FIG. 2 is a cross-sectional view of a semiconductor device after forming a semiconductor fin, isolation structures, and a dummy gate structure over the semiconductor fin, in accordance with some embodiments. -
FIG. 3 is a cross-sectional view of the semiconductor device ofFIG. 2 after forming source/drain regions in the semiconductor fin on opposite sides of a dummy gate stack in the dummy gate structure, in accordance with some embodiments. -
FIG. 4 is a cross-sectional view of the semiconductor device ofFIG. 3 after depositing an inter-layer dielectric (ILD) layer over the source/drain regions and the isolation structures, in accordance with some embodiments. -
FIG. 5 is a cross-sectional view of the semiconductor device ofFIG. 4 after removing the dummy gate stack to forming an opening, in accordance with some embodiments. -
FIG. 6 is a cross-sectional view of the semiconductor device ofFIG. 5 after depositing a gate dielectric layer along sidewalls and bottom of the opening and above the ILD layer, in accordance with some embodiments. -
FIG. 7 is a cross-sectional view of the semiconductor device ofFIG. 6 after depositing a work function material layer over the gate dielectric layer, in accordance with some embodiments. -
FIG. 8 is a cross-sectional view of the semiconductor device ofFIG. 7 after depositing a gate electrode layer over the work function material layer, in accordance with some embodiments. -
FIG. 9 is a cross-sectional view of the semiconductor device ofFIG. 8 after removing excess portions of the gate dielectric layer, the work function material layer, and the gate electrode layer above the ILD layer, in accordance with some embodiments. -
FIG. 10 is a perspective view of a FinFET, in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- In a replacement metal gate process, i.e., gate last process, a dummy gate stack is formed over a semiconductor fin as a placeholder for a functional gate stack. Then, gate spacers are formed surrounding the dummy gate stack. After source/drain regions are formed adjacent to the gate spacer, the dummy gate stack is removed, leaving an opening surrounded by the spacer. Finally, a metal gate is formed in the opening. The metal gate includes a high-k gate dielectric layer, a work function metal layer, and a metal gate electrode layer.
- Low resistance metals such as tungsten are often used as the metal gate electrode material. Processes for depositing bulk tungsten layers involve hydrogen reduction of tungsten-containing precursors in chemical vapor deposition (CVD) processes. One difficulty, however, with tungsten CVD deposition is that a halide by-product, such as fluoride or chloride, generated from the reduction of a halide-containing tungsten precursor, such as tungsten hexafluoride (WF6) or tungsten hexachloride (WCl6), diffuses across the work function metal layer into the underlying gate dielectric layer. The halide by-product, once incorporated into the gate dielectric layer, degrades the gate dielectric material, causing threshold voltage Vt variation and dielectric leakage. These conditions lead to decreased device reliability.
- In some embodiments of the current description, in order to reduce or avoid degradation of the gate dielectric material and performance drifting of the FinFET, dopants are introduced into the work function metal layer. A dopant is a species added into a lattice structure of a material that is different from the main components of the material. The dopants occupy locations in a lattice structure of the work function metal, which would otherwise enable the halide by-product to diffuse into the underlying gate dielectric layer, thereby blocking the available diffusion routes through which the halide by-product is diffused. The introduction of the dopants in the work function metal layer thus helps to prevent the halide by-product from diffusing to the underlying gate dielectric layer.
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FIG. 1 is a flowchart illustrating amethod 100 of fabricating asemiconductor device 200 comprising a metal gate structure, in accordance with some embodiments of the present disclosure.FIGS. 2 through 9 are cross-sectional views of thesemiconductor device 200 in various stages of a manufacturing process, in accordance with some embodiments. Themethod 100 is discussed in detail below, with reference to thesemiconductor device 200, inFIGS. 2-9 . In some embodiments, additional operations are performed before, during, and/or after themethod 100, or some of the operations described are replaced, and/or eliminated. In some embodiments, additional features are added to thesemiconductor device 200. In some embodiments, some of the features described below are replaced or eliminated. One of ordinary skill in the art would understand that although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order. In some embodiments, thesemiconductor device 200 includes a FinFET. - Referring to
FIG. 1 andFIG. 2 , themethod 100 comprises anoperation 102, in which an initial structure of asemiconductor device 200 is formed on asubstrate 202. The initial structure of thesemiconductor device 200 includes asemiconductor fin 204 extending upwardly from thesubstrate 202, a plurality of isolation structures over thesubstrate 202 and surrounding a bottom portion of thesemiconductor fin 204, and adummy gate structure 210 over a portion of thesemiconductor fin 204. AlthoughFIG. 2 shows asingle semiconductor fin 204, one of ordinary skill in the art would understand that some embodiments include multiple semiconductor fins formed over thesubstrate 202. Furthermore, althoughFIG. 2 shows a singledummy gate structure 210, one of ordinary skill in the art would understand that some embodiments include additional dummy gate structure(s) similar to and parallel to thedummy gate structure 210. One of ordinary skill in the art would further understand that in some embodiments a single dummy gate structure will extend across multiple semiconductor fins. - In some embodiments, the
semiconductor fin 204 is formed by first providing asemiconductor substrate 202. In some embodiments, the semiconductor substrate is a bulk semiconductor substrate. A “bulk” semiconductor substrate refers to a substrate that is entirely composed of at least one semiconductor material. In some embodiments, the bulk semiconductor substrate includes a semiconductor material or a stack of semiconductor materials such as, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon doped silicon (Si:C), silicon germanium carbon (SiGeC), or an III-V compound semiconductor such as, for example, gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium indium arsenide phosphide (GaInAsP). In some embodiments, the bulk semiconductor substrate includes a single crystalline semiconductor material such as, for example, single crystalline silicon. In some embodiments, the bulk semiconductor substrate is doped depending on design requirements. In some embodiments, the bulk semiconductor substrate is doped with p-type dopants or n-type dopants. The term “p-type” refers to the addition of impurities that creates deficiencies of valence electrons to an intrinsic semiconductor. Exemplary p-type dopants, i.e., p-type impurities, include, but are not limited to, boron, aluminum, gallium, and indium. “N-type” refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. Exemplary n-type dopants, i.e., n-type impurities, include, but are not limited to, antimony, arsenic, and phosphorous. In some embodiments, the semiconductor substrate is a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer formed on an insulator layer (not shown). The top semiconductor layer includes the above-mentioned semiconductor material such as, for example, Si, Ge, SiGe, Si:C, SiGeC, or an III-V compound semiconductor including GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, or GaInASP. The insulator layer is, for example, a silicon oxide layer, or the like. The insulator layer is provided over a substrate, typically a silicon or glass substrate. - The
semiconductor substrate 202 is then patterned to form trenches therein. The trenches define thesemiconductor fin 204 in the upper portion of the semiconductor substrate, while thesubstrate 202 represents a remaining portion of the semiconductor substrate. In some embodiments, the semiconductor substrate is patterned using suitable lithography and etching processes. For example, a mask layer (not shown) is applied over a topmost surface of the semiconductor substrate and lithographically patterned to define a set of areas covered by a patterned mask layer. In some embodiments, the mask layer is a photoresist layer. In some embodiments, the mask layer is a photoresist layer in conjunction with hardmask layer(s). The semiconductor substrate is then patterned by an anisotropic etch using the patterned mask layer as an etch mask. In some embodiments, a dry etch such as, for example, a reactive ion etch (RIE) or a plasma etch is used. In some embodiments, a wet etch using a chemical etchant is used. In still some further embodiments, a combination of dry etch and wet etch is used. After formation of thesemiconductor fin 204, the patterned mask layer is removed, for example, by oxygen plasma or ashing. Alternatively, in some embodiments, thesemiconductor fin 204 is formed utilizing a sidewall image transfer (SIT) process. In a SIT process, spacers are formed on a mandrel. The mandrel is removed and the remaining spacers are used as a hard mask to etch the semiconductor substrate. The spacers are then removed after semiconductor fins are formed. In some embodiments, sequential SIT processes are utilized to form semiconductor fins with highly scaled fin width and pitches. - After formation of the
semiconductor fin 204, the isolation structures (not shown inFIG. 2 ) are formed within trenches so that thesemiconductor fin 204 protrudes from between neighboring isolation structures. The isolation structures surround a bottom portion of thesemiconductor fin 204 to electrically isolate thesemiconductor fin 204 from neighboring semiconductor fins (not shown). In some embodiments, the isolation structures surround a plurality offins 204. In some embodiments, the isolation structures include silicon oxide, silicon nitride, silicon oxynitride, and/or other suitable insulating material. In some embodiments, the isolation structures include a multi-layer structure, for example, having one or more thermal oxide liner layers disposed on the bottom portion of thesemiconductor fin 204 and thesubstrate 202. In some embodiments, the isolation structure are shallow trench isolation (STI) structures. Other isolation structures such as filed oxide, local oxidation of silicon (LOCOS), and/or other suitable structures are possible. In some embodiments, the isolation structures are formed by filling trenches with an insulating material using suitable deposition processes. In some embodiments, the deposition of the insulating material is performed, for example, by CVD, plasma enhance chemical vapor deposition (PECVD), or spin coating. In some embodiments, the isolation structures include silicon oxide formed by a flowable CVD process (FCVD) during which a flowable oxide is deposited and a post-deposition anneal is then performed to convert the flowable oxide into silicon oxide. Excess deposited insulating material is subsequently removed from above the top surface of thesemiconductor fin 204, for example, by a chemical mechanical planarization (CMP) process. After planarization, the top surfaces of the isolation structures are coplanar with the top surface of thesemiconductor fin 204. Next, the isolation structures are recessed relative to the top surface of thesemiconductor fin 204. In some embodiments, an etch back process that is selective to the semiconductor material of thesemiconductor fin 204 is performed to recess the isolation structures. For example, in instances where the isolation structures include silicon oxide, a wet etch employing dilute hydrofluoric acid is performed to recess the isolation structures. The top portion of thesemiconductor fin 204 is thus physically exposed. - The
dummy gate structure 210 is formed traversing thesemiconductor fin 204. Thedummy gate structure 210 includes a dummy gate stack (212, 214, 216) wrapping around a portion of thesemiconductor fin 204 that becomes achannel region 204C of the resulting FinFET. The term “dummy gate stack” is used throughout the present disclosure to denote a material stack that serves as a placeholder for a functional gate stack to be subsequently formed. e term “functional gate stack” as used herein refers to a permanent gate stack used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical fields. In some embodiments, the dummy gate stack (212, 214, 216) include one or more material layers, such as, a dummygate dielectric layer 212, a dummygate electrode layer 214, a dummygate cap layer 216, or other suitable layers. - The dummy
gate dielectric layer 212 is over thesemiconductor fin 204. In some embodiments, the dummygate dielectric layer 212 includes a dielectric material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the dummygate dielectric layer 212 is formed utilizing a deposition process such as, for example, CVD, PECVD, atomic layer deposition (ALD), or physical vapor deposition (PVD). In some embodiments, the dummygate dielectric layer 212 is formed by conversion of a surface portion of the semiconductor fin utilizing chemical oxidation, thermal oxidation, or nitridation. - The dummy
gate electrode layer 214 is over the dummygate dielectric layer 212. In some embodiments, the dummygate electrode layer 214 includes a semiconductor material such as polysilicon or a silicon-containing semiconductor alloy such as SiGe. In some embodiments, the dummygate electrode layer 214 is formed by a suitable deposition process such as, for example, CVD, PECVD, ALD, or PVD. - The dummy
gate cap layer 216 is over the dummygate electrode layer 214. In some embodiments, the dummygate cap layer 216 includes a dielectric material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the dummygate cap layer 216 is formed utilizing a deposition process such as, for example, CVD, PECVD, ALD, PVD. - In some embodiments, the various layers in the dummy gate stack (212, 214, 216) are deposited as blanket layers. Then the blanket layers are patterned using lithography and etching processes to remove portions of the blanket layers. The remaining portions of the blanket layers over the
channel region 204C ofsemiconductor fin 204 constitute the dummy gate stack (212, 314, 216). In some embodiments, the lithography process includes forming a photoresist layer (resist) overlying the topmost surface of the blanket layers, exposing the resist to a pattern, performing post-exposure baking, and developing the resist to form a patterned photoresist layer. - The pattern in the photoresist layer is sequentially transferred into the blanket layers by at least one anisotropic etch. In some embodiments, the anisotropic etch is a dry etch such as, for example, RIE. After formation of the dummy gate stack (212, 214, 216), the patterned photoresist layer is removed, for example, by wet stripping or plasma ashing.
- The
dummy gate structure 210 further includesgate spacers 218 along sidewalls of the dummy gate stack (212, 214, 216). The gate spacers 218 include a material different from the material(s) for the dummy gate stack (212, 214, 216). In some embodiments, thegate spacers 218 include a dielectric material such as, for example, silicon nitride, silicon carbonitride, silicon oxynitride, or silicon carbon oxynitride. In some embodiments, thegate spacers 218 include a single layer. In some embodiments, thegate spacers 218 include multiple layers of dielectric materials. In some embodiments, thegate spacers 218 are formed by conformally depositing spacer material(s) over thesemiconductor fin 204, the isolation structures and the dummy gate stack (212, 214, 216) using a conformal deposition process such as, for example, CVD or ALD. Thereafter, an anisotropic etch is performed to remove horizontal portions of the deposited spacer material(s) to form thegate spacers 218. In some embodiments, the anisotropic etch includes a dry etch such as, for example, RIE. - Referring to
FIG. 1 andFIG. 3 , themethod 100 proceeds tooperation 104, in which a source/drain region and a drain region (collectively referred to source/drain regions 220) are formed in portions of thesemiconductor fin 204 on opposite sides of the dummy gate stack (212, 214, 216), in accordance with some embodiments. The names “source” and “drain” are interchangeable based on the voltage that is applied to those terminals when the resulting FinFET is operated. - The source/
drain regions 220 are doped semiconductor regions. In some embodiments, the source/drain regions 220 include p-type dopants such as, for example, boron for a p-type FinFET. In some embodiments, the source/drain regions 220 include n-type dopants such as, for example, arsenic or phosphorus for an n-type FinFET. The source/drain regions 220 includes an epitaxial semiconductor material that is able to apply a stress on thechannel region 204C of thesemiconductor fin 204 to improve carrier mobility. In the embodiments in which thesemiconductor device 200 is a p-type FinFET, the source/drain regions 220 include SiGe that exerts a compressive stress towards thechannel region 204C of thesemiconductor fin 204. In the embodiments in which thesemiconductor device 200 is an n-type FET, the source/drain regions 220 include silicon phosphorous (SiP) or Si:C that exerts a tensile stress towards thechannel region 204C of thesemiconductor fin 204. - In some embodiments, the source/
drain regions 220 are formed by implanting dopants into portions of thesemiconductor fin 204 that are not covered by the dummy gate stack (212, 214, 216) using, for example, ion implantation. In some embodiments, the source/drain regions 220 are formed by epitaxial growing a semiconductor material on portions of thesemiconductor fin 204 that are not covered by the dummy gate stack (212, 214, 216). In still some further embodiments, the source/drain regions 220 are formed by etching recesses in thesemiconductor fin 204 followed by performing an epitaxy to grow a semiconductor material in the recesses (FIG. 3 ). In some embodiments, the recesses are formed in thesemiconductor fin 204, for example, by an anisotropic etch, an isotropic etch, or a combination thereof. In some embodiments, a dry etch such as, for example, RIE, is performed to remove the semiconductor material of thesemiconductor fin 204 selective to the dielectric materials of the dummygate cap layer 216,gate spacers 218, and the isolation structures, thereby forming the recesses. In some embodiments, a timed wet etch using an etchant solution of tetramethylammonium hydroxide (TMAH) or carbon tetrafluoride (CF4) is performed to form the recesses. In some embodiments, the recesses are formed to have faceted surfaces. In some embodiments, the recesses have a substantially trapezoidal shape or a diamond shape. Alternatively, the recesses have other shapes, such as rectangular, rounded or elliptical shapes. In some embodiments, the recesses are formed to extend under thegate spacer 218. In some embodiments, the recesses extend under thegate spacer 218 by a distance substantially equal to the width of thegate spacers 218. The edges of the recesses are thus aligned with inner sidewalls of thegate spacer 218. - A semiconductor material is deposited in recesses to provide the source/
drain regions 220. In some embodiments, a selective epitaxial growth process is performed to deposit the semiconductor material in the recesses. The term “epitaxial growth and/or deposition” means the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same (or nearly the same) crystalline characteristics as the semiconductor material of the deposition surface. During the selective epitaxial growth process, the deposited semiconductor material grows only on exposed semiconductor surfaces, i.e., surfaces of the recesses in thesemiconductor fin 204 and does not grow on dielectric surfaces, such as surfaces of the isolation structures, the dummygate cap layer 216 and thegate spacers 218. In some embodiments, a mask (not shown) is used to prevent the semiconductor material from growing in unwanted regions of thesemiconductor fin 204. In some embodiments, the epitaxial growth process includes metalorganic chemical vapor deposition (MOCVD), molecular beam deposition (MBE), low pressure chemical vapor deposition (LPCVD), or other suitable deposition processes. In some embodiments, the epitaxial growth process continues until top surfaces of the source/drain regions 220 above the top surface of thesemiconductor fin 204. In some embodiments, the epitaxial growth process is continued until the top surfaces of the source/drain regions 220 are coplanar with the top surface of thesemiconductor fin 204. In some embodiments, the source/drain regions 220 are in-situ doped with dopants of p-type or n-type during the epitaxial growth process. Alternatively, in some embodiments, the source/drain regions 220 are undoped during the epitaxial growth process, and are doped during a subsequent doping process. The subsequent doping process is achieved by an ion implantation, plasma immersion ion implantation, gas and/or solid source diffusion, other suitable processes, and/or combinations thereof. In some embodiments, source/drain regions 220 are further exposed to an annealing process to active the dopants in the source/drain regions 220 after forming the source/drain regions 220 and/or after the subsequent doping process. In some embodiments, the dopants in the source/drain regions 220 are activated by a thermal annealing process including a rapid thermal annealing process, a laser annealing process, or a furnace annealing process. - Referring to
FIG. 1 andFIG. 4 , themethod 100 proceeds tooperation 106, in which an inter-layer dielectric (ILD)layer 230 is deposited over the source/drain regions 220 and the isolation structures. TheILD layer 230 fills the gap between thedummy gate structure 210 and adjacent dummy gate structures (not shown). In some embodiments, theILD layer 230 includes a dielectric material such as, for example, silicon oxide, silicon nitride, tetraethylorthosilicate (TEOS) oxide, phosphorous-doped silicate glass (PSG), boron-doped silicate glass (BSG), boron-phosphorous-doped silicate glass (PSG), fluorine doped silicate glass, an organosilicate glass (OSG), or a porous dielectric material. In some embodiments, theILD layer 230 is deposited, for example, by CVD, PECVD, FCVD, or spin coating. In some embodiments, theILD layer 230 is deposited to have a top surface above the topmost surface of the dummy gate stack (212, 214, 216) (e.g., the top surface of the dummy gate cap layer 216). TheILD layer 230 is subsequently planarized, for example, by a CMP process and/or a recess etch using thedummy gate cap 216 as a polishing and/or etch stop layer. After the planarization, theILD layer 230 has a top surface coplanar with the topmost surface of the dummy gate stack (212, 214, 216). - Referring to
FIG. 1 andFIG. 5 , themethod 100 proceeds tooperation 108, in which the dummy gate stack (212, 214, 216) is removed, forming anopening 232 exposing thechannel region 204C of thesemiconductor fin 204. Theopening 232 occupies a volume from which the dummy gate stack (212, 214, 216) is removed. Theopening 232 extends through theILD layer 230 and is confined by inner sidewalls of thegate spacer 218. In some embodiments, one or more etching processes are performed to remove various components of the dummy gate stack (212, 214, 216) selective to the semiconductor material of thesemiconductor fin 204 and the dielectric materials of thegate spacers 218, the isolation structures, and theILD layer 230. In some embodiments, the etching processes include a wet etch, a dry etch, or a combination thereof. In some embodiments, a dry etch using chlorine-containing gases or fluorine-containing gases is performed. In some embodiments, a wet etch using an etchant solution of TMAH or diluted hydrofluoric acid is performed - Referring to
FIG. 1 andFIG. 6 , themethod 100 proceeds tooperation 110, in which agate dielectric layer 244 is deposited along sidewalls and bottom of theopening 232 and above theILD layer 230. In some embodiments, prior to depositing thegate dielectric layer 244, aninterfacial layer 242 is formed on the exposed surface of thechannel region 204C of thesemiconductor fin 204 and underneath thegate dielectric layer 244. Theinterfacial layer 242 is optional, and is omitted in some embodiments. - In some embodiments, the
interfacial layer 242 includes a dielectric oxide such as, for example, silicon oxide. In some embodiments, theinterfacial layer 242 is formed through thermal oxidation or chemical oxidation of a surface portion of thechannel region 204C of thesemiconductor fin 204, or by a deposition process such as ALD or CVD. In some embodiments, the chemical oxidation includes exposing thesemiconductor fin 204 to a chemical oxidant such as, ozone, hydrogen peroxide, or the like. - In some embodiments, the
gate dielectric layer 244 includes a high-k dielectric material having a dielectric constant greater than 3.9. Exemplary high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), lanthanum Aluminum oxide (LaAlO3), and yttrium oxide (Y2O3). Thegate dielectric layer 244 is deposited as a conformal layer using a suitable deposition process including, for example, CVD, PECVD, PVD, or ALD. - Referring to
FIG. 1 andFIG. 7 , themethod 100 proceeds tooperation 112, in which a workfunction metal layer 246 is deposited over thegate dielectric layer 244. The workfunction metal layer 246 includes a metal having a work function suitable to turn the work function of the resulting FinFET. In some embodiments, the workfunction metal layer 246 includes a high work function metal having a work function value of about 4.7 eV or more for a p-type FinFET. In some embodiments, a thickness of the workfunction metal layer 246 ranges from about 3 nanometers (nm) to about 9 nm. If a thickness of the workfunction metal layer 246 is too small, a risk of insufficiently adjusting the work function of the gate of the transistor increases in some instances. If a thickness of the workfunction metal layer 246 is too large, a threshold voltage of a resulting transistor will be too large in some instances. Exemplary p-type work function metals include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), zirconium silicide (ZrSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), nickel silicide (NiSi2), tungsten nitride (WN), other suitable p-type work function materials, or combinations thereof. In some embodiments, the workfunction metal layer 246 includes TiN for a p-type FinFET. In some embodiments, the workfunction metal layer 246 includes a low work function metal having a work function value of about 4.5 eV or less for an n-type FinFET. Exemplary n-type work function metals include tantalum (Ta), titanium aluminide (TiAl), tantalum aluminide (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), other suitable n-type work function materials, or combinations thereof. In some embodiments, the workfunction metal layer 246 includes TiAl for an n-type FinFET. - The work
function metal layer 246 is doped with dopants (i.e., impurities) comprising at least one halide-blocking element such as, for example, boron (B), nitrogen (N), aluminum (Al), silicon (Si), phosphorus (P), gallium (Ga), germanium (Ge), arsenic (As), indium (In), tin (Sn), antimony (Sb), titanium (Ti), lead (Pb), bismuth (Bi), and carbon (C), a mixture of carbon and a hydrocarbon species, or a mixture of carbon, a hydrocarbon species and oxygen. The dopants occupy locations in a lattice structure of the work function metal which would otherwise enable the halide by-product generated during the deposition process used for formation of the gate electrode layer 248 (FIG. 8 ) to diffuse through the workfunction metal layer 246 into thegate dielectric layer 244. The dopants help to block a number of available diffusion routes through which the halide by-product is able to diffuse into thegate dielectric layer 244. The amount of dopants in the workfunction metal layer 246 is adjusted to provide a suitable level of blocking effect. In some embodiments, the concentration of dopants in the workfunction metal layer 246 is from about 0.5% to about 5% by weight. If the dopant concentration is too small, the workfunction metal layer 246 will be unable to sufficiently block the halide by-product diffusion, in some instances. If the dopant concentration is too great, the resistance of the workfunction metal layer 246 will be high, in some instances. One of ordinary skill in the art would recognize that the concentration of dopants depends on a size of the dopant species and a material of the workfunction metal layer 246. For example, as a size of the dopant species increases the concentration of the dopant is in the lower portion of the above range in some instances. In some embodiments, the dopants are distributed uniformly throughout the workfunction metal layer 246. In some embodiments, the dopants forms a dopant gradient within the workfunction metal layer 246. In some embodiments, the workfunction metal layer 246 has a dopant concentration which increase to a maximum as the distance fromgate dielectric layer 244 increases and decreases from the maximum as the distance from thegate dielectric layer 244 continues to increase. In some embodiments, the maximum dopant concentration is at about 2 nm to about 5 nm from an interface between the workfunction metal layer 246 and thegate dielectric layer 244. In some embodiments, the location of the maximum dopant concentration from the interface between the workfunction metal layer 246 and thegate dielectric layer 244 ranges from about 20% to about 70% of a total thickness of the workfunction metal layer 246. If the maximum dopant concentration is too close to the interface between the workfunction metal layer 246 and thegate dielectric layer 244, a risk of the dopants entering thegate dielectric layer 244 increases in some instances. If the maximum dopant concentration is too far from the interface between the workfunction metal layer 246 and thegate dielectric layer 244, effectiveness of the dopant in protecting thegate dielectric layer 244 is reduced in some instances. The dopants are confined within the workfunction metal layer 246 such that the underlyinggate dielectric layer 244 and interfacial layer are free of any of these halide-blocking dopants. - In some embodiments, the work
function metal layer 246 is formed using ALD, PVD, CVD, e-beam evaporation, or other suitable deposition processes. In some embodiments, the workfunction metal layer 246 is doped using an ion implantation process after formation of the workfunction metal layer 246. In some embodiments, the ion implantation process is performed at an implantation energy ranging from about 130 kilo-electron volts (KeV) to about 150 KeV. In some embodiments, the workfunction metal layer 246 is doped using an in-situ doping process. In some embodiments, the ion implantation process is performed using an implantation angle ranging from about 5 degrees to about 10 degrees. In some embodiments, the in-situ doping process includes introducing a dopant precursor into the deposition chamber during the formation of the workfunction metal layer 246. In some embodiments, the workfunction metal layer 246 includes TiAl and is formed while in-situ doped using a combination of titanium chloride (TiCl4), TEAL (Al2(C2H5)6) and other impurities. In some embodiments, the impurities include a hydrocarbon, chlorine, an organosilicon material or another suitable material. In some embodiments, an amount of impurities is less than 10% but greater than 0% of a total flow of material into the deposition chamber during formation of the workfunction metal layer 246. In some embodiments, an amount of impurities is less than 5% but greater than 0% of a total flow of material into the deposition chamber during formation of the workfunction metal layer 246. In some embodiments, an amount of impurities is less than 1% but greater than 0% of a total flow of material into the deposition chamber during formation of the workfunction metal layer 246. As an amount of impurities decreases, a cost of materials for the production process increases. If an amount of impurities is too high, the ability of the impurities will negatively impact the formation of the workfunction metal layer 246 in some instances. If the amount of impurities is 0% then the lattice structure of the workfunction metal layer 246 lacks dopants to block by-products from reaching thegate dielectric layer 244. In the embodiments in which the workfunction metal layer 246 is doped with carbon, the impurities include a hydrocarbon (CxHy) such as, for example CO, CO2, CH2O, CH, CH2, CH3, CH4, C2H6, C7H7, C16H10, or another suitable hydrocarbon is co-flowed to the reaction chamber with the precursors that form the workfunction metal layer 246. By filling the spaces within the lattice structure, the hydrocarbon helps to prevent by-products from being able to pass through the lattice structure of the workfunction metal layer 246. - Referring to
FIG. 1 andFIG. 8 , themethod 100 proceeds tooperation 114, in which agate electrode layer 248 is deposited over the workfunction metal layer 246. Thegate electrode layer 248 fills the remaining volume of theopening 232. In some embodiments, thegate electrode layer 248 includes a low resistance metal such as, for example, tungsten, copper, cobalt and/or other suitable materials. In some embodiments, thegate electrode layer 248 is deposited by CVD, PVD, plating, and/or other suitable processes. In some embodiments, thegate electrode layer 248 includes tungsten and is formed by reducing a tungsten-containing precursor such as WF6 in a reduction gas, such as a diborane (B2H6) gas or hydrogen gas (H2). The reaction between the tungsten-containing precursor produces metallic tungsten to form thegate electrode layer 248. The reaction also produces by-products such as fluorine ions (F−) as well as hydrofluoric acid (HF). In some embodiments, thegate electrode layer 248 is formed by reducing WF6, for example by WF6+3H2→W+HF+5H++5F−. The dopants in workfunction metal layer 246 help to prevent these by-products from migrating from the depositedgate electrode layer 248 through the workfunction metal layer 246 and into thegate dielectric layer 244. As a result, thegate dielectric layer 244 is less likely to be damaged and the FinFET is more likely to function as designed. - As noted above, in some instances, the reaction chemistry associated with the formation of the
gate electrode layer 248 generates a halide by-product (e.g., fluoride or chloride). The halide by-product diffuses through the workfunction metal layer 246 into thegate dielectric layer 244, causing the degradation of the gate dielectric material. The dopants in the workfunction metal layer 246 help to block the halide by-product from diffusing into thegate dielectric layer 244, thereby helps to prevent the degradation of the high-k dielectric material in the underlyinggate dielectric layer 244. Accordingly, the performance and the reliability of the resulting FinFET are improved. - Referring to
FIG. 1 andFIG. 9 , themethod 100 proceeds tooperation 116, in which the excess portions of thegate dielectric layer 244, the workfunction metal layer 246, and thegate electrode layer 248 are removed. In some embodiments, a planarization process, such as, a CMP process is performed to remove portions of thegate dielectric layer 244, the workfunction metal layer 246, and thegate electrode layer 248 from the top surface of theILD layer 230. The resulting remaining portions of thegate dielectric layer 244, the workfunction metal layer 246 and thegate electrode layer 248 in theopening 232 form afunctional gate stack 240 over thechannel region 204C of the resulting FinFET. In some embodiments, each of the remaining portions of thegate dielectric layer 244, the workfunction metal layer 246, and thegate electrode layer 248 includes a bottom portion, and sidewall portions over and connected to the bottom portion. -
FIG. 10 is a perspective view of aFinFET 1000, in accordance with some embodiments. AFinFET 1000 normally includesmultiple semiconductor fins 1010 above asemiconductor substrate 1002, and agate structure 1020 over thesemiconductor substrate 1002 and straddling thesemiconductor fins 1010. Shallow trench isolation (STI)structures 1030 are between thesemiconductor fins 1010 to electrically insulate thesemiconductor fins 1010. - In an integrated circuit, FinFETs having different fin numbers are formed in different regions of a semiconductor substrate. A manufacturing technique that is employed in manufacturing FinFETs with different fin numbers is to initially form trenches in a semiconductor substrate to define an array of uniformly spaced semiconductor fins across the entire substrate, followed by removing some dummy fins to define active semiconductor fins in device regions. STI structures are then formed to separate and isolate the active and dummy semiconductor fins from each other. Generally, fabricating the STI structures involves deposition of a dielectric material to fill spaces between the active and dummy semiconductor fins.
- As FinFETs are scaled to meet ever increasing performance and size requirements, the width of the fins has become very small, and the fin pitch has also been significantly decreased. The reduced fin pitch makes filling the dielectric between the fins challenging. Flowable dielectric materials are thus introduced to provide scalable, defect-free, high yield dielectric fill between semiconductor fins, in some instances. When forming STI structures, a flowable dielectric material is deposited to fill gaps between semiconductor fins using a flowable chemical vapor deposition (FCVD) process. After the flowable dielectric film is deposited, the flowable dielectric film is cured and then annealed to form a dielectric layer, e.g., silicon dioxide. The flowable dielectric film is usually annealed at a high temperature, e.g., greater than 1000° C. to densify the film so as to obtain the desired mechanical property.
- The high temperature annealing consumes silicon atoms in the active semiconductor fins due to the reaction of silicon atoms and the water vapor in the processing chamber, which in turn causes shrinkage of fin critical dimensions (CDs). Active semiconductor fins in the different device regions having different fin numbers experience different flowable dielectric loading effects, i.e., the fin CD losses in different device regions are different. A larger volume of flowable dielectric between adjacent fins has a more significant impact on the fin CDs than a smaller volume of flowable dielectric. As a result, the final CDs of active semiconductor fins in different device regions vary based on fin density. The fin CD variation in different device regions affects the consistency of device performance.
- Improving fin CD control provides more consistent device performance in an integrated circuit. In some embodiments, the STI structures are formed before the removal of nonfunctional dummy fins such that all the semiconductor fins on the semiconductor substrate experience the same dielectric loading environment during the high temperature annealing of the flowable dielectric material for formation of the STI structures. By annealing the flowable dielectric material before the fin cut stage, the fin CD shrinkage differences caused by the different flowable dielectric loading effects in different device regions are avoided. The more uniform fin CDs help to produce FinFETs with more consistent device performance.
- One aspect of this description relates to a semiconductor device. The semiconductor device includes a semiconductor fin, and a gate stack over the semiconductor fin. The gate stack includes a gate dielectric layer over a channel region of the semiconductor fin, a work function material layer over the gate dielectric layer, wherein the work function material layer includes dopants, and a gate electrode layer over the work function material layer. The gate dielectric layer is free of the dopants. In some embodiments, the dopants comprise boron, nitrogen, aluminum, silicon, phosphorus, gallium, germanium, arsenic, indium, tin, antimony, titanium, lead, bismuth, carbon, or a mixture of carbon and a hydrocarbon species, or carbon, a hydrocarbon species and oxygen. In some embodiments, the dopants includes a hydrocarbon species comprising at least one of CH, CH2, or CH3. In some embodiments, the work function material layer has a dopant concentration ranging from about 0.5% to about 5% by weight. In some embodiments, the work function material layer has a gradient dopant concentration with a maximum dopant concentration at about 5 nm from an interface between the gate dielectric layer and the work function material layer. In some embodiments, a position of a maximum dopant concentration in the work function material layer from the interface between the work function material layer and the gate dielectric layer ranges from about 20% to about 70% of a total thickness of the work function material layer. In some embodiments, the gate electrode includes fluorine ions. In some embodiments, a thickness of the work function material layer ranges from about 3 nanometers (nm) to about 9 nm. In some embodiments, the work function material layer includes titanium nitride or titanium aluminide. In some embodiments, the gate electrode layer includes tungsten, cobalt, or copper.
- Another aspect of this description relates to a semiconductor device. The semiconductor device includes a semiconductor fin protruding from a substrate, and a gate stack over the semiconductor fin. The gate stack includes a gate dielectric layer over a channel region of the semiconductor fin, a work function material layer over the gate dielectric layer, wherein the work function material layer includes a hydrocarbon-containing dopant, and a gate electrode layer over the work function material layer. In some embodiments, the hydrocarbon species includes at least one of CH, CH2, and CH3. In some embodiments, the work function material layer has a concentration of the hydrocarbon-containing dopant ranging from about 0.5% to about 5% by weight. In some embodiments, a concentration of the hydrocarbon-containing dopant varies within the work function material layer. In some embodiments, the work function material layer has a maximum concentration of the hydrocarbon-containing dopant at about 5 nm from an interface between the gate dielectric layer and the work function material layer.
- Still another aspect of this description relates to a method of fabricating a semiconductor device. The method includes forming a dummy gate structure over a semiconductor fin. The dummy gate structure includes a dummy gate stack and gate spacers along sidewalls of the dummy gate stack. The method further includes forming an inter-layer dielectric (ILD) layer surrounding the dummy gate structure, removing the dummy gate stack to provide an opening exposing a channel region of the semiconductor fin, depositing a gate dielectric layer over bottom and sidewalls of the opening and over the ILD layer, forming a doped work function material layer over the gate dielectric layer using an in-situ doping process, and depositing a gate electrode layer over the doped work function material layer. In some embodiments, forming the doped work function material layer comprises forming the doped work function material layer using a precursor gas mixture having less than 10% impurities. In some embodiments, depositing the gate electrode layer comprises forming by-products in the gate electrode layer. In some embodiments, forming by-products in the gate electrode layer comprises forming fluorine ions in the gate electrode layer. In some embodiments, forming the doped work function material layer includes using the precursor gas mixture includes WF6 and hydrogen gas.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070173008A1 (en) * | 2006-01-20 | 2007-07-26 | International Business Machines Corporation | Introduction of metal impurity to change workfunction of conductive electrodes |
US20090179285A1 (en) * | 2008-01-10 | 2009-07-16 | Bingxi Sun Wood | Metal gate electrodes for replacement gate integration scheme |
US9698241B1 (en) * | 2016-03-16 | 2017-07-04 | GlobalFoundries, Inc. | Integrated circuits with replacement metal gates and methods for fabricating the same |
US20180019164A1 (en) * | 2016-07-14 | 2018-01-18 | International Business Machines Corporation | Method for forming improved liner layer and semiconductor device including the same |
US20180097085A1 (en) * | 2016-09-30 | 2018-04-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20190088555A1 (en) * | 2017-09-18 | 2019-03-21 | Asm Ip Holding B.V. | Method for forming a semiconductor device structure and related semiconductor device structures |
US20200388707A1 (en) * | 2019-06-06 | 2020-12-10 | Globalfoundries Inc. | Semiconductor devices with uniform gate height and method of forming same |
US20210028291A1 (en) * | 2019-07-22 | 2021-01-28 | Samsung Electronics Co., Ltd. | Semiconductor devices having multiple barrier patterns |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US8030718B2 (en) * | 2008-09-12 | 2011-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Local charge and work function engineering on MOSFET |
CN104810368B (en) | 2014-01-28 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Cmos transistor and forming method thereof |
KR102217246B1 (en) * | 2014-11-12 | 2021-02-18 | 삼성전자주식회사 | Integrated circuit device and method of manufacturing the same |
KR102443695B1 (en) * | 2015-08-25 | 2022-09-15 | 삼성전자주식회사 | Method of manufacturing semiconductor device |
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Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070173008A1 (en) * | 2006-01-20 | 2007-07-26 | International Business Machines Corporation | Introduction of metal impurity to change workfunction of conductive electrodes |
US20090179285A1 (en) * | 2008-01-10 | 2009-07-16 | Bingxi Sun Wood | Metal gate electrodes for replacement gate integration scheme |
US9698241B1 (en) * | 2016-03-16 | 2017-07-04 | GlobalFoundries, Inc. | Integrated circuits with replacement metal gates and methods for fabricating the same |
US20180019164A1 (en) * | 2016-07-14 | 2018-01-18 | International Business Machines Corporation | Method for forming improved liner layer and semiconductor device including the same |
US20180097085A1 (en) * | 2016-09-30 | 2018-04-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20190088555A1 (en) * | 2017-09-18 | 2019-03-21 | Asm Ip Holding B.V. | Method for forming a semiconductor device structure and related semiconductor device structures |
US20200388707A1 (en) * | 2019-06-06 | 2020-12-10 | Globalfoundries Inc. | Semiconductor devices with uniform gate height and method of forming same |
US20210028291A1 (en) * | 2019-07-22 | 2021-01-28 | Samsung Electronics Co., Ltd. | Semiconductor devices having multiple barrier patterns |
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