US20210375750A1 - Interconnection structure having increased conductive features and method of manufacturing the same - Google Patents
Interconnection structure having increased conductive features and method of manufacturing the same Download PDFInfo
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- US20210375750A1 US20210375750A1 US16/886,133 US202016886133A US2021375750A1 US 20210375750 A1 US20210375750 A1 US 20210375750A1 US 202016886133 A US202016886133 A US 202016886133A US 2021375750 A1 US2021375750 A1 US 2021375750A1
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
Definitions
- the present disclosure relates to a wiring structure for use in a semiconductor integrated circuit and a method of manufacturing the same, and more particularly, to an interconnect structure of a semiconductor device having conductive features with a high aspect ratio and continuous configuration, and a method of manufacturing the same.
- the semiconductor device includes a substrate, a diffusion barrier layer, a passivation layer and a plurality of conductive features.
- the diffusion barrier layer is disposed on the substrate.
- the passivation layer is disposed on the diffusion barrier layer.
- the plurality of conductive features penetrate through the passivation layer and contact the diffusion barrier layer.
- the conductive features are arranged in an equally-spaced configuration.
- the conductive features have an aspect ratio greater than 1.
- the conductive feature has a thickness less than 37 nm.
- the semiconductor device further comprises a plurality of insulative liners interposed between the conductive features and the passivation layer.
- the passivation layer has a first dielectric constant
- the insulative liners have a second dielectric constant greater than the first dielectric constant
- the substrate includes a semiconductor wafer, at least one main component, a dielectric layer, a wiring layer and at least one plug.
- the main component is disposed in the semiconductor wafer.
- the dielectric layer covers the semiconductor wafer and the main component.
- the wiring layer is surrounded by the dielectric layer, and the plug is disposed in the dielectric layer to connect the main component to the wiring layer.
- the diffusion barrier layer is disposed on the dielectric layer and the wiring layer.
- the semiconductor device further includes a plurality of voids buried in the passivation layer.
- the voids are disposed between the conductive features.
- Another aspect of the present disclosure provides a method of manufacturing a semiconductor device.
- the method includes steps of depositing a diffusion barrier layer on a substrate; depositing a conductive layer on the diffusion barrier layer; patterning the conductive layer using a target pattern as a mask to form a plurality of conductive features spaced by a plurality of trenches; and depositing a passivation layer in the trench.
- the method further includes a step of forming a plurality of insulative liners on peripheries of the conductive features prior to the deposition of the passivation layer.
- the forming of the insulative liners includes steps of depositing an insulative layer to cover the conductive features and the diffusion barrier layer exposed through the trenches, wherein the insulative layer has a topology following the topology of the conductive features and the diffusion barrier layer; and removing portions of the insulative layer on topmost surfaces of the conductive features and the diffusion barrier layer.
- the method further includes a step of enclosing a plurality of voids in the passivation layer.
- the formation of the conductive features includes steps of applying a photosensitive layer on the conductive layer; performing a first exposure process to expose portions of the photosensitive layer to actinic radiation through a mask; performing a second exposure process to expose other portions of the photosensitive layer to actinic radiation through the mask; performing a developing process to remove the portions exposed to the actinic radiation and form the target pattern; and performing an etching process to remove portions of the conductive layer not covered by the target pattern.
- the formation of the conductive features includes steps of forming a sacrificial layer on the conductive layer; applying a first photosensitive layer on the sacrificial layer; performing a first lithography process on the first photosensitive layer to remove portions of the first photosensitive layer exposed to actinic radiation through a mask; performing a first etching process to remove portions of the sacrificial layer not covered by unexposed portions of the first photosensitive layer to form a plurality of sacrificial blocks; applying a second photosensitive layer on the sacrificial blocks; performing a second lithography process on the second photoresist layer to remove portions of the second photosensitive layer exposed to actinic radiation through the mask; performing a second etching process to remove portions of the sacrificial blocks not covered by unexposed portions of the second photosensitive layer to form the target pattern; and performing a third etching process to remove portions of the conductive layer exposed through the target pattern.
- the diffusion barrier layer has a first thickness, and the conductive features have a second thickness greater than the first thickness.
- the second thickness of the conductive feature is less than 37 nm, and an aspect ratio of the conductive feature is greater than 1.
- the density of the conductive features, having continuous configuration, over the substrate can be increased.
- FIG. 1 is a cross-sectional view of a comparative semiconductor device.
- FIG. 2 is a flow diagram illustrating a method of manufacturing a comparative semiconductor device.
- FIGS. 3A through 3D are cross-sectional views of intermediate stages in the formation of the comparative semiconductor device.
- FIGS. 4A and 4B are cross-sectional views of a semiconductor device in accordance with some embodiments of the present disclosure.
- FIG. 5 is a flow diagram illustrating a method of manufacturing a semiconductor device in accordance with some embodiments of the present disclosure.
- FIG. 6 is a cross-sectional view of an intermediate stage in the formation of the semiconductor device in accordance with some embodiments of the present disclosure.
- FIGS. 7A through 7D are cross-sectional views of intermediate stages in the formation of the semiconductor device in accordance with some embodiments of the present disclosure.
- FIGS. 8A through 8G are cross-sectional views of intermediate stages in the formation of the semiconductor device in accordance with some embodiments of the present disclosure.
- FIGS. 9 through 12 are cross-sectional views of intermediate stages in the formation of the semiconductor device in accordance with some embodiments of the present disclosure.
- first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
- FIG. 1 is a cross-sectional view of a comparative semiconductor device 10 .
- the semiconductor device 10 includes a semiconductor substrate 110 , a dielectric layer 122 disposed on the semiconductor substrate 110 , and a plurality of interconnect structures 130 disposed in the dielectric layer 122 .
- the interconnect structures 130 include a conductive feature 132 disposed in the dielectric layer 122 and a diffusion barrier liner 134 sandwiched between the dielectric layer 122 and the conductive feature 132 .
- a portion of the diffusion barrier liner 134 between the dielectric layer 122 and the conductive feature 132 functions as an adhesive layer to prevent the conductive feature 132 from flaking or spalling from the dielectric layer 122 .
- the diffusion barrier liner 134 is further interposed between the semiconductor substrate 110 and the conductive feature 132 if the interconnect structure 130 , formed in back-end-of-line (BEOL) processes, for example, penetrates through the dielectric layer 122 .
- the diffusion barrier liner 134 can isolate the conductive feature 132 from the semiconductor substrate 110 containing silicon, thereby preventing the metal in the conductive feature 132 from diffusing into the semiconductor substrate 110 .
- the interconnect structures 130 formed in the BEOL processes are employed to electrically connect individual devices (not shown) disposed in the semiconductor substrate 110 formed in front-end-of-line (FEOL) processes.
- the comparative semiconductor device 10 shown in FIG. 1 can be manufactured by a method 20 shown in FIG. 2 .
- the method 20 includes a step S 202 of depositing a dielectric layer on a substrate; a step S 204 of creating one or more trenches in the dielectric layer; a step S 206 of depositing a diffusion barrier layer in the trenches; a step S 208 of performing a plating process to deposit a conductive material in the trenches; and a step S 210 of performing a removal process to remove the diffusion barrier layer and the conductive layer above the dielectric layer.
- the following describes an exemplary process flow of the method 20 of manufacturing the comparative semiconductor device 10 .
- the method 20 can begin with the step S 202 , in which the dielectric layer 120 is deposited on a front surface 112 of the semiconductor substrate 110 that has various device elements (not shown). After the deposition of the dielectric layer 120 , a planarizing process can be performed on the dielectric layer 120 to yield an acceptably flat topology.
- a patterned mask 140 is applied on the dielectric layer 120 .
- the patterned mask 140 can be a hard mask and includes a plurality of windows 142 to expose portions of the dielectric layer 120 .
- the patterned mask 140 can be formed by steps including (1) blanketly depositing a sacrificial layer to form the patterned mask 140 on the dielectric layer 120 , (2) coating a photosensitive material on the sacrificial layer 120 , (3) exposing and developing the photosensitive material to form a feature pattern, and (4) performing an etching process to remove portions of the sacrificial layer not covered by the feature pattern to expose the portions of the dielectric layer 120 .
- the method 20 then proceeds to the step S 204 , in which the trenches 150 , as shown in FIG. 3B , are created.
- the dielectric layer 120 can be anisotropically dry-etched, using a reactive ion etching (RIE) process, for example, through the windows 142 to form the trenches 150 , so that a width of the windows 142 is maintained in the trenches 150 .
- the trenches 150 shown in FIG. 3B , penetrate through the remaining dielectric layer 122 to expose portions of the semiconductor substrate 110 .
- the patterned mask 140 is removed using a wet strip process, for example.
- the method 20 proceeds to the step S 206 , in which the diffusion barrier layer 160 is deposited in the trench 150 , as shown in FIG. 3C .
- the diffusion barrier layer 160 having a substantially uniform thickness, covers portions of the semiconductor substrate 110 exposed through the trenches 150 and the remaining dielectric layer 122 , but does not fill the trenches 150 .
- the diffusion barrier layer 160 includes at least one refractory metal, such as tantalum or titanium.
- the method 20 then proceeds to the step S 208 , in which the plating process is performed to fill the trenches 150 with the conductive material 170 , as shown in FIG. 3D .
- the conductive material 170 can be conformally and uniformly deposited, by way of an electroplating process, for example, on the diffusion barrier layer 160 until the trenches 150 are completely filled.
- the conductive material 170 can include copper, aluminum, or the like.
- the method 20 proceeds to the step S 210 , in which at least one removal process is performed to remove the conductive material 170 and the diffusion barrier layer 160 overflowing the trenches 150 , thereby exposing the remaining dielectric layer 122 . Consequently, interconnection structures 130 including a conductive feature 132 and a diffusion barrier liner 134 are formed, and thus the comparative semiconductor device 10 , shown in FIG. 1 , is formed.
- the size of the interconnect structures 130 is reduced, thus increasing an aspect ratio of the trenches 150 in which the interconnect structures 130 are to be formed.
- the aspect ratio of the trenches 150 is increased, it is difficult to fill the trenches 150 with the diffusion barrier layer 160 and the conductive material 170 .
- metal coverage in the bottom of the trenches 150 is reduced to less than ten percent due to the high aspect ratio, and an undercut may be formed.
- the interconnect structures 130 suffer from even lower step coverage at the bottom and corners of the trenches 150 , and thus it may be observed that the interconnect structures 130 have a discontinuous configuration.
- FIG. 4A is a cross-sectional view of a semiconductor device 30 in accordance with some embodiments of the present disclosure.
- the semiconductor device 30 includes an interconnect structure 300 disposed on a substrate 310 .
- the interconnect structure 300 includes a diffusion barrier layer 320 disposed on the substrate 310 , a passivation layer 350 disposed on the diffusion barrier layer 320 , and a plurality of conductive features 332 penetrating through the passivation layer 350 and contacting the diffusion barrier layer 320 .
- the substrate 310 can include one or more main components 3102 formed in or on a semiconductor wafer 3104 , a dielectric layer 3106 covering the semiconductor wafer 3104 and the main components 3102 , a metal wiring layer 3108 (i.e., metallization level M 1 ) surrounded by the dielectric layer 3106 , and one or more (conductive) plugs 3110 disposed in the dielectric layer 3106 to connect the main components 3102 to the wiring layer 3108 .
- the main components 3102 and the plugs 3110 are formed in FEOL processes, and the wiring layer 3108 may be formed in BEOL processes.
- the diffusion barrier layer 320 covers the dielectric layer 3106 and the wiring layer 3108 .
- the diffusion barrier layer 320 between the dielectric layer 3106 and the conductive features 332 , is employed to prevent the conductive feature 332 from flaking or spalling from the dielectric layer 3106 , so that the footprint for the formation of the conductive features 332 can be increased.
- the diffusion barrier layer 320 can be patterned to create a specific route for electrically connecting the main components 3102 .
- the semiconductor device 30 further includes a plurality of insulative liners 342 interposed between conductive features 332 , arranged in an equally-spaced configuration, and the passivation layer 350 .
- the insulative liners 342 function as a sealing layer to prevent the metal in the conductive features 332 from diffusing into the passivation layer 350 .
- the insulative liners 342 and the passivation layer 350 are silicon-containing dielectrics.
- the passivation layer 350 has a first dielectric constant, and the insulative liners 342 have a second dielectric constant greater than the first dielectric constant.
- the passivation layer 350 includes silicon oxide or silicon dioxide, and the insulative liners 342 include silicon carbide or silicon nitride.
- FIG. 4B is a cross-sectional view of a semiconductor device 30 A in accordance with some embodiments of the present disclosure.
- the semiconductor device 30 A includes an interconnect structure 300 A disposed on a substrate 310 .
- the interconnect structure 300 A includes a diffusion barrier layer 320 disposed on the substrate 310 , a plurality of conductive features 332 disposed on the diffusion barrier layer 320 , a passivation layer 352 enclosing the conductive features 332 , a plurality of insulative liners 342 disposed between conductive features 332 , and a plurality of voids 360 , holding an ambient gas (such as air), buried in the passivation layer 352 .
- an ambient gas such as air
- the insulative liners 342 enclosing the conductive features 332 , and the passivation layer 352 , which the conductive features 332 and the insulative liners 342 penetrate, have different dielectric constants.
- the void 360 holds air, which has a dielectric constant or k value of about 1, and which can reduce an effective dielectric constant of the passivation layer 350 . Therefore, RC delay of the interconnect structure 300 A can be reduced and the speed of the signal transmission through the interconnect structure 300 A is thus increased, wherein the RC delay is defined by the product of a resistance (R) of the conductive features 332 and a capacitance (C) between the conductive features 332 and the dielectric layer between the conductive features 332 .
- R resistance
- C capacitance
- FIG. 5 is a flow diagram illustrating a method 50 of manufacturing a semiconductor device 30 in accordance with some embodiments of the present disclosure
- FIGS. 6 through 12 illustrate cross-sectional views of intermediate stages in the formation of the semiconductor device 30 in accordance with some embodiments of the present disclosure.
- the stages shown in FIGS. 6 to 12 are referred to in the flow diagram in FIG. 5 .
- the fabrication stages shown in FIGS. 6 to 12 are discussed in reference to the process steps shown in FIG. 5 .
- a diffusion barrier layer 320 and a conductive layer 330 are sequentially stacked on a substrate 310 according to a step S 502 in FIG. 5 .
- the substrate 310 includes a semiconductor wafer 3104 and one or more main components 3102 disposed in or on the semiconductor wafer 3104 .
- the semiconductor wafer 3104 can be made of silicon. Alternatively or additionally, the semiconductor wafer 3104 may include other elementary semiconductor materials such as germanium. In some embodiments, the semiconductor wafer 3104 is made of a compound semiconductor such as silicon carbide, gallium arsenic, or indium phosphide.
- the semiconductor wafer 3104 is made of an alloy semiconductor such as silicon germanium or silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.
- the semiconductor wafer 3104 can include an epitaxial layer.
- the semiconductor wafer 3104 has an epitaxial layer overlying a bulk semiconductor.
- the semiconductor wafer 3104 can include various doped regions (not shown) doped with p-type dopants, such as boron, and/or n-type dopants, such as phosphorus or arsenic.
- isolation features such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features, can be introduced in the semiconductor wafer 3104 to define and isolate various main components 3102 in the semiconductor wafer 3104 .
- the main components 3102 may be formed in active areas (not shown) defined by the isolation features.
- the main feature 3102 can include active components, such as transistors and/or diodes, and passive components, such as capacitors, resistors or the like.
- the main components 3102 are formed using various processes including deposition, etching, implantation, photolithography, annealing, and or other applicable processes. In some embodiments, the main components 3102 may be formed in the semiconductor wafer 3104 during front-end-of-line (FEOL) processes.
- FEOL front-end-of-line
- the substrate 310 further includes a dielectric layer 3106 , a wiring layer 3108 , and one or more plugs 3110 formed over the semiconductor wafer 3102 and the main components 3104 .
- the plugs 3110 and the wiring layers 3108 are sequentially formed in the dielectric layer 3106 using conventional damascene processes.
- the diffusion barrier layer 320 is deposited on the substrate 310 to cover the dielectric layer 3106 and the wiring layers 3108 .
- the diffusion barrier layer 320 can be deposited on the substrate 310 using a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, for example.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- a planarizing process can be optionally performed on the diffusion barrier layer 320 to yield an acceptably flat topology.
- the diffusion barrier layer 320 can be optionally patterned to create a specific route for electrically connecting the main components 3102 .
- the diffusion barrier layer 320 can be patterned using at least one photolithography process to expose portions of the dielectric layer 3106 and the wiring layer 3108 . After the patterning of the diffusion barrier layer 320 , an insulative material is deposited to cover the exposed dielectric layer 3106 and the wiring layer 3108 to prevent short circuit.
- the diffusion barrier layer 320 can be a single-layered structure including refractory metals (such as tantalum and titanium), refractory metal nitrides, or refractory metal silicon nitrides. Alternatively, the diffusion barrier layer 320 may be a multi-layered structure including two or more refractory metals, refractory metal nitrides, or refractory metal silicon nitrides.
- the conductive layer 330 is conformally formed on the diffusion barrier layer 320 , so that the diffusion barrier layer 320 is buried in the conductive layer 330 .
- the conductive layer 330 is formed using a CVD process, a plating process or another suitable process.
- the conductive layer 330 can include copper, aluminum, or the like.
- a planarizing process can be performed on the conductive layer 330 to yield an acceptably flat topology.
- the diffusion barrier layer 320 has a first thickness T 1
- the conductive layer 330 has a second thickness T 2 greater than the first thickness T 1 .
- the second thickness T 2 is less than 40 nm.
- the second thickness T 2 is about 35 nm.
- the conductive layer 330 is patterned to form a plurality of conductive features 340 according to a step S 504 in FIG. 5 .
- the conductive layer 330 can be patterned using two exposure processes and a develop process on a photosensitive material 410 to form a target pattern 410 a on the conductive layer 330 , and an etching process on the conductive layer 330 using the target pattern 410 a as a mask to form the conductive features 332 , as described with reference to FIGS. 7A to 7D below.
- the conductive layer 330 can be patterned to form the conductive features 332 using two photolithography processes, as described with reference to FIGS. 8A to 8G below.
- a photosensitive layer 410 is applied on the conductive layer 330 by a spin-coating process and then dried using a soft-baking process.
- the soft-baking process can remove solvent from the photosensitive layer 410 , fully cover the conductive layer 330 , and harden the photosensitive layer 410 .
- an antireflective coating (ARC) layer 420 can be optionally deposited on the conductive layer 330 prior to the formation of the photosensitive layer 410 to minimize the optical reflection of the radiation used to expose the photosensitive layer 410 .
- the ARC layer 420 can be formed of an inorganic material, including nitride, using a CVD process, a spin-coating process or another suitable process.
- a mask 430 including a plate 432 and a geometric pattern attached to the plate 432 .
- the plate 432 can be made of glass or quartz, and the geometric pattern includes a plurality of lines 434 arranged in an equally-spaced configuration; that is, the geometric pattern is a line-and-space pattern.
- the geometric pattern has a minimum pitch P that is achievable with current photolithographic equipment, wherein the pitch P represents a length including one line 434 and one space between adjacent lines 434 .
- the pitch P is less than 70 nm.
- the pitch P is about 64 nm.
- a central axis C of the substrate 310 is aligned with one of the spaces between two adjacent lines 434 of the mask 430 .
- a first exposure process is performed to expose the photosensitive layer 410 to actinic radiation 440 through the mask 430 , so that a duplicate of the geometric pattern appears in the photosensitive layer 410 .
- the photosensitive layer 410 is comprised of a plurality of first exposed portions 412 and a plurality of unexposed portions 414 .
- the mask 430 is shifted so that the central axis C of the substrate 310 is aligned with one of the lines 434 of the mask 430 .
- a second exposure process is then performed to expose the unexposed portions 414 (shown in FIG. 7A ) to actinic radiation 440 through the mask 430 .
- the photosensitive layer 410 is comprised of the plurality of first exposed portions 412 , a plurality of second exposed portions 416 , and a plurality of unexposed portions 418 .
- a developing process is performed to preferentially remove the first and second exposed portions 412 and 416 by the developer, such that the target pattern 410 a for etching the conductive layer 330 is formed.
- the double exposure technique splits the unexposed portions 414 from the first exposed process into two complimentary portions during the performing of the second exposure process and creates the target pattern 410 a having half-pitch unexposed portions 418 .
- a post-baking process is performed to drive off the solvent from the target pattern 410 a, and toughens and improves the adhesion of the target pattern 410 a.
- a deep ultraviolet (UV) treatment (baking the target pattern 410 a at about 150 to 200 degrees Celsius in UV light) can be used to further strengthen the target pattern 410 a for better resistance against the subsequent etches.
- At least one etching step is conducted to remove portions of the ARC layer 420 and the conductive layer 330 not covered by the target pattern 410 a; therefore, a plurality of conductive features 332 are formed.
- the ARC layer 420 and the conductive layer 330 can be anisotropically dry-etched, using an RIE etching process, for example, so that the width of spaces between the unexposed portions 418 is maintained in trenches 334 between the conductive features 332 .
- the etching step may utilize multiple etchants, selected based on the materials of the conductive layer 330 and the ARC layer 420 , to sequentially etch the ARC layer 420 and the conductive layer 330 .
- the diffusion barrier layer 320 may serve as an etch-stop layer during the performing of the etching step.
- the target pattern 410 a is removed using a stripping process, for example.
- the target pattern 410 a including photosensitive material can be removed using a wet stripping process.
- the target pattern 410 a made of the photosensitive material is dissolved by a solution such as acetone or strong acids.
- the remaining ARC layer 422 is then removed using a wet-etching process, for example.
- FIGS. 8A to 8G another process for producing the conductive features 332 is disclosed.
- a sacrificial layer 450 is deposited on the conductive layer 330 using a CVD process, for example, and a first photosensitive layer 460 is applied on the conductive layer 330 by a spin-coating process and then dried using a soft-baking process.
- the mask 430 having the geometric pattern is provided, and a first exposure process is performed to expose the first photosensitive layer 460 to actinic radiation 440 through the mask 430 . Consequently, the first photosensitive layer 460 is comprised of a plurality of exposed portions 462 and a plurality of unexposed portions 464 .
- a first developing process is performed to remove the exposed portions 462 of the first photosensitive layer 460 , while the unexposed portions 464 are left in place.
- the unexposed portions 464 of the first photosensitive layer 460 function as a mask for patterning the sacrificial layer 450 .
- a first etching process is performed to remove portions of the sacrificial layer 450 not covered by the unexposed portions 464 of the first photosensitive layer 460 . Consequentially, a plurality of sacrificial blocks 452 are formed.
- the conductive layer 330 serves as an etch-stop layer during the first etching process.
- an ashing process or a wet strip process may be used to remove the first photosensitive layer 460 , wherein the wet strip process may chemically alter the first photosensitive layer 460 so that it no longer adheres to the sacrificial blocks 452 .
- a second photosensitive layer 470 is applied on the sacrificial blocks 452 and in spaces between adjacent sacrificial blocks 452 .
- the mask 430 is shifted to make the central axis C of the substrate 310 be aligned to one of the lines 434 of the mask 430 .
- a second exposure process is then performed to expose the second photosensitive layer 470 to actinic radiation 440 through the mask 430 .
- the second photosensitive layer 470 is comprised of a plurality of exposed portions 472 and a plurality of unexposed portions 474 .
- a second developing process is performed to remove the exposed portions 472 of the second photosensitive layer 470 , while the unexposed portions 474 are left in place.
- the unexposed portions 474 of the second photosensitive layer 470 function as a mask for patterning the sacrificial block 452 .
- a second etching step is conducted to remove portions of the sacrificial block 452 exposed through the unexposed portions 474 of the second photosensitive layer 470 , thereby forming a target pattern 454 for pattern the conductive layer 330 .
- the conductive layer 330 serves as an etch-stop layer during the second etching process as well.
- the unexposed portions 474 of the second photosensitive layer 470 are removed using an ashing process or a wet strip process, for example.
- a third etching process is performed to remove portions of the conductive layer 330 not covered by the target pattern 454 .
- the plurality of conductive features 332 are formed.
- the conductive layer 330 can be anisotropically dry-etched, using an RIE etching process, for example, so that the width of spaces in the target pattern 454 is maintained in trenches 334 between the conductive features 332 .
- the diffusion barrier layer 320 serves as an etch-stop layer during the third etching process.
- the target pattern 454 is removed using a suitable process after the formation of the conductive features 332 .
- an insulative layer 340 is deposited to cover the conductive features 332 and the diffusion barrier layer 320 exposed through the conductive features 332 according to a step S 506 in FIG. 5 .
- the insulative layer 340 can have a uniform thickness.
- the insulative layer 340 has a topology following the topology of the exposed diffusion barrier layer 320 and the conductive features 332 .
- the insulative layer 340 including silicon-containing dielectric, such as silicon carbide or silicon nitride can be deposited using a CVD process, an ALD process, a high-density plasma CVD process or the like.
- portions of the insulative layer 340 covering the diffusion barrier layer 320 and topmost surfaces 3322 of the conductive features 332 are removed using an etching process according to a step S 508 in FIG. 5 .
- a plurality of insulative liners 342 are formed in the trenches 334 , wherein the conductive features 332 are surrounded by the insulative liners 342 .
- an anisotropic etching process is performed to remove horizontal portions of the insulative layer 340 , while the vertical portions of the insulative layer 340 are left on the conductive features 332 .
- the chemistry of the anisotropic etching process can be selective to the material of the insulative layer 340 . In other words, no substantial quantity of the material of the conductive layer 330 is removed during the etching of the horizontal portions of the insulative layer 340 .
- a passivation layer 350 is deposited to fill the trenches 334 between adjacent conductive features 342 according to a step S 510 in FIG. 5 .
- the passivation layer 350 is a dielectric material and is conformally and uniformly deposited on the diffusion barrier layer 320 and the conductive feature 342 .
- the trenches 334 can be entirely filled with the dielectric material by performing a high-density plasma CVD process.
- the passivation layer 350 shown in FIG. 11 is a void-free layer.
- a plurality of voids 360 holding an ambient gas (such as air), can be enclosed in the dielectric material for forming the passivation layer 350 , as shown in FIG. 12 , by performing a CVD process.
- a planarizing process can be performed to remove a portion of the passivation layer 350 above the conductive features 332 .
- the semiconductor components 30 and 30 A shown in FIGS. 4A and 4B are completely formed.
- the conductive feature 332 is formed with continuous configuration using the double exposure (DE) technique or the double patterning (DP) technique. Therefore, the aspect ratio of the conductive features 332 is increased, thereby increasing the density of the conductive feature in the interconnect structure 300 / 300 A.
- the semiconductor device includes a substrate, a diffusion barrier layer disposed on the substrate, a passivation layer disposed on the diffusion barrier layer, and a plurality of conductive features penetrating through the passivation layer and contacting the diffusion barrier layer.
- One aspect of the present disclosure provides a method of manufacturing a semiconductor device.
- the method comprises steps of depositing a diffusion barrier layer on a substrate; depositing a conductive layer on the diffusion barrier layer; patterning the conductive layer using a target pattern as a mask to form a plurality of conductive features spaced by a plurality of trenches; and depositing a passivation layer in the trench.
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Abstract
The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a diffusion barrier layer, a passivation layer, and a plurality of conductive features. The diffusion barrier layer is disposed on the substrate, and the passivation layer is disposed on the diffusion barrier layer. The conductive features penetrate through the passivation layer and contact the diffusion barrier layer.
Description
- The present disclosure relates to a wiring structure for use in a semiconductor integrated circuit and a method of manufacturing the same, and more particularly, to an interconnect structure of a semiconductor device having conductive features with a high aspect ratio and continuous configuration, and a method of manufacturing the same.
- In order to build modem integrated circuits, it is necessary to fabricate millions of active devices such as transistors on a single substrate. These individual devices are electrically connected by means of metal wires to form circuits. Further, interconnects (“vias”) are used to electrically connect lower and upper metal wirings. Since active devices invariably require more than one level of interconnect, a multi-level interconnect structure is a key element for ultra-large-scale integration (ULSI) technology.
- This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this Discussion of the Background section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.
- One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a diffusion barrier layer, a passivation layer and a plurality of conductive features. The diffusion barrier layer is disposed on the substrate. The passivation layer is disposed on the diffusion barrier layer. The plurality of conductive features penetrate through the passivation layer and contact the diffusion barrier layer.
- In some embodiments, the conductive features are arranged in an equally-spaced configuration.
- In some embodiments, the conductive features have an aspect ratio greater than 1.
- In some embodiments, the conductive feature has a thickness less than 37 nm.
- In some embodiments, the semiconductor device further comprises a plurality of insulative liners interposed between the conductive features and the passivation layer.
- In some embodiments, the passivation layer has a first dielectric constant, and the insulative liners have a second dielectric constant greater than the first dielectric constant.
- In some embodiments, the substrate includes a semiconductor wafer, at least one main component, a dielectric layer, a wiring layer and at least one plug. The main component is disposed in the semiconductor wafer. The dielectric layer covers the semiconductor wafer and the main component. The wiring layer is surrounded by the dielectric layer, and the plug is disposed in the dielectric layer to connect the main component to the wiring layer. The diffusion barrier layer is disposed on the dielectric layer and the wiring layer.
- In some embodiments, the semiconductor device further includes a plurality of voids buried in the passivation layer.
- In some embodiments, the voids are disposed between the conductive features.
- Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of depositing a diffusion barrier layer on a substrate; depositing a conductive layer on the diffusion barrier layer; patterning the conductive layer using a target pattern as a mask to form a plurality of conductive features spaced by a plurality of trenches; and depositing a passivation layer in the trench.
- In some embodiments, the method further includes a step of forming a plurality of insulative liners on peripheries of the conductive features prior to the deposition of the passivation layer.
- In some embodiments, the forming of the insulative liners includes steps of depositing an insulative layer to cover the conductive features and the diffusion barrier layer exposed through the trenches, wherein the insulative layer has a topology following the topology of the conductive features and the diffusion barrier layer; and removing portions of the insulative layer on topmost surfaces of the conductive features and the diffusion barrier layer.
- In some embodiments, the method further includes a step of enclosing a plurality of voids in the passivation layer.
- In some embodiments, the formation of the conductive features includes steps of applying a photosensitive layer on the conductive layer; performing a first exposure process to expose portions of the photosensitive layer to actinic radiation through a mask; performing a second exposure process to expose other portions of the photosensitive layer to actinic radiation through the mask; performing a developing process to remove the portions exposed to the actinic radiation and form the target pattern; and performing an etching process to remove portions of the conductive layer not covered by the target pattern.
- In some embodiments, the formation of the conductive features includes steps of forming a sacrificial layer on the conductive layer; applying a first photosensitive layer on the sacrificial layer; performing a first lithography process on the first photosensitive layer to remove portions of the first photosensitive layer exposed to actinic radiation through a mask; performing a first etching process to remove portions of the sacrificial layer not covered by unexposed portions of the first photosensitive layer to form a plurality of sacrificial blocks; applying a second photosensitive layer on the sacrificial blocks; performing a second lithography process on the second photoresist layer to remove portions of the second photosensitive layer exposed to actinic radiation through the mask; performing a second etching process to remove portions of the sacrificial blocks not covered by unexposed portions of the second photosensitive layer to form the target pattern; and performing a third etching process to remove portions of the conductive layer exposed through the target pattern.
- In some embodiments, the diffusion barrier layer has a first thickness, and the conductive features have a second thickness greater than the first thickness.
- In some embodiments, the second thickness of the conductive feature is less than 37 nm, and an aspect ratio of the conductive feature is greater than 1.
- With the above-mentioned configurations of the interconnect structure, the density of the conductive features, having continuous configuration, over the substrate can be increased.
- The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and technical advantages of the disclosure are described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the concepts and specific embodiments disclosed may be utilized as a basis for modifying or designing other structures, or processes, for carrying out the purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit or scope of the disclosure as set forth in the appended claims.
- A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims. The disclosure should also be understood to be coupled to the figures' reference numbers, which refer to similar elements throughout the description.
-
FIG. 1 is a cross-sectional view of a comparative semiconductor device. -
FIG. 2 is a flow diagram illustrating a method of manufacturing a comparative semiconductor device. -
FIGS. 3A through 3D are cross-sectional views of intermediate stages in the formation of the comparative semiconductor device. -
FIGS. 4A and 4B are cross-sectional views of a semiconductor device in accordance with some embodiments of the present disclosure. -
FIG. 5 is a flow diagram illustrating a method of manufacturing a semiconductor device in accordance with some embodiments of the present disclosure. -
FIG. 6 is a cross-sectional view of an intermediate stage in the formation of the semiconductor device in accordance with some embodiments of the present disclosure. -
FIGS. 7A through 7D are cross-sectional views of intermediate stages in the formation of the semiconductor device in accordance with some embodiments of the present disclosure. -
FIGS. 8A through 8G are cross-sectional views of intermediate stages in the formation of the semiconductor device in accordance with some embodiments of the present disclosure. -
FIGS. 9 through 12 are cross-sectional views of intermediate stages in the formation of the semiconductor device in accordance with some embodiments of the present disclosure. - Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.
- It shall be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
- The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
-
FIG. 1 is a cross-sectional view of acomparative semiconductor device 10. Thesemiconductor device 10 includes asemiconductor substrate 110, adielectric layer 122 disposed on thesemiconductor substrate 110, and a plurality ofinterconnect structures 130 disposed in thedielectric layer 122. Theinterconnect structures 130 include aconductive feature 132 disposed in thedielectric layer 122 and adiffusion barrier liner 134 sandwiched between thedielectric layer 122 and theconductive feature 132. A portion of thediffusion barrier liner 134 between thedielectric layer 122 and theconductive feature 132 functions as an adhesive layer to prevent theconductive feature 132 from flaking or spalling from thedielectric layer 122. - It should be noted that the
diffusion barrier liner 134 is further interposed between thesemiconductor substrate 110 and theconductive feature 132 if theinterconnect structure 130, formed in back-end-of-line (BEOL) processes, for example, penetrates through thedielectric layer 122. Thediffusion barrier liner 134 can isolate theconductive feature 132 from thesemiconductor substrate 110 containing silicon, thereby preventing the metal in theconductive feature 132 from diffusing into thesemiconductor substrate 110. Theinterconnect structures 130 formed in the BEOL processes are employed to electrically connect individual devices (not shown) disposed in thesemiconductor substrate 110 formed in front-end-of-line (FEOL) processes. - The
comparative semiconductor device 10 shown inFIG. 1 can be manufactured by amethod 20 shown inFIG. 2 . Referring toFIG. 2 , themethod 20 includes a step S202 of depositing a dielectric layer on a substrate; a step S204 of creating one or more trenches in the dielectric layer; a step S206 of depositing a diffusion barrier layer in the trenches; a step S208 of performing a plating process to deposit a conductive material in the trenches; and a step S210 of performing a removal process to remove the diffusion barrier layer and the conductive layer above the dielectric layer. - The following describes an exemplary process flow of the
method 20 of manufacturing thecomparative semiconductor device 10. - The
method 20 can begin with the step S202, in which thedielectric layer 120 is deposited on afront surface 112 of thesemiconductor substrate 110 that has various device elements (not shown). After the deposition of thedielectric layer 120, a planarizing process can be performed on thedielectric layer 120 to yield an acceptably flat topology. - Next, a
patterned mask 140 is applied on thedielectric layer 120. The patternedmask 140 can be a hard mask and includes a plurality ofwindows 142 to expose portions of thedielectric layer 120. The patternedmask 140 can be formed by steps including (1) blanketly depositing a sacrificial layer to form the patternedmask 140 on thedielectric layer 120, (2) coating a photosensitive material on thesacrificial layer 120, (3) exposing and developing the photosensitive material to form a feature pattern, and (4) performing an etching process to remove portions of the sacrificial layer not covered by the feature pattern to expose the portions of thedielectric layer 120. - The
method 20 then proceeds to the step S204, in which thetrenches 150, as shown inFIG. 3B , are created. Referring toFIGS. 3A and 3B , thedielectric layer 120 can be anisotropically dry-etched, using a reactive ion etching (RIE) process, for example, through thewindows 142 to form thetrenches 150, so that a width of thewindows 142 is maintained in thetrenches 150. Thetrenches 150, shown inFIG. 3B , penetrate through the remainingdielectric layer 122 to expose portions of thesemiconductor substrate 110. After the formation of thetrenches 150, the patternedmask 140 is removed using a wet strip process, for example. - After the formation of the
trenches 150, themethod 20 proceeds to the step S206, in which thediffusion barrier layer 160 is deposited in thetrench 150, as shown inFIG. 3C . Thediffusion barrier layer 160, having a substantially uniform thickness, covers portions of thesemiconductor substrate 110 exposed through thetrenches 150 and the remainingdielectric layer 122, but does not fill thetrenches 150. Thediffusion barrier layer 160 includes at least one refractory metal, such as tantalum or titanium. - The
method 20 then proceeds to the step S208, in which the plating process is performed to fill thetrenches 150 with theconductive material 170, as shown inFIG. 3D . Theconductive material 170 can be conformally and uniformly deposited, by way of an electroplating process, for example, on thediffusion barrier layer 160 until thetrenches 150 are completely filled. Theconductive material 170 can include copper, aluminum, or the like. - Next, the
method 20 proceeds to the step S210, in which at least one removal process is performed to remove theconductive material 170 and thediffusion barrier layer 160 overflowing thetrenches 150, thereby exposing the remainingdielectric layer 122. Consequently,interconnection structures 130 including aconductive feature 132 and adiffusion barrier liner 134 are formed, and thus thecomparative semiconductor device 10, shown inFIG. 1 , is formed. - When the metal design rules are scaled down, the size of the
interconnect structures 130 is reduced, thus increasing an aspect ratio of thetrenches 150 in which theinterconnect structures 130 are to be formed. When the aspect ratio of thetrenches 150 is increased, it is difficult to fill thetrenches 150 with thediffusion barrier layer 160 and theconductive material 170. It is found that metal coverage in the bottom of thetrenches 150 is reduced to less than ten percent due to the high aspect ratio, and an undercut may be formed. Further, it is found that theinterconnect structures 130 suffer from even lower step coverage at the bottom and corners of thetrenches 150, and thus it may be observed that theinterconnect structures 130 have a discontinuous configuration. It should be realized that a resistance of theinterconnect structures 130 having the undercut or the discontinuous configuration is increased, and the reliability of theinterconnect structures 130 and performance of the entire circuit are therefore reduced. Therefore, there is a need for a method other than the damascene method described inFIG. 2 to manufacture reliable interconnect features having high aspect ration and high density. -
FIG. 4A is a cross-sectional view of asemiconductor device 30 in accordance with some embodiments of the present disclosure. Referring toFIG. 4A , thesemiconductor device 30 includes aninterconnect structure 300 disposed on asubstrate 310. Theinterconnect structure 300 includes adiffusion barrier layer 320 disposed on thesubstrate 310, apassivation layer 350 disposed on thediffusion barrier layer 320, and a plurality ofconductive features 332 penetrating through thepassivation layer 350 and contacting thediffusion barrier layer 320. - The
substrate 310 can include one or moremain components 3102 formed in or on asemiconductor wafer 3104, adielectric layer 3106 covering thesemiconductor wafer 3104 and themain components 3102, a metal wiring layer 3108 (i.e., metallization level M1) surrounded by thedielectric layer 3106, and one or more (conductive) plugs 3110 disposed in thedielectric layer 3106 to connect themain components 3102 to thewiring layer 3108. In some embodiments, themain components 3102 and theplugs 3110 are formed in FEOL processes, and thewiring layer 3108 may be formed in BEOL processes. - The
diffusion barrier layer 320, having a substantially uniform thickness, covers thedielectric layer 3106 and thewiring layer 3108. In some embodiments, thediffusion barrier layer 320, between thedielectric layer 3106 and theconductive features 332, is employed to prevent theconductive feature 332 from flaking or spalling from thedielectric layer 3106, so that the footprint for the formation of theconductive features 332 can be increased. In some embodiments, thediffusion barrier layer 320 can be patterned to create a specific route for electrically connecting themain components 3102. - The
semiconductor device 30 further includes a plurality ofinsulative liners 342 interposed betweenconductive features 332, arranged in an equally-spaced configuration, and thepassivation layer 350. Theinsulative liners 342 function as a sealing layer to prevent the metal in theconductive features 332 from diffusing into thepassivation layer 350. Theinsulative liners 342 and thepassivation layer 350 are silicon-containing dielectrics. In some embodiments, thepassivation layer 350 has a first dielectric constant, and theinsulative liners 342 have a second dielectric constant greater than the first dielectric constant. For example, thepassivation layer 350 includes silicon oxide or silicon dioxide, and theinsulative liners 342 include silicon carbide or silicon nitride. -
FIG. 4B is a cross-sectional view of asemiconductor device 30A in accordance with some embodiments of the present disclosure. Referring toFIG. 4B , thesemiconductor device 30A includes aninterconnect structure 300A disposed on asubstrate 310. Theinterconnect structure 300A includes adiffusion barrier layer 320 disposed on thesubstrate 310, a plurality ofconductive features 332 disposed on thediffusion barrier layer 320, apassivation layer 352 enclosing theconductive features 332, a plurality ofinsulative liners 342 disposed betweenconductive features 332, and a plurality ofvoids 360, holding an ambient gas (such as air), buried in thepassivation layer 352. - The
insulative liners 342, enclosing theconductive features 332, and thepassivation layer 352, which the conductive features 332 and theinsulative liners 342 penetrate, have different dielectric constants. Thevoid 360 holds air, which has a dielectric constant or k value of about 1, and which can reduce an effective dielectric constant of thepassivation layer 350. Therefore, RC delay of theinterconnect structure 300A can be reduced and the speed of the signal transmission through theinterconnect structure 300A is thus increased, wherein the RC delay is defined by the product of a resistance (R) of theconductive features 332 and a capacitance (C) between theconductive features 332 and the dielectric layer between the conductive features 332. -
FIG. 5 is a flow diagram illustrating amethod 50 of manufacturing asemiconductor device 30 in accordance with some embodiments of the present disclosure, andFIGS. 6 through 12 illustrate cross-sectional views of intermediate stages in the formation of thesemiconductor device 30 in accordance with some embodiments of the present disclosure. The stages shown inFIGS. 6 to 12 are referred to in the flow diagram inFIG. 5 . In the following discussion, the fabrication stages shown inFIGS. 6 to 12 are discussed in reference to the process steps shown inFIG. 5 . - Referring to
FIG. 6 , adiffusion barrier layer 320 and aconductive layer 330 are sequentially stacked on asubstrate 310 according to a step S502 inFIG. 5 . Thesubstrate 310 includes asemiconductor wafer 3104 and one or moremain components 3102 disposed in or on thesemiconductor wafer 3104. Thesemiconductor wafer 3104 can be made of silicon. Alternatively or additionally, thesemiconductor wafer 3104 may include other elementary semiconductor materials such as germanium. In some embodiments, thesemiconductor wafer 3104 is made of a compound semiconductor such as silicon carbide, gallium arsenic, or indium phosphide. In some embodiments, thesemiconductor wafer 3104 is made of an alloy semiconductor such as silicon germanium or silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, thesemiconductor wafer 3104 can include an epitaxial layer. For example, thesemiconductor wafer 3104 has an epitaxial layer overlying a bulk semiconductor. - The
semiconductor wafer 3104 can include various doped regions (not shown) doped with p-type dopants, such as boron, and/or n-type dopants, such as phosphorus or arsenic. In some embodiments, isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features, can be introduced in thesemiconductor wafer 3104 to define and isolate variousmain components 3102 in thesemiconductor wafer 3104. Themain components 3102 may be formed in active areas (not shown) defined by the isolation features. - The
main feature 3102 can include active components, such as transistors and/or diodes, and passive components, such as capacitors, resistors or the like. Themain components 3102 are formed using various processes including deposition, etching, implantation, photolithography, annealing, and or other applicable processes. In some embodiments, themain components 3102 may be formed in thesemiconductor wafer 3104 during front-end-of-line (FEOL) processes. - The
substrate 310 further includes adielectric layer 3106, awiring layer 3108, and one ormore plugs 3110 formed over thesemiconductor wafer 3102 and themain components 3104. Theplugs 3110 and thewiring layers 3108 are sequentially formed in thedielectric layer 3106 using conventional damascene processes. - After the formation of the
wiring layer 3108 in thesubstrate 310, thediffusion barrier layer 320 is deposited on thesubstrate 310 to cover thedielectric layer 3106 and the wiring layers 3108. Thediffusion barrier layer 320 can be deposited on thesubstrate 310 using a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, for example. In some embodiments, after the deposition of thediffusion barrier layer 320, a planarizing process can be optionally performed on thediffusion barrier layer 320 to yield an acceptably flat topology. Thediffusion barrier layer 320 can be optionally patterned to create a specific route for electrically connecting themain components 3102. Thediffusion barrier layer 320 can be patterned using at least one photolithography process to expose portions of thedielectric layer 3106 and thewiring layer 3108. After the patterning of thediffusion barrier layer 320, an insulative material is deposited to cover the exposeddielectric layer 3106 and thewiring layer 3108 to prevent short circuit. Thediffusion barrier layer 320 can be a single-layered structure including refractory metals (such as tantalum and titanium), refractory metal nitrides, or refractory metal silicon nitrides. Alternatively, thediffusion barrier layer 320 may be a multi-layered structure including two or more refractory metals, refractory metal nitrides, or refractory metal silicon nitrides. - The
conductive layer 330 is conformally formed on thediffusion barrier layer 320, so that thediffusion barrier layer 320 is buried in theconductive layer 330. Theconductive layer 330 is formed using a CVD process, a plating process or another suitable process. Theconductive layer 330 can include copper, aluminum, or the like. In some embodiments, after the deposition of theconductive layer 330, a planarizing process can be performed on theconductive layer 330 to yield an acceptably flat topology. As shown inFIG. 6 , thediffusion barrier layer 320 has a first thickness T1, and theconductive layer 330 has a second thickness T2 greater than the first thickness T1. In some embodiments, the second thickness T2 is less than 40 nm. For example, the second thickness T2 is about 35 nm. - Next, the
conductive layer 330 is patterned to form a plurality ofconductive features 340 according to a step S504 inFIG. 5 . Theconductive layer 330 can be patterned using two exposure processes and a develop process on aphotosensitive material 410 to form atarget pattern 410 a on theconductive layer 330, and an etching process on theconductive layer 330 using thetarget pattern 410 a as a mask to form the conductive features 332, as described with reference toFIGS. 7A to 7D below. Alternatively, theconductive layer 330 can be patterned to form theconductive features 332 using two photolithography processes, as described with reference toFIGS. 8A to 8G below. - Referring to
FIG. 7A , after the formation of theconductive layer 330, aphotosensitive layer 410 is applied on theconductive layer 330 by a spin-coating process and then dried using a soft-baking process. The soft-baking process can remove solvent from thephotosensitive layer 410, fully cover theconductive layer 330, and harden thephotosensitive layer 410. - In some embodiments, an antireflective coating (ARC)
layer 420 can be optionally deposited on theconductive layer 330 prior to the formation of thephotosensitive layer 410 to minimize the optical reflection of the radiation used to expose thephotosensitive layer 410. TheARC layer 420 can be formed of an inorganic material, including nitride, using a CVD process, a spin-coating process or another suitable process. - Next, a
mask 430, including aplate 432 and a geometric pattern attached to theplate 432, is provided. Theplate 432 can be made of glass or quartz, and the geometric pattern includes a plurality oflines 434 arranged in an equally-spaced configuration; that is, the geometric pattern is a line-and-space pattern. The geometric pattern has a minimum pitch P that is achievable with current photolithographic equipment, wherein the pitch P represents a length including oneline 434 and one space betweenadjacent lines 434. In some embodiments, the pitch P is less than 70 nm. For example, the pitch P is about 64 nm. As shown inFIG. 7A , a central axis C of thesubstrate 310 is aligned with one of the spaces between twoadjacent lines 434 of themask 430. - Next, a first exposure process is performed to expose the
photosensitive layer 410 toactinic radiation 440 through themask 430, so that a duplicate of the geometric pattern appears in thephotosensitive layer 410. After the first exposure process, thephotosensitive layer 410 is comprised of a plurality of first exposedportions 412 and a plurality ofunexposed portions 414. - Referring to
FIG. 7B , themask 430 is shifted so that the central axis C of thesubstrate 310 is aligned with one of thelines 434 of themask 430. A second exposure process is then performed to expose the unexposed portions 414 (shown inFIG. 7A ) toactinic radiation 440 through themask 430. Hence, thephotosensitive layer 410 is comprised of the plurality of first exposedportions 412, a plurality of second exposedportions 416, and a plurality ofunexposed portions 418. - Referring to
FIG. 7C , a developing process is performed to preferentially remove the first and second exposedportions target pattern 410 a for etching theconductive layer 330 is formed. The double exposure technique splits theunexposed portions 414 from the first exposed process into two complimentary portions during the performing of the second exposure process and creates thetarget pattern 410 a having half-pitchunexposed portions 418. After the developing step, a post-baking process is performed to drive off the solvent from thetarget pattern 410 a, and toughens and improves the adhesion of thetarget pattern 410 a. In addition, a deep ultraviolet (UV) treatment (baking thetarget pattern 410 a at about 150 to 200 degrees Celsius in UV light) can be used to further strengthen thetarget pattern 410 a for better resistance against the subsequent etches. - Referring to
FIGS. 7C and 7D , at least one etching step is conducted to remove portions of theARC layer 420 and theconductive layer 330 not covered by thetarget pattern 410 a; therefore, a plurality ofconductive features 332 are formed. TheARC layer 420 and theconductive layer 330 can be anisotropically dry-etched, using an RIE etching process, for example, so that the width of spaces between theunexposed portions 418 is maintained intrenches 334 between the conductive features 332. It should be noted that the etching step may utilize multiple etchants, selected based on the materials of theconductive layer 330 and theARC layer 420, to sequentially etch theARC layer 420 and theconductive layer 330. In some embodiments, thediffusion barrier layer 320 may serve as an etch-stop layer during the performing of the etching step. - After the formation of the
conductive features 332, thetarget pattern 410 a is removed using a stripping process, for example. In some embodiments, thetarget pattern 410 a including photosensitive material can be removed using a wet stripping process. In the wet stripping process, thetarget pattern 410 a made of the photosensitive material is dissolved by a solution such as acetone or strong acids. The remainingARC layer 422 is then removed using a wet-etching process, for example. - Referring to
FIGS. 8A to 8G , another process for producing the conductive features 332 is disclosed. Referring toFIG. 8A , after the formation of theconductive layer 330, asacrificial layer 450 is deposited on theconductive layer 330 using a CVD process, for example, and a firstphotosensitive layer 460 is applied on theconductive layer 330 by a spin-coating process and then dried using a soft-baking process. - Next, the
mask 430 having the geometric pattern is provided, and a first exposure process is performed to expose the firstphotosensitive layer 460 toactinic radiation 440 through themask 430. Consequently, the firstphotosensitive layer 460 is comprised of a plurality of exposedportions 462 and a plurality ofunexposed portions 464. - Referring to
FIG. 8B , a first developing process is performed to remove the exposedportions 462 of the firstphotosensitive layer 460, while theunexposed portions 464 are left in place. Theunexposed portions 464 of the firstphotosensitive layer 460 function as a mask for patterning thesacrificial layer 450. - Referring to
FIG. 8C , a first etching process is performed to remove portions of thesacrificial layer 450 not covered by theunexposed portions 464 of the firstphotosensitive layer 460. Consequentially, a plurality ofsacrificial blocks 452 are formed. Theconductive layer 330 serves as an etch-stop layer during the first etching process. After the performing of the first etching step, an ashing process or a wet strip process may be used to remove the firstphotosensitive layer 460, wherein the wet strip process may chemically alter the firstphotosensitive layer 460 so that it no longer adheres to thesacrificial blocks 452. - Referring to
FIG. 8D , after the formation of thesacrificial blocks 452, a secondphotosensitive layer 470 is applied on thesacrificial blocks 452 and in spaces between adjacentsacrificial blocks 452. Next, themask 430 is shifted to make the central axis C of thesubstrate 310 be aligned to one of thelines 434 of themask 430. - A second exposure process is then performed to expose the second
photosensitive layer 470 toactinic radiation 440 through themask 430. Consequentially, the secondphotosensitive layer 470 is comprised of a plurality of exposedportions 472 and a plurality ofunexposed portions 474. - Referring to
FIG. 8E , a second developing process is performed to remove the exposedportions 472 of the secondphotosensitive layer 470, while theunexposed portions 474 are left in place. Theunexposed portions 474 of the secondphotosensitive layer 470 function as a mask for patterning thesacrificial block 452. - Referring to
FIG. 8F , a second etching step is conducted to remove portions of thesacrificial block 452 exposed through theunexposed portions 474 of the secondphotosensitive layer 470, thereby forming atarget pattern 454 for pattern theconductive layer 330. Theconductive layer 330 serves as an etch-stop layer during the second etching process as well. After the performing of the second etching process, theunexposed portions 474 of the secondphotosensitive layer 470, as shown inFIG. 8E , are removed using an ashing process or a wet strip process, for example. - Referring to
FIG. 8G , a third etching process is performed to remove portions of theconductive layer 330 not covered by thetarget pattern 454. Hence, the plurality ofconductive features 332 are formed. Theconductive layer 330 can be anisotropically dry-etched, using an RIE etching process, for example, so that the width of spaces in thetarget pattern 454 is maintained intrenches 334 between the conductive features 332. Thediffusion barrier layer 320 serves as an etch-stop layer during the third etching process. Thetarget pattern 454 is removed using a suitable process after the formation of the conductive features 332. - Referring to
FIG. 9 , after the formation of theconductive features 332, aninsulative layer 340 is deposited to cover theconductive features 332 and thediffusion barrier layer 320 exposed through theconductive features 332 according to a step S506 inFIG. 5 . Theinsulative layer 340 can have a uniform thickness. In other words, theinsulative layer 340 has a topology following the topology of the exposeddiffusion barrier layer 320 and the conductive features 332. For example, theinsulative layer 340 including silicon-containing dielectric, such as silicon carbide or silicon nitride, can be deposited using a CVD process, an ALD process, a high-density plasma CVD process or the like. - Referring to
FIG. 10 , portions of theinsulative layer 340 covering thediffusion barrier layer 320 andtopmost surfaces 3322 of theconductive features 332 are removed using an etching process according to a step S508 inFIG. 5 . Consequentially, a plurality ofinsulative liners 342 are formed in thetrenches 334, wherein theconductive features 332 are surrounded by theinsulative liners 342. Specifically, an anisotropic etching process is performed to remove horizontal portions of theinsulative layer 340, while the vertical portions of theinsulative layer 340 are left on the conductive features 332. The chemistry of the anisotropic etching process can be selective to the material of theinsulative layer 340. In other words, no substantial quantity of the material of theconductive layer 330 is removed during the etching of the horizontal portions of theinsulative layer 340. - Referring to
FIGS. 10 to 12 , apassivation layer 350 is deposited to fill thetrenches 334 between adjacentconductive features 342 according to a step S510 inFIG. 5 . Thepassivation layer 350 is a dielectric material and is conformally and uniformly deposited on thediffusion barrier layer 320 and theconductive feature 342. In some embodiments, thetrenches 334 can be entirely filled with the dielectric material by performing a high-density plasma CVD process. In other words, thepassivation layer 350 shown inFIG. 11 is a void-free layer. Alternatively, a plurality ofvoids 360, holding an ambient gas (such as air), can be enclosed in the dielectric material for forming thepassivation layer 350, as shown inFIG. 12 , by performing a CVD process. - After the deposition of the of the
passivation layer 350, a planarizing process can be performed to remove a portion of thepassivation layer 350 above the conductive features 332. Thus, thesemiconductor components FIGS. 4A and 4B are completely formed. - In conclusion, with the configuration of
interconnect structure 300/300A, theconductive feature 332 is formed with continuous configuration using the double exposure (DE) technique or the double patterning (DP) technique. Therefore, the aspect ratio of theconductive features 332 is increased, thereby increasing the density of the conductive feature in theinterconnect structure 300/300A. - One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a diffusion barrier layer disposed on the substrate, a passivation layer disposed on the diffusion barrier layer, and a plurality of conductive features penetrating through the passivation layer and contacting the diffusion barrier layer.
- One aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method comprises steps of depositing a diffusion barrier layer on a substrate; depositing a conductive layer on the diffusion barrier layer; patterning the conductive layer using a target pattern as a mask to form a plurality of conductive features spaced by a plurality of trenches; and depositing a passivation layer in the trench.
- Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
- Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods and steps.
Claims (9)
1-9. (canceled)
10. A method of manufacturing a semiconductor device, comprising:
depositing a diffusion barrier layer on a substrate;
depositing a conductive layer on the diffusion barrier layer;
patterning the conductive layer using a target pattern as a mask to form a plurality of conductive features spaced by a plurality of trenches; and
depositing a passivation layer in the trench,
wherein the formation of the conductive features comprises:
applying a photosensitive layer on the conductive layer;
performing a first exposure process to expose portions of the photosensitive layer to actinic radiation through a mask;
performing a second exposure process to expose other portions of the photosensitive layer to actinic radiation through the mask;
performing a developing process to remove the portions exposed to the actinic radiation and form the target pattern; and
performing an etching process to remove portions of the conductive layer not covered by the target pattern.
11. The method of claim 10 , further comprising forming a plurality of insulative liners on peripheries of the conductive features prior to the deposition of the passivation layer.
12. The method of claim 11 , wherein the forming of the insulative liners comprises:
depositing an insulative layer to cover the conductive features and portions of the diffusion barrier layer exposed through the trenches, wherein the insulative layer has a topology following the topology of the conductive features and the diffusion barrier layer; and
removing portions of the insulative layer on topmost surfaces of the conductive features and the diffusion barrier layer.
13. The method of claim 10 , further comprising enclosing a plurality of voids in the passivation layer.
14. (canceled)
15. A method of manufacturing a semiconductor device, comprising:
depositing a diffusion barrier layer on a substrate;
depositing a conductive layer on the diffusion barrier layer;
patterning the conductive layer using a target pattern as a mask to form a plurality of conductive features spaced by a plurality of trenches; and
depositing a passivation layer in the trench,
wherein the formation of the conductive features comprises:
forming a sacrificial layer on the conductive layer;
applying a first photosensitive layer on the sacrificial layer;
performing a first lithography process on the first photosensitive layer to remove portions of the first photosensitive layer exposed to actinic radiation through a mask;
performing a first etching process to remove portions of the sacrificial layer not covered by unexposed portions of the first photosensitive layer to form a plurality of sacrificial blocks;
applying a second photosensitive layer on the sacrificial blocks;
performing a second lithography process on the second photoresist layer to remove portions of the second photosensitive layer exposed to actinic radiation through the mask;
performing a second etching process to remove portions of the sacrificial blocks not covered by unexposed portions of the second photosensitive layer to form the target pattern; and
performing a third etching process to remove portions of the conductive layer exposed through the target pattern.
16. The method of claim 10 , wherein the diffusion barrier layer has a first thickness, and the conductive features have a second thickness greater than the first thickness.
17. The method of claim 16 , wherein the second thickness of the conductive feature is less than 37 nm, and an aspect ratio of the conductive features is greater than 1.
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US11164778B2 (en) * | 2019-11-25 | 2021-11-02 | International Business Machines Corporation | Barrier-free vertical interconnect structure |
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