US20210341544A1

US20210341544A1 - Independent ground fault detection using current transformer

Info

Publication number: US20210341544A1
Application number: US16/861,375
Authority: US
Inventors: Robert J. Vovos; Peter A. Carruthers; Andrew S. Clark; Arthur P. Lyons; Benjamin T. Webster
Original assignee: BAE Systems Controls Inc
Current assignee: BAE Systems Controls Inc
Priority date: 2020-04-29
Filing date: 2020-04-29
Publication date: 2021-11-04
Also published as: BR112021013950A2; WO2021221769A1; MX2022013548A; US20230349984A1; MX2021008586A; WO2021222162A1; BR112022022164A2; CA3181405A1; EP4143050A1; CA3126052A1

Abstract

A fault detection system for a system having a single DC input and a plurality of A/C loads such as an electric or hybrid electric vehicle. A plurality of inverters convert DC to 3-phase A/C and supply A/C power to a corresponding individual A/C load. Each inverter includes a common mode current transformer and a controller. An individual corresponding common mode current transformer is coupled to the 3-phase A/C output of the inverter. An individual corresponding controller is coupled to the output of an individual corresponding common mode current transformer and is coupled to an individual corresponding A/C load. Each controller is configured to detect a fault at the individual corresponding A/C load and in the case of detection of a fault at an individual corresponding A/C load, the corresponding controller disables the A/C load.

Description

BACKGROUND

Detection of an A/C ground fault, for example a phase to chassis fault, in the electric drive train and accessory power system of a vehicle has been cause to fault the electric drive/accessory power system as a whole since there was no clear way to detect which component was compromised and all components shared a common energy source (DC-Link). This would mean that the vehicle would be stranded wherever the fault occurs until repairs can be made or the vehicle is towed to a service station. At the vehicle level, the system controller would need to shut down propulsion as well as accessory loads since it could not pinpoint where the fault was and isolate it.
Typical solutions for this problem involve summing current sensors for all three phases. However the combined error in those sensors in some cases is more than the fault current that would need to be detected.

SUMMARY OF THE INVENTION

In one embodiment, a fault detection system is provided for a system having a single DC input and a plurality of A/C loads. One example of such a system is an electric or hybrid electric vehicle. The fault detection system in one embodiment of this disclosure includes a plurality of inverters coupled to the DC power source. The plurality of inverters each convert DC to 3-phase A/C and supply A/C power to a corresponding individual A/C load. The fault detection system includes a plurality of common mode current transformers and a plurality of controllers. An individual corresponding one of the plurality of common mode current transformers are coupled to the 3-phase A/C output of each of the plurality of inverters. An individual corresponding one of the plurality of controllers is coupled to the output of an individual corresponding one of the plurality of common mode current transformers and is coupled to an individual corresponding A/C load. Each of the plurality of controllers is configured to detect a fault at the individual corresponding A/C load and in the case of detection of a fault at an individual corresponding A/C load, the corresponding controller disables the A/C load.
In one embodiment, each of the common mode current transformers is configured with a primary coil coupled to the 3-phase A/C output of the corresponding inverter and a secondary coil is coupled to an imbalance detection circuit of the corresponding controller. A voltage on the secondary of the common mode current transformer is input to the imbalance detection circuit for fault threshold comparison.
The improvement over prior art solutions is that the disclosed system can independently detect and isolate the fault. Independent fault detection combined with independent inverters allows for detection of a fault within a single A/C load and an isolated turn-off of that load so that the vehicle is able to continue back to the depot for maintenance without the use of a road call.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of one embodiment of the system disclosed in this specification.

FIG. 2 is a schematic diagram of one embodiment of a common mode current transformer disclosed in this specification.

FIG. 3 is a block diagram of one embodiment of the inverter disclosed in this specification.

FIG. 4 is a flow diagram of one embodiment of the method disclosed in this specification.

FIG. 5 is one embodiment of a modular line replaceable unit disclosed in this specification.

FIG. 6 is a block diagram of an exemplary computing system suitable for implementation of the embodiments disclosed in this specification.

Further features as well as the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements.

DETAILED DESCRIPTION

In one embodiment, independent inverters are provided for each A/C load of a system having a single DC input and a plurality of A/C loads. One example of such a system is an electric or hybrid electric vehicle. An independent common mode current transformer is connected between the A/C output of each inverter and the corresponding A/C load. The common mode current transformer is configured with the primary on the high voltage 3-phase A/C output and the secondary is input to a controller. The voltage of the secondary of the common mode current transformer is input to the controller for fault threshold comparison. Any imbalance between the phases creates a field which couples to the secondary. In one embodiment a current from the secondary is detected by the controller as fault current. In one embodiment the current on the secondary is detected by measuring a voltage across a shunt resistor detected by low voltage circuitry of the controller.
FIG. 1 is a schematic diagram of one embodiment of an electric or hybrid electric vehicle control system having independent A/C ground fault detection. The system 10 includes a system controller 12 and a high voltage battery pack 14. The system includes several A/C loads 16 that require 3-phase power to operate. The main A/C load is the traction motor of the vehicle. Additional A/C loads are the traction generator and one or more accessories that require A/C power. For example, one such A/C accessory is the air conditioning system that has a 3-phase motor. Shown in FIG. 1 are N A/C loads, 16-1, 16-22 . . . 16-N.
The system 10 includes an independent A/C drive 18 for each A/C load 16. As shown in FIG. 1, A/C drives 18-1, 18-2 . . . 18-N are connected between the system controller 12 and its corresponding A/C load 16-1, 16-2 . . . 16-N, respectively. Each A/C drive 18 is connected to the battery pack 14 by a corresponding DC link 20-1, 20-2 . . . 20-N. The A/C drives 18 include inverters 22 (22-1, 22-2 . . . 22-N) that convert high voltage, high current DC from the battery pack 14 to AC and supply 3-phase AC power to each A/C load 16. In one embodiment, the inverters 22 contain a full bridge switch architecture for the three phases which puts out square wave A/C power that is fed to the primary winding in a transformer 24 within each of the A/C drives 18. Through the switches, the direction of the flow of current is continuously and regularly flip-flopped. For example, the electrical charge travels into the primary winding and load, then abruptly reverses and flows back out. The in/out flow of electricity produces AC current in the transformer's primary winding circuit. This induced alternating current electricity provides power for the AC load 16. In one embodiment, the A/C drives 18 are setup with high and low voltage sections to allow use of low voltage parts where possible. In one embodiment, the A/C drives 18 are comprised of a logic-level electronic circuit that provides the driving signals to power switches that feed DC, AC, or power signals to a variety of loads, including the A/C loads 16.
In one embodiment, transformer 24 is an independent common mode current transformer which is connected between the A/C output of each inverter 22 and the corresponding A/C load 16. As shown in FIG. 1, common mode current transformers 24-1, 24-2 . . . 24-N are connected between the A/C output from the inverters 22-1, 22-2 . . . 22-N of each A/C drive 18 and the corresponding A/C loads 16-1, 16-2 . . . 16-N, respectively.
As shown in FIG. 2, each of the common mode current transformers 24 is configured with the primary 26 on the high voltage 3-phase A/C output of the corresponding inverter 18 and the secondary 28 of the common mode current transformer 24 is input to a controller 30. All 3 phases pass through the same common mode current transformer core that has a separate primary coil 26-A, 26-B and 26-C for each phase. In one embodiment, the voltage on the secondary 28 is stepped down through a resistor 32 and op-amp 34 to be low voltage so it can be input to the controller 30 without damaging the controller. In one embodiment, the 3-phase conductors pass through the core with a single turn.
The voltage of the secondary 28 of the common mode current transformer 24 is input to the controller 30 for fault threshold comparison. Any imbalance between the phases creates a field which couples to the secondary 28 and current from the secondary is detected by the controller 30 as fault current. If there is no imbalance in current then the current flowing out to one phase cancels with the current coming back from the other two. A current on the secondary 28 is detected by the controller 30 as a fault current. In one embodiment, the current on the secondary 28 is detected by measuring a voltage across the shunt resistor 32 detected by low voltage circuitry of the controller 30.
The controller 30 in response to the fault current sends a signal to its corresponding A/C load 16 to disable the motor of that load. In case of a fault, the vehicle is able to run without the generator since it has onboard battery power. The vehicle is also able to run without air conditioning as well as other accessory loads. The only drive that is absolutely necessary of the traction motor. A fault in the traction motor would not result in a disable signal.
The improvement over prior art solutions is that the disclosed system can independently detect and isolate the fault. Since all the invertors and A/C loads are tied to a common DC link input, the system controller would need to shutdown the whole link in order to stop the fault if the independent fault detection of this disclosure was not provided. Independent fault detection combined with independent inverters allows for detection of a fault within a single A/C load and an isolated turn-off of that load so that the vehicle is able to continue back to the depot for maintenance without the use of a road call.
In one embodiment, each A/C drive 18 includes two circuit card assemblies (CCA). One CCA 40 includes the controller 30 which has a processor with all the program instructions and other intelligence to control the operation of the switches of the inverter 22 on the card. The second CCA 42 is a filter card which has a dV/dT filter circuit 36, the CMCT 24, the shunt resistor 32 and EMI filtering 33. In one embodiment, as shown in FIG. 3, the dV/dT filter circuit 36 is coupled between the common mode current transformer (CMCT) 24 and the inverter 22. The dV/dT filter circuit 36 is a device that controls the voltage spikes generated by adjustable frequency drives and long motor lead lengths. As shown in FIG. 3, the dV/dT filter circuit 36 has a separate filter circuit 36-A, 36-b and 36-C for each phase of the 3-phase A/C input from the inverter 22. The controller 30 controls an imbalance detector circuit 38 which includes the op-amp 34 that is coupled to the secondary 28 of CMCT 24 through the shunt resistor 32. Any imbalance between the phases creates a field which generates a current on the secondary 28 that is detected by the imbalance detector circuit 38 as a fault current. By limiting the number of loads that need to be disabled the vehicle has a greater chance of being able to return to the service depot under its own power and control rather than requiring roadside service. Providing each individual load with a separate A/C drive with independent fault detection provided by the common mode current transformer allows the vehicle to not lose all electric drive/accessory power, this would also be a large advantage in reducing road calls by allowing individual outputs to be disabled instead of disabling the entire electric drive/accessory power system. Limiting the fault to a single output reduces roadside service calls which limits cost of ownership and enhances customer satisfaction. By being able to isolate the fault, limit the loss of functionality is limited. For example, if the fault was related to an accessory item, then that accessory would be able to be disengaged and in some cases the vehicle would be able to return to the service station/depot under its own power.
In addition, fault detection can be measured with higher accuracy then the prior art known solutions. By using a common mode current transformer (CMCT) the lack of accuracy of the summing operation using phase current sensors is eliminated. The only accuracy that limits the fault detection is the accuracy with which the transformer output current is measured. If the CMCT outputs a current then this is only possible if a fault exists. In contrast, if an imbalance is seen in the sum of three phase current sensors, it is unclear whether the imbalance is due to a small chassis fault, or simply the error in the three different phase current sensors. Moreover, since the current rating of the phase current sensor often has to be quite large to handle normal phase currents and because the sensor could have several percent of its full range in error, this means that these systems can have many amps of error in the summing operation when using phase current sensors to sum currents. In the CMCT system disclosed herein, the only measureable current is fault current so the accuracy with which a fault can be detected is much higher. This means that the trip point can be much lower than a current sensor summing method and the issue can be flagged much sooner to the operator. Due to the higher resolution, the CMCT system helps protect the hardware faster and to a much finer level.
FIG. 4 is a flow diagram of one embodiment of a fault detection method. The method includes step S1 of converting DC to a 3-phase A/C output to supply A/C power to a corresponding individual A/C load, step S2 of providing a common mode current transformer coupled to the 3-phase A/C output, step S3 of detecting an imbalance between the phases as a fault and step S4 of disabling the corresponding individual A/C load in response to the detection of a fault.
In one embodiment, as shown in FIG. 5, independent inverters are housed within a single line replaceable unit (LRU) 44 for all accessory power draws. The accessory power system includes individual D/C loads and individual A/C loads drawn by various accessory components. In one embodiment, the LRU 44 is a modular accessory power system that includes up to five DC drive modules 46 and up to five A/C drive modules 48. In one embodiment, the DC drive modules 46 are individual DC-DC drives that provide accessory power control. Each drive 46 provides 28 Vdc at 200 A. In one embodiment, the A/C drive modules are individual DC-AC drives that include a DC to AC inverter that provides accessory power input of 230 Vac at 28 A rms per drive. A separate common mode current transformer is provided in each DC-AC drive module 48. The modular accessory power system 44 includes a single DC-link input 50.
In one embodiment, the independent drives 46 and 48 may be stackable within the housing of LRU 44 to conserve space. As described above, each DC-AC drive 48 has a common mode current transformer which directly measures the imbalance in phase currents and allows fault detection at very low levels of common mode current. Each individual load has a separate DC-AC drive 48 with independent fault detection provided by the common mode current transformer. This allows an individual drive 48 the ability to directly measure common mode current and thereby to detect an issue within itself or the load and disable that individual drive.
FIG. 6 illustrates a schematic of an example computer or processing system that may implement the system and method of fault detection in one embodiment of the present disclosure. The computer system is only one example of a suitable processing system that may be used to implement the controller 30 and is not intended to suggest any limitation as to the scope of use or functionality of embodiments of the methodology described herein. The processing system shown may be operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, and/or configurations that may be suitable for use with the processing system shown in FIG. 6 may include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, field programmable gate arrays and distributed cloud computing environments that include any of the above systems or devices, and the like.
The components of computer system may include, but are not limited to, one or more processors or processing units 100, a system memory 106, and a bus 104 that couples various system components including system memory 106 to processor 100. The processor 100 may include a program module 102 that performs the methods described herein. The module 102 may be programmed into the integrated circuits of the processor 100, or loaded from memory 106, storage device 108, or network 114 or combinations thereof.
Bus 104 may represent one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnects (PCI) bus.
The computer system may include a variety of computer system readable media. Such media may be any available media that is accessible by computer system, and it may include both volatile and non-volatile media, removable and non-removable media.
System memory 106 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) and/or cache memory or others. Computer system may further include other removable/non-removable, volatile/non-volatile computer system storage media. By way of example only, storage system 108 can be provided for reading from and writing to a non-removable, non-volatile magnetic media (e.g., a “hard drive”). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such instances, each can be connected to bus 104 by one or more data media interfaces.
The computer system may also communicate with one or more external devices 116 such as a keyboard, a pointing device, a display 118, etc.; one or more devices that enable a user to interact with computer system; and/or any devices (e.g., network card, modem, etc.) that enable computer system to communicate with one or more other computing devices. Such communication can occur via Input/Output (I/O) interfaces 110.
Still yet, the computer system can communicate with one or more networks 114 such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet) via network adapter 112. As depicted, network adapter 112 communicates with the other components of computer system via bus 104. It should be understood that although not shown, other hardware and/or software components could be used in conjunction with computer system. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.
Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (for example, transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASICs, programmable logic devices, digital signal processors, FPGAs, logic gates, registers, semiconductor devices, chips, microchips, chipsets, and so forth. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power level, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints.
Some embodiments may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not intended as synonyms for each other. For example, some embodiments may be described using the terms “connected” and/or “coupled” to indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still cooperate or interact with each other.
The various embodiments disclosed herein can be implemented in various forms of hardware, software, firmware, and/or special purpose processors. For example, in one embodiment at least one non-transitory computer readable storage medium has instructions encoded thereon that, when executed by one or more processors, cause one or more of the network address configuration methodologies disclosed herein to be implemented. The instructions can be encoded using a suitable programming language, such as C, C++, object oriented C, Java, JavaScript, Visual Basic .NET, Beginner's All-Purpose Symbolic Instruction Code (BASIC), or alternatively, using custom or proprietary instruction sets. The instructions can be provided in the form of one or more computer software applications and/or applets that are tangibly embodied on a memory device, and that can be executed by a computer having any suitable architecture. In one embodiment, the system can be hosted on a given website and implemented, for example, using JavaScript or another suitable browser-based technology. For instance, in certain embodiments, the system may leverage processing resources provided by a remote computer system accessible via network. The computer software applications disclosed herein may include any number of different modules, sub-modules, or other components of distinct functionality, and can provide information to, or receive information from, still other components. These modules can be used, for example, to communicate with input and/or output devices such as a display screen, a touch sensitive surface, a printer, and/or any other suitable device. Other components and functionality not reflected in the illustrations will be apparent in light of this disclosure, and it will be appreciated that other embodiments are not limited to any particular hardware or software configuration. Thus in other embodiments system may comprise additional, fewer, or alternative subcomponents as compared to those included in the example embodiments.
The aforementioned non-transitory computer readable medium may be any suitable medium for storing digital information, such as a hard drive, a server, a flash memory, and/or random access memory (RAM), or a combination of memories. In alternative embodiments, the components and/or modules disclosed herein can be implemented with hardware, including gate level logic such as a field-programmable gate array (FPGA), or alternatively, a purpose-built semiconductor such as an application-specific integrated circuit (ASIC). Still other embodiments may be implemented with a microcontroller having a number of input/output ports for receiving and outputting data, and a number of embedded routines for carrying out the various functionalities disclosed herein. It will be apparent that any suitable combination of hardware, software, and firmware can be used, and that other embodiments are not limited to any particular system architecture.
Some embodiments may be implemented, for example, using a machine readable medium or article which may store an instruction or a set of instructions that, if executed by a machine, may cause the machine to perform a method and/or operations in accordance with the embodiments disclosed herein. Such a machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, process, or the like, and may be implemented using any suitable combination of hardware and/or software. The machine readable medium or article may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium, and/or storage unit, such as memory, removable or non-removable media, erasable or non-erasable media, writeable or rewriteable media, digital or analog media, hard disk, floppy disk, compact disk read only memory (CD-ROM), compact disk recordable (CD-R) memory, compact disk rewriteable (CR-RW) memory, optical disk, magnetic media, magneto-optical media, removable memory cards or disks, various types of digital versatile disk (DVD), a tape, a cassette, or the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, and the like, implemented using any suitable high level, low level, object oriented, visual, compiled, and/or interpreted programming language.
Unless specifically stated otherwise, it may be appreciated that terms such as “processing,” “computing,” “calculating,” “determining,” or the like refer to the action and/or process of a computer or computing system, or similar electronic computing device, that manipulates and/or transforms data represented as physical quantities (for example, electronic) within the registers and/or memory units of the computer system into other data similarly represented as physical quantities within the registers, memory units, or other such information storage transmission or displays of the computer system. The embodiments are not limited in this context.
The terms “circuit” or “circuitry,” as used in any embodiment herein, are functional and may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry such as computer processors comprising one or more individual instruction processing cores, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The circuitry may include a processor and/or controller configured to execute one or more instructions to perform one or more operations described herein. The instructions may be embodied as, for example, an application, software, firmware, etc. configured to cause the circuitry to perform any of the aforementioned operations. Software may be embodied as a software package, code, instructions, instruction sets and/or data recorded on a computer-readable storage device. Software may be embodied or implemented to include any number of processes, and processes, in turn, may be embodied or implemented to include any number of threads, etc., in a hierarchical fashion. Firmware may be embodied as code, instructions or instruction sets and/or data that are hard-coded (e.g., nonvolatile) in memory devices. The circuitry may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), an application-specific integrated circuit (ASIC), a system on-chip (SoC), desktop computers, laptop computers, tablet computers, servers, smart phones, etc. Other embodiments may be implemented as software executed by a programmable control device. In such cases, the terms “circuit” or “circuitry” are intended to include a combination of software and hardware such as a programmable control device or a processor capable of executing the software. As described herein, various embodiments may be implemented using hardware elements, software elements, or any combination thereof. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth.
Numerous specific details have been set forth herein to provide a thorough understanding of the embodiments. It will be understood by an ordinarily-skilled artisan, however, that the embodiments may be practiced without these specific details. In other instances, well known operations, components and circuits have not been described in detail so as not to obscure the embodiments. It can be appreciated that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments. In addition, although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described herein. Rather, the specific features and acts described herein are disclosed as example forms of implementing the claims.
The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents. Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications. It is intended that the scope of the present disclosure not be limited by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more elements as variously disclosed or otherwise demonstrated herein.
While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

What is claimed is:

1. A fault detection system comprising:

a DC power source;

a plurality of inverters coupled to the DC power source, the plurality of inverters converting DC to 3-phase A/C, the plurality of inverters each supplying A/C power to a corresponding individual A/C load;

a plurality of common mode current transformers, an individual corresponding one of the plurality of common mode current transformers being coupled to the 3-phase A/C output of each of the plurality of inverters; and

a plurality of controllers, an individual corresponding one of the plurality of controllers being coupled to the output of an individual corresponding one of the plurality of common mode current transformers and being coupled to an individual corresponding A/C load, each of the plurality of controllers being configured to detect a fault at the individual corresponding A/C load,

wherein in the case of detection of a fault at an individual corresponding A/C load, the corresponding controller disables the A/C load.

2. The fault detection system of claim 1, wherein each of the common mode current transformers is configured with a primary coil coupled to the 3-phase A/C output of the corresponding inverter and a secondary coil coupled to an imbalance detection circuit of the corresponding controller, wherein a current on the secondary of the common mode current transformer is input to the imbalance detection circuit for fault threshold comparison.

3. The fault detection system of claim 2, wherein each of the common mode current transformers has a separate primary coil for each phase of the 3-phase A/C output of the corresponding inverter.

4. The fault detection system of claim 2, wherein the current on the secondary of the common mode current transformer is measured as voltage across a high precision resistor using an op amp to input a low voltage to the corresponding controller.

5. The fault detection system of claim 1, each of the plurality of inverters includes a dV/dT filter circuit coupled to the corresponding common mode current transformer.

6. A line replaceable unit comprising:

a DC link input configured to be coupled to DC power source;

a plurality of DC drive modules coupled to the DC link input; and

a plurality of DC-AC drive modules coupled to the DC link input, each DC-AC drive module comprising:

an inverter coupled to the DC link input, the inverter converting DC to 3-phase A/C to supply A/C power to a corresponding individual A/C load;

a common mode current transformer coupled to the 3-phase A/C output of the inverter; and

a controller coupled to the output of the common mode current transformer and coupled to the corresponding A/C load, the plurality of controller being configured to detect a fault at the individual corresponding A/C load,

wherein in the case of detection of a fault at the individual corresponding A/C load, the controller disables the corresponding A/C load.

7. The line replaceable unit of claim 6, wherein the common mode current transformer is configured with a primary coil coupled to the 3-phase A/C output of the inverter and a secondary coil coupled to an imbalance detection circuit of the controller, wherein a current on the secondary of the common mode current transformer is input to the imbalance detection circuit for fault threshold comparison.

8. The line replaceable unit of claim 7, wherein the common mode current transformer has a separate primary coil for each phase of the 3-phase A/C output of the inverter.

9. A fault detection method comprising:

converting DC to 3-phase A/C output to supply A/C power to a corresponding individual A/C load;

providing a common mode current transformer coupled to the 3-phase A/C output;

detecting an imbalance between the phases as a fault; and

disabling the corresponding individual A/C load in response to the detection of a fault.

10. The method of claim 9, wherein the common mode current transformer is configured with a primary coil coupled to the 3-phase A/C output and a secondary coil coupled to an imbalance detection circuit of a controller, wherein a current on the secondary of the common mode current transformer is input to the imbalance detection circuit for fault threshold comparison.

11. The method of claim 10, wherein a current from the secondary of the common mode current transformer is detected as a voltage on a shunt resistor by the controller as a fault.

12. A computer system for detecting a fault, comprising:

one or more computer processors;

one or more non-transitory computer-readable storage media;

program instructions, stored on the one or more non-transitory computer-readable storage media, which when implemented by the one or more processors, cause the computer system to perform the steps of:

converting DC to 3-phase A/C to supply A/C power to a corresponding individual A/C load;

providing a common mode current transformer coupled to the 3-phase A/C output of the inverter;

detecting an imbalance between the phases as a fault; and

13. The computer system of claim 12, wherein the common mode current transformer is configured with a primary coil coupled to the 3-phase A/C output of the inverter and a secondary coil coupled to an imbalance detection circuit of a controller, wherein a current on the secondary of the common mode current transformer is input to the imbalance detection circuit for fault threshold comparison.

14. A computer program product comprising:

program instructions on a computer-readable storage medium, where execution of the program instructions using a computer causes the computer to perform a method for detecting a fault, comprising:

detecting an imbalance between the phases as a fault; and

15. The computer program product of claim 14, wherein the common mode current transformer is configured with a primary coil coupled to the 3-phase A/C output of the inverter and a secondary coil coupled to an imbalance detection circuit of a controller, wherein a current on the secondary of the common mode current transformer is input to the imbalance detection circuit for fault threshold comparison.