US20210313321A1 - Multi-level isolation structure - Google Patents
Multi-level isolation structure Download PDFInfo
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- US20210313321A1 US20210313321A1 US16/842,075 US202016842075A US2021313321A1 US 20210313321 A1 US20210313321 A1 US 20210313321A1 US 202016842075 A US202016842075 A US 202016842075A US 2021313321 A1 US2021313321 A1 US 2021313321A1
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- 238000002955 isolation Methods 0.000 title claims abstract description 85
- 239000010410 layer Substances 0.000 claims description 56
- 239000011810 insulating material Substances 0.000 claims description 53
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000001465 metallisation Methods 0.000 claims description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 239000002356 single layer Substances 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 5
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- 238000004519 manufacturing process Methods 0.000 description 4
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- 230000015572 biosynthetic process Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
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- 238000000231 atomic layer deposition Methods 0.000 description 2
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- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
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- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
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- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
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- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- the present disclosure generally relates to various novel embodiments of a multi-level isolation structure for integrated circuit products and various novel methods of making such multi-level isolation structures.
- Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc.
- the transistors are typically either NFET or PFET type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices.
- the various transistor devices that are formed for an IC product must be electrically isolated from one another to properly function in an electrical circuit.
- forming such an isolation structure involves depositing an insulating material, such as silicon dioxide, such that it overfills the spaces between the fins.
- a CMP process is typically performed to planarize the upper surface of the insulating material.
- a recess etching process is performed to remove a portion of the vertical thickness of the insulating material. This recess etching process exposes the desired final fin height of the fins for the devices.
- This recess etching process also results in an isolation structure that has a substantially planar upper surface.
- the present disclosure is generally directed to various novel embodiments of a multi-level isolation structure for integrated circuit products and various novel methods of making such multi-level isolation structures.
- One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region.
- the first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface of the isolation structure is positioned at a first level and the second upper surface of the isolation structure is positioned at a second level and wherein the first level is below the second level.
- the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.
- FIGS. 1-21 depict various novel embodiments of a multi-level isolation structure for integrated circuit products and various novel methods of making such multi-level isolation structures.
- the drawings are not to scale.
- the various components, structures and layers of material depicted herein may be formed using a variety of different materials and by performing a variety of known process operations, e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), a thermal growth process, spin-coating techniques, masking, etching, etc.
- CVD chemical vapor deposition
- ALD atomic layer deposition
- thermal growth process spin-coating techniques
- masking etching
- etching etc.
- the thicknesses of these various layers of material may also vary depending upon the particular application.
- FIGS. 1-21 depict various novel embodiments of a multi-level isolation structure for integrated circuit products and various novel methods of making such multi-level isolation structures.
- FIG. 1 is a simplistic plan view of the IC product 100 at a relatively early stage of fabrication.
- the IC product 100 when completed, will comprise a first transistor device 101 A and a second transistor device 101 B (collectively referenced using the numeral 101 ).
- the first transistor device 101 A may be an N-type FinFET device while the second transistor device 101 B may be a P-type FinFET device, or vice-versa.
- both of the devices 101 could also be the same type, both of the devices 101 could be P-type devices.
- the methods and multi-level isolation structures disclosed herein can be employed to improve the performance of a single transistor device.
- FIG. 1 also depicts a plurality of fins 104 A-D (collectively referenced using the numeral 104 ) that were formed in a semiconductor substrate 102 (see FIG. 2 ).
- the first transistor device 101 A comprises the fins 104 A-B
- the second transistor device 101 B comprises the fins 104 C-D.
- the devices 101 may comprise one or more fins 104 , and the first transistor device 101 A and the second transistor device 101 B need not have the same number of fins 104 , but that may be the case in some applications.
- FIG. 1 Various cross-sectional views (“X-X” and “Y-Y”) of the IC product 100 that are depicted in some of the attached drawings are taken where indicated in FIG. 1 .
- the cross-sectional view X-X is taken in the gate width direction of the devices 101
- the view Y-Y is a cross-sectional view taken along the long axis (i.e., the axial length) of the fin 104 B.
- the IC product 100 will be formed above a semiconductor substrate 102 .
- the substrate 102 may have a variety of configurations, such as a simple bulk configuration, as depicted herein or a semiconductor-on-insulator (SOI) configuration that includes a base semiconductor layer, a buried insulation layer positioned on the base semiconductor layer and an active semiconductor layer positioned above the buried insulation layer, wherein the transistor devices 101 are formed in and above the active semiconductor layer.
- the substrate 102 may be made of silicon or it may be made of semiconductor materials other than silicon.
- the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconductor materials and all forms of such materials.
- FIGS. 1-3 depict the IC product 100 after several process operations were performed. More specifically, the fins 104 were formed in the substrate 102 using traditional manufacturing techniques. For example, a patterned fin-formation etch mask (not shown—comprised of, for example, a layer of silicon dioxide and a layer of silicon nitride) was formed above the substrate 102 . Thereafter, one or more etching processes, e.g., anisotropic etching processes, were performed through the patterned fin-formation etch mask to form a plurality of fin-formation trenches 103 in the substrate 102 and thereby define the plurality of fins 104 each having an upper surface 104 X.
- etching processes e.g., anisotropic etching processes
- the overall size, shape and configuration of the fin-formation trenches 103 and fins 104 may vary depending on the particular application.
- the fins 104 will be depicted as have a simplistic rectangular cross-sectional configuration having a substantially uniform thickness throughout the height of the fin 104 .
- the fins 104 may have a tapered cross-sectional configuration, wherein the width of the upper surface 104 X of the fin 104 (i.e., the top critical dimension) is less than the width of the bottom of the fin 104 .
- a layer of insulating material 106 was formed so as to over-fill the trenches 103 between the fins 104 . That is, the layer of insulating material 106 was initially formed such that its upper surface was positioned above the upper surface of the patterned fin-formation etch mask. Thereafter, one or more planarization processes (e.g., a CMP and/or etch-back process) was performed to remove portions of the layer of insulating material 106 and the patterned fin-formation etch mask. These processes result in the layer of insulating material 106 having a planarized upper surface 106 X and in the exposure of the upper surface 104 X of the fins 104 .
- the layer of insulating material 106 may be comprised of, for example, silicon dioxide.
- FIGS. 4 and 5 depict the IC product 100 after a layer of material 110 was formed above the substrate 102 .
- the layer of material 110 may be comprised of, for example, silicon nitride, and it may be formed to any desired thickness.
- FIGS. 6 and 7 depict the IC product 100 after several process operations were performed.
- a patterned etch mask (not shown) was formed above the layer of material 110 .
- the patterned etch mask may be a patterned layer of photoresist or OPL.
- an etching process was performed to remove exposed portions of the layer of material 110 .
- FIGS. 8 and 9 depict the IC product 100 after several process operations were performed.
- a layer of insulating material 112 was formed so as to over-fill the openings 110 A in the patterned layer of material 110 .
- one or more planarization processes e.g., a CMP and/or etch-back process
- planarization processes e.g., a CMP and/or etch-back process
- the layer of insulating material 112 may be comprised of any of a variety of different oxide materials, e.g., an HDP oxide, etc.
- FIGS. 10 and 11 are cross-sectional views that depict the IC product 100 after an etching process was performed to remove the patterned layer of material 110 selectively relative to the surrounding materials.
- FIG. 12 is a plan view of the IC product 100 showing the remaining islands of the layer of insulating material 112 after the patterned layer of material 110 was removed. Note that the upper surface 112 X of the islands of the layer of insulating material 112 is positioned at a level that is above the level of the upper surface 106 X of the insulating material 106 .
- FIG. 13 cross-sectional view
- FIG. 14 cross-sectional view
- FIG. 15 plan view
- the recess etching process was performed for a sufficient duration such that the layer of insulating material 106 in the area adjacent and between the fins 104 has a recessed upper surface 106 S that is positioned at a desired height level within the trenches 103 .
- the amount of recessing of the layer of insulating material 106 may vary depending upon the particular application.
- This recess etching process exposes the desired final fin height of the fins 104 for the devices 101 . Also note that, due to the presence of the islands of the layer of insulating material 112 , the portions of the layer of insulating material 106 positioned under the islands of the layer of insulating material 112 may not be etched at all, or to a much less extent than the exposed portions of the layer of insulating material 106 positioned adjacent and between the fins 104 .
- This process operation results in the formation of a multi-level isolation structure 128 that has a non-planar upper surface, i.e., there is a step height in the upper surface of the overall isolation structure 128 .
- the elevated regions 120 of the insulating material 106 have an upper surface 120 S that is positioned at a level that is above the level of the recessed surface 106 S of the insulating material 106 positioned between and adjacent the fins 104 .
- the differences in these height levels, i.e., the step height may vary depending upon the particular application, e.g., 30-50 nm.
- the upper surface 120 S of the elevated regions 120 of insulating material may be positioned at a level that is substantially coplanar with the upper surface 104 X of the fins 104 .
- the upper surface 120 S of the elevated regions 120 of insulating material may be positioned at a level that is below or above the upper surface 104 X of the fins 104 by an amount that may vary depending upon the particular application, e.g., about 10 nm above or about 10 nm below the upper surface 104 X of the fins 104 .
- the isolation structure 128 is a single layer of material, e.g., silicon dioxide, wherein the stepped upper surface is formed in the single layer of silicon dioxide.
- the regions of insulating material 120 may be islands of such material.
- the elevated island regions 120 of insulating material may be positioned between the fins 104 of the two adjacent transistor devices 101 .
- the process flow could be modified such that substantially rectangular shaped openings 120 Y are formed in the regions 120 of elevated insulating material, with the fins 104 being positioned within the substantially rectangular shaped openings 120 Y. Irrespective of the form or shape of the elevated regions 120 of the insulating material, the magnitude of the lateral spacing between the elevated regions 120 of insulating material and the sidewall of the nearest fin 104 may vary depending upon the particular application.
- FIG. 17 depicts the IC product 100 after an illustrative gate structure 130 and source/drain metallization structures 132 have been formed for the devices by performing known manufacturing operations.
- FIG. 18 is a cross-sectional view taken through the gate structure 130 in a direction corresponding to the gate width direction of the devices 101
- FIG. 19 is a cross-sectional view taken through one of the source/drain metallization structures 132 in a direction corresponding to the gate width direction of the devices 101 .
- FIGS. 17-19 depicts the IC product 100 after an illustrative gate structure 130 and source/drain metallization structures 132 have been formed for the devices by performing known manufacturing operations.
- FIG. 18 is a cross-sectional view taken through the gate structure 130 in a direction corresponding to the gate width direction of the devices 101
- FIG. 19 is a cross-sectional view taken through one of the source/drain metallization structures 132 in a direction corresponding to the gate width direction of the devices 101 .
- the gate structure 130 of the transistor devices 101 disclosed herein may be manufactured using known gate-first or replacement gate manufacturing techniques, and the materials of construction for the gate structure 130 may vary depending upon the particular application.
- the gate structure 130 may comprise a high-k gate insulation layer 140 , such as hafnium oxide, a material having a dielectric constant greater than 10, etc., one or more conductive work-function adjusting metal layers 142 , e.g., titanium, tantalum, titanium nitride, tantalum nitride, titanium carbide, etc., as well as one or more bulk conductive layers of material 144 , e.g., titanium, tungsten, aluminum, etc.
- the thickness of the layers of material 140 , 142 and 144 may vary depending upon the particular application. In other situations, the gate structure 130 may comprise a gate insulation layer 140 made of silicon dioxide and the bulk conductive layer of material 144 may comprise polysilicon.
- FIG. 19 depicts the IC product 100 after several process operations were performed.
- epitaxial semiconductor material 146 was formed on the portions of the fins 104 in the source/drain regions of the devices.
- various known process operations were performed to form the illustrative conductive source/drain metallization structures 132 (e.g., trench silicide structures) that are conductively coupled to the epi semiconductor material 146 in the source/drain regions of the transistor devices.
- the conductive source/drain metallization structures 132 extend across substantially the entire active region of the devices 101 in the gate width (GW) direction of the devices 101 .
- GW gate width
- the conductive source/drain metallization structures 132 may comprise a variety of different conductive materials, e.g., tungsten, cobalt, aluminum, a metal, a metal compound, cobalt silicide, nickel silicide, titanium silicide, nickel platinum silicide, etc.
- the multi-level isolation structure 128 disclosed herein can reduce capacitance (Csg (F)) of the devices 101 as reflected in Table I below, wherein the step-height of the isolation structure is the difference in height between the upper surface 106 S of the insulating material 106 positioned between the fins 104 and the upper surface 120 S of the elevated regions 120 of the insulating material.
- isolation structure 1 with zero step-height—was used to compare the impact of the formation of the multi-level isolation structure 128 disclosed herein (isolation structures 2 and 3 ) in terms of reducing the parasitic capacitance of the devices 101 .
- the above-referenced decreases in the parasitic capacitance of the devices 101 using the multi-level isolation structure 128 disclosed herein can be useful in improving the performance characteristics of the devices 101 .
- FIGS. 20 and 21 show an embodiment where separate transistor devices 101 A, 101 B with separate gate structures 130 A, 130 B and separate conductive source/drain metallization structures 132 A, 132 B are formed above the novel multi-level isolation structure 128 disclosed herein. As shown in FIG.
- a sidewall spacer 150 e.g., silicon nitride
- an insulating material 152 e.g., silicon dioxide
- one illustrative IC product disclosed herein comprises at least one fin structure, e.g., one of the fin structures 104 A, 104 B, an isolation structure 128 comprising a single layer of insulating material, the layer of insulating material 106 having a stepped upper surface comprising a first upper surface 106 S and a second upper surface 120 S, wherein the first upper surface 106 S is positioned at a first level and the second upper surface 120 S is positioned at a second level, wherein the first level is below the second level.
- the product also includes a gate structure 130 A comprising a first portion and a second portion, wherein the first portion of the gate structure 130 A is positioned above the first upper surface 106 S of the layer of insulating material 106 and above the at least one fin structure, e.g., one of the fin structures 104 A, 104 B, and the second portion of the gate structure is positioned above the second upper surface 120 S of the layer of insulating material 106 , i.e., one or both of the end portions of the gate structure 130 A is positioned above regions 120 of elevated insulating material 106 .
- a gate structure 130 A comprising a first portion and a second portion, wherein the first portion of the gate structure 130 A is positioned above the first upper surface 106 S of the layer of insulating material 106 and above the at least one fin structure, e.g., one of the fin structures 104 A, 104 B, and the second portion of the gate structure is positioned above the second upper surface 120 S of the layer of insulating material
- another illustrative IC product disclosed herein comprises at least one fin structure, e.g., one of the fin structures 104 A, 104 B, an isolation structure 128 comprising a first region of insulating material positioned adjacent the at least one fin structure, i.e., the portion of the insulation material 106 with a recessed upper surface 106 S and a second region of insulating material, i.e., the elevated regions 120 of the insulating material that are positioned adjacent the first region of insulating material.
- the upper surface 106 S of the first region of the isolation structure 128 is positioned at a first level and the upper surface 120 S of the second region of the isolation structure 128 is positioned at a second level, wherein the first level is below the second level.
- the gate structure 130 A comprises a first portion and a second portion, wherein the first portion of the gate structure 130 A is positioned above the first region of the isolation structure and above the at least one fin structure, e.g., one of the fin structures 104 A, 104 B, and wherein the second portion of the gate structure 130 A is positioned above the second portion of the isolation structure 128 , i.e., one or both of the end portions of the gate structure 130 is positioned above elevated regions 120 of insulating material.
- another illustrative IC product disclosed herein comprises a first transistor 101 A comprising at least one first fin structure, e.g., one of the fin structures 104 A, 104 B, and a second transistor comprising at least one second fin structure, e.g., one of the fin structures 104 C, 104 D.
- the IC product also includes an isolation structure 128 comprising an upper surface having a first region, a second region and a third region that is positioned between the first region and the second region, wherein the first region of the isolation structure 128 is positioned adjacent the at least one first fin structure and the second region of the isolation structure 128 is positioned adjacent the at least one second fin structure.
- the upper surface 106 S of the first and second regions of the isolation structure 128 are positioned at a first level and an upper surface 120 S of the third region of the isolation structure 128 is positioned at a second level, wherein the first level is below the second level.
- This embodiment of the IC product 100 also includes a shared gate structure 130 comprising a first portion, a second portion and a third portion, wherein the second portion is positioned between the first portion and the third portion.
- the first portion of the shared gate structure 130 is positioned above the first region of the isolation structure 128 and above the at least one first fin structure, e.g., one of the fin structures 104 A, 104 B, the third portion of the shared gate structure 130 is positioned above the second region of the isolation structure 128 and above the at least one second fin structure, e.g., one of the fin structures 104 C, 104 D, and the third portion of the shared gate structure 130 is positioned above the second portion of the isolation structure 128 .
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Abstract
Description
- The present disclosure generally relates to various novel embodiments of a multi-level isolation structure for integrated circuit products and various novel methods of making such multi-level isolation structures.
- In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NFET or PFET type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices.
- The various transistor devices that are formed for an IC product must be electrically isolated from one another to properly function in an electrical circuit. Typically, in the case of FinFET devices, forming such an isolation structure involves depositing an insulating material, such as silicon dioxide, such that it overfills the spaces between the fins. Thereafter, a CMP process is typically performed to planarize the upper surface of the insulating material. At that point, a recess etching process is performed to remove a portion of the vertical thickness of the insulating material. This recess etching process exposes the desired final fin height of the fins for the devices. This recess etching process also results in an isolation structure that has a substantially planar upper surface.
- The present disclosure is generally directed to various novel embodiments of a multi-level isolation structure for integrated circuit products and various novel methods of making such multi-level isolation structures.
- The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
- The present disclosure is directed to various novel embodiments of a multi-level isolation structure for integrated circuit products and various novel methods of making such multi-level isolation structures. One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface of the isolation structure is positioned at a first level and the second upper surface of the isolation structure is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.
- The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
-
FIGS. 1-21 depict various novel embodiments of a multi-level isolation structure for integrated circuit products and various novel methods of making such multi-level isolation structures. The drawings are not to scale. - While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
- The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the presently disclosed method may be applicable to a variety of products, including, but not limited to, logic products, memory products, etc., and the transistor devices disclosed herein may be NFET or PFET devices. The various components, structures and layers of material depicted herein may be formed using a variety of different materials and by performing a variety of known process operations, e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), a thermal growth process, spin-coating techniques, masking, etching, etc. The thicknesses of these various layers of material may also vary depending upon the particular application. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
-
FIGS. 1-21 depict various novel embodiments of a multi-level isolation structure for integrated circuit products and various novel methods of making such multi-level isolation structures.FIG. 1 is a simplistic plan view of theIC product 100 at a relatively early stage of fabrication. In the example depicted herein, when completed, theIC product 100 will comprise afirst transistor device 101A and asecond transistor device 101B (collectively referenced using the numeral 101). In one illustrative example, thefirst transistor device 101A may be an N-type FinFET device while thesecond transistor device 101B may be a P-type FinFET device, or vice-versa. As will be appreciated by those skilled in the art after a complete reading of the present application, both of the devices 101 could also be the same type, both of the devices 101 could be P-type devices. Moreover, the methods and multi-level isolation structures disclosed herein can be employed to improve the performance of a single transistor device. -
FIG. 1 also depicts a plurality offins 104A-D (collectively referenced using the numeral 104) that were formed in a semiconductor substrate 102 (seeFIG. 2 ). Thefirst transistor device 101A comprises thefins 104A-B, while thesecond transistor device 101B comprises thefins 104C-D. Of course, in practice, the devices 101 may comprise one or more fins 104, and thefirst transistor device 101A and thesecond transistor device 101B need not have the same number of fins 104, but that may be the case in some applications. - Various cross-sectional views (“X-X” and “Y-Y”) of the
IC product 100 that are depicted in some of the attached drawings are taken where indicated inFIG. 1 . The cross-sectional view X-X is taken in the gate width direction of the devices 101, while the view Y-Y is a cross-sectional view taken along the long axis (i.e., the axial length) of thefin 104B. - With reference to
FIG. 2 , in the examples depicted herein, theIC product 100 will be formed above asemiconductor substrate 102. Thesubstrate 102 may have a variety of configurations, such as a simple bulk configuration, as depicted herein or a semiconductor-on-insulator (SOI) configuration that includes a base semiconductor layer, a buried insulation layer positioned on the base semiconductor layer and an active semiconductor layer positioned above the buried insulation layer, wherein the transistor devices 101 are formed in and above the active semiconductor layer. Thesubstrate 102 may be made of silicon or it may be made of semiconductor materials other than silicon. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconductor materials and all forms of such materials. -
FIGS. 1-3 depict theIC product 100 after several process operations were performed. More specifically, the fins 104 were formed in thesubstrate 102 using traditional manufacturing techniques. For example, a patterned fin-formation etch mask (not shown—comprised of, for example, a layer of silicon dioxide and a layer of silicon nitride) was formed above thesubstrate 102. Thereafter, one or more etching processes, e.g., anisotropic etching processes, were performed through the patterned fin-formation etch mask to form a plurality of fin-formation trenches 103 in thesubstrate 102 and thereby define the plurality of fins 104 each having anupper surface 104X. The overall size, shape and configuration of the fin-formation trenches 103 and fins 104 may vary depending on the particular application. In the examples depicted herein, the fins 104 will be depicted as have a simplistic rectangular cross-sectional configuration having a substantially uniform thickness throughout the height of the fin 104. In a real-world device, the fins 104 may have a tapered cross-sectional configuration, wherein the width of theupper surface 104X of the fin 104 (i.e., the top critical dimension) is less than the width of the bottom of the fin 104. - Next, a layer of
insulating material 106 was formed so as to over-fill thetrenches 103 between the fins 104. That is, the layer of insulatingmaterial 106 was initially formed such that its upper surface was positioned above the upper surface of the patterned fin-formation etch mask. Thereafter, one or more planarization processes (e.g., a CMP and/or etch-back process) was performed to remove portions of the layer of insulatingmaterial 106 and the patterned fin-formation etch mask. These processes result in the layer of insulatingmaterial 106 having a planarizedupper surface 106X and in the exposure of theupper surface 104X of the fins 104. The layer of insulatingmaterial 106 may be comprised of, for example, silicon dioxide. -
FIGS. 4 and 5 depict theIC product 100 after a layer ofmaterial 110 was formed above thesubstrate 102. The layer ofmaterial 110 may be comprised of, for example, silicon nitride, and it may be formed to any desired thickness. -
FIGS. 6 and 7 depict theIC product 100 after several process operations were performed. First, a patterned etch mask (not shown) was formed above the layer ofmaterial 110. In one illustrative example, the patterned etch mask may be a patterned layer of photoresist or OPL. Thereafter, an etching process was performed to remove exposed portions of the layer ofmaterial 110. These operations result in the formation of a plurality of substantially rectangular shapedopenings 110A (when viewed from above) in the patterned layer ofmaterial 110. -
FIGS. 8 and 9 depict theIC product 100 after several process operations were performed. First, a layer of insulatingmaterial 112 was formed so as to over-fill theopenings 110A in the patterned layer ofmaterial 110. Thereafter, one or more planarization processes (e.g., a CMP and/or etch-back process) was performed to remove portions of the layer of insulatingmaterial 112 positioned above the upper surface of the patterned layer ofmaterial 110. These processes result in portions of the layer of insulatingmaterial 112 being positioned in theopenings 110A in the patterned layer ofmaterial 110. The layer of insulatingmaterial 112 may be comprised of any of a variety of different oxide materials, e.g., an HDP oxide, etc. -
FIGS. 10 and 11 are cross-sectional views that depict theIC product 100 after an etching process was performed to remove the patterned layer ofmaterial 110 selectively relative to the surrounding materials.FIG. 12 is a plan view of theIC product 100 showing the remaining islands of the layer of insulatingmaterial 112 after the patterned layer ofmaterial 110 was removed. Note that theupper surface 112X of the islands of the layer of insulatingmaterial 112 is positioned at a level that is above the level of theupper surface 106X of the insulatingmaterial 106. -
FIG. 13 (cross-sectional view),FIG. 14 (cross-sectional view) andFIG. 15 (plan view) depict theIC product 100 after a timed, anisotropic recess etching process was performed to remove some of the thickness of the exposed portions of the layer of insulatingmaterial 106 and to remove substantially all of the islands of the layer of insulatingmaterial 112. The recess etching process was performed for a sufficient duration such that the layer of insulatingmaterial 106 in the area adjacent and between the fins 104 has a recessedupper surface 106S that is positioned at a desired height level within thetrenches 103. The amount of recessing of the layer of insulatingmaterial 106 may vary depending upon the particular application. This recess etching process exposes the desired final fin height of the fins 104 for the devices 101. Also note that, due to the presence of the islands of the layer of insulatingmaterial 112, the portions of the layer of insulatingmaterial 106 positioned under the islands of the layer of insulatingmaterial 112 may not be etched at all, or to a much less extent than the exposed portions of the layer of insulatingmaterial 106 positioned adjacent and between the fins 104. - This process operation results in the formation of a
multi-level isolation structure 128 that has a non-planar upper surface, i.e., there is a step height in the upper surface of theoverall isolation structure 128. In the depicted example, theelevated regions 120 of the insulatingmaterial 106 have anupper surface 120S that is positioned at a level that is above the level of the recessedsurface 106S of the insulatingmaterial 106 positioned between and adjacent the fins 104. The differences in these height levels, i.e., the step height, may vary depending upon the particular application, e.g., 30-50 nm. In one illustrative embodiment, theupper surface 120S of theelevated regions 120 of insulating material may be positioned at a level that is substantially coplanar with theupper surface 104X of the fins 104. In other situations, theupper surface 120S of theelevated regions 120 of insulating material may be positioned at a level that is below or above theupper surface 104X of the fins 104 by an amount that may vary depending upon the particular application, e.g., about 10 nm above or about 10 nm below theupper surface 104X of the fins 104. In the illustrative example wherein theupper surface 120S of theelevated regions 120 of the insulating material are positioned above theupper surface 104X of the fins 104, a portion of the layer ofmaterial 112 will be part of theelevated regions 120 of the insulating material. In other applications, theisolation structure 128 is a single layer of material, e.g., silicon dioxide, wherein the stepped upper surface is formed in the single layer of silicon dioxide. - In some applications, the regions of insulating
material 120 may be islands of such material. In one illustrative embodiment, the elevatedisland regions 120 of insulating material may be positioned between the fins 104 of the two adjacent transistor devices 101. With reference toFIG. 16 , if desired, the process flow could be modified such that substantially rectangular shapedopenings 120Y are formed in theregions 120 of elevated insulating material, with the fins 104 being positioned within the substantially rectangular shapedopenings 120Y. Irrespective of the form or shape of theelevated regions 120 of the insulating material, the magnitude of the lateral spacing between theelevated regions 120 of insulating material and the sidewall of the nearest fin 104 may vary depending upon the particular application. -
FIG. 17 depicts theIC product 100 after anillustrative gate structure 130 and source/drain metallization structures 132 have been formed for the devices by performing known manufacturing operations. As indicated inFIG. 17 ,FIG. 18 is a cross-sectional view taken through thegate structure 130 in a direction corresponding to the gate width direction of the devices 101, whileFIG. 19 is a cross-sectional view taken through one of the source/drain metallization structures 132 in a direction corresponding to the gate width direction of the devices 101. As will be appreciated by those skilled in the art, other structures or components of the completeddevices 100 are not depicted in one or more ofFIGS. 17-19 , e.g., gate cap structures, sidewall spacers, epitaxial material that may be formed in the source/drain regions of the devices 101, etc. - With reference to
FIG. 18 , and as will be appreciated by those skilled in the art after a complete reading of the present application, thegate structure 130 of the transistor devices 101 disclosed herein may be manufactured using known gate-first or replacement gate manufacturing techniques, and the materials of construction for thegate structure 130 may vary depending upon the particular application. In one illustrative example, thegate structure 130 may comprise a high-kgate insulation layer 140, such as hafnium oxide, a material having a dielectric constant greater than 10, etc., one or more conductive work-function adjustingmetal layers 142, e.g., titanium, tantalum, titanium nitride, tantalum nitride, titanium carbide, etc., as well as one or more bulk conductive layers ofmaterial 144, e.g., titanium, tungsten, aluminum, etc. The thickness of the layers ofmaterial gate structure 130 may comprise agate insulation layer 140 made of silicon dioxide and the bulk conductive layer ofmaterial 144 may comprise polysilicon. -
FIG. 19 depicts theIC product 100 after several process operations were performed. First,epitaxial semiconductor material 146 was formed on the portions of the fins 104 in the source/drain regions of the devices. Thereafter, various known process operations were performed to form the illustrative conductive source/drain metallization structures 132 (e.g., trench silicide structures) that are conductively coupled to theepi semiconductor material 146 in the source/drain regions of the transistor devices. In the depicted example, the conductive source/drain metallization structures 132 extend across substantially the entire active region of the devices 101 in the gate width (GW) direction of the devices 101. In one illustrative embodiment, the conductive source/drain metallization structures 132 may comprise a variety of different conductive materials, e.g., tungsten, cobalt, aluminum, a metal, a metal compound, cobalt silicide, nickel silicide, titanium silicide, nickel platinum silicide, etc. - Simulations have shown that the
multi-level isolation structure 128 disclosed herein can reduce capacitance (Csg (F)) of the devices 101 as reflected in Table I below, wherein the step-height of the isolation structure is the difference in height between theupper surface 106S of the insulatingmaterial 106 positioned between the fins 104 and theupper surface 120S of theelevated regions 120 of the insulating material. -
TABLE I Structure Step-Height (nm) Csg (F) Isolation Structure 1 0 (control) 8.9167e−17 Isolation Structure 236 8.9605e−17 Isolation Structure 3 65 8.3956e−17
As reflected in the above Table 1, isolation structure 1—with zero step-height—was used to compare the impact of the formation of themulti-level isolation structure 128 disclosed herein (isolation structures 2 and 3) in terms of reducing the parasitic capacitance of the devices 101. As will be appreciated by those skilled in the art after a complete reading of the present application, the above-referenced decreases in the parasitic capacitance of the devices 101 using themulti-level isolation structure 128 disclosed herein can be useful in improving the performance characteristics of the devices 101. - In the example depicted above, the
gate structure 130 was shared by both of the transistor devices 101. However, as will be appreciated by those skilled in the art after a complete reading of the present application, the novelmulti-level isolation structure 128 disclosed herein can be used on single transistor devices as well.FIGS. 20 and 21 show an embodiment whereseparate transistor devices separate gate structures drain metallization structures multi-level isolation structure 128 disclosed herein. As shown inFIG. 20 , asidewall spacer 150, e.g., silicon nitride, was formed on each of thegate structures material 152, e.g., silicon dioxide, was formed between thespacers 150. As shown inFIG. 21 , the conductive source/drain metallization structures material 152. - With reference to the
single device 101A shown inFIG. 20 , one illustrative IC product disclosed herein comprises at least one fin structure, e.g., one of thefin structures isolation structure 128 comprising a single layer of insulating material, the layer of insulatingmaterial 106 having a stepped upper surface comprising a firstupper surface 106S and a secondupper surface 120S, wherein the firstupper surface 106S is positioned at a first level and the secondupper surface 120S is positioned at a second level, wherein the first level is below the second level. The product also includes agate structure 130A comprising a first portion and a second portion, wherein the first portion of thegate structure 130A is positioned above the firstupper surface 106S of the layer of insulatingmaterial 106 and above the at least one fin structure, e.g., one of thefin structures upper surface 120S of the layer of insulatingmaterial 106, i.e., one or both of the end portions of thegate structure 130A is positioned aboveregions 120 of elevated insulatingmaterial 106. - With reference to the
single device 101A shown inFIG. 20 , another illustrative IC product disclosed herein comprises at least one fin structure, e.g., one of thefin structures isolation structure 128 comprising a first region of insulating material positioned adjacent the at least one fin structure, i.e., the portion of theinsulation material 106 with a recessedupper surface 106S and a second region of insulating material, i.e., theelevated regions 120 of the insulating material that are positioned adjacent the first region of insulating material. In this example, theupper surface 106S of the first region of theisolation structure 128 is positioned at a first level and theupper surface 120S of the second region of theisolation structure 128 is positioned at a second level, wherein the first level is below the second level. Additionally, thegate structure 130A comprises a first portion and a second portion, wherein the first portion of thegate structure 130A is positioned above the first region of the isolation structure and above the at least one fin structure, e.g., one of thefin structures gate structure 130A is positioned above the second portion of theisolation structure 128, i.e., one or both of the end portions of thegate structure 130 is positioned aboveelevated regions 120 of insulating material. - With reference to the two devices 101 shown in
FIG. 18 , another illustrative IC product disclosed herein comprises afirst transistor 101A comprising at least one first fin structure, e.g., one of thefin structures fin structures isolation structure 128 comprising an upper surface having a first region, a second region and a third region that is positioned between the first region and the second region, wherein the first region of theisolation structure 128 is positioned adjacent the at least one first fin structure and the second region of theisolation structure 128 is positioned adjacent the at least one second fin structure. In this example, theupper surface 106S of the first and second regions of theisolation structure 128 are positioned at a first level and anupper surface 120S of the third region of theisolation structure 128 is positioned at a second level, wherein the first level is below the second level. This embodiment of theIC product 100 also includes a sharedgate structure 130 comprising a first portion, a second portion and a third portion, wherein the second portion is positioned between the first portion and the third portion. The first portion of the sharedgate structure 130 is positioned above the first region of theisolation structure 128 and above the at least one first fin structure, e.g., one of thefin structures gate structure 130 is positioned above the second region of theisolation structure 128 and above the at least one second fin structure, e.g., one of thefin structures gate structure 130 is positioned above the second portion of theisolation structure 128. - The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is there-fore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
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