US20210257480A1 - Multi-Gate Device and Method of Fabrication Thereof - Google Patents
Multi-Gate Device and Method of Fabrication Thereof Download PDFInfo
- Publication number
- US20210257480A1 US20210257480A1 US17/238,569 US202117238569A US2021257480A1 US 20210257480 A1 US20210257480 A1 US 20210257480A1 US 202117238569 A US202117238569 A US 202117238569A US 2021257480 A1 US2021257480 A1 US 2021257480A1
- Authority
- US
- United States
- Prior art keywords
- layer
- semiconductor
- gate
- sacrificial
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 claims abstract description 286
- 239000004065 semiconductor Substances 0.000 claims abstract description 212
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 125000006850 spacer group Chemical group 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 239000000463 material Substances 0.000 claims description 56
- 238000000151 deposition Methods 0.000 claims description 36
- 238000002955 isolation Methods 0.000 claims description 28
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 22
- 239000000203 mixture Substances 0.000 claims description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 11
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 357
- 230000008569 process Effects 0.000 description 191
- 238000005229 chemical vapour deposition Methods 0.000 description 25
- 238000000231 atomic layer deposition Methods 0.000 description 18
- 239000003989 dielectric material Substances 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 230000003647 oxidation Effects 0.000 description 15
- 238000007254 oxidation reaction Methods 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- 238000002161 passivation Methods 0.000 description 11
- 238000005240 physical vapour deposition Methods 0.000 description 11
- 238000001039 wet etching Methods 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- 230000008901 benefit Effects 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 7
- -1 GaAsP Inorganic materials 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 230000002829 reductive effect Effects 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 230000009969 flowable effect Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000002135 nanosheet Substances 0.000 description 5
- 239000002070 nanowire Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 230000000670 limiting effect Effects 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000005350 fused silica glass Substances 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- 229910002370 SrTiO3 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 2
- 229910002938 (Ba,Sr)TiO3 Inorganic materials 0.000 description 1
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- AIRCTMFFNKZQPN-UHFFFAOYSA-N AlO Inorganic materials [Al]=O AIRCTMFFNKZQPN-UHFFFAOYSA-N 0.000 description 1
- 229910017121 AlSiO Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910018245 LaO Inorganic materials 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910004481 Ta2O3 Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GEIAQOFPUVMAGM-UHFFFAOYSA-N ZrO Inorganic materials [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- ZDZIJHSDFUXADX-UHFFFAOYSA-N azanium hydrogen peroxide hydroxide hydrate Chemical compound O.OO.[OH-].[NH4+] ZDZIJHSDFUXADX-UHFFFAOYSA-N 0.000 description 1
- ONRPGGOGHKMHDT-UHFFFAOYSA-N benzene-1,2-diol;ethane-1,2-diamine Chemical compound NCCN.OC1=CC=CC=C1O ONRPGGOGHKMHDT-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910000167 hafnon Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000004224 protection Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Definitions
- multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs).
- One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET).
- the FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel.
- GAA devices get their name from the gate structure which can extend around the channel region providing access to the channel on four sides.
- GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs.
- CMOS complementary metal-oxide-semiconductor
- dielectric fins have been introduced to improve the uniformity of fins (including semiconductor fins and dielectric fins) and define space for source/drain (S/D) features.
- Sacrificial capping layers comprising crystalline semiconductor materials may also be introduced to fill between semiconductor fins and dielectric fins to reserve space for metal gate stacks in a replacement gate process. Due to natural crystal orientation, sacrificial capping layers may form a quadrilateral cavity defined by facets, such as (111) facets after an etch process, which may result in metal gate stack and inner spacer taper profiles and in turn cause S/D epi defects. Therefore, while the current methods have been satisfactory in many respects, challenges with respect to performance of the resulting device may not be satisfactory in all respects.
- FIGS. 1A and 1B show a flow chart of a method for forming a multi-gate device, according to one or more aspects of the present disclosure.
- FIGS. 2A, 3A, 9A, 10A, 11A, 12A, and 13A illustrate perspective views of a semiconductor structure during a fabrication process according to the method of FIGS. 1A and 1B , according to aspects of the present disclosure.
- FIGS. 2B, 3B, 4, 5, 6, 7, 8, 9B, 9C, 9D, 10B, 10C, 10D, 11B, 11C, 11D, 12B, 12C, 12D, 13B, 13C , and 13 D illustrate cross-sectional views of a semiconductor structure during a fabrication process according to the method of FIGS. 1A and 1B , according to aspects of the present disclosure.
- FIGS. 14A and 14B show a flow chart of another method for forming a multi-gate device, according to one or more aspects of the present disclosure.
- FIG. 20A illustrates a perspective view of a semiconductor structure during a fabrication process according to the method of FIGS. 14A and 14B , according to aspects of the present disclosure.
- FIGS. 15, 16, 17, 18, 19, 20B, 20C, and 20D illustrate cross-sectional views of a semiconductor structure during a fabrication process according to the method of FIGS. 14A and 14B , according to aspects of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within +/ ⁇ 10% of the number described, unless otherwise specified. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.
- multi-gate devices include those transistors whose gate structures are formed on at least two-sides of a channel region. These multi-gate devices may include a p-type metal-oxide-semiconductor device or an n-type metal-oxide-semiconductor device. Specific examples may be presented and referred to herein as FinFET, on account of their fin-like structure. Also presented herein are embodiments of a type of multi-gate transistor referred to as a gate-all-around (GAA) device.
- GAA gate-all-around
- a GAA device includes any device that has its gate structure, or portion thereof, formed on 4-sides of a channel region (e.g., surrounding a portion of a channel region).
- Devices presented herein also include embodiments that have channel regions disposed in nanosheet channel(s), nanowire channel(s), bar-shaped channel(s), and/or other suitable channel configuration.
- Presented herein are embodiments of devices that may have one or more channel regions (e.g., nanowires/nanosheets) associated with a single, contiguous gate structure.
- the teaching can apply to a single channel (e.g., single nanowire/nanosheet) or any number of channels.
- semiconductor devices may benefit from aspects of the present disclosure.
- Embodiments of the present disclosure offer advantages over the existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments.
- embodiments discussed herein include methods and structures for providing dielectric fins for improving fin uniformity and defining space for source/drain (S/D) features, and sacrificial capping layers with amorphous or polycrystalline semiconductor material for reserving space for metal gate stacks.
- the amorphous or polycrystalline semiconductor material allows sacrificial capping layers to maintain vertical footing after etching process, which in turn improves inner spacer layer footing profile and metal gate stack footing profile and reduces S/D feature defects (e.g., pits in S/D features) in footing regions.
- FIGS. 1A and 1B Illustrated in FIGS. 1A and 1B is a method 100 of semiconductor fabrication including fabrication of multi-gate devices.
- the method 100 is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method 100 , and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method.
- the method 100 is described below in conjunction with FIGS. 2A-13D .
- FIGS. 2A, 3A, 9A, 10A, 11A, 12A, and 13A are perspective views of an embodiment of a semiconductor device 200 according to various stages of the method 100 of FIGS. 1A and 1B .
- FIGS. 9C, 10C, 11C, 12C, and 13C are corresponding cross-sectional views of an embodiment of the semiconductor device 200 along a second cut (e.g., cut C-C in FIG. 9A ), which is in the channel region and along a lengthwise direction of the channel.
- FIGS. 9C, 10C, 11C, 12C, and 13C are corresponding cross-sectional views of an embodiment of the semiconductor device 200 along a second cut (e.g., cut C-C in FIG. 9A ), which is in the channel region and along a lengthwise direction of the channel.
- 9D, 10D, 11D, 12D, and 13D are corresponding cross-sectional views of an embodiment of the semiconductor device 200 along a third cut (e.g., cut D-D in FIG. 9A ), which is in a gate region approximate to the channel and along a lengthwise direction of the channel.
- a third cut e.g., cut D-D in FIG. 9A
- the exemplary semiconductor devices may include various other devices and features, such as other types of devices such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM) and/or other logic circuits, etc., but is simplified for a better understanding of the inventive concepts of the present disclosure.
- the exemplary devices include a plurality of semiconductor devices (e.g., transistors), including P-FETs, N-FETs, etc., which may be interconnected.
- the method 100 at operation 102 provides (or is provided with) a semiconductor device (or device) 200 .
- the device 200 includes a substrate 202 and an epitaxial stack 204 above the substrate 202 .
- the substrate 202 may be a semiconductor substrate such as a silicon substrate.
- the substrate 202 may include various layers, including conductive or insulating layers formed on a semiconductor substrate.
- the substrate 202 may include various doping configurations depending on design requirements as is known in the art.
- n-wells, p-wells may be formed on the substrate 202 in regions designed for different device types (e.g., n-type field effect transistors (N-FET), p-type field effect transistors (P-FET)).
- the suitable doping may include ion implantation of dopants and/or diffusion processes.
- the substrate 202 may have isolation features (e.g., shallow trench isolation (STI) features) interposing the regions providing different device types.
- the substrate 202 may also include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond.
- the substrate 202 may include a compound semiconductor and/or an alloy semiconductor.
- the substrate 202 may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and/or may have other suitable enhancement features.
- epi-layer epitaxial layer
- SOI silicon-on-insulator
- the epitaxial stack 204 includes epitaxial layers 206 of a first composition interposed by epitaxial layers 208 of a second composition.
- the first and second compositions can be different.
- the epitaxial layers 208 may include the same composition as the substrate 202 .
- the epitaxial layers 206 are silicon germanium (SiGe) and the epitaxial layers 208 are silicon (Si).
- SiGe silicon germanium
- Si silicon
- other embodiments are possible including those that provide for a first composition and a second composition having different oxidation rates and/or etch selectivity.
- either of the epitaxial layers 206 , 208 of the first composition or the second composition may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof.
- germanium germanium
- a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide
- an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof.
- the epitaxial layers 206 and 208 are substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm-3 to about 1 ⁇ 1017 cm-3), where for example, no intentional doping is performed during the epitaxial growth process.
- epitaxial growth of the epitaxial layers 206 , 208 of the first composition or the second composition may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes.
- the substrate 202 is a crystalline substrate, and the epitaxial layers 206 , 208 are crystalline semiconductor layers.
- each epitaxial layer 206 has a thickness ranging from about 2 nanometers (nm) to about 6 nm.
- the epitaxial layers 206 may be substantially uniform in thickness.
- the top epitaxial layer 206 is thinner (e.g., half the thickness) than other epitaxial layers 206 thereunder.
- the top epitaxial layer 206 functions as a capping layer providing protections to other epitaxial layers in subsequent processes.
- each epitaxial layer 208 has a thickness ranging from about 6 nm to about 12 nm. In some embodiments, the epitaxial layers 208 of the stack are substantially uniform in thickness.
- the epitaxial layers 208 or portions thereof may form channel member(s) of the subsequently-formed multi-gate device 200 and the thickness is chosen based on device performance considerations.
- channel member(s) is used herein to designate any material portion for channel(s) in a transistor with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion.
- this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including for example a cylindrical in shape or substantially rectangular cross-section.
- the epitaxial layers 206 in channel regions(s) may eventually be removed and serve to define a vertical distance between adjacent channel members for a subsequently-formed multi-gate device and the thickness is chosen based on device performance considerations. Accordingly, the epitaxial layers 206 may also be referred to as sacrificial layers, and epitaxial layers 208 may also be referred to as channel layers.
- FIGS. 2A and 2B four (4) layers of the epitaxial layers 206 and three (3) layers of the epitaxial layers 208 are alternately arranged as illustrated in FIGS. 2A and 2B , which is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of epitaxial layers can be formed in the epitaxial stack 204 ; the number of layers depending on the desired number of channels members for the device 200 . In some embodiments, the number of epitaxial layers 208 is between 2 and 10.
- epitaxial layers 206 , 208 are shown as having a particular stacking sequence, where an epitaxial layer 206 is the topmost layer of the epitaxial stack 204 , other configurations are possible.
- an epitaxial layer 208 may alternatively be the topmost layer of the epitaxial stack 204 .
- the order of growth for the epitaxial layers 206 , 208 , and thus their stacking sequence, may be switched or otherwise be different than what is shown in the figures, while remaining within the scope of the present disclosure.
- each of the semiconductor fins 210 includes a substrate portion 203 formed from the substrate 202 and an epitaxial stack portion 204 formed from portions of each of the epitaxial layers of the epitaxial stack including epitaxial layers 206 and 208 .
- the semiconductor fins 210 may be fabricated using suitable processes including double-patterning or multi-patterning processes.
- double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
- a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the semiconductor fins 210 by etching initial epitaxial stack 204 .
- the etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes.
- a hard mask (HM) layer 212 is formed over the epitaxial stack 204 prior to patterning the semiconductor fins 210 .
- the HM layer 212 includes an oxide layer 212 A (e.g., a pad oxide layer that may include SiO 2 ) and a nitride layer 212 B (e.g., a pad nitride layer that may include Si 3 N 4 ) formed over the oxide layer 212 A.
- the oxide layer 212 A may act as an adhesion layer between the epitaxial stack 204 and the nitride layer 212 B and may act as an etch stop layer for etching the nitride layer 212 B.
- the HM layer 212 includes thermally grown oxide, chemical vapor deposition (CVD)-deposited oxide, and/or atomic layer deposition (ALD)-deposited oxide.
- the HM layer 212 includes a nitride layer deposited by CVD and/or other suitable technique.
- the semiconductor fins 210 may subsequently be fabricated using suitable processes including photolithography and etch processes.
- the photolithography process may include forming a photoresist layer (not shown) over the HM layer 212 , exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist.
- patterning the resist to form the masking element may be performed using an electron beam (e-beam) lithography process.
- e-beam electron beam
- the masking element may then be used to protect regions of the substrate 202 , and layers formed thereupon, while an etch process forms trenches 214 in unprotected regions through the HM layer 212 , through the epitaxial stack 204 , and into the substrate 202 , thereby leaving the plurality of extending semiconductor fins 210 .
- the trenches 214 may be etched using dry etching, wet etching, RIE, and/or other suitable processes.
- forming the semiconductor fins 210 may include a trim process to decrease the width of the semiconductor fins 210 .
- the trim process may include wet and/or dry etching processes.
- the method 100 forms a passivation liner along top and sidewall surfaces of the semiconductor fins 210 .
- the passivation liner 216 is an oxide layer (e.g., SiO 2 ) formed by oxidizing exposed surfaces of the semiconductor fins 210 and the substrate 202 .
- the oxidation process results in the oxide layer having a determined thickness.
- the oxide layer may have a thickness from about 1 nm to about 3 nm.
- the oxidation process comprises a rapid thermal oxidation (RTO) process, high pressure oxidation (HPO), chemical oxidation process, in-situ stream generation (ISSG) process, or enhanced in-situ stream generation (EISSG) process.
- RTO rapid thermal oxidation
- HPO high pressure oxidation
- the RTO process is performed at a temperature of about 400° C. to about 700° C., using O 2 and O 3 as reaction gases, for about 1 second to about 30 seconds.
- an HPO is performed using a process gas of O 2 , O 2 +N 2 , N 2 , or the like, at a pressure from about 1 atm to about 25 atm and a temperature from about 300° C. to about 700° C., for about 1 minute to about 10 minutes.
- Examples of a chemical oxidation process include wet SPM clean, wet O 3 /H 2 O, or the like.
- the O 3 may have a concentration of about 1 ppm to about 50 ppm.
- the method 100 deposits a semiconductor liner on the passivation liner 216 .
- the semiconductor liner 218 is disposed conformally on top and sidewall surfaces of the semiconductor fins 210 .
- the term “conformally” may be used herein for ease of description upon a layer having substantial same thickness over various regions.
- the semiconductor liner 218 may be formed by depositing a semiconductor material over the passivation liner 216 using processes such as, CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process.
- the semiconductor liner 218 may have a thickness from about 2 nm to about 5 nm. Due to the underneath passivation liner 216 , the crystalline structures in the epitaxial layers 206 , 208 and the substrate would not extend into the semiconductor composition in the semiconductor liner 218 . The material structure form of the semiconductor composition in the semiconductor liner 218 stays in amorphous form instead.
- the semiconductor liner 218 includes amorphous silicon and may also be referred to as an amorphous silicon layer. As will be explained in detail below, the semiconductor liner 218 functions as a seed layer, allowing an amorphous or polycrystalline semiconductor layer (i.e., subsequently-formed sacrificial capping layer) to be deposited thereon.
- the method 100 forms isolation features, such as shallow trench isolation (STI) features, between the semiconductor fins 210 .
- STI features 220 is disposed on the substrate 202 interposing the semiconductor fins 210 .
- a dielectric layer is first deposited over the substrate 202 , filling the trenches 214 with dielectric material.
- the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials.
- the dielectric layer may be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and/or other suitable process.
- the device 200 may be annealed, for example, to improve the quality of the dielectric layer.
- the dielectric layer may include a multi-layer structure, for example, having one or more liner layers.
- a surface portion of the semiconductor liner 218 may intermix with the dielectric layer, resulting in a reduced thickness of the semiconductor liner 218 .
- the semiconductor liner 218 may lose over half in its thickness.
- a reduced thickness of the semiconductor liner 218 may range from about 1 nm to about 3 nm.
- the semiconductor liner 218 has a reduced thickness less than the passivation liner 216 after operation 110 .
- the deposited dielectric material is thinned and planarized, for example by a chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- the HM layer 212 functions as a CMP stop layer.
- the dielectric layer interposing the semiconductor fins 210 are recessed. Referring to the example of FIG. 5 , the STI features 220 are recessed providing the semiconductor fins 210 extending above the STI features 220 .
- the recessing process may include a dry etching process, a wet etching process, and/or a combination thereof.
- a recessing depth is controlled (e.g., by controlling an etching time) so as to result in a desired height of the exposed upper portion of the semiconductor fins 210 .
- the desired height exposes each of the layers of the epitaxial stack 204 .
- a top surface of the STI features 220 is recessed below the bottommost epitaxial layer 206 .
- the method 100 deposits a capping layer on top and sidewall surfaces of the semiconductor fins.
- the capping layer 222 is selectively deposited over the device 200 .
- the capping layer 222 may be selectively and conformally deposited over the exposed surfaces of the semiconductor liner 218 .
- the capping layer 222 is not deposited on top surfaces of the STI features 220 between the semiconductor fins 210 .
- the capping layer 222 may be a semiconductor layer and deposited by an epitaxial growing process, such that the epitaxial growth of the capping layer 222 is limited to exposed semiconductor surfaces of the semiconductor liner 218 , which functions as a seed layer, but not on dielectric material surfaces of the STI features 220 .
- the semiconductor liner 218 intermixes with the capping layer 222 and becomes a portion of the capping layer 222 . Therefore, portions of the semiconductor liner 218 above the STI features 220 are not shown in FIG. 6 .
- the semiconductor liner 218 with a further reduced thickness may remain underneath the capping layer 222 , in some embodiments.
- the capping layer 222 may be deposited by an MBE process, an MOCVD process, an ALD process, and/or other suitable epitaxial growth processes.
- the semiconductor liner 218 is an amorphous silicon layer
- the capping layer 222 includes the same semiconductor material as the epitaxial layer 206 , such as silicon germanium (SiGe). Due to the amorphous form of the seed layer, the semiconductor material in the capping layer 222 won't grow in crystalline structures but in either amorphous form or polycrystalline form instead, such as amorphous SiGe or polycrystalline SiGe in some embodiments.
- the capping layer 222 may have a mixture of semiconductor material in both amorphous form and polycrystalline form, such as 60% SiGe in amorphous form and 40% SiGe in polycrystalline form.
- amorphous or polycrystalline is used herein to designate composition in amorphous form, polycrystalline form, or a combination thereof.
- the capping layer 222 reserves a space for subsequently-formed metal gate stack and will be removed in a subsequent processing stage. Therefore, the capping layer 222 is also referred to as a sacrificial capping layer.
- the method 100 forms a dielectric fin between adjacent semiconductor fins.
- a dielectric layer 224 is deposited conformally within the trenches 214 including along sidewalls of the sacrificial capping layer 222 and along a top surface of the STI features 220 .
- a dielectric layer 226 is deposited over the dielectric layer 224 .
- the dielectric layers 224 , 226 may collectively define a dielectric fin 228 (or hybrid fin 228 ).
- a dielectric fin 228 may further include a high-K dielectric layer formed over the dielectric layers 224 , 226 , for example after recessing of the dielectric layers 224 , 226 , as discussed below.
- the dielectric layers 224 , 226 may include SiN, SiCN, SiOC, SiOCN, SiOx, or other appropriate material.
- the dielectric layer 224 may include a low-K dielectric layer, and the dielectric layer 226 may include a flowable oxide layer.
- the dielectric layers 224 , 226 may be deposited by a CVD process, an ALD process, a PVD process, a spin-coating and baking process, and/or other suitable process.
- a CMP process may be performed to remove excess material portions and to planarize a top surface of the device 200 .
- the method 200 at operation 124 may further include a recessing process, a high-K dielectric layer deposition process, and a CMP process. Still referring to FIGS. 7 and 8 , in an embodiment of operation 124 , a recessing process is performed to remove top portions of the dielectric layers 224 and 226 .
- the recessing process may include a dry etching process, a wet etching process, and/or a combination thereof.
- a recessing depth is controlled (e.g., by controlling an etching time) to result in a desired recess depth.
- the recessing process may optionally remove at least part of the sacrificial capping layer 222 .
- a high-K dielectric layer 230 is deposited within trenches formed by the recessing process.
- the high-K dielectric layer 230 may include HfO 2 , ZrO 2 , HfAlOx, HfSiOx, Y 2 O 3 , Al 2 O 3 , or another high-K material.
- the high-K dielectric layer 230 may be deposited by a CVD process, an ALD process, a PVD process, and/or other suitable process.
- a CMP process is performed to remove excess material portions and to planarize a top surface of the device 200 .
- the CMP process removes a portion of the sacrificial capping layer 222 from the top of the semiconductor fins 210 to expose the HM layer 212 .
- a dielectric fin 228 is defined as having a lower portion including the recessed portions of the dielectric layers 224 , 226 and an upper portion including the high-K dielectric layer 230 .
- a height of the high-K dielectric layer 230 may be about 10-30 nm.
- the dielectric fin 228 may be alternatively described as a bi-layer dielectric having a high-K upper portion and a low-K lower portion.
- a height ratio of the upper portion to the lower portion may be about 1:20 to about 20:1. The height ratio may be adjusted, for example, by changing the recess depth and thus the height of the high-K dielectric layer 230 , as noted above.
- the dielectric fins 228 are used to effectively prevent the undesirable lateral merging of the epitaxial S/D features formed on adjacent semiconductor fins 210 , as will be discussed in more detail below.
- the method 100 then proceeds to operation 126 ( FIG. 1B ) where sacrificial layers/features are formed and in particular, a dummy gate structure. While the present discussion is directed to a replacement gate (or gate-last) process whereby a dummy gate structure is formed and subsequently replaced, other configurations may be possible.
- FIG. 9A is a perspective view of the device 200
- FIG. 9B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line)
- FIG. 9C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line)
- FIG. 9D refers to a cross-sectional view taken though the sacrificial capping layer 222 and along the lengthwise direction of the channel (e.g., along the D-D line).
- the gate stack 232 is a dummy (sacrificial) gate stack that is subsequently removed (with reference to operation 136 ).
- the gate stack 232 is a dummy gate stack and will be replaced by the final gate stack at a subsequent processing stage of the device 200 .
- the dummy gate stack 232 may be replaced at a later processing stage by a high-K dielectric layer (HK) and metal gate electrode (MG) as will be discussed in more detail below.
- the HM layer 212 and a top portion of the sacrificial capping layer 222 may initially be etched-back.
- the topmost epitaxial layer 206 may act as an etch stop layer for etching the HM layer 212 and be subsequently removed.
- the top potion of the sacrificial capping layer 222 may be removed together with the topmost epitaxial layer 206 by the same etchant that targets the same semiconductor material, such as SiGe.
- a top surface of the etched-back sacrificial capping layer 222 is substantially level with top surfaces of the topmost epitaxial layer 208 of the semiconductor fins 210 .
- the etch-back of the HM layer 212 and the top portion of the sacrificial capping layer 222 may be performed using a wet etch process, a dry etch process, a multiple-step etch process, and/or a combination thereof.
- the HM layer 212 may be removed, for example, by a wet etching process using H 3 PO 4 or other suitable etchants.
- the dummy gate stack 232 is disposed over the semiconductor fins 210 , the sacrificial capping layer 222 , and the dielectric fins 228 .
- the portion of the semiconductor fins 210 underlying the dummy gate stack 232 may be referred to as the channel region.
- the dummy gate stack 232 may also define source/drain (S/D) regions of the semiconductor fins 210 , for example, the regions of the semiconductor fin 210 adjacent and on opposing sides of the channel region.
- the dummy gate stack 232 includes a dummy dielectric layer 234 and a dummy electrode layer 236 .
- the dummy dielectric layer 234 may include SiO 2 , silicon nitride, a high-K dielectric material and/or other suitable material.
- the dummy dielectric layer 234 may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process.
- SACVD subatmospheric CVD
- the dummy dielectric layer 234 may be used to prevent damages to the semiconductor fins 210 by subsequent processes (e.g., subsequent formation of the dummy gate stack).
- the dummy gate stack 232 is formed by various process steps such as layer deposition, patterning, etching, as well as other suitable processing steps.
- exemplary layer deposition processes include CVD (including both low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof.
- the patterning process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof.
- the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods.
- the dummy electrode layer 236 may include polycrystalline silicon (polysilicon).
- the hard mask 240 includes an oxide layer 240 A such as a pad oxide layer that may include SiO 2 .
- hard mask 240 includes a nitride layer 240 B such as a pad nitride layer that may include Si 3 N 4 , silicon oxynitride and/or silicon carbide.
- the dummy dielectric layer 234 is removed from the S/D regions of the semiconductor fins 210 .
- the etch process may include a wet etch, a dry etch, and/or a combination thereof. The etch process is chosen to selectively etch the dummy dielectric layer 234 without substantially etching the semiconductor fins 210 , the hard mask 240 , and the dummy electrode layer 236 .
- the method 100 forms sidewall spacers on sidewall surfaces of the dummy gate stacks.
- the sidewall spacers 242 may have a thickness of about 2-10 nm.
- the sidewall spacers 242 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-K material, and/or combinations thereof.
- the sidewall spacers 242 include multiple layers, such as a liner spacer layer 242 A and a main spacer layer 242 B, and the like.
- the sidewall spacers 242 may be formed by conformally depositing a dielectric material over the device 200 using processes such as a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. Following the conformal deposition of the dielectric material, portions of the dielectric material used to form the sidewall spacers 242 may be etched-back to expose portions of the semiconductor fins 210 not covered by the dummy gate stacks 232 (e.g., for example, in source/drain regions).
- a CVD process such as a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process.
- SACVD subatmospheric CVD
- ALD atomic layer deposition
- PVD vapor deposition
- portions of the dielectric material used to form the sidewall spacers 242
- the etch-back process removes portions of dielectric material used to form the sidewall spacers 242 along a top surface of the dummy gate stack 232 , thereby exposing the hard mask layer 240 .
- the etch-back process may include a wet etch process, a dry etch process, a multiple-step etch process, and/or a combination thereof. It is noted that after the etch-back process, the sidewall spacers 242 remain disposed on sidewall surfaces of the dummy gate stack 232 .
- the method 100 forms inner spacers. Still referring to FIGS. 9A-9D , in some embodiments of operation 130 , a source/drain etch process is performed prior to the forming of inner spacers. A source/drain etch process is performed to remove portions of the semiconductor fins 210 and the sacrificial capping layer 222 not covered by the dummy gate stack 232 (e.g., in source/drain regions) and that were previously exposed (e.g., during the sidewall spacer 242 etch-back process).
- the source/drain etch process may serve to remove the exposed epitaxial layer portions 206 , 208 in source/drain regions of the device 200 (as well as the passivation liner 216 ) to expose underlying substrate portions 203 of the semiconductor fins 210 .
- the source/drain etch process may include a dry etching process, a wet etching process, and/or a combination thereof.
- FIG. 10A is a perspective view of the device 200
- FIG. 10B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line)
- FIG. 10C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line)
- FIG. 10A is a perspective view of the device 200
- FIG. 10B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line)
- FIG. 10C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line)
- FIG. 10A is a perspective view of the device 200
- FIG. 10B refers to a cross-sectional view taken in the gate region and perpendicular to a
- 10D refers to a cross-sectional view taken though the sacrificial capping layer 222 and along the lengthwise direction of the channel (e.g., along the D-D line).
- the amount of etching of the epitaxial layers 206 and the sacrificial capping layer 222 is in a range from about 2 nm to about 10 nm in some embodiments.
- end portions (edges) of the epitaxial layer 206 and the sacrificial capping layer 222 under the dummy gate stack 232 are substantially flush with the sidewall surfaces of the dummy electrode layer 236 .
- “being substantially flush” means the difference in the relative position is less than about 1 nm.
- the lateral etching process may use the same etchant, such as, but not limited to, ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions.
- NH 4 OH ammonium hydroxide
- TMAH tetramethylammonium hydroxide
- EDP ethylenediamine pyrocatechol
- KOH potassium hydroxide
- FIG. 11A is a perspective view of the device 200
- FIG. 11B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line)
- FIG. 11C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line)
- FIG. 11A is a perspective view of the device 200
- FIG. 11B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line)
- FIG. 11C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line)
- FIG. 11A is a perspective view of the device 200
- FIG. 11B refers to a cross-sectional view taken in the gate region and perpendicular to a
- the insulating layer 11D refers to a cross-sectional view taken though the sacrificial capping layer 222 and along the lengthwise direction of the channel (e.g., along the D-D line).
- the insulating layer may include a dielectric material, such as SiN, SiOC, SiOCN, SiCN, SiO 2 , and/or other suitable material.
- the insulating layer is conformally deposited, for example, by ALD or any other suitable method. After the conformal deposition of the insulating layer, an etch-back process is performed to partially remove the insulating layer from outside of the recesses 246 . By this etching the insulating layer remains substantially within the recesses 246 .
- the etch-back process may also etch a portion of the high-K dielectric layer 230 of the dielectric fins 228 not covered by the dummy gate stack 232 . Since the insulating layer also fills the recesses 246 provided by the recessing of the sacrificial capping layer 222 , the inner spacers 248 are continuously connected and wrap around the lateral ends of the epitaxial layers 208 in the channel region.
- the continuously connected inner spacers 248 may also be referred to jointly as an inner spacer layer.
- the method 100 forms S/D features (also referred to as epitaxial S/D features).
- S/D features 250 are formed in S/D regions adjacent to and on either side of the dummy gate stack 232 .
- the S/D features 250 may be formed over the exposed substrate portions 203 of the semiconductor fins 210 and in contact with the adjacent inner spacers 248 and the semiconductor channel layers (the epitaxial layers 208 ).
- the S/D features 250 is also in contact with a top surface of the STI features 220 and sidewalls of the dielectric fins 228 .
- the S/D features 250 are formed by epitaxially growing a semiconductor material layer in the S/D regions.
- the S/D features 250 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material.
- the S/D features 250 may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants, such as boron or BF 2 ; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof.
- an implantation process i.e., a junction implant process
- the S/D features 250 in an NMOS device include SiP
- those in a PMOS device include GeSnB and/or SiGeSnB.
- silicidation or germano-silicidation may be formed on the S/D features 250 .
- silicidation such as nickel silicide
- silicidation may be formed by depositing a metal layer over the epitaxial S/D features 250 , annealing the metal layer such that the metal layer reacts with silicon in the S/D features 250 to form the metal silicidation, and thereafter removing the non-reacted metal layer.
- the dielectric fins 228 which may have a partially etched-back high-K dielectric layer 230 , effectively prevents the undesirable lateral merging of the S/D features 250 formed on adjacent semiconductor fins 210 .
- footing profile 252 (highlighted in a dotted circle in FIG. 11D ) of end portions of the sacrificial capping layer 222 has a substantially straight etched surface (sidewall) perpendicular to a top surface of the STI features 220 .
- the etched surface at the footing profile 252 may have a quadrilateral cavity defined by (111) facets.
- the quadrilateral cavity may cause notches in the footing profile of the inner spacer layer 248 and in turn cause defects, such as pits, in the subsequently-formed S/D features 250 .
- subsequently-formed metal gate structure may also have facets in the footing profile.
- FIG. 12A is a perspective view of the device 200
- FIG. 12B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line)
- FIG. 12C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line)
- FIG. 12A is a perspective view of the device 200
- FIG. 12B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line)
- FIG. 12C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line)
- the CESL 256 includes a silicon nitride layer, silicon oxide layer, a silicon oxynitride layer, and/or other materials known in the art.
- the CESL 256 may be formed by plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes.
- PECVD plasma-enhanced chemical vapor deposition
- the ILD layer 258 includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials.
- TEOS tetraethylorthosilicate
- BPSG borophosphosilicate glass
- FSG fused silica glass
- PSG phosphosilicate glass
- BSG boron doped silicon glass
- the ILD layer 258 may be deposited by a PECVD process or other suitable deposition technique.
- the semiconductor device 200 may be subject to a high thermal budget process to anneal the ILD layer.
- a planarization process may be performed to remove excessive dielectric materials.
- a planarization process includes a chemical mechanical planarization (CMP) process which removes portions of the ILD layer 258 (and CESL 256 , if present) overlying the dummy gate stack 232 and planarizes a top surface of the semiconductor device 200 .
- CMP chemical mechanical planarization
- the CMP process also removes hard mask 240 and exposes the dummy electrode layer 236 .
- the method 100 removes the dummy gate stack 232 to form a gate trench 260 in the channel region, as shown in FIGS. 12A-12D .
- a final gate structure (e.g., including a high-K dielectric layer and metal gate electrode) may be subsequently formed in the gate trench 260 , as will be described below.
- Operation 136 may include one or more etching processes that are selective to the material in the dummy gate stack 232 .
- the removal of the dummy gate stack 232 may be performed using a selective etch process such as a selective wet etch, a selective dry etch, or a combination thereof.
- the epitaxial layers 206 and 208 of the semiconductor fins 210 and the sacrificial capping layer 222 are exposed in the gate trench 260 .
- the method 100 removes the epitaxial layers 206 from the semiconductor fins 210 and the sacrificial capping layer 222 (as well as the passivation liner 216 ) in the gate trench 260 .
- the resultant structure 200 is shown in FIGS. 13A-13D .
- the epitaxial layers 206 and the sacrificial capping layer 222 both include SiGe (in crystalline structure and amorphous or polycrystalline structure, respectively) and the epitaxial layers 208 are silicon, allowing for the selective removal of the epitaxial layers 206 and the sacrificial capping layer 222 .
- the epitaxial layers 206 and the sacrificial capping layer 222 are removed by a selective wet etching process.
- the selective wet etching includes an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture).
- the selective removal includes SiGe oxidation followed by a SiGeOx removal.
- the oxidation may be provided by O 3 clean and then SiGeOx removed by an etchant such as NH 4 OH.
- gaps 262 are provided between the adjacent channel members (e.g., nanowires or nanosheet) in the channel region (e.g., gaps 262 between epitaxial layers 208 ).
- the gaps 262 may be filled with ambient environment conditions (e.g., air, nitrogen).
- FIG. 13A is a perspective view of the device 200
- FIG. 13B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line)
- FIG. 13C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line)
- FIG. 13A is a perspective view of the device 200
- FIG. 13B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line)
- FIG. 13C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line)
- the gate structure 13D refers to a cross-sectional view taken though a gate region previously reserved by the sacrificial capping layer 222 and along the lengthwise direction of the channel (e.g., along the D-D line).
- the gate structure may be the gate of a multi-gate transistor.
- the gate structure may be a high-K/metal gate (HK MG) stack, however other compositions are possible.
- the gate structure forms the gate associated with the multi-channels provided by the plurality of channel members (e.g., nanosheets or nanowires having gaps therebetween) in the channel region.
- a HK MG stack 264 is formed within the gate trench 260 of the device 200 provided by the release of the epitaxial layers 208 , described above with reference to prior operation 138 .
- the HK MG stack 264 includes an interfacial layer (not shown), a high-K gate dielectric layer 266 formed over the interfacial layer, and a gate electrode layer 268 formed over the high-K gate dielectric layer 266 .
- High-K gate dielectrics include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide ( ⁇ 3.9).
- the gate electrode layer used within HK MG stack may include a metal, metal alloy, or metal silicide.
- the formation of the HK MG stack may include depositions to form various gate materials, one or more liner layers, and one or more CMP processes to remove excessive gate materials and thereby planarize a top surface of the semiconductor device 200 .
- Interposing the HK MG stack 264 and the S/D features 250 is the inner spacers 248 , providing isolation.
- the interfacial layer of the HK MG stack 264 may include a dielectric material such as silicon oxide (SiO 2 ), HfSiO, or silicon oxynitride (SiON).
- the interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method.
- the high-K gate dielectric layer 266 of the HK MG stack 264 may include a high-K dielectric such as hafnium oxide (HfO 2 ).
- the high-K gate dielectric layer 266 of the HK MG stack 264 may include other high-K dielectrics, such as TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST), Al 2 O 3 , Si 3 N 4 , oxynitrides (SiON), combinations thereof, or other suitable material.
- other high-K dielectrics such as TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2
- the high-K gate dielectric layer 266 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and/or other suitable methods. As illustrated in FIG. 13D , in some embodiments, the high-K gate dielectric layer 266 is deposited conformally on sidewalls of the inner spacers 248 and top surfaces of the STI features 220 .
- the gate electrode layer 268 of the HK MG stack 264 may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide.
- the gate electrode layer 268 of HK MG stack 264 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or a combination thereof.
- the gate electrode layer 268 of the HK MG stack 264 may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the gate electrode layer 284 may be formed separately for N-FET and P-FET transistors which may use different metal layers (e.g., for providing an N-type or P-type work function). In various embodiments, a CMP process may be performed to remove excessive metal from the gate electrode layer 268 of the HK MG stack 264 , and thereby provide a substantially planar top surface of the HK MG stack 264 .
- the HK MG stack 264 includes portions that interpose each of the epitaxial layers (channel members) 208 , which form channels of the multi-gate device 200 .
- the device 200 may undergo further processing to form various features and regions known in the art.
- subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate 202 , configured to connect the various features to form a functional circuit that may include one or more multi-gate devices.
- a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines.
- the various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide.
- a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure.
- additional process steps may be implemented before, during, and after the method 100 , and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method 100 .
- FIGS. 14A and 14B demonstrate a flow chart for a method 100 ′.
- the method 100 ′ shares operations 102 and 104 with method 100 .
- the method 100 ′ proceeds to operation 105 .
- the method 100 ′ shares operation 110 with the method 100 .
- the method 100 ′ proceeds to operations 114 , 116 , 118 , and 120 .
- the method 100 ′ shares operations 124 , 126 , 128 , 130 , 132 , 134 , 136 , 138 , and 140 with the method 100 .
- the method 100 ′ is described below in conjunction with FIGS. 15-20D . Shared operations are not repeated below in the interest of conciseness.
- the method 100 ′ at operation 105 deposits a semiconductor liner 270 along top and sidewall surfaces of the semiconductor fins 210 and the top surface of the substrate 202 .
- the semiconductor liner 270 is a silicon layer formed in an epitaxial growth process, such as an MBE process, an MOCVD process, an ALD process, and/or other suitable epitaxial growth processes.
- the epitaxial growth results in the silicon layer having a determined thickness.
- the silicon layer may have a thickness from about 1 nm to about 3 nm.
- the semiconductor material (e.g., Si) of the semiconductor liner 270 extends the crystalline structure of the epitaxial stack 204 through the epitaxial growing process. Therefore, the semiconductor liner 270 may also be referred to a crystalline semiconductor liner.
- the method 100 ′ at operation 110 ( FIG. 14A ) that is shared with the method 100 forms isolation features, such as shallow trench (STI) features 220 , between the semiconductor fins 210 .
- isolation features such as shallow trench (STI) features 220
- a top surface of the STI features 220 is below the bottommost epitaxial layer 206 .
- the crystalline semiconductor liner 270 is stacked between the STI features 220 and the substrate 202 .
- the method 100 ′ at operation 114 performs a passivation treatment to the exposed portions of the crystalline semiconductor liner 270 .
- the passivation treatment may include an oxidation process, a nitridation process, or a combination thereof.
- the passivation treatment is a nitridation process comprising rapid thermal nitridation (RTN) process, high pressure nitridation (HPN), or decoupled plasma nitridation (DPN) process.
- RTN rapid thermal nitridation
- HPN high pressure nitridation
- DPN decoupled plasma nitridation
- the RTN process is performed at a temperature of about 400° C. to about 800° C., using NH3 as reaction gas, for about 1 second to about 180 seconds.
- the HPN process is performed using a process gas of NH 3 at a pressure from about 1 atm to about 25 atm and a temperature from about 300° C. to about 700° C. for about 1 minute to about 10 minutes.
- the DPN process is performed under a power of about 300 Watts to about 2250 Watts, using a process gas of N 2 , NH 3 , N 2 +Ar, N 2 +He, NH 3 +Ar, or the like as process gases.
- the nitridation process causes the semiconductor material in the crystalline semiconductor liner 270 to react with the N, which converts exposed portions of the crystalline semiconductor liner 270 to a nitride compound.
- the crystalline semiconductor liner 270 is a crystalline silicon layer and is converted to silicon nitride after operation 114 .
- the nitridation process may also passivate a surface portion of the STI features 220 (e.g., above a dotted line 272 ).
- the STI features 220 includes silicon oxide and the surface portion above the dotted line 272 is converted to silicon oxynitride after operation 114 , while the bottom portion below the dotted line 272 remains as silicon oxide.
- the dotted line 272 is about 1 nm to about 3 nm from the top surface of the STI features 220 .
- a vertical portion of the crystalline semiconductor liner 270 stacked between the STI features 220 and the substrate 202 which is above the dotted line 272 may also be converted to a nitride compound, such as silicon nitride in one example.
- the method 100 ′ at operation 116 deposits a semiconductor liner 274 on the exposed portions of the nitrified liner 270 and the top surfaces of the STI features 220 .
- the semiconductor liner 274 may be disposed conformally.
- the semiconductor liner 274 may be formed by depositing a semiconductor material over the device 200 using processes such as, CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process.
- the semiconductor liner 274 may have a thickness from about 1 nm to about 3 nm.
- the semiconductor liner 274 includes amorphous silicon and may also be referred to as an amorphous silicon layer. As will be explained in detail below, the semiconductor liner 274 functions as a seed layer, allowing an amorphous or polycrystalline semiconductor layer as a sacrificial capping layer to be deposited thereon.
- the method 100 ′ at operation 118 deposits a capping layer 222 on top and sidewall surfaces of the semiconductor liner 274 .
- the capping layer 222 is conformally deposited over the device 200 .
- the capping layer 222 is a semiconductor layer and deposited by an epitaxial growing process, such that the epitaxial growth of the capping layer 222 is on the exposed semiconductor surfaces of the semiconductor liner 274 as a seed layer.
- the semiconductor liner 274 intermixes with the capping layer 222 and becomes a portion of the capping layer 222 . Accordingly, the semiconductor liner 274 is not shown in FIG. 18 .
- the semiconductor liner 218 with a further reduced thickness may remain underneath the capping layer 222 .
- the capping layer 222 may be deposited by an MBE process, an MOCVD process, an ALD process, and/or other suitable epitaxial growth processes.
- the semiconductor liner 274 is an amorphous silicon layer, and the capping layer 222 includes the same semiconductor material as the epitaxial layer 206 , such as SiGe. Due to the amorphous form of the seed layer, the semiconductor material in the capping layer 222 won't grow in crystalline structures but in amorphous form or polycrystalline form instead, such as amorphous SiGe or polycrystalline SiGe in some embodiments.
- the capping layer 222 reserves a space for subsequently-formed metal gate stack and will be removed in a subsequent processing stage. Therefore, the capping layer 222 is also referred to as a sacrificial capping layer.
- the method 100 ′ at operation 120 performs an etch-back process to remove portions of the sacrificial capping layer 222 to expose top surfaces of the STI features 220 .
- the etch-back process may include a wet etch process, a dry etch process, a multiple-step etch process, and/or a combination thereof. It is noted that after the etch-back process, the capping layer 222 remains disposed on sidewall surfaces of the semiconductor fins 210 . In furtherance of some embodiments, a thinned portion of the capping layer 222 also remains on the top surfaces of the semiconductor fins, as illustrated in FIG. 19 .
- FIG. 20A is a perspective view of the device 200
- FIG. 20B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line)
- FIG. 20C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line)
- FIG. 20A is a perspective view of the device 200
- FIG. 20B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line)
- FIG. 20C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line)
- the device 200 may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate 202 , configured to connect the various features to form a functional circuit that may include one or more multi-gate devices.
- a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines.
- the various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide.
- a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure.
- additional process steps may be implemented before, during, and after the method 100 ′, and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method 100 ′.
- embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof.
- embodiments of the present disclosure provide dielectric fins for improving fin uniformity and defining space for source/drain (S/D) features, and sacrificial capping layers with amorphous or polycrystalline semiconductor material for reserving space for metal gate stacks.
- the amorphous or polycrystalline semiconductor material allows sacrificial capping layers to maintain vertical footing after etching process, which in turn improves inner spacer layer footing profile and metal gate stack footing profile and reduces S/D feature defects in footing regions.
- the dielectric fin and sacrificial capping layer formation method can be easily integrated into existing semiconductor fabrication processes.
- the present disclosure is directed to a method.
- the method includes forming a semiconductor fin extruding from a substrate; forming a sacrificial capping layer on sidewalls of the semiconductor fin; forming first and second dielectric fins sandwiching the semiconductor fin; forming a sacrificial gate stack over the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; forming gate spacers on sidewalls of the sacrificial gate stack; removing the sacrificial gate stack to form a gate trench, wherein the gate trench exposes the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; removing the sacrificial capping layer from the gate trench, thereby exposing the sidewalls of the semiconductor fin; and forming a metal gate stack in the gate trench engaging the semiconductor fin.
- the sacrificial capping layer includes amorphous or polycrystalline semiconductor material.
- the semiconductor material is silicon germanium.
- the forming of the sacrificial capping layer includes depositing an amorphous silicon layer covering the semiconductor fin; forming an isolation feature covering a bottom portion of the amorphous silicon layer; and depositing the sacrificial capping layer over a top portion of the amorphous silicon layer.
- the forming of the sacrificial capping layer includes forming an isolation feature on the sidewalls of the semiconductor fin; depositing an amorphous silicon layer covering the semiconductor fin and the isolation feature; and depositing the sacrificial capping layer covering the amorphous silicon layer.
- the forming of the sacrificial capping layer further includes etching the sacrificial capping layer, thereby exposing a top surface of the isolation feature.
- the method further includes forming an isolation feature on the sidewalls of the semiconductor fin prior to the forming of the sacrificial capping layer, wherein the first and second dielectric fins are in contact with the isolation feature and the sacrificial capping layer.
- the method further includes recessing the semiconductor fin and the sacrificial capping layer after the forming of the gate spacers; and epitaxially growing a source/drain (S/D) feature on the recessed semiconductor fin.
- S/D source/drain
- the first and second dielectric fins limit the epitaxially growing of the S/D feature in a lateral direction.
- the semiconductor fin includes a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are alternately arranged.
- the method further includes laterally etching the sacrificial layers and the sacrificial capping layer, thereby forming cavities between the channel layers; and depositing an inner spacer layer in the cavities.
- the present disclosure is directed to a method of fabricating a semiconductor device.
- the method includes forming a stack of a first type and a second type epitaxial layers on a semiconductor substrate, the first type and second type epitaxial layers having different material compositions and the first type and second type epitaxial layers being alternatingly disposed in a vertical direction; patterning the stack to form a plurality of fin elements; depositing a first liner over the fin elements, wherein the first liner incudes an amorphous semiconductor material; depositing a second liner over the first liner, wherein the second liner includes an amorphous or polycrystalline semiconductor material; forming a sacrificial gate stack over the fin elements; forming gate spacers over the sacrificial gate stack; removing the sacrificial gate stack, thereby forming a gate trench; removing the second type epitaxial layers and the second liner from the gate trench, thereby exposing the first type epitaxial layers in the gate trench; and forming a
- the second type epitaxial layers and the second liner include a same semiconductor composition in different material structure forms. In some embodiments, the second type epitaxial layers and the second liner both include silicon germanium. In some embodiments, the method further includes depositing a dielectric layer between the fin elements, wherein the dielectric layer is in contact with the second liner, and wherein the gate stack is in contact with the dielectric layer after the forming of the gate stack. In some embodiments, the method further includes prior to the depositing of the first liner, depositing a third liner over the fin elements; and performing a nitridation treatment to the third liner.
- the present disclosure is directed to a multi-gate semiconductor device.
- the multi-gate semiconductor device includes channel members disposed over a substrate; an isolation feature over the substrate; an amorphous semiconductor layer stacked between the isolation feature and the substrate; first and second dielectric fins disposed over the isolation feature and sandwiching the channel members; and a gate structure engaging the channel members and over the first and second dielectric fins.
- the multi-gate semiconductor device further includes an oxide layer stacked between the amorphous semiconductor layer and the substrate.
- the multi-gate semiconductor device further includes a source/drain (S/D) feature adjacent the channel members, wherein the S/D feature is in contact with the isolation feature and the first and second dielectric fins.
- each of the first and second dielectric fins has a bottom portion including a low-K material and a top portion including a high-K material.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Nanotechnology (AREA)
- Composite Materials (AREA)
- Plasma & Fusion (AREA)
- Materials Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
- The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
- Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. Another multi-gate device, introduced in part to address performance challenges associated with FinFETs, is the gate-all-around (GAA) transistor. GAA devices get their name from the gate structure which can extend around the channel region providing access to the channel on four sides. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs.
- To continue to provide the desired scaling and increased density for multi-gate devices (e.g., FinFETs and GAA devices) in advanced technology nodes, dielectric fins have been introduced to improve the uniformity of fins (including semiconductor fins and dielectric fins) and define space for source/drain (S/D) features. Sacrificial capping layers comprising crystalline semiconductor materials may also be introduced to fill between semiconductor fins and dielectric fins to reserve space for metal gate stacks in a replacement gate process. Due to natural crystal orientation, sacrificial capping layers may form a quadrilateral cavity defined by facets, such as (111) facets after an etch process, which may result in metal gate stack and inner spacer taper profiles and in turn cause S/D epi defects. Therefore, while the current methods have been satisfactory in many respects, challenges with respect to performance of the resulting device may not be satisfactory in all respects.
- The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIGS. 1A and 1B show a flow chart of a method for forming a multi-gate device, according to one or more aspects of the present disclosure. -
FIGS. 2A, 3A, 9A, 10A, 11A, 12A, and 13A illustrate perspective views of a semiconductor structure during a fabrication process according to the method ofFIGS. 1A and 1B , according to aspects of the present disclosure. -
FIGS. 2B, 3B, 4, 5, 6, 7, 8, 9B, 9C, 9D, 10B, 10C, 10D, 11B, 11C, 11D, 12B, 12C, 12D, 13B, 13C , and 13D illustrate cross-sectional views of a semiconductor structure during a fabrication process according to the method ofFIGS. 1A and 1B , according to aspects of the present disclosure. -
FIGS. 14A and 14B show a flow chart of another method for forming a multi-gate device, according to one or more aspects of the present disclosure. -
FIG. 20A illustrates a perspective view of a semiconductor structure during a fabrication process according to the method ofFIGS. 14A and 14B , according to aspects of the present disclosure. -
FIGS. 15, 16, 17, 18, 19, 20B, 20C, and 20D illustrate cross-sectional views of a semiconductor structure during a fabrication process according to the method ofFIGS. 14A and 14B , according to aspects of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within +/−10% of the number described, unless otherwise specified. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.
- The present disclosure is generally related to semiconductor devices and fabrication methods, and more particularly to fabricating multi-gate devices with dielectric fins and sacrificial capping layers in advanced technology nodes. It is noted that multi-gate devices include those transistors whose gate structures are formed on at least two-sides of a channel region. These multi-gate devices may include a p-type metal-oxide-semiconductor device or an n-type metal-oxide-semiconductor device. Specific examples may be presented and referred to herein as FinFET, on account of their fin-like structure. Also presented herein are embodiments of a type of multi-gate transistor referred to as a gate-all-around (GAA) device. A GAA device includes any device that has its gate structure, or portion thereof, formed on 4-sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein also include embodiments that have channel regions disposed in nanosheet channel(s), nanowire channel(s), bar-shaped channel(s), and/or other suitable channel configuration. Presented herein are embodiments of devices that may have one or more channel regions (e.g., nanowires/nanosheets) associated with a single, contiguous gate structure. However, one of ordinary skill would recognize that the teaching can apply to a single channel (e.g., single nanowire/nanosheet) or any number of channels. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.
- Embodiments of the present disclosure offer advantages over the existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments. For example, embodiments discussed herein include methods and structures for providing dielectric fins for improving fin uniformity and defining space for source/drain (S/D) features, and sacrificial capping layers with amorphous or polycrystalline semiconductor material for reserving space for metal gate stacks. The amorphous or polycrystalline semiconductor material allows sacrificial capping layers to maintain vertical footing after etching process, which in turn improves inner spacer layer footing profile and metal gate stack footing profile and reduces S/D feature defects (e.g., pits in S/D features) in footing regions.
- Illustrated in
FIGS. 1A and 1B is amethod 100 of semiconductor fabrication including fabrication of multi-gate devices. Themethod 100 is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after themethod 100, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. Themethod 100 is described below in conjunction withFIGS. 2A-13D .FIGS. 2A, 3A, 9A, 10A, 11A, 12A, and 13A are perspective views of an embodiment of asemiconductor device 200 according to various stages of themethod 100 ofFIGS. 1A and 1B .FIGS. 2B, 3B, 4, 5, 6, 7, 8, 9B, 10B, 11B, 12B, and 13B are corresponding cross-sectional views of an embodiment of thesemiconductor device 200 along a first cut (e.g., cut B-B inFIG. 9A ), which is in the gate region and perpendicular to the lengthwise direction of the channel.FIGS. 9C, 10C, 11C, 12C, and 13C are corresponding cross-sectional views of an embodiment of thesemiconductor device 200 along a second cut (e.g., cut C-C inFIG. 9A ), which is in the channel region and along a lengthwise direction of the channel.FIGS. 9D, 10D, 11D, 12D, and 13D are corresponding cross-sectional views of an embodiment of thesemiconductor device 200 along a third cut (e.g., cut D-D inFIG. 9A ), which is in a gate region approximate to the channel and along a lengthwise direction of the channel. - As with the other method embodiments and exemplary devices discussed herein, it is understood that parts of the
semiconductor device 200 may be fabricated by a CMOS technology process flow, and thus some processes are only briefly described herein. Further, the exemplary semiconductor devices may include various other devices and features, such as other types of devices such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM) and/or other logic circuits, etc., but is simplified for a better understanding of the inventive concepts of the present disclosure. In some embodiments, the exemplary devices include a plurality of semiconductor devices (e.g., transistors), including P-FETs, N-FETs, etc., which may be interconnected. Moreover, it is noted that the process steps ofmethod 100, including any descriptions given with reference toFIGS. 2A-13D , as with the remainder of the method and exemplary figures provided in this disclosure, are merely exemplary and are not intended to be limiting beyond what is specifically recited in the claims that follow. - The
method 100 at operation 102 (FIG. 1A ) provides (or is provided with) a semiconductor device (or device) 200. Referring toFIGS. 2A and 2B , thedevice 200 includes asubstrate 202 and anepitaxial stack 204 above thesubstrate 202. In some embodiments, thesubstrate 202 may be a semiconductor substrate such as a silicon substrate. Thesubstrate 202 may include various layers, including conductive or insulating layers formed on a semiconductor substrate. Thesubstrate 202 may include various doping configurations depending on design requirements as is known in the art. - For example, different doping profiles (e.g., n-wells, p-wells) may be formed on the
substrate 202 in regions designed for different device types (e.g., n-type field effect transistors (N-FET), p-type field effect transistors (P-FET)). The suitable doping may include ion implantation of dopants and/or diffusion processes. Thesubstrate 202 may have isolation features (e.g., shallow trench isolation (STI) features) interposing the regions providing different device types. Thesubstrate 202 may also include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, thesubstrate 202 may include a compound semiconductor and/or an alloy semiconductor. Further, thesubstrate 202 may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and/or may have other suitable enhancement features. - The
epitaxial stack 204 includesepitaxial layers 206 of a first composition interposed byepitaxial layers 208 of a second composition. The first and second compositions can be different. Theepitaxial layers 208 may include the same composition as thesubstrate 202. In the illustrated embodiment, theepitaxial layers 206 are silicon germanium (SiGe) and theepitaxial layers 208 are silicon (Si). However, other embodiments are possible including those that provide for a first composition and a second composition having different oxidation rates and/or etch selectivity. For example, in some embodiments, either of theepitaxial layers epitaxial layers epitaxial layers substrate 202 is a crystalline substrate, and theepitaxial layers - In some embodiments, each
epitaxial layer 206 has a thickness ranging from about 2 nanometers (nm) to about 6 nm. Theepitaxial layers 206 may be substantially uniform in thickness. Yet in the illustrated embodiment, thetop epitaxial layer 206 is thinner (e.g., half the thickness) than otherepitaxial layers 206 thereunder. Thetop epitaxial layer 206 functions as a capping layer providing protections to other epitaxial layers in subsequent processes. In some embodiments, eachepitaxial layer 208 has a thickness ranging from about 6 nm to about 12 nm. In some embodiments, theepitaxial layers 208 of the stack are substantially uniform in thickness. As described in more detail below, theepitaxial layers 208 or portions thereof may form channel member(s) of the subsequently-formedmulti-gate device 200 and the thickness is chosen based on device performance considerations. The term channel member(s) is used herein to designate any material portion for channel(s) in a transistor with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including for example a cylindrical in shape or substantially rectangular cross-section. Theepitaxial layers 206 in channel regions(s) may eventually be removed and serve to define a vertical distance between adjacent channel members for a subsequently-formed multi-gate device and the thickness is chosen based on device performance considerations. Accordingly, theepitaxial layers 206 may also be referred to as sacrificial layers, andepitaxial layers 208 may also be referred to as channel layers. - It is noted that four (4) layers of the
epitaxial layers 206 and three (3) layers of theepitaxial layers 208 are alternately arranged as illustrated inFIGS. 2A and 2B , which is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of epitaxial layers can be formed in theepitaxial stack 204; the number of layers depending on the desired number of channels members for thedevice 200. In some embodiments, the number ofepitaxial layers 208 is between 2 and 10. It is also noted that while theepitaxial layers epitaxial layer 206 is the topmost layer of theepitaxial stack 204, other configurations are possible. For example, in some cases, anepitaxial layer 208 may alternatively be the topmost layer of theepitaxial stack 204. Stated another way, the order of growth for theepitaxial layers - The
method 100 then proceeds to operation 104 (FIG. 1A ) where semiconductor fins (also referred to as device fins or fin elements) are formed by patterning. With reference to the example ofFIGS. 3A and 3B , in an embodiment ofoperation 104, a plurality ofsemiconductor fins 210 extending from thesubstrate 202 are formed. In various embodiments, each of thesemiconductor fins 210 includes asubstrate portion 203 formed from thesubstrate 202 and anepitaxial stack portion 204 formed from portions of each of the epitaxial layers of the epitaxial stack includingepitaxial layers semiconductor fins 210 may be fabricated using suitable processes including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern thesemiconductor fins 210 by etching initialepitaxial stack 204. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. - In the illustrated embodiment, a hard mask (HM)
layer 212 is formed over theepitaxial stack 204 prior to patterning thesemiconductor fins 210. In some embodiments, theHM layer 212 includes anoxide layer 212A (e.g., a pad oxide layer that may include SiO2) and anitride layer 212B (e.g., a pad nitride layer that may include Si3N4) formed over theoxide layer 212A. Theoxide layer 212A may act as an adhesion layer between theepitaxial stack 204 and thenitride layer 212B and may act as an etch stop layer for etching thenitride layer 212B. In some examples, theHM layer 212 includes thermally grown oxide, chemical vapor deposition (CVD)-deposited oxide, and/or atomic layer deposition (ALD)-deposited oxide. In some embodiments, theHM layer 212 includes a nitride layer deposited by CVD and/or other suitable technique. - The
semiconductor fins 210 may subsequently be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer (not shown) over theHM layer 212, exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. In some embodiments, patterning the resist to form the masking element may be performed using an electron beam (e-beam) lithography process. The masking element may then be used to protect regions of thesubstrate 202, and layers formed thereupon, while an etch process formstrenches 214 in unprotected regions through theHM layer 212, through theepitaxial stack 204, and into thesubstrate 202, thereby leaving the plurality of extendingsemiconductor fins 210. Thetrenches 214 may be etched using dry etching, wet etching, RIE, and/or other suitable processes. - Numerous other embodiments of methods to form the semiconductor fins on the substrate may also be used including, for example, defining the fin region (e.g., by mask or isolation regions) and epitaxially growing the
epitaxial stack 204 in the form of thesemiconductor fins 210. In some embodiments, forming thesemiconductor fins 210 may include a trim process to decrease the width of thesemiconductor fins 210. The trim process may include wet and/or dry etching processes. - At
operation 106, the method 100 (FIG. 1A ) forms a passivation liner along top and sidewall surfaces of thesemiconductor fins 210. Referring toFIG. 4 , in the illustrated embodiment, thepassivation liner 216 is an oxide layer (e.g., SiO2) formed by oxidizing exposed surfaces of thesemiconductor fins 210 and thesubstrate 202. The oxidation process results in the oxide layer having a determined thickness. For example, the oxide layer may have a thickness from about 1 nm to about 3 nm. In some embodiments, the oxidation process comprises a rapid thermal oxidation (RTO) process, high pressure oxidation (HPO), chemical oxidation process, in-situ stream generation (ISSG) process, or enhanced in-situ stream generation (EISSG) process. In some embodiments, the RTO process is performed at a temperature of about 400° C. to about 700° C., using O2 and O3 as reaction gases, for about 1 second to about 30 seconds. In other embodiments, an HPO is performed using a process gas of O2, O2+N2, N2, or the like, at a pressure from about 1 atm to about 25 atm and a temperature from about 300° C. to about 700° C., for about 1 minute to about 10 minutes. Examples of a chemical oxidation process include wet SPM clean, wet O3/H2O, or the like. The O3 may have a concentration of about 1 ppm to about 50 ppm. - At
operation 108, the method 100 (FIG. 1A ) deposits a semiconductor liner on thepassivation liner 216. Still referring toFIG. 4 , thesemiconductor liner 218 is disposed conformally on top and sidewall surfaces of thesemiconductor fins 210. The term “conformally” may be used herein for ease of description upon a layer having substantial same thickness over various regions. By way of example, thesemiconductor liner 218 may be formed by depositing a semiconductor material over thepassivation liner 216 using processes such as, CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. In some embodiments, thesemiconductor liner 218 may have a thickness from about 2 nm to about 5 nm. Due to theunderneath passivation liner 216, the crystalline structures in theepitaxial layers semiconductor liner 218. The material structure form of the semiconductor composition in thesemiconductor liner 218 stays in amorphous form instead. In some embodiments, thesemiconductor liner 218 includes amorphous silicon and may also be referred to as an amorphous silicon layer. As will be explained in detail below, thesemiconductor liner 218 functions as a seed layer, allowing an amorphous or polycrystalline semiconductor layer (i.e., subsequently-formed sacrificial capping layer) to be deposited thereon. - At
operation 110, the method 100 (FIG. 1A ) forms isolation features, such as shallow trench isolation (STI) features, between thesemiconductor fins 210. Referring toFIG. 5 , STI features 220 is disposed on thesubstrate 202 interposing thesemiconductor fins 210. By way of example, in some embodiments, a dielectric layer is first deposited over thesubstrate 202, filling thetrenches 214 with dielectric material. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and/or other suitable process. In some embodiments, after deposition of the dielectric layer, thedevice 200 may be annealed, for example, to improve the quality of the dielectric layer. In some embodiments, the dielectric layer may include a multi-layer structure, for example, having one or more liner layers. A surface portion of thesemiconductor liner 218 may intermix with the dielectric layer, resulting in a reduced thickness of thesemiconductor liner 218. For example, thesemiconductor liner 218 may lose over half in its thickness. A reduced thickness of thesemiconductor liner 218 may range from about 1 nm to about 3 nm. In one embodiment, thesemiconductor liner 218 has a reduced thickness less than thepassivation liner 216 afteroperation 110. - In some embodiments of forming the isolation (STI) features, after deposition of the dielectric layer, the deposited dielectric material is thinned and planarized, for example by a chemical mechanical polishing (CMP) process. In some embodiments, the
HM layer 212 functions as a CMP stop layer. Subsequently, the dielectric layer interposing thesemiconductor fins 210 are recessed. Referring to the example ofFIG. 5 , the STI features 220 are recessed providing thesemiconductor fins 210 extending above the STI features 220. In some embodiments, the recessing process may include a dry etching process, a wet etching process, and/or a combination thereof. In some embodiments, a recessing depth is controlled (e.g., by controlling an etching time) so as to result in a desired height of the exposed upper portion of thesemiconductor fins 210. In the illustrated embodiment, the desired height exposes each of the layers of theepitaxial stack 204. In furtherance of the embodiment, a top surface of the STI features 220 is recessed below thebottommost epitaxial layer 206. - At
operation 112, the method 100 (FIG. 1A ) deposits a capping layer on top and sidewall surfaces of the semiconductor fins. Referring toFIG. 6 , in the illustrated embodiment, thecapping layer 222 is selectively deposited over thedevice 200. In particular, thecapping layer 222 may be selectively and conformally deposited over the exposed surfaces of thesemiconductor liner 218. In various embodiments, thecapping layer 222 is not deposited on top surfaces of the STI features 220 between thesemiconductor fins 210. For example, thecapping layer 222 may be a semiconductor layer and deposited by an epitaxial growing process, such that the epitaxial growth of thecapping layer 222 is limited to exposed semiconductor surfaces of thesemiconductor liner 218, which functions as a seed layer, but not on dielectric material surfaces of the STI features 220. In some embodiments, during the epitaxial growing process, thesemiconductor liner 218 intermixes with thecapping layer 222 and becomes a portion of thecapping layer 222. Therefore, portions of thesemiconductor liner 218 above the STI features 220 are not shown inFIG. 6 . Alternatively, thesemiconductor liner 218 with a further reduced thickness (not shown inFIG. 6 ) may remain underneath thecapping layer 222, in some embodiments. By way of example, thecapping layer 222 may be deposited by an MBE process, an MOCVD process, an ALD process, and/or other suitable epitaxial growth processes. In furtherance of the example, thesemiconductor liner 218 is an amorphous silicon layer, and thecapping layer 222 includes the same semiconductor material as theepitaxial layer 206, such as silicon germanium (SiGe). Due to the amorphous form of the seed layer, the semiconductor material in thecapping layer 222 won't grow in crystalline structures but in either amorphous form or polycrystalline form instead, such as amorphous SiGe or polycrystalline SiGe in some embodiments. In yet some embodiments, thecapping layer 222 may have a mixture of semiconductor material in both amorphous form and polycrystalline form, such as 60% SiGe in amorphous form and 40% SiGe in polycrystalline form. The term “amorphous or polycrystalline” is used herein to designate composition in amorphous form, polycrystalline form, or a combination thereof. As will be explained in detail below, thecapping layer 222 reserves a space for subsequently-formed metal gate stack and will be removed in a subsequent processing stage. Therefore, thecapping layer 222 is also referred to as a sacrificial capping layer. - At
operation 124, the method 100 (FIG. 1B ) forms a dielectric fin between adjacent semiconductor fins. Referring to the example ofFIGS. 7 and 8 , in an embodiment ofoperation 124, adielectric layer 224 is deposited conformally within thetrenches 214 including along sidewalls of thesacrificial capping layer 222 and along a top surface of the STI features 220. Thereafter, adielectric layer 226 is deposited over thedielectric layer 224. In at least some embodiments, thedielectric layers dielectric fin 228 may further include a high-K dielectric layer formed over thedielectric layers dielectric layers dielectric layers dielectric layer 224 may include a low-K dielectric layer, and thedielectric layer 226 may include a flowable oxide layer. In various cases, thedielectric layers dielectric layers device 200. - The
method 200 atoperation 124 may further include a recessing process, a high-K dielectric layer deposition process, and a CMP process. Still referring toFIGS. 7 and 8 , in an embodiment ofoperation 124, a recessing process is performed to remove top portions of thedielectric layers sacrificial capping layer 222. After performing the recessing process, and in a further embodiment ofoperation 124, a high-K dielectric layer 230 is deposited within trenches formed by the recessing process. In some embodiments, the high-K dielectric layer 230 may include HfO2, ZrO2, HfAlOx, HfSiOx, Y2O3, Al2O3, or another high-K material. The high-K dielectric layer 230 may be deposited by a CVD process, an ALD process, a PVD process, and/or other suitable process. After deposition of the high-K dielectric layer 230, and in a further embodiment ofoperation 124, a CMP process is performed to remove excess material portions and to planarize a top surface of thedevice 200. In some examples, the CMP process removes a portion of thesacrificial capping layer 222 from the top of thesemiconductor fins 210 to expose theHM layer 212. Thus, in various cases, adielectric fin 228 is defined as having a lower portion including the recessed portions of thedielectric layers K dielectric layer 230. In some examples, a height of the high-K dielectric layer 230 may be about 10-30 nm. In some cases, thedielectric fin 228 may be alternatively described as a bi-layer dielectric having a high-K upper portion and a low-K lower portion. In some examples, a height ratio of the upper portion to the lower portion may be about 1:20 to about 20:1. The height ratio may be adjusted, for example, by changing the recess depth and thus the height of the high-K dielectric layer 230, as noted above. In some embodiments, thedielectric fins 228 are used to effectively prevent the undesirable lateral merging of the epitaxial S/D features formed onadjacent semiconductor fins 210, as will be discussed in more detail below. - The
method 100 then proceeds to operation 126 (FIG. 1B ) where sacrificial layers/features are formed and in particular, a dummy gate structure. While the present discussion is directed to a replacement gate (or gate-last) process whereby a dummy gate structure is formed and subsequently replaced, other configurations may be possible. - With reference to
FIGS. 9A-9D , agate stack 232 is formed.FIG. 9A is a perspective view of thedevice 200,FIG. 9B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line),FIG. 9C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line), andFIG. 9D refers to a cross-sectional view taken though thesacrificial capping layer 222 and along the lengthwise direction of the channel (e.g., along the D-D line). In an embodiment, thegate stack 232 is a dummy (sacrificial) gate stack that is subsequently removed (with reference to operation 136). Thus, in some embodiments using a gate-last process, thegate stack 232 is a dummy gate stack and will be replaced by the final gate stack at a subsequent processing stage of thedevice 200. In particular, thedummy gate stack 232 may be replaced at a later processing stage by a high-K dielectric layer (HK) and metal gate electrode (MG) as will be discussed in more detail below. - In an embodiment of
operation 126, theHM layer 212 and a top portion of thesacrificial capping layer 222 may initially be etched-back. Thetopmost epitaxial layer 206 may act as an etch stop layer for etching theHM layer 212 and be subsequently removed. The top potion of thesacrificial capping layer 222 may be removed together with thetopmost epitaxial layer 206 by the same etchant that targets the same semiconductor material, such as SiGe. In some embodiments, a top surface of the etched-backsacrificial capping layer 222 is substantially level with top surfaces of thetopmost epitaxial layer 208 of thesemiconductor fins 210. In some embodiments, the etch-back of theHM layer 212 and the top portion of thesacrificial capping layer 222 may be performed using a wet etch process, a dry etch process, a multiple-step etch process, and/or a combination thereof. TheHM layer 212 may be removed, for example, by a wet etching process using H3PO4 or other suitable etchants. After performing the etch-back process, and in a further embodiment ofoperation 126, thedummy gate stack 232 is disposed over thesemiconductor fins 210, thesacrificial capping layer 222, and thedielectric fins 228. The portion of thesemiconductor fins 210 underlying thedummy gate stack 232 may be referred to as the channel region. Thedummy gate stack 232 may also define source/drain (S/D) regions of thesemiconductor fins 210, for example, the regions of thesemiconductor fin 210 adjacent and on opposing sides of the channel region. - In some embodiments, the
dummy gate stack 232 includes adummy dielectric layer 234 and adummy electrode layer 236. In some embodiments, thedummy dielectric layer 234 may include SiO2, silicon nitride, a high-K dielectric material and/or other suitable material. In various examples, thedummy dielectric layer 234 may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. By way of example, thedummy dielectric layer 234 may be used to prevent damages to thesemiconductor fins 210 by subsequent processes (e.g., subsequent formation of the dummy gate stack). Subsequently, other portions of thedummy gate stack 232 are formed, including adummy electrode layer 236 and ahard mask 240 which may includemultiple layers oxide layer 240A and anitride layer 240B). In some embodiments, thedummy gate stack 232 is formed by various process steps such as layer deposition, patterning, etching, as well as other suitable processing steps. Exemplary layer deposition processes include CVD (including both low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. In forming the gate stack for example, the patterning process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods. In some embodiments, thedummy electrode layer 236 may include polycrystalline silicon (polysilicon). In some embodiments, thehard mask 240 includes anoxide layer 240A such as a pad oxide layer that may include SiO2. In some embodiments,hard mask 240 includes anitride layer 240B such as a pad nitride layer that may include Si3N4, silicon oxynitride and/or silicon carbide. In some embodiments, after formation of thedummy gate stack 232, thedummy dielectric layer 234 is removed from the S/D regions of thesemiconductor fins 210. The etch process may include a wet etch, a dry etch, and/or a combination thereof. The etch process is chosen to selectively etch thedummy dielectric layer 234 without substantially etching thesemiconductor fins 210, thehard mask 240, and thedummy electrode layer 236. - At
operation 128, the method 100 (FIG. 1B ) forms sidewall spacers on sidewall surfaces of the dummy gate stacks. Still referring toFIGS. 9A-9D , thesidewall spacers 242 may have a thickness of about 2-10 nm. In some examples, thesidewall spacers 242 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-K material, and/or combinations thereof. In some embodiments, thesidewall spacers 242 include multiple layers, such as aliner spacer layer 242A and amain spacer layer 242B, and the like. By way of example, thesidewall spacers 242 may be formed by conformally depositing a dielectric material over thedevice 200 using processes such as a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. Following the conformal deposition of the dielectric material, portions of the dielectric material used to form thesidewall spacers 242 may be etched-back to expose portions of thesemiconductor fins 210 not covered by the dummy gate stacks 232 (e.g., for example, in source/drain regions). In some cases, the etch-back process removes portions of dielectric material used to form thesidewall spacers 242 along a top surface of thedummy gate stack 232, thereby exposing thehard mask layer 240. In some embodiments, the etch-back process may include a wet etch process, a dry etch process, a multiple-step etch process, and/or a combination thereof. It is noted that after the etch-back process, thesidewall spacers 242 remain disposed on sidewall surfaces of thedummy gate stack 232. - At
operation 130, the method 100 (FIG. 1B ) forms inner spacers. Still referring toFIGS. 9A-9D , in some embodiments ofoperation 130, a source/drain etch process is performed prior to the forming of inner spacers. A source/drain etch process is performed to remove portions of thesemiconductor fins 210 and thesacrificial capping layer 222 not covered by the dummy gate stack 232 (e.g., in source/drain regions) and that were previously exposed (e.g., during thesidewall spacer 242 etch-back process). In particular, the source/drain etch process may serve to remove the exposedepitaxial layer portions underlying substrate portions 203 of thesemiconductor fins 210. In some embodiments, the source/drain etch process may include a dry etching process, a wet etching process, and/or a combination thereof. - Referring to
FIGS. 10A-10D , in some embodiments ofoperation 130, a lateral etching (or horizontal recessing) is subsequently performed to recess theepitaxial layers 206 and thesacrificial capping layer 222 to form recesses 246.FIG. 10A is a perspective view of thedevice 200,FIG. 10B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line),FIG. 10C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line), andFIG. 10D refers to a cross-sectional view taken though thesacrificial capping layer 222 and along the lengthwise direction of the channel (e.g., along the D-D line). The amount of etching of theepitaxial layers 206 and thesacrificial capping layer 222 is in a range from about 2 nm to about 10 nm in some embodiments. In furtherance of some embodiments, end portions (edges) of theepitaxial layer 206 and thesacrificial capping layer 222 under thedummy gate stack 232 are substantially flush with the sidewall surfaces of thedummy electrode layer 236. Here, “being substantially flush” means the difference in the relative position is less than about 1 nm. When theepitaxial layers 206 are crystalline SiGe and thesacrificial capping layer 222 is amorphous or polycrystalline SiGe, the lateral etching process may use the same etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. - Referring to
FIGS. 11A-11D , in some embodiments ofoperation 130, an insulating layer is subsequently formed on the lateral ends of theepitaxial layers 206 and thesacrificial capping layer 222 to fill therecesses 246, thereby forminginner spacers 248.FIG. 11A is a perspective view of thedevice 200,FIG. 11B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line),FIG. 11C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line), andFIG. 11D refers to a cross-sectional view taken though thesacrificial capping layer 222 and along the lengthwise direction of the channel (e.g., along the D-D line). The insulating layer may include a dielectric material, such as SiN, SiOC, SiOCN, SiCN, SiO2, and/or other suitable material. In some embodiments, the insulating layer is conformally deposited, for example, by ALD or any other suitable method. After the conformal deposition of the insulating layer, an etch-back process is performed to partially remove the insulating layer from outside of therecesses 246. By this etching the insulating layer remains substantially within therecesses 246. In some examples, the etch-back process may also etch a portion of the high-K dielectric layer 230 of thedielectric fins 228 not covered by thedummy gate stack 232. Since the insulating layer also fills therecesses 246 provided by the recessing of thesacrificial capping layer 222, theinner spacers 248 are continuously connected and wrap around the lateral ends of theepitaxial layers 208 in the channel region. The continuously connectedinner spacers 248 may also be referred to jointly as an inner spacer layer. - At
operation 132, the method 100 (FIG. 1B ) forms S/D features (also referred to as epitaxial S/D features). Still referring toFIGS. 11A-11D , in an embodiment ofoperation 132, S/D features 250 are formed in S/D regions adjacent to and on either side of thedummy gate stack 232. For example, the S/D features 250 may be formed over the exposedsubstrate portions 203 of thesemiconductor fins 210 and in contact with the adjacentinner spacers 248 and the semiconductor channel layers (the epitaxial layers 208). In the illustrated embodiment, the S/D features 250 is also in contact with a top surface of the STI features 220 and sidewalls of thedielectric fins 228. In some embodiments, the S/D features 250 are formed by epitaxially growing a semiconductor material layer in the S/D regions. In various embodiments, the S/D features 250 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The S/D features 250 may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the S/D features 250 are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the S/D features 250. In an exemplary embodiment, the S/D features 250 in an NMOS device include SiP, while those in a PMOS device include GeSnB and/or SiGeSnB. Furthermore, silicidation or germano-silicidation may be formed on the S/D features 250. For example, silicidation, such as nickel silicide, may be formed by depositing a metal layer over the epitaxial S/D features 250, annealing the metal layer such that the metal layer reacts with silicon in the S/D features 250 to form the metal silicidation, and thereafter removing the non-reacted metal layer. As illustrated inFIG. 11A , thedielectric fins 228, which may have a partially etched-back high-K dielectric layer 230, effectively prevents the undesirable lateral merging of the S/D features 250 formed onadjacent semiconductor fins 210. - Due to the amorphous or polycrystalline form of the semiconductor material in the
sacrificial capping layer 222, footing profile 252 (highlighted in a dotted circle inFIG. 11D ) of end portions of thesacrificial capping layer 222 has a substantially straight etched surface (sidewall) perpendicular to a top surface of the STI features 220. As a comparison, if thesacrificial capping layer 222 may be formed of crystalline semiconductor material, the etched surface at thefooting profile 252 may have a quadrilateral cavity defined by (111) facets. The quadrilateral cavity may cause notches in the footing profile of theinner spacer layer 248 and in turn cause defects, such as pits, in the subsequently-formed S/D features 250. Furthermore, subsequently-formed metal gate structure may also have facets in the footing profile. By forming thesacrificial capping layer 222 with amorphous or polycrystalline semiconductor material, theinner spacer layer 248 has substantially straight sidewalls interfacing thesacrificial capping layer 222 and the S/D features 250 in footing regions. In turn, pits in the S/D features 250 are less likely to form in footing regions. - At
operation 134, the method 100 (FIG. 1B ) forms an inter-layer dielectric (ILD) layer. Referring toFIGS. 12A-12D , in some embodiments ofoperation 134, a contact etch stop layer (CESL) is also formed prior to forming the ILD layer.FIG. 12A is a perspective view of thedevice 200,FIG. 12B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line),FIG. 12C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line), andFIG. 12D refers to a cross-sectional view taken though a space reserved by thesacrificial capping layer 222 and along the lengthwise direction of the channel (e.g., along the D-D line). In some examples, theCESL 256 includes a silicon nitride layer, silicon oxide layer, a silicon oxynitride layer, and/or other materials known in the art. TheCESL 256 may be formed by plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, theILD layer 258 includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. TheILD layer 258 may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of theILD layer 258, thesemiconductor device 200 may be subject to a high thermal budget process to anneal the ILD layer. - In some examples, after depositing the ILD layer, a planarization process may be performed to remove excessive dielectric materials. For example, a planarization process includes a chemical mechanical planarization (CMP) process which removes portions of the ILD layer 258 (and
CESL 256, if present) overlying thedummy gate stack 232 and planarizes a top surface of thesemiconductor device 200. In some embodiments, the CMP process also removeshard mask 240 and exposes thedummy electrode layer 236. - At
operation 136, the method 100 (FIG. 1B ) removes thedummy gate stack 232 to form agate trench 260 in the channel region, as shown inFIGS. 12A-12D . A final gate structure (e.g., including a high-K dielectric layer and metal gate electrode) may be subsequently formed in thegate trench 260, as will be described below.Operation 136 may include one or more etching processes that are selective to the material in thedummy gate stack 232. For example, the removal of thedummy gate stack 232 may be performed using a selective etch process such as a selective wet etch, a selective dry etch, or a combination thereof. Theepitaxial layers semiconductor fins 210 and thesacrificial capping layer 222 are exposed in thegate trench 260. - At
operation 138, the method 100 (FIG. 1B ) removes theepitaxial layers 206 from thesemiconductor fins 210 and the sacrificial capping layer 222 (as well as the passivation liner 216) in thegate trench 260. Theresultant structure 200 is shown inFIGS. 13A-13D . In an embodiment, theepitaxial layers 206 and thesacrificial capping layer 222 both include SiGe (in crystalline structure and amorphous or polycrystalline structure, respectively) and theepitaxial layers 208 are silicon, allowing for the selective removal of theepitaxial layers 206 and thesacrificial capping layer 222. In an embodiment, theepitaxial layers 206 and thesacrificial capping layer 222 are removed by a selective wet etching process. In some embodiments, the selective wet etching includes an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal includes SiGe oxidation followed by a SiGeOx removal. For example, the oxidation may be provided by O3 clean and then SiGeOx removed by an etchant such as NH4OH. It is noted that during the interim processing stage ofoperation 138,gaps 262 are provided between the adjacent channel members (e.g., nanowires or nanosheet) in the channel region (e.g.,gaps 262 between epitaxial layers 208). Thegaps 262 may be filled with ambient environment conditions (e.g., air, nitrogen). - The
method 100 then proceeds to operation 140 (FIG. 1B ) where a gate structure is formed. The resultant structure is shown inFIGS. 13A-13D .FIG. 13A is a perspective view of thedevice 200,FIG. 13B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line),FIG. 13C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line), andFIG. 13D refers to a cross-sectional view taken though a gate region previously reserved by thesacrificial capping layer 222 and along the lengthwise direction of the channel (e.g., along the D-D line). The gate structure may be the gate of a multi-gate transistor. The gate structure may be a high-K/metal gate (HK MG) stack, however other compositions are possible. In some embodiments, the gate structure forms the gate associated with the multi-channels provided by the plurality of channel members (e.g., nanosheets or nanowires having gaps therebetween) in the channel region. - In an embodiment of
operation 140, aHK MG stack 264 is formed within thegate trench 260 of thedevice 200 provided by the release of theepitaxial layers 208, described above with reference toprior operation 138. In various embodiments, theHK MG stack 264 includes an interfacial layer (not shown), a high-K gatedielectric layer 266 formed over the interfacial layer, and agate electrode layer 268 formed over the high-K gatedielectric layer 266. High-K gate dielectrics, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The gate electrode layer used within HK MG stack may include a metal, metal alloy, or metal silicide. Additionally, the formation of the HK MG stack may include depositions to form various gate materials, one or more liner layers, and one or more CMP processes to remove excessive gate materials and thereby planarize a top surface of thesemiconductor device 200. Interposing theHK MG stack 264 and the S/D features 250 is theinner spacers 248, providing isolation. - In some embodiments, the interfacial layer of the
HK MG stack 264 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The high-K gatedielectric layer 266 of theHK MG stack 264 may include a high-K dielectric such as hafnium oxide (HfO2). Alternatively, the high-K gatedielectric layer 266 of theHK MG stack 264 may include other high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. The high-K gatedielectric layer 266 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and/or other suitable methods. As illustrated inFIG. 13D , in some embodiments, the high-K gatedielectric layer 266 is deposited conformally on sidewalls of theinner spacers 248 and top surfaces of the STI features 220. - The
gate electrode layer 268 of theHK MG stack 264 may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, thegate electrode layer 268 ofHK MG stack 264 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or a combination thereof. In various embodiments, thegate electrode layer 268 of theHK MG stack 264 may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the gate electrode layer 284 may be formed separately for N-FET and P-FET transistors which may use different metal layers (e.g., for providing an N-type or P-type work function). In various embodiments, a CMP process may be performed to remove excessive metal from thegate electrode layer 268 of theHK MG stack 264, and thereby provide a substantially planar top surface of theHK MG stack 264. TheHK MG stack 264 includes portions that interpose each of the epitaxial layers (channel members) 208, which form channels of themulti-gate device 200. - The
device 200 may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on thesubstrate 202, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after themethod 100, and some process steps described above may be replaced or eliminated in accordance with various embodiments of themethod 100. - Reference is now made to
FIGS. 14A and 14B , which demonstrate a flow chart for amethod 100′. Themethod 100′shares operations method 100. Afteroperation 104, themethod 100′ proceeds tooperation 105. Afteroperation 105, themethod 100′shares operation 110 with themethod 100. Afteroperation 110, themethod 100′ proceeds tooperations operation 120, themethod 100′shares operations method 100. Themethod 100′ is described below in conjunction withFIGS. 15-20D . Shared operations are not repeated below in the interest of conciseness. - Referring to
FIG. 15 , afteroperations semiconductor fins 210, themethod 100′ at operation 105 (FIG. 14A ) deposits asemiconductor liner 270 along top and sidewall surfaces of thesemiconductor fins 210 and the top surface of thesubstrate 202. In the illustrated embodiment, thesemiconductor liner 270 is a silicon layer formed in an epitaxial growth process, such as an MBE process, an MOCVD process, an ALD process, and/or other suitable epitaxial growth processes. The epitaxial growth results in the silicon layer having a determined thickness. For example, the silicon layer may have a thickness from about 1 nm to about 3 nm. The semiconductor material (e.g., Si) of thesemiconductor liner 270 extends the crystalline structure of theepitaxial stack 204 through the epitaxial growing process. Therefore, thesemiconductor liner 270 may also be referred to a crystalline semiconductor liner. - Still referring to
FIG. 15 , themethod 100′ at operation 110 (FIG. 14A ) that is shared with themethod 100 forms isolation features, such as shallow trench (STI) features 220, between thesemiconductor fins 210. In the illustrated embodiment, a top surface of the STI features 220 is below thebottommost epitaxial layer 206. Thecrystalline semiconductor liner 270 is stacked between the STI features 220 and thesubstrate 202. - Referring to
FIG. 16 , themethod 100′ at operation 114 (FIG. 14A ) performs a passivation treatment to the exposed portions of thecrystalline semiconductor liner 270. The passivation treatment may include an oxidation process, a nitridation process, or a combination thereof. In some embodiments, the passivation treatment is a nitridation process comprising rapid thermal nitridation (RTN) process, high pressure nitridation (HPN), or decoupled plasma nitridation (DPN) process. In some embodiments, the RTN process is performed at a temperature of about 400° C. to about 800° C., using NH3 as reaction gas, for about 1 second to about 180 seconds. In some embodiments, the HPN process is performed using a process gas of NH3 at a pressure from about 1 atm to about 25 atm and a temperature from about 300° C. to about 700° C. for about 1 minute to about 10 minutes. In some embodiments, the DPN process is performed under a power of about 300 Watts to about 2250 Watts, using a process gas of N2, NH3, N2+Ar, N2+He, NH3+Ar, or the like as process gases. The nitridation process causes the semiconductor material in thecrystalline semiconductor liner 270 to react with the N, which converts exposed portions of thecrystalline semiconductor liner 270 to a nitride compound. In one example, thecrystalline semiconductor liner 270 is a crystalline silicon layer and is converted to silicon nitride afteroperation 114. The nitridation process may also passivate a surface portion of the STI features 220 (e.g., above a dotted line 272). In one example, the STI features 220 includes silicon oxide and the surface portion above the dottedline 272 is converted to silicon oxynitride afteroperation 114, while the bottom portion below the dottedline 272 remains as silicon oxide. In some embodiments, the dottedline 272 is about 1 nm to about 3 nm from the top surface of the STI features 220. A vertical portion of thecrystalline semiconductor liner 270 stacked between the STI features 220 and thesubstrate 202 which is above the dottedline 272 may also be converted to a nitride compound, such as silicon nitride in one example. - Referring to
FIG. 17 , themethod 100′ at operation 116 (FIG. 14A ) deposits asemiconductor liner 274 on the exposed portions of the nitrifiedliner 270 and the top surfaces of the STI features 220. Thesemiconductor liner 274 may be disposed conformally. By way of example, thesemiconductor liner 274 may be formed by depositing a semiconductor material over thedevice 200 using processes such as, CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. In some embodiments, thesemiconductor liner 274 may have a thickness from about 1 nm to about 3 nm. Due to the underneath nitrifiedliner 270 and the STI features 220, semiconductor composition in thesemiconductor liner 274 won't grow in crystalline structures but stays in amorphous form instead. In some embodiments, thesemiconductor liner 274 includes amorphous silicon and may also be referred to as an amorphous silicon layer. As will be explained in detail below, thesemiconductor liner 274 functions as a seed layer, allowing an amorphous or polycrystalline semiconductor layer as a sacrificial capping layer to be deposited thereon. - Referring to
FIG. 18 , themethod 100′ at operation 118 (FIG. 14A ) deposits acapping layer 222 on top and sidewall surfaces of thesemiconductor liner 274. In the illustrated embodiment, thecapping layer 222 is conformally deposited over thedevice 200. For example, thecapping layer 222 is a semiconductor layer and deposited by an epitaxial growing process, such that the epitaxial growth of thecapping layer 222 is on the exposed semiconductor surfaces of thesemiconductor liner 274 as a seed layer. In some embodiments, during the epitaxial growing process, thesemiconductor liner 274 intermixes with thecapping layer 222 and becomes a portion of thecapping layer 222. Accordingly, thesemiconductor liner 274 is not shown inFIG. 18 . Alternatively, thesemiconductor liner 218 with a further reduced thickness (not shown inFIG. 18 ) may remain underneath thecapping layer 222. By way of example, thecapping layer 222 may be deposited by an MBE process, an MOCVD process, an ALD process, and/or other suitable epitaxial growth processes. In furtherance of the example, thesemiconductor liner 274 is an amorphous silicon layer, and thecapping layer 222 includes the same semiconductor material as theepitaxial layer 206, such as SiGe. Due to the amorphous form of the seed layer, the semiconductor material in thecapping layer 222 won't grow in crystalline structures but in amorphous form or polycrystalline form instead, such as amorphous SiGe or polycrystalline SiGe in some embodiments. Thecapping layer 222 reserves a space for subsequently-formed metal gate stack and will be removed in a subsequent processing stage. Therefore, thecapping layer 222 is also referred to as a sacrificial capping layer. - Referring to
FIG. 19 , themethod 100′ at operation 120 (FIG. 14A ) performs an etch-back process to remove portions of thesacrificial capping layer 222 to expose top surfaces of the STI features 220. In some embodiments, the etch-back process may include a wet etch process, a dry etch process, a multiple-step etch process, and/or a combination thereof. It is noted that after the etch-back process, thecapping layer 222 remains disposed on sidewall surfaces of thesemiconductor fins 210. In furtherance of some embodiments, a thinned portion of thecapping layer 222 also remains on the top surfaces of the semiconductor fins, as illustrated inFIG. 19 . - After
operation 120, themethod 100′shares operations method 100. Shared operations are not repeated below in the interest of conciseness. Afteroperation 140, theresultant structure 200 is shown inFIGS. 20A-20D .FIG. 20A is a perspective view of thedevice 200,FIG. 20B refers to a cross-sectional view taken in the gate region and perpendicular to a lengthwise direction of the channel (e.g., along the B-B line),FIG. 20C refers to a cross-sectional view taken in the channel region and along the lengthwise direction of the channel (e.g., along the C-C line), andFIG. 20D refers to a cross-sectional view taken though a gate region previously reserved by thesacrificial capping layer 222 and along the lengthwise direction of the channel (e.g., along the D-D line). Afteroperation 140, thedevice 200 may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on thesubstrate 202, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after themethod 100′, and some process steps described above may be replaced or eliminated in accordance with various embodiments of themethod 100′. - Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, embodiments of the present disclosure provide dielectric fins for improving fin uniformity and defining space for source/drain (S/D) features, and sacrificial capping layers with amorphous or polycrystalline semiconductor material for reserving space for metal gate stacks. The amorphous or polycrystalline semiconductor material allows sacrificial capping layers to maintain vertical footing after etching process, which in turn improves inner spacer layer footing profile and metal gate stack footing profile and reduces S/D feature defects in footing regions. Furthermore, the dielectric fin and sacrificial capping layer formation method can be easily integrated into existing semiconductor fabrication processes.
- In one exemplary aspect, the present disclosure is directed to a method. The method includes forming a semiconductor fin extruding from a substrate; forming a sacrificial capping layer on sidewalls of the semiconductor fin; forming first and second dielectric fins sandwiching the semiconductor fin; forming a sacrificial gate stack over the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; forming gate spacers on sidewalls of the sacrificial gate stack; removing the sacrificial gate stack to form a gate trench, wherein the gate trench exposes the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; removing the sacrificial capping layer from the gate trench, thereby exposing the sidewalls of the semiconductor fin; and forming a metal gate stack in the gate trench engaging the semiconductor fin. In some embodiments, the sacrificial capping layer includes amorphous or polycrystalline semiconductor material. In some embodiments, the semiconductor material is silicon germanium. In some embodiments, the forming of the sacrificial capping layer includes depositing an amorphous silicon layer covering the semiconductor fin; forming an isolation feature covering a bottom portion of the amorphous silicon layer; and depositing the sacrificial capping layer over a top portion of the amorphous silicon layer. In some embodiments, the forming of the sacrificial capping layer includes forming an isolation feature on the sidewalls of the semiconductor fin; depositing an amorphous silicon layer covering the semiconductor fin and the isolation feature; and depositing the sacrificial capping layer covering the amorphous silicon layer. In some embodiments, the forming of the sacrificial capping layer further includes etching the sacrificial capping layer, thereby exposing a top surface of the isolation feature. In some embodiments, the method further includes forming an isolation feature on the sidewalls of the semiconductor fin prior to the forming of the sacrificial capping layer, wherein the first and second dielectric fins are in contact with the isolation feature and the sacrificial capping layer. In some embodiments, the method further includes recessing the semiconductor fin and the sacrificial capping layer after the forming of the gate spacers; and epitaxially growing a source/drain (S/D) feature on the recessed semiconductor fin. In some embodiments, the first and second dielectric fins limit the epitaxially growing of the S/D feature in a lateral direction. In some embodiments, the semiconductor fin includes a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are alternately arranged. In some embodiments, the method further includes laterally etching the sacrificial layers and the sacrificial capping layer, thereby forming cavities between the channel layers; and depositing an inner spacer layer in the cavities.
- In another exemplary aspect, the present disclosure is directed to a method of fabricating a semiconductor device. The method includes forming a stack of a first type and a second type epitaxial layers on a semiconductor substrate, the first type and second type epitaxial layers having different material compositions and the first type and second type epitaxial layers being alternatingly disposed in a vertical direction; patterning the stack to form a plurality of fin elements; depositing a first liner over the fin elements, wherein the first liner incudes an amorphous semiconductor material; depositing a second liner over the first liner, wherein the second liner includes an amorphous or polycrystalline semiconductor material; forming a sacrificial gate stack over the fin elements; forming gate spacers over the sacrificial gate stack; removing the sacrificial gate stack, thereby forming a gate trench; removing the second type epitaxial layers and the second liner from the gate trench, thereby exposing the first type epitaxial layers in the gate trench; and forming a gate stack in the gate trench and wrapping around the first type epitaxial layers. In some embodiments, the second type epitaxial layers and the second liner include a same semiconductor composition in different material structure forms. In some embodiments, the second type epitaxial layers and the second liner both include silicon germanium. In some embodiments, the method further includes depositing a dielectric layer between the fin elements, wherein the dielectric layer is in contact with the second liner, and wherein the gate stack is in contact with the dielectric layer after the forming of the gate stack. In some embodiments, the method further includes prior to the depositing of the first liner, depositing a third liner over the fin elements; and performing a nitridation treatment to the third liner.
- In yet another exemplary aspect, the present disclosure is directed to a multi-gate semiconductor device. The multi-gate semiconductor device includes channel members disposed over a substrate; an isolation feature over the substrate; an amorphous semiconductor layer stacked between the isolation feature and the substrate; first and second dielectric fins disposed over the isolation feature and sandwiching the channel members; and a gate structure engaging the channel members and over the first and second dielectric fins. In some embodiments, the multi-gate semiconductor device further includes an oxide layer stacked between the amorphous semiconductor layer and the substrate. In some embodiments, the multi-gate semiconductor device further includes a source/drain (S/D) feature adjacent the channel members, wherein the S/D feature is in contact with the isolation feature and the first and second dielectric fins. In some embodiments, each of the first and second dielectric fins has a bottom portion including a low-K material and a top portion including a high-K material.
- The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/238,569 US11532732B2 (en) | 2019-09-26 | 2021-04-23 | Multi-gate device and method of fabrication thereof |
TW111108360A TW202243025A (en) | 2019-09-26 | 2022-03-08 | Methods for fabricating semiconductor devices |
CN202210301227.4A CN115241128A (en) | 2019-09-26 | 2022-03-24 | Method for manufacturing semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962906158P | 2019-09-26 | 2019-09-26 | |
US17/238,569 US11532732B2 (en) | 2019-09-26 | 2021-04-23 | Multi-gate device and method of fabrication thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
US20210257480A1 true US20210257480A1 (en) | 2021-08-19 |
US11532732B2 US11532732B2 (en) | 2022-12-20 |
Family
ID=75162191
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/931,717 Active 2040-10-20 US11482610B2 (en) | 2019-09-26 | 2020-07-17 | Method of forming a gate structure |
US17/238,569 Active 2041-07-07 US11532732B2 (en) | 2019-09-26 | 2021-04-23 | Multi-gate device and method of fabrication thereof |
US17/877,221 Pending US20220384618A1 (en) | 2019-09-26 | 2022-07-29 | Method of Forming a Gate Structure |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/931,717 Active 2040-10-20 US11482610B2 (en) | 2019-09-26 | 2020-07-17 | Method of forming a gate structure |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/877,221 Pending US20220384618A1 (en) | 2019-09-26 | 2022-07-29 | Method of Forming a Gate Structure |
Country Status (3)
Country | Link |
---|---|
US (3) | US11482610B2 (en) |
CN (1) | CN115241128A (en) |
TW (2) | TW202117811A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220028729A1 (en) * | 2020-01-13 | 2022-01-27 | International Business Machines Corporation | Nanosheet transistor with self-aligned dielectric pillar |
US11581415B2 (en) * | 2020-04-24 | 2023-02-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-layer channel structures and methods of fabricating the same in field-effect transistors |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102582670B1 (en) * | 2018-07-13 | 2023-09-25 | 삼성전자주식회사 | Semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170250281A1 (en) * | 2016-02-25 | 2017-08-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin-type field effect transistor structure and manufacturing method thereof |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US20080026517A1 (en) * | 2006-07-28 | 2008-01-31 | Grudowski Paul A | Method for forming a stressor layer |
US20080145978A1 (en) * | 2006-12-18 | 2008-06-19 | Air Liquide Electronics U.S. Lp | Deposition of silicon germanium nitrogen precursors for strain engineering |
US9245805B2 (en) | 2009-09-24 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs with metal gates and stressors |
US8962400B2 (en) | 2011-07-07 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | In-situ doping of arsenic for source and drain epitaxy |
US8841701B2 (en) | 2011-08-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device having a channel defined in a diamond-like shape semiconductor structure |
US8815712B2 (en) | 2011-12-28 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for epitaxial re-growth of semiconductor region |
US9236267B2 (en) | 2012-02-09 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut-mask patterning process for fin-like field effect transistor (FinFET) device |
US8847293B2 (en) | 2012-03-02 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure for semiconductor device |
US8836016B2 (en) | 2012-03-08 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods with high mobility and high energy bandgap materials |
US9171929B2 (en) | 2012-04-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of semiconductor device and method of making the strained structure |
US9093530B2 (en) | 2012-12-28 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of FinFET |
US8853025B2 (en) | 2013-02-08 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET/tri-gate channel doping for multiple threshold voltage tuning |
US9093514B2 (en) | 2013-03-06 | 2015-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained and uniform doping technique for FINFETs |
US9214555B2 (en) | 2013-03-12 | 2015-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier layer for FinFET channels |
US8963258B2 (en) | 2013-03-13 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company | FinFET with bottom SiGe layer in source/drain |
US8796666B1 (en) | 2013-04-26 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with strain buffer layer and methods of forming the same |
CN104517822B (en) * | 2013-09-27 | 2017-06-16 | 中芯国际集成电路制造(北京)有限公司 | A kind of manufacture method of semiconductor devices |
US9136106B2 (en) | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
US9548303B2 (en) | 2014-03-13 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices with unique fin shape and the fabrication thereof |
US9543438B2 (en) * | 2014-10-15 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact resistance reduction technique |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US10269926B2 (en) * | 2016-08-24 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Purging deposition tools to reduce oxygen and moisture in wafers |
-
2020
- 2020-07-17 US US16/931,717 patent/US11482610B2/en active Active
- 2020-09-10 TW TW109131064A patent/TW202117811A/en unknown
-
2021
- 2021-04-23 US US17/238,569 patent/US11532732B2/en active Active
-
2022
- 2022-03-08 TW TW111108360A patent/TW202243025A/en unknown
- 2022-03-24 CN CN202210301227.4A patent/CN115241128A/en active Pending
- 2022-07-29 US US17/877,221 patent/US20220384618A1/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170250281A1 (en) * | 2016-02-25 | 2017-08-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin-type field effect transistor structure and manufacturing method thereof |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220028729A1 (en) * | 2020-01-13 | 2022-01-27 | International Business Machines Corporation | Nanosheet transistor with self-aligned dielectric pillar |
US11688626B2 (en) * | 2020-01-13 | 2023-06-27 | International Business Machines Corporation | Nanosheet transistor with self-aligned dielectric pillar |
US11581415B2 (en) * | 2020-04-24 | 2023-02-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-layer channel structures and methods of fabricating the same in field-effect transistors |
Also Published As
Publication number | Publication date |
---|---|
CN115241128A (en) | 2022-10-25 |
TW202117811A (en) | 2021-05-01 |
US20220384618A1 (en) | 2022-12-01 |
US11482610B2 (en) | 2022-10-25 |
US11532732B2 (en) | 2022-12-20 |
TW202243025A (en) | 2022-11-01 |
US20210098604A1 (en) | 2021-04-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11355611B2 (en) | Multi-gate device and method of fabrication thereof | |
US11942548B2 (en) | Multi-gate device and method of fabrication thereof | |
US10157799B2 (en) | Multi-gate device and method of fabrication thereof | |
US11862734B2 (en) | Self-aligned spacers for multi-gate devices and method of fabrication thereof | |
US10790280B2 (en) | Multi-gate device and method of fabrication thereof | |
US11955554B2 (en) | Method of fabricating a multi-gate device | |
US9666581B2 (en) | FinFET with source/drain structure and method of fabrication thereof | |
US20220208763A1 (en) | Multi-gate device and related methods | |
US11107904B2 (en) | Inner spacer formation in multi-gate transistors | |
US11532732B2 (en) | Multi-gate device and method of fabrication thereof | |
US11121036B2 (en) | Multi-gate device and related methods | |
US20240047462A1 (en) | Semiconductor device and method of forming thereof | |
US11652043B2 (en) | Integrated circuit structure with backside via | |
US11854908B2 (en) | Multi-gate device and related methods | |
US11935781B2 (en) | Integrated circuit structure with backside dielectric layer having air gap | |
US20230253313A1 (en) | Integrated circuit structure with backside via | |
US20230395681A1 (en) | Multi-gate device and method of fabrication thereof | |
US20230163186A1 (en) | Epitaxial features in semiconductor devices and manufacturing method of the same | |
US20230326989A1 (en) | Buffer epitaxial region in semiconductor devices and manufacturing method of the same | |
US20230395655A1 (en) | Semiconductor device and method of forming the same | |
US20240055480A1 (en) | Semiconductor structure and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: APPLICATION DISPATCHED FROM PREEXAM, NOT YET DOCKETED |
|
AS | Assignment |
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JHAN, YI-RUEI;PAN, KUAN-TING;CHIANG, KUO-CHENG;AND OTHERS;SIGNING DATES FROM 20210424 TO 20210426;REEL/FRAME:057152/0581 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |