US20210159212A1 - Inductor design in active 3d stacking technology - Google Patents
Inductor design in active 3d stacking technology Download PDFInfo
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- US20210159212A1 US20210159212A1 US16/694,476 US201916694476A US2021159212A1 US 20210159212 A1 US20210159212 A1 US 20210159212A1 US 201916694476 A US201916694476 A US 201916694476A US 2021159212 A1 US2021159212 A1 US 2021159212A1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
Definitions
- Examples of the present disclosure generally relate to inductors and, in particular, to inductor designs for stacked integrated circuit packages.
- Inductors and transformers have been extensively used in radio frequency (RF) integrated circuit (IC) designs, including LC VCO circuits, Accurate and predictable inductor characteristics with high quality factors are desirable for successful RF IC design, especially for LC VCO circuits, in order to meet product performance and frequency targets.
- RF radio frequency
- IC integrated circuit
- the environmental effect can dramatically degrade an inductor quality factor (Q-factor) and alter its inductance value from its modeled behavior, causing products to be unable to meet their intended performance and causing shifts in frequency from their design targets.
- Q-factor inductor quality factor
- the environmental effect is hard to predict before manufacture because various direct current (DC) or alternating current (AC) loops can be formed as a return path by the surrounding circuits, power grids, and complicated routings around the inductors.
- An example is a multi-chip device comprising a chip stack comprising a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer of the first chip being a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer of the first chip, the isolation wall comprising a through substrate via (TSV) of the first chip, the isolation wall being disposed around the inductor.
- TSV through substrate via
- the method comprises forming a stack of a plurality of chips comprising forming the plurality of chips, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate wherein forming a first chip of the plurality of chips includes: forming an inductor disposed in a backside dielectric layer of the first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side; and forming an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer of the first chip, the isolation wall comprising a through-substrate via (TSV) through the semiconductor substrate of the first chip, the isolation wall being disposed around the inductor.
- TSV through-substrate via
- Another example is a multi-chip device, comprising: a chip stack; an inductor disposed in a backside dielectric layer of a first chip of the chip stack; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer of the first chip, the isolation wall being disposed around the inductor.
- FIG. 1 is a cross-section of a multi-chip device, according to some examples.
- FIGS. 2A and 2B illustrate a layout of an isolation wall and a patterned ground shield (PGS) around an inductor, according to some examples.
- PPS patterned ground shield
- FIG. 3 illustrates effects on transformer performance in inductor Q-factor for different frequencies based on different substrate thicknesses, according to some examples.
- FIGS. 4A-4B illustrate inductance characteristics with and without an isolation wall in order to simulate shielding against the environmental effects of vertically stacked chips in a stacked integrated circuit (IC) environment, according to some examples.
- FIGS. 5A-5B illustrate Q-factor characteristics with and without the isolation wall, according to some examples.
- FIG. 6 is a flowchart of a method of forming the multi-chip device of FIG. 1 according to some examples.
- the inductor of the IC can become unpredictable in an integrated Active-on-Active (AoA) environment (referred herein as a stacked IC environment).
- AoA Active-on-Active
- the inductor performance can be dramatically degraded, which can cause the IC chip (which can include a voltage controlled oscillator (VCO) circuit) to not meet its performance metrics.
- VCO voltage controlled oscillator
- the inductor can no longer function in the stacked IC environment.
- examples herein describe an IC design to effectively isolate the uncertain 3D environmental effects on an inductor and yield stable and predictable inductor characteristics in the stacked IC environment.
- Examples described herein describe a multi-chip device with an isolation wall surrounding an inductor.
- the isolation wall can assist in isolating the environmental effects arising in the stacked IC environment (e.g., including environmental effects from vertically stacked chips stacked on the chip on which the inductor is disposed).
- the multi-chip device includes a plurality of chips, each chip comprising a semiconductor substrate having a backside and a front side opposite the backside.
- the multi-chip device includes an inductor disposed on the backside of a first chip of the plurality of chips, and an isolation wall disposed from the backside of the first chip to the front side of the first chip.
- the isolation wall passes through one or more backside through substrate vias (BTSVs) of the first chip and is disposed around the inductor.
- BTSVs substrate vias
- the isolation wall surrounding the inductor disclosed herein can be used with stacked devices, such as including active-on-active (AoA) chips.
- processing integrated circuit or “processing IC” refers to an IC comprising a circuit capable of, configured to, and/or configurable to process or manipulate data, as opposed to memory that merely stores data and any circuit ancillary to memory (e.g., a memory controller, an address decoder, etc.).
- a processing IC may include memory in addition to a circuit capable of, configured to, and/or configurable to process or manipulate data.
- processing ICs include ICs including a programmable logic region (e.g., FPGA), a processor (e.g., a central processing unit (CPU), graphics processing unit (GPU), etc.), an application specific integrated circuit (ASIC), the like, or a combination thereof.
- a programmable logic region e.g., FPGA
- a processor e.g., a central processing unit (CPU), graphics processing unit (GPU), etc.
- ASIC application specific integrated circuit
- FIG. 1 is a structure of a multi-chip device according to some examples.
- the multi-chip device of FIG. 1 includes a chip stack that includes a base chip 102 , intermediate chips 104 a , 104 b , 104 c (collectively or individually, intermediate chip(s) 104 ), and a distal chip 108 .
- the intermediate chips 104 are arranged active or front side facing towards the base chip 102 .
- Various other multi-chip devices can have different structures, different number of chips, additional components, etc.
- the chips 102 , 104 a , 104 b , 104 c , 108 are stacked and form a chip stack in the multi-chip device.
- the chips 102 , 104 a , 104 b , 104 c , 108 are stacked to form, in some examples, an Active chip-on-Active chip (AoA) device.
- AoA Active chip-on-Active chip
- more or fewer chips can be included in the chip stack.
- the intermediate chips 104 can be removed from or added into a chip stack.
- the chip stack can be or include two chips, such as the base chip 102 bonded to an intermediate chip 104 .
- the chip stack can be or include two other chips, such as the base chip 102 bonded to the distal chip 108 .
- the chip stack can be or include three chips (e.g., the base chip 102 bonded to an intermediate chip 104 , which is bonded to the distal chip 108 ), four chips (e.g., the base chip 102 , two intermediate chips 104 , and the distal chip 108 ), etc.
- the base chip 102 is an input/output (I/O) chip
- the intermediate chips 104 and distal chips 108 are chips having a programmable IC that include programmable logic regions (e.g., fabric chips).
- Each of the chips 102 , 104 a , 104 b , 104 c , 108 includes a respective semiconductor substrate 112 , 114 a , 114 b , 114 c 118 and respective front side dielectric layer(s) 122 , 124 a , 124 b , 124 c , 128 on a front side of the respective semiconductor substrate 112 , 114 a , 114 b , 114 c 118 .
- the front side dielectric layer(s) 122 , 124 a , 124 b , 124 c , 128 include metallization (e.g., metal lines and/or vias) (illustrated but not specifically numbered) formed therein which can electrically connect various components in an IC.
- metallization e.g., metal lines and/or vias
- Each of the chips 102 , 104 a , 104 b , 104 c includes backside dielectric layer(s) 132 , 134 a , 134 b , 134 c on a backside of the respective semiconductor substrate 112 , 114 a , 114 b , 114 c .
- the backside dielectric layer(s) 132 , 134 a , 134 b , 134 c include metallization (e.g., metal lines and/or vias) (illustrated but not specifically numbered) formed therein which can electrically connect various components in an IC.
- metallization e.g., metal lines and/or vias
- Each semiconductor substrate 112 , 114 a , 114 b , 114 c , 118 of the chips 102 , 104 a , 104 b , 104 c , 108 includes, e.g., one or more transistors 142 , 144 a , 144 b , 144 c , 148 formed on and/or in the front side surface of the respective semiconductor substrate 112 , 114 a , 114 b , 114 c , 118 .
- the transistor(s) 142 , 144 a , 144 b , 144 c , 148 and any other components can be connected to the metallization (illustrated but not labeled) in the front side dielectric layer(s) 122 , 124 a , 124 b , 124 c , 128 .
- Each semiconductor substrate 112 , 114 a , 114 b , 114 c of the respective chip 102 , 104 a , 104 b , 104 c has backside through-substrate via(s) (TSV(s)) 162 , 164 a , 164 b , 164 c therethrough, which can electrically connect the metallization in the front side dielectric layer(s) 122 , 124 a , 124 b , 124 c to the metallization in the backside dielectric layer(s) 132 , 134 a , 134 b of the respective chip 102 , 104 a , 104 b , 104 c.
- TSV(s) through-substrate via
- Front side bond pads 152 , 154 a , 154 b , 154 c , 158 are formed in the respective front side dielectric layer(s) 122 , 124 a , 124 b , 124 c , 128 of the chips 102 , 104 a , 104 b , 104 c , 108 at an exterior surface distal from the respective semiconductor substrate 112 , 114 a , 114 b , 114 c , 118 .
- the front side bond pads 152 , 154 a , 154 b , 154 c , 158 can be in an arrangement that forms a respective chip-to-chip interface.
- the front side bond pads 152 , 154 a , 154 b , 154 c , 158 are connected to the metallization in the respective front side dielectric layer(s) 122 , 124 a , 124 b , 124 c , 128 .
- Backside bond pads 174 a , 174 b , 174 c are formed in the respective backside dielectric layer(s) 134 a , 134 b , 134 c of the chips 104 a , 104 b , 104 c at an exterior surface distal from the respective semiconductor substrate 114 a , 114 b , 114 c .
- the backside bond pads 174 a , 174 b , 174 c can be in an arrangement that forms a respective chip-to-chip interface.
- the backside bond pads 174 a , 174 b , 174 c are connected to the metallization in the respective backside dielectric layer(s) 134 a , 134 b , 134 c.
- Exterior connector backside pads 172 are formed in the backside dielectric layer(s) 132 of the base chip 102 at an exterior surface distal from the semiconductor substrate 112 of the base chip 102 .
- the exterior connector backside pads 172 are connected to the metallization in the backside dielectric layer(s) 132 of the base chip 102 .
- a passivation layer 180 is formed on the exterior surface distal from the semiconductor substrate 112 of the base chip 102 with respective openings therethrough exposing the exterior connector backside pads 172 .
- External connectors 182 e.g., controlled collapse chip connections (C4), minibumps, etc.
- C4 controlled collapse chip connections
- minibumps minibumps
- the external connectors 182 can be attached to a package substrate.
- the package substrate may further be attached to, e.g., a printed circuit board (PCB) to attach the package substrate (and hence, the multi-chip device) to the PCB.
- PCB printed circuit board
- Various other components can be included in a multi-chip device.
- an interposer, an encapsulant (such as a molding compound (MUF) or the like), etc. can be included in the multi-chip device.
- an encapsulant such as a molding compound (MUF) or the like
- the chips 102 , 104 a , 104 b , 104 c , 108 are bonded (e.g., by hybrid bonding using metal-to-metal and oxide-to-oxide bonding) together to form a chip stack.
- the base chip 102 is bonded to the intermediate chip 104 a front side to front side such that the front side bond pads 152 and exterior surface of the front side dielectric layer(s) 122 of the base chip 102 are bonded to the front side bond pads 154 a and exterior surface of the front side dielectric layer(s) 124 a of the intermediate chip 104 a .
- the intermediate chip 104 a is bonded to the intermediate chip 104 b backside to front side such that the backside bond pads 174 a and exterior surface of the backside dielectric layer(s) 134 a of the intermediate chip 104 a are bonded to the front side bond pads 154 b and exterior surface of the front side dielectric layer(s) 124 b of the intermediate chip 104 b .
- the intermediate chip 104 b is bonded to the intermediate chip 104 c backside to front side.
- the intermediate chip 104 c is bonded to the distal chip 108 backside to front side such that the backside bond pads 174 b and exterior surface of the backside dielectric layer(s) 134 b of the intermediate chip 104 c are bonded to the front side bond pads 158 and exterior surface of the front side dielectric layer(s) 128 of the distal chip 108 .
- an inductor 190 is formed in the backside dielectric layer(s) 132 of the base chip 102 . Forming the inductor 190 in the backside dielectric layer(s) 132 of the base chip 102 increases the distance between the inductor 190 and metallization of intermediate chip 104 a . In some examples, the inductor 190 is formed in the backside dielectric layer(s) 132 of the base chip 102 , while devices (e.g., transistors) of other I/O circuits (e.g., GM cell, fine-tuning, and course-tuning circuits) are formed on the front side of the semiconductor substrate 112 the base chip 102 .
- devices e.g., transistors
- I/O circuits e.g., GM cell, fine-tuning, and course-tuning circuits
- an isolation wall 192 and pattern ground shield (PGS) 194 can provide additional isolation for the inductor 190 from environmental effects of the stacked IC environment.
- the isolation wall 192 is disposed in the base chip 102 around the inductor 190 , and extends from the metallization layer in the backside dielectric layer(s) 132 of the base chip 102 to an upper metallization layer in the front side dielectric layer(s) 122 of the base chip 102 .
- the isolation wall 192 is formed by conductive metal lines and vias in the metallization of the base chip 102 .
- the isolation wall 192 can include metal lines in the same metallization layer as the inductor 190 , and can be connected to through substrate vias (TSVs), which in turn are connected to vias and metal lines in the metallization on the front side of the base chip 102 .
- TSVs through substrate vias
- the isolation wall 192 includes conductive lines and/or vias in metallization in adjacent chips (e.g., intermediate chip 104 a ), which can be connected to the portion of the isolation wall on the base chip 102 by bonded front side bond pads 152 and 154 a.
- the isolation wall 192 can have any shape, size, and location to improve circuit performance (e.g., to improve chip area utilization, to reduce coupling effect with other devices located in the chip, etc.).
- the thickness of the isolation wall may be tuned to adjust the resistance of the isolation wall (e.g., reducing the resistance by increasing the thickness of the isolation wall).
- portions of the isolation wall 192 may have different thicknesses determined based on resistance requirements and the available space.
- the isolation wall 192 extends through the front side dielectric layer(s) 122 to a PGS 194 disposed in an upper metallization layer in the front side dielectric layer(s) 122 of the base chip 102 .
- the PGS 194 can assist in shielding environmental effects from the intermediate chip(s) 104 and/or distal chip 108 .
- the PGS 194 is inserted between (i) the inductor 190 and (ii) the intermediate chips 104 and the distal chip 108 .
- the PGS 194 is disposed in the top metallization layer in the base chip 102 so the distance between the inductor 190 and the PGS 194 is maximized within the base chip 102 to minimize parasitic capacitance.
- the PGS 194 is disposed in the topmost metallization layer in the front side dielectric layer(s) 122 of the base chip 102 while the inductor 190 is disposed in the backside dielectric layer(s) 132 of the base chip 102 .
- the PGS 194 can be disposed in any chip of the multi-chip device 100 , and the isolation wall 192 can extend through any number of front side dielectric layers, backside dielectric layers, and TSVs to reach the PGS 194 .
- the PGS 194 is described in further detail with reference to FIGS. 2A and 2B .
- the isolation wall 192 can be electrically connected and extend through the backside TSVs 164 and bond pads bonded between the base chip 102 and intermediate chips 104 .
- the inductor 190 can be disposed in the front side or the backside dielectric layers of a chip depending on the circuit requirement.
- the inductor 190 and the other circuits are electrically connected through interconnect metals on the same chip or through backside TSVs 162 , 164 a , 164 b , 164 c and/or bonding for cross-chip cases.
- the backside TSVs 162 , 164 a , 164 b , 164 c electrically connect metallization(s) in the backside dielectric layer(s) with these circuits in the base chip 102 , and can reduce the parasitic resistance of the isolation wall 192 , which also benefits from the higher density BTSV of a thinner semiconductor substrate.
- the electrical grounds for each chip of the multi-chip device 100 can be electrically connected together through controlled collapse chip connection (C4) bumps at a package level in the stacked IC environment.
- C4 controlled collapse chip connection
- the electrically connected grounds can form various returning paths, which can be different based on the surrounding environments. These various returning paths can modulate the inductor characteristics.
- the metallization of the intermediate chip 104 underneath the inductor can act as a conducting mirror, which can terminate the magnetic field and cause dramatic degradation on inductor Q-factor.
- the multi-chip device with an isolation wall as described herein can be optimized to achieve the highest device performance within a given chip area and metal scheme with a desired inductance value.
- the C4 bump geometry in packaging is also considered so that the inductor and the isolation wall can fit in the empty area between C4 bumps to minimize the impact from the bumps.
- the distance between the inductor and the semiconductor substrate of a chip is shorter compared to the distance in a single (i.e., monolithic) chip.
- loss caused by a highly doped semiconductor substrate can significantly degrade inductor performance.
- a region of the semiconductor substrate vertically corresponding with the location of the inductor 190 e.g., surrounded by the TSVs of the isolation wall 192
- the semiconductor substrate can have a certain thickness to reduce substrate loss.
- the thickness of the semiconductor substrate 112 of the base chip 102 is less than or equal to 2.7 um.
- FIGS. 2A and 2B illustrate an isolation wall 192 around a PGS 194 and an inductor 190 , according to some examples.
- the isolation wall 192 is formed in the backside dielectric layer(s) 132 of the base chip 102 and through backside TSVs 162 , and is designed to isolate the inductor 190 from the environmental effects and to maintain the quality factor (Q-factor) of the inductor.
- FIG. 2A is a top view of a PGS and isolation wall.
- a PGS 194 associated with the inductor enables shielding and enhances the Q-factor of the inductor 190 .
- the PGS 194 may include groups of parallel, conductive fingers 214 , and may be coupled together at the outer perimeter. These fingers 214 can be constructed to be perpendicular to the current direction of the inductor 190 to minimize eddy current and reduce magnetic loss.
- the PGS 194 and the isolation wall 192 may isolate the electrical field generated by current flow through devices disposed over the PGS 194 (e.g., inductor 190 ) from devices in a region disposed between the PGS 194 and the semiconductor substrate 112 .
- the PGS 194 can be shaped as an octagon to match the shape of the coil portion of the inductor 190 .
- the isolation wall 192 extends up from the PGS 194 , and in some examples, the isolation wall 192 can surround the PGS 194 . In some examples, the isolation wall 192 includes a portion adjacent to legs of a transformer (shown in FIG. 2B ).
- the PGS 194 can be formed from conductive materials such as aluminum, copper, aluminum/silicon/copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, other suitable conductive materials, or combinations thereof.
- FIG. 2B illustrates a top view of the isolation wall 192 around an inductor 190 , which in this example is in a transformer (e.g., which includes two inductors).
- the inductor 190 can be merely an inductor, and a person having ordinary skill in the art will readily understand such a structure, particularly in view of FIG. 2B .
- the transformer includes an outer inductor L 1 and an inner inductor L 0 .
- Inner inductor L 0 is placed inside the outer inductor L 1 .
- Each of the inductors L 0 , L 1 can be formed in multiple metal layers in series or in parallel.
- Transformer legs 202 , 204 and 206 , 208 are coupled to respective coil portions.
- the transformer legs 202 , 204 and 206 , 208 comprise traces in the metallization of the backside dielectric layer(s) 132 of the base chip 102 .
- the transformer legs 202 , 204 , 206 , 208 can be connected to metal layers in the front side dielectric layer(s) 122 of the base chip 102 , and to metal layers of other chips, through backside TSVs 162 .
- Overlapping portions of the coil portions of the inductors L 0 , L 1 in different metal layers are connected by vias along the length of the portion of the coil to provide larger coils to increase inductance.
- One or ordinary skill in the art would understand how to design a transformer to be formed with the multi-chip device of FIG.
- FIG. 3 illustrates the effect on transformer performance in inductor Q-factor for different frequencies based on different thicknesses of semiconductor substrate 112 according to some examples.
- FIG. 3 illustrates the effects based on three different semiconductor substrate thicknesses for semiconductor substrate 112 : 2.7 ⁇ m ( 302 ), 10 ⁇ m ( 304 ), and 100 ⁇ m ( 306 ).
- a thinner substrate thickness shows smaller degradation to inductor Q-factor and accordingly inductor performance, as frequency increases.
- a thinner substrate thickness also allows for more BTSVs, which in turn can benefit in lower resistive paths for power and signal integrity.
- FIGS. 4A and 4B respectively illustrate inductance characteristics with and without the isolation wall in order to simulate shielding against the 3D environmental effects of vertically stacked chips in the stacked IC environment.
- FIG. 4A-4B also show the inductance characteristics of three different thicknesses of semiconductor substrate 112 : 2.7 ⁇ m ( 402 ), 10 ⁇ m ( 402 ), and 100 ⁇ m ( 406 ).
- FIG. 4A without the isolation wall, inductance of the inductor can vary dramatically in stacked ICs because different return paths are formed in different stacked IC environments.
- FIG. 4B with the isolation wall, the inductance of the inductor becomes more stable and predictable in the stacked IC environment.
- FIGS. 5A and 5B respectively illustrate the Q-factor characteristics with and without the isolation wall.
- FIG. 5A-5B also show the inductance characteristics of three different thicknesses of semiconductor substrate 112 : 2.7 ⁇ m ( 502 ), 10 ⁇ m ( 504 ), and 100 ⁇ m ( 506 ).
- the Q-factor of the inductor changes differently based on the semiconductor substrate thicknesses.
- the Q-factor of the inductor stabilizes between the semiconductor substrate thicknesses in the stacked IC environment.
- the multi-chip device including the isolation wall can demonstrate device performance metrics to meet VCO design requirements in an active 3D stacking environment.
- FIG. 6 is a flowchart of a method 600 of forming the multi-chip device of FIG. 1 according to some examples.
- the processing of the method 600 of FIG. 6 is generally described, and a person having ordinary skill in the art will readily understand the more specific processing that can be performed.
- the more specific processing can be according to any semiconductor processing for forming an IC on substrate, which is to be singulated into a chip.
- a wafer on which one or more base chips 102 are formed is referred to as a base wafer; a wafer on which one or more intermediate chips 104 are formed is referred to as an intermediate wafer; and a wafer on which one or more distal chips are formed is referred to as a distal wafer.
- Any wafer can be any shape and/or size.
- front side processing for chips on the respective wafers is performed.
- front side processing of each semiconductor substrate 112 , 114 a , 114 b , 114 c , 118 can include forming devices (e.g., transistors 142 , 144 a , 144 b , 144 c , 148 ) in and/or on the front surface of the semiconductor substrate 112 , 114 a , 114 b , 114 c , 118 , and forming front side dielectric layer(s) 122 , 124 a , 124 b , 124 c , 128 with metallization and front side bond pads 152 , 154 a , 154 b , 154 c , 158 on the front surface of the semiconductor substrate 112 , 114 a , 114 b , 114 c , 118 .
- Multiple base chips 102 e.g., transistors 142 , 144 a , 144
- front side processing of a base wafer includes forming at least a portion of an isolation wall (e.g., isolation wall 192 ) in the front side dielectric layer(s) with metallization.
- Front side processing of the base wafer can also include forming a PGS (e.g., PGS 194 ) in the front side dielectric layer(s) with metallization.
- a base wafer is bonded to a first intermediate wafer, such as front side to front side bonding as shown in FIG. 1 .
- a front side of a base chip 102 is bonded to a front side of an intermediate chip 104 a , as shown in FIG. 1 .
- the bonding can be hybrid bonding, such as bonding front side bond pads 152 on the base wafer to front side bond pads 154 a on the first intermediate wafer, and bonding the exterior surface of the front side dielectric layer(s) 122 on the base wafer to the exterior surface of the front side dielectric layer(s) 124 a on the first intermediate wafer.
- the semiconductor substrate of the first intermediate wafer is thinned from a backside of the first intermediate wafer.
- the semiconductor substrate 114 a of the intermediate chip 104 a is thinned from the backside.
- the thinning can be by a chemical mechanical polish (CMP) or other appropriate process.
- the backside processing can include forming backside TSVs 164 a through the semiconductor substrate 114 a of the first intermediate wafer and connecting to metallization in the front side dielectric layer(s) 124 a on the first intermediate wafer.
- the backside processing can further include forming backside dielectric layer(s) 134 a with metallization and backside bond pads 174 a on the backside of the semiconductor substrate 114 a .
- the metallization in the backside dielectric layer(s) 134 a can be connected to the metallization in the front side dielectric layer(s) 124 a through the backside TSVs 164 a.
- the first intermediate wafer is bonded to a second intermediate wafer, such as backside to front side bonding as shown in FIG. 1 .
- a backside of an intermediate chip 104 a is bonded to a front side of an intermediate chip 104 b , as shown in FIG. 1 .
- the bonding can be hybrid bonding, such as bonding backside bond pads 174 a on the first intermediate wafer to front side bond pads 154 b on the second intermediate wafer, and bonding the exterior surface of the backside dielectric layer(s) 134 a on the first intermediate wafer to the exterior surface of the front side dielectric layer(s) 124 b on the second intermediate wafer.
- the semiconductor substrate of the second intermediate wafer is thinned from a backside of the second intermediate wafer, like described with respect to block 606 .
- the semiconductor substrate 114 b of the intermediate chip 104 b is thinned from the backside.
- backside processing for intermediate chips on the second intermediate wafer is performed, like described with respect to block 608 .
- the backside processing can include forming backside TSVs 164 b through the semiconductor substrate 114 b of the second intermediate wafer and connecting to metallization in the front side dielectric layer(s) 124 b on the second intermediate wafer.
- the backside processing can further include forming backside dielectric layer(s) 134 b with metallization and backside bond pads 174 b on the backside of the semiconductor substrate 114 b .
- the metallization in the backside dielectric layer(s) 134 b can be connected to the metallization in the front side dielectric layer(s) 124 b through the backside TSVs 164 b.
- the second intermediate wafer is bonded to a third intermediate wafer, such as backside to front side bonding as shown in FIG. 1 .
- a backside of an intermediate chip 104 b is bonded to the front side of an intermediate chip 104 c , as shown in FIG. 1 .
- the bonding can be hybrid bonding, such as bonding backside bond pads 174 b on the second intermediate wafer to front side bond pads 154 c on the second intermediate wafer, and bonding the exterior surface of the backside dielectric layer(s) 134 b on the second intermediate wafer to the exterior surface of the front side dielectric layer(s) 124 c on the third intermediate wafer.
- the semiconductor substrate of the third intermediate wafer is thinned from a backside of the third intermediate wafer, like described with respect to block 606 . As shown in FIG. 1 , the semiconductor substrate 114 c of the intermediate chip 104 c is thinned from the backside.
- backside processing for intermediate chips on the third intermediate wafer is performed, like described with respect to block 608 .
- the backside processing can include forming backside TSVs 164 c through the semiconductor substrate 114 c of the third intermediate wafer and connecting to metallization in the front side dielectric layer(s) 124 c on the third intermediate wafer.
- the backside processing can further include forming backside dielectric layer(s) 134 c with metallization and backside bond pads 174 c on the backside of the semiconductor substrate 114 c .
- the metallization in the backside dielectric layer(s) 134 c can be connected to the metallization in the front side dielectric layer(s) 124 c through the backside TSVs 164 c.
- the third intermediate wafer is bonded to a distal wafer, such as backside to front side bonding as shown in FIG. 1 .
- a backside of an intermediate chip 104 c is bonded to a front side of a distal chip 108 , as shown in FIG. 1 .
- the bonding can be hybrid bonding, such as bonding backside bond pads 174 c on the third intermediate wafer to front side bond pads 158 on the distal wafer, and bonding the exterior surface of the backside dielectric layer(s) 134 c on the third intermediate wafer to the exterior surface of the front side dielectric layer(s) 128 on the distal wafer.
- the semiconductor substrate of the base wafer is thinned from a backside of the base wafer, like described with respect to block 606 . As shown in FIG. 1 , the semiconductor substrate 112 of the base chip 102 is thinned from the backside.
- backside processing for base chips on the base wafer is performed, like described with respect to block 608 .
- the backside processing can include forming backside TSVs 162 through the semiconductor substrate 112 of the base wafer and connecting to metallization in the front side dielectric layer(s) 122 on the base wafer.
- the backside processing can further include forming backside dielectric layer(s) 132 with metallization and exterior connector backside pads 172 on the backside of the semiconductor substrate 112 .
- the metallization in the backside dielectric layer(s) 132 can be connected to the metallization in the front side dielectric layer(s) 122 through the backside TSVs 162 .
- the backside processing for the base chips 102 can further include forming the passivation layer 180 and external connectors 182 .
- Backside processing of the base chip can include forming an inductor (e.g., inductor 190 ) and at least a portion of an isolation wall (e.g., isolation wall 192 ).
- the bonded wafers are singulated (e.g., by sawing) to separate individual multi-chip devices that have been formed.
- Each of the multi-chip devices can be as shown in FIG. 1 .
Abstract
Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.
Description
- Examples of the present disclosure generally relate to inductors and, in particular, to inductor designs for stacked integrated circuit packages.
- Inductors and transformers have been extensively used in radio frequency (RF) integrated circuit (IC) designs, including LC VCO circuits, Accurate and predictable inductor characteristics with high quality factors are desirable for successful RF IC design, especially for LC VCO circuits, in order to meet product performance and frequency targets. As technology continues to evolve, the number of devices dramatically increases within a given area of an IC. This increased density in an IC can cause increased parasitic effects on devices or circuits.
- The environmental effect can dramatically degrade an inductor quality factor (Q-factor) and alter its inductance value from its modeled behavior, causing products to be unable to meet their intended performance and causing shifts in frequency from their design targets. The environmental effect is hard to predict before manufacture because various direct current (DC) or alternating current (AC) loops can be formed as a return path by the surrounding circuits, power grids, and complicated routings around the inductors.
- Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer of the first chip being a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer of the first chip, the isolation wall comprising a through substrate via (TSV) of the first chip, the isolation wall being disposed around the inductor.
- Another example is a method for constructing a multi-chip device. The method comprises forming a stack of a plurality of chips comprising forming the plurality of chips, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate wherein forming a first chip of the plurality of chips includes: forming an inductor disposed in a backside dielectric layer of the first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side; and forming an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer of the first chip, the isolation wall comprising a through-substrate via (TSV) through the semiconductor substrate of the first chip, the isolation wall being disposed around the inductor.
- Another example is a multi-chip device, comprising: a chip stack; an inductor disposed in a backside dielectric layer of a first chip of the chip stack; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer of the first chip, the isolation wall being disposed around the inductor.
- Aspects generally include methods as substantially described herein with reference to and as illustrated by the accompanying drawings.
- So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.
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FIG. 1 is a cross-section of a multi-chip device, according to some examples. -
FIGS. 2A and 2B illustrate a layout of an isolation wall and a patterned ground shield (PGS) around an inductor, according to some examples. -
FIG. 3 illustrates effects on transformer performance in inductor Q-factor for different frequencies based on different substrate thicknesses, according to some examples. -
FIGS. 4A-4B illustrate inductance characteristics with and without an isolation wall in order to simulate shielding against the environmental effects of vertically stacked chips in a stacked integrated circuit (IC) environment, according to some examples. -
FIGS. 5A-5B illustrate Q-factor characteristics with and without the isolation wall, according to some examples. -
FIG. 6 is a flowchart of a method of forming the multi-chip device ofFIG. 1 according to some examples. - To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples.
- Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. They are not intended as an exhaustive description of the description or as a limitation on the scope of the claims. In addition, an illustrated example does not need to have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated, or if not so explicitly described.
- In active 3D stacking, multiple chips are bonded vertically together, which can provide high-density multi-functional devices. The electrical and magnetic parasitic interactions between the chips is accordingly three dimensional, and these three-dimensional electrical and magnetic parasitic interactions can affect and modulate an IC with an inductor and surrounding circuits. In some cases, the inductor of the IC can become unpredictable in an integrated Active-on-Active (AoA) environment (referred herein as a stacked IC environment). The inductor performance can be dramatically degraded, which can cause the IC chip (which can include a voltage controlled oscillator (VCO) circuit) to not meet its performance metrics. In some cases, the inductor can no longer function in the stacked IC environment. These problems are especially severe for inductors with sub-nano Henry inductance that are often used for high speed VCO circuits in advanced semiconductor technologies.
- Accordingly, examples herein describe an IC design to effectively isolate the uncertain 3D environmental effects on an inductor and yield stable and predictable inductor characteristics in the stacked IC environment.
- Examples described herein describe a multi-chip device with an isolation wall surrounding an inductor. The isolation wall can assist in isolating the environmental effects arising in the stacked IC environment (e.g., including environmental effects from vertically stacked chips stacked on the chip on which the inductor is disposed).
- The multi-chip device includes a plurality of chips, each chip comprising a semiconductor substrate having a backside and a front side opposite the backside. The multi-chip device includes an inductor disposed on the backside of a first chip of the plurality of chips, and an isolation wall disposed from the backside of the first chip to the front side of the first chip. The isolation wall passes through one or more backside through substrate vias (BTSVs) of the first chip and is disposed around the inductor. The isolation wall surrounding the inductor disclosed herein can be used with stacked devices, such as including active-on-active (AoA) chips.
- Concepts described herein can be extended to chips of a multi-chip device having any IC. As used herein, “processing integrated circuit” or “processing IC” refers to an IC comprising a circuit capable of, configured to, and/or configurable to process or manipulate data, as opposed to memory that merely stores data and any circuit ancillary to memory (e.g., a memory controller, an address decoder, etc.). A processing IC may include memory in addition to a circuit capable of, configured to, and/or configurable to process or manipulate data. Examples of processing ICs include ICs including a programmable logic region (e.g., FPGA), a processor (e.g., a central processing unit (CPU), graphics processing unit (GPU), etc.), an application specific integrated circuit (ASIC), the like, or a combination thereof.
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FIG. 1 is a structure of a multi-chip device according to some examples. The multi-chip device ofFIG. 1 includes a chip stack that includes abase chip 102,intermediate chips distal chip 108. In the multi-chip device ofFIG. 1 , the intermediate chips 104 are arranged active or front side facing towards thebase chip 102. Various other multi-chip devices can have different structures, different number of chips, additional components, etc. - Referring to
FIG. 1 , generally, thechips chips base chip 102 bonded to an intermediate chip 104. In another example, the chip stack can be or include two other chips, such as thebase chip 102 bonded to thedistal chip 108. In further examples, the chip stack can be or include three chips (e.g., thebase chip 102 bonded to an intermediate chip 104, which is bonded to the distal chip 108), four chips (e.g., thebase chip 102, two intermediate chips 104, and the distal chip 108), etc. In some examples, thebase chip 102 is an input/output (I/O) chip, and the intermediate chips 104 anddistal chips 108 are chips having a programmable IC that include programmable logic regions (e.g., fabric chips). - Each of the
chips respective semiconductor substrate respective semiconductor substrate c 118. The front side dielectric layer(s) 122, 124 a, 124 b, 124 c, 128 include metallization (e.g., metal lines and/or vias) (illustrated but not specifically numbered) formed therein which can electrically connect various components in an IC. Each of thechips respective semiconductor substrate semiconductor substrate chips more transistors respective semiconductor substrate semiconductor substrate respective chip respective chip - Front
side bond pads chips respective semiconductor substrate side bond pads side bond pads Backside bond pads chips respective semiconductor substrate backside bond pads backside bond pads - Exterior connector backside pads 172 (e.g., metal (e.g., aluminum) pads) are formed in the backside dielectric layer(s) 132 of the
base chip 102 at an exterior surface distal from thesemiconductor substrate 112 of thebase chip 102. The exteriorconnector backside pads 172 are connected to the metallization in the backside dielectric layer(s) 132 of thebase chip 102. Apassivation layer 180 is formed on the exterior surface distal from thesemiconductor substrate 112 of thebase chip 102 with respective openings therethrough exposing the exteriorconnector backside pads 172. External connectors 182 (e.g., controlled collapse chip connections (C4), minibumps, etc.) are formed on respective exteriorconnector backside pads 172 through the openings in thepassivation layer 180. - The
external connectors 182 can be attached to a package substrate. The package substrate may further be attached to, e.g., a printed circuit board (PCB) to attach the package substrate (and hence, the multi-chip device) to the PCB. Various other components can be included in a multi-chip device. For example, an interposer, an encapsulant (such as a molding compound (MUF) or the like), etc. can be included in the multi-chip device. A person having ordinary skill in the art will readily envision various modifications that can be made to the multi-chip device. - As described above, in some examples, the
chips FIG. 1 , thebase chip 102 is bonded to theintermediate chip 104 a front side to front side such that the frontside bond pads 152 and exterior surface of the front side dielectric layer(s) 122 of thebase chip 102 are bonded to the frontside bond pads 154 a and exterior surface of the front side dielectric layer(s) 124 a of theintermediate chip 104 a. Theintermediate chip 104 a is bonded to theintermediate chip 104 b backside to front side such that thebackside bond pads 174 a and exterior surface of the backside dielectric layer(s) 134 a of theintermediate chip 104 a are bonded to the frontside bond pads 154 b and exterior surface of the front side dielectric layer(s) 124 b of theintermediate chip 104 b. Similarly, theintermediate chip 104 b is bonded to theintermediate chip 104 c backside to front side. Theintermediate chip 104 c is bonded to thedistal chip 108 backside to front side such that thebackside bond pads 174 b and exterior surface of the backside dielectric layer(s) 134 b of theintermediate chip 104 c are bonded to the frontside bond pads 158 and exterior surface of the front side dielectric layer(s) 128 of thedistal chip 108. - In some examples, an
inductor 190 is formed in the backside dielectric layer(s) 132 of thebase chip 102. Forming theinductor 190 in the backside dielectric layer(s) 132 of thebase chip 102 increases the distance between theinductor 190 and metallization ofintermediate chip 104 a. In some examples, theinductor 190 is formed in the backside dielectric layer(s) 132 of thebase chip 102, while devices (e.g., transistors) of other I/O circuits (e.g., GM cell, fine-tuning, and course-tuning circuits) are formed on the front side of thesemiconductor substrate 112 thebase chip 102. - In some examples, an
isolation wall 192 and pattern ground shield (PGS) 194 can provide additional isolation for theinductor 190 from environmental effects of the stacked IC environment. - As illustrated, the
isolation wall 192 is disposed in thebase chip 102 around theinductor 190, and extends from the metallization layer in the backside dielectric layer(s) 132 of thebase chip 102 to an upper metallization layer in the front side dielectric layer(s) 122 of thebase chip 102. In some examples, theisolation wall 192 is formed by conductive metal lines and vias in the metallization of thebase chip 102. Theisolation wall 192 can include metal lines in the same metallization layer as theinductor 190, and can be connected to through substrate vias (TSVs), which in turn are connected to vias and metal lines in the metallization on the front side of thebase chip 102. In some examples, theisolation wall 192 includes conductive lines and/or vias in metallization in adjacent chips (e.g.,intermediate chip 104 a), which can be connected to the portion of the isolation wall on thebase chip 102 by bonded frontside bond pads - As illustrated in
FIGS. 2A and 2B , theisolation wall 192 can have any shape, size, and location to improve circuit performance (e.g., to improve chip area utilization, to reduce coupling effect with other devices located in the chip, etc.). In some examples, the thickness of the isolation wall may be tuned to adjust the resistance of the isolation wall (e.g., reducing the resistance by increasing the thickness of the isolation wall). In some examples, portions of theisolation wall 192 may have different thicknesses determined based on resistance requirements and the available space. - As illustrated, the
isolation wall 192 extends through the front side dielectric layer(s) 122 to aPGS 194 disposed in an upper metallization layer in the front side dielectric layer(s) 122 of thebase chip 102. ThePGS 194 can assist in shielding environmental effects from the intermediate chip(s) 104 and/ordistal chip 108. In such examples, thePGS 194 is inserted between (i) theinductor 190 and (ii) the intermediate chips 104 and thedistal chip 108. In some examples, thePGS 194 is disposed in the top metallization layer in thebase chip 102 so the distance between theinductor 190 and thePGS 194 is maximized within thebase chip 102 to minimize parasitic capacitance. For example, thePGS 194 is disposed in the topmost metallization layer in the front side dielectric layer(s) 122 of thebase chip 102 while theinductor 190 is disposed in the backside dielectric layer(s) 132 of thebase chip 102. - The
PGS 194 can be disposed in any chip of themulti-chip device 100, and theisolation wall 192 can extend through any number of front side dielectric layers, backside dielectric layers, and TSVs to reach thePGS 194. ThePGS 194 is described in further detail with reference toFIGS. 2A and 2B . - Where intermediate chips 104 are bonded front side to backside, the
isolation wall 192 can be electrically connected and extend through the backside TSVs 164 and bond pads bonded between thebase chip 102 and intermediate chips 104. Theinductor 190 can be disposed in the front side or the backside dielectric layers of a chip depending on the circuit requirement. Theinductor 190 and the other circuits are electrically connected through interconnect metals on the same chip or throughbackside TSVs - The
backside TSVs base chip 102, and can reduce the parasitic resistance of theisolation wall 192, which also benefits from the higher density BTSV of a thinner semiconductor substrate. - In some examples, the electrical grounds for each chip of the
multi-chip device 100 can be electrically connected together through controlled collapse chip connection (C4) bumps at a package level in the stacked IC environment. The electrically connected grounds can form various returning paths, which can be different based on the surrounding environments. These various returning paths can modulate the inductor characteristics. The metallization of the intermediate chip 104 underneath the inductor can act as a conducting mirror, which can terminate the magnetic field and cause dramatic degradation on inductor Q-factor. - Accordingly, the multi-chip device with an isolation wall as described herein can be optimized to achieve the highest device performance within a given chip area and metal scheme with a desired inductance value. In some examples, the C4 bump geometry in packaging is also considered so that the inductor and the isolation wall can fit in the empty area between C4 bumps to minimize the impact from the bumps.
- In some examples, the distance between the inductor and the semiconductor substrate of a chip is shorter compared to the distance in a single (i.e., monolithic) chip. In some examples, loss caused by a highly doped semiconductor substrate can significantly degrade inductor performance. Accordingly, in some examples, a region of the semiconductor substrate vertically corresponding with the location of the inductor 190 (e.g., surrounded by the TSVs of the isolation wall 192) can comprise or be a highly resistive semiconductor material, such as an intrinsic semiconductor material, like intrinsic silicon. In another example, the semiconductor substrate can have a certain thickness to reduce substrate loss. In some examples, the thickness of the
semiconductor substrate 112 of thebase chip 102 is less than or equal to 2.7 um. -
FIGS. 2A and 2B illustrate anisolation wall 192 around aPGS 194 and aninductor 190, according to some examples. As described withFIG. 1 , theisolation wall 192 is formed in the backside dielectric layer(s) 132 of thebase chip 102 and throughbackside TSVs 162, and is designed to isolate theinductor 190 from the environmental effects and to maintain the quality factor (Q-factor) of the inductor. -
FIG. 2A is a top view of a PGS and isolation wall. As mentioned, aPGS 194 associated with the inductor enables shielding and enhances the Q-factor of theinductor 190. In some examples, thePGS 194 may include groups of parallel,conductive fingers 214, and may be coupled together at the outer perimeter. Thesefingers 214 can be constructed to be perpendicular to the current direction of theinductor 190 to minimize eddy current and reduce magnetic loss. ThePGS 194 and theisolation wall 192 may isolate the electrical field generated by current flow through devices disposed over the PGS 194 (e.g., inductor 190) from devices in a region disposed between thePGS 194 and thesemiconductor substrate 112. - The
PGS 194 can be shaped as an octagon to match the shape of the coil portion of theinductor 190. Theisolation wall 192 extends up from thePGS 194, and in some examples, theisolation wall 192 can surround thePGS 194. In some examples, theisolation wall 192 includes a portion adjacent to legs of a transformer (shown inFIG. 2B ). - In some examples, by implementing the
PGS 194 in a metal layer adjacent to a top-most metal layer of the front side dielectric layer(s) 122 of thebase chip 102, more distance between thePGS 194 and theinductor 190 may be achieved to improve circuit performance. ThePGS 194 can be formed from conductive materials such as aluminum, copper, aluminum/silicon/copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, other suitable conductive materials, or combinations thereof. -
FIG. 2B illustrates a top view of theisolation wall 192 around aninductor 190, which in this example is in a transformer (e.g., which includes two inductors). In other examples, theinductor 190 can be merely an inductor, and a person having ordinary skill in the art will readily understand such a structure, particularly in view ofFIG. 2B . In some examples, the transformer includes an outer inductor L1 and an inner inductor L0. Inner inductor L0 is placed inside the outer inductor L1. Each of the inductors L0, L1 can be formed in multiple metal layers in series or in parallel. -
Transformer legs transformer legs base chip 102. Thetransformer legs base chip 102, and to metal layers of other chips, throughbackside TSVs 162. Overlapping portions of the coil portions of the inductors L0, L1 in different metal layers are connected by vias along the length of the portion of the coil to provide larger coils to increase inductance. One or ordinary skill in the art would understand how to design a transformer to be formed with the multi-chip device of FIG. -
FIG. 3 illustrates the effect on transformer performance in inductor Q-factor for different frequencies based on different thicknesses ofsemiconductor substrate 112 according to some examples.FIG. 3 illustrates the effects based on three different semiconductor substrate thicknesses for semiconductor substrate 112: 2.7 μm (302), 10 μm (304), and 100 μm (306). As illustrated, a thinner substrate thickness shows smaller degradation to inductor Q-factor and accordingly inductor performance, as frequency increases. A thinner substrate thickness also allows for more BTSVs, which in turn can benefit in lower resistive paths for power and signal integrity. -
FIGS. 4A and 4B respectively illustrate inductance characteristics with and without the isolation wall in order to simulate shielding against the 3D environmental effects of vertically stacked chips in the stacked IC environment.FIG. 4A-4B also show the inductance characteristics of three different thicknesses of semiconductor substrate 112: 2.7 μm (402), 10 μm (402), and 100 μm (406). As shown byFIG. 4A , without the isolation wall, inductance of the inductor can vary dramatically in stacked ICs because different return paths are formed in different stacked IC environments. As shown inFIG. 4B , with the isolation wall, the inductance of the inductor becomes more stable and predictable in the stacked IC environment. -
FIGS. 5A and 5B respectively illustrate the Q-factor characteristics with and without the isolation wall.FIG. 5A-5B also show the inductance characteristics of three different thicknesses of semiconductor substrate 112: 2.7 μm (502), 10 μm (504), and 100 μm (506). As shown byFIG. 5A , without the isolation wall, the Q-factor of the inductor changes differently based on the semiconductor substrate thicknesses. As shown byFIG. 5B , with the isolation wall, the Q-factor of the inductor stabilizes between the semiconductor substrate thicknesses in the stacked IC environment. - Accordingly, the multi-chip device including the isolation wall can demonstrate device performance metrics to meet VCO design requirements in an active 3D stacking environment.
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FIG. 6 is a flowchart of amethod 600 of forming the multi-chip device ofFIG. 1 according to some examples. The processing of themethod 600 ofFIG. 6 is generally described, and a person having ordinary skill in the art will readily understand the more specific processing that can be performed. The more specific processing can be according to any semiconductor processing for forming an IC on substrate, which is to be singulated into a chip. For ease of description herein, a wafer on which one ormore base chips 102 are formed is referred to as a base wafer; a wafer on which one or more intermediate chips 104 are formed is referred to as an intermediate wafer; and a wafer on which one or more distal chips are formed is referred to as a distal wafer. Any wafer can be any shape and/or size. - Referring to
FIG. 6 , atblock 602, front side processing for chips on the respective wafers is performed. For example, front side processing of eachsemiconductor substrate transistors semiconductor substrate side bond pads semiconductor substrate Multiple base chips 102 can be formed on a base wafer. Multiple intermediate chips 104 can be formed on a plurality of intermediate wafers. Multipledistal chips 108 can be formed on a distal wafer. - In some examples, front side processing of a base wafer includes forming at least a portion of an isolation wall (e.g., isolation wall 192) in the front side dielectric layer(s) with metallization. Front side processing of the base wafer can also include forming a PGS (e.g., PGS 194) in the front side dielectric layer(s) with metallization.
- At
block 604, a base wafer is bonded to a first intermediate wafer, such as front side to front side bonding as shown inFIG. 1 . As a result of the bonding, a front side of abase chip 102 is bonded to a front side of anintermediate chip 104 a, as shown inFIG. 1 . The bonding can be hybrid bonding, such as bonding frontside bond pads 152 on the base wafer to frontside bond pads 154 a on the first intermediate wafer, and bonding the exterior surface of the front side dielectric layer(s) 122 on the base wafer to the exterior surface of the front side dielectric layer(s) 124 a on the first intermediate wafer. - At
block 606, the semiconductor substrate of the first intermediate wafer is thinned from a backside of the first intermediate wafer. As shown inFIG. 1 , thesemiconductor substrate 114 a of theintermediate chip 104 a is thinned from the backside. The thinning can be by a chemical mechanical polish (CMP) or other appropriate process. - At
block 608, backside processing for intermediate chips on the first intermediate wafer is performed. As illustrated byFIG. 1 , the backside processing can include formingbackside TSVs 164 a through thesemiconductor substrate 114 a of the first intermediate wafer and connecting to metallization in the front side dielectric layer(s) 124 a on the first intermediate wafer. The backside processing can further include forming backside dielectric layer(s) 134 a with metallization andbackside bond pads 174 a on the backside of thesemiconductor substrate 114 a. The metallization in the backside dielectric layer(s) 134 a can be connected to the metallization in the front side dielectric layer(s) 124 a through thebackside TSVs 164 a. - At
block 610, the first intermediate wafer is bonded to a second intermediate wafer, such as backside to front side bonding as shown inFIG. 1 . As a result of the bonding, a backside of anintermediate chip 104 a is bonded to a front side of anintermediate chip 104 b, as shown inFIG. 1 . The bonding can be hybrid bonding, such as bondingbackside bond pads 174 a on the first intermediate wafer to frontside bond pads 154 b on the second intermediate wafer, and bonding the exterior surface of the backside dielectric layer(s) 134 a on the first intermediate wafer to the exterior surface of the front side dielectric layer(s) 124 b on the second intermediate wafer. - At
block 612, the semiconductor substrate of the second intermediate wafer is thinned from a backside of the second intermediate wafer, like described with respect to block 606. As show inFIG. 1 , thesemiconductor substrate 114 b of theintermediate chip 104 b is thinned from the backside. - At
block 614, backside processing for intermediate chips on the second intermediate wafer is performed, like described with respect to block 608. As illustrated byFIG. 1 , the backside processing can include formingbackside TSVs 164 b through thesemiconductor substrate 114 b of the second intermediate wafer and connecting to metallization in the front side dielectric layer(s) 124 b on the second intermediate wafer. The backside processing can further include forming backside dielectric layer(s) 134 b with metallization andbackside bond pads 174 b on the backside of thesemiconductor substrate 114 b. The metallization in the backside dielectric layer(s) 134 b can be connected to the metallization in the front side dielectric layer(s) 124 b through thebackside TSVs 164 b. - At
block 616, the second intermediate wafer is bonded to a third intermediate wafer, such as backside to front side bonding as shown inFIG. 1 . As a result of the bonding, a backside of anintermediate chip 104 b is bonded to the front side of anintermediate chip 104 c, as shown inFIG. 1 . The bonding can be hybrid bonding, such as bondingbackside bond pads 174 b on the second intermediate wafer to frontside bond pads 154 c on the second intermediate wafer, and bonding the exterior surface of the backside dielectric layer(s) 134 b on the second intermediate wafer to the exterior surface of the front side dielectric layer(s) 124 c on the third intermediate wafer. - At
block 618, the semiconductor substrate of the third intermediate wafer is thinned from a backside of the third intermediate wafer, like described with respect to block 606. As shown inFIG. 1 , thesemiconductor substrate 114 c of theintermediate chip 104 c is thinned from the backside. - At
block 620, backside processing for intermediate chips on the third intermediate wafer is performed, like described with respect to block 608. As illustrated byFIG. 1 , the backside processing can include formingbackside TSVs 164 c through thesemiconductor substrate 114 c of the third intermediate wafer and connecting to metallization in the front side dielectric layer(s) 124 c on the third intermediate wafer. The backside processing can further include forming backside dielectric layer(s) 134 c with metallization andbackside bond pads 174 c on the backside of thesemiconductor substrate 114 c. The metallization in the backside dielectric layer(s) 134 c can be connected to the metallization in the front side dielectric layer(s) 124 c through thebackside TSVs 164 c. - At
block 622, the third intermediate wafer is bonded to a distal wafer, such as backside to front side bonding as shown inFIG. 1 . As a result of the bonding, a backside of anintermediate chip 104 c is bonded to a front side of adistal chip 108, as shown inFIG. 1 . The bonding can be hybrid bonding, such as bondingbackside bond pads 174 c on the third intermediate wafer to frontside bond pads 158 on the distal wafer, and bonding the exterior surface of the backside dielectric layer(s) 134 c on the third intermediate wafer to the exterior surface of the front side dielectric layer(s) 128 on the distal wafer. - At
block 624, the semiconductor substrate of the base wafer is thinned from a backside of the base wafer, like described with respect to block 606. As shown inFIG. 1 , thesemiconductor substrate 112 of thebase chip 102 is thinned from the backside. - At
block 626, backside processing for base chips on the base wafer is performed, like described with respect to block 608. As illustrated byFIG. 1 , the backside processing can include formingbackside TSVs 162 through thesemiconductor substrate 112 of the base wafer and connecting to metallization in the front side dielectric layer(s) 122 on the base wafer. The backside processing can further include forming backside dielectric layer(s) 132 with metallization and exteriorconnector backside pads 172 on the backside of thesemiconductor substrate 112. The metallization in the backside dielectric layer(s) 132 can be connected to the metallization in the front side dielectric layer(s) 122 through thebackside TSVs 162. The backside processing for the base chips 102 can further include forming thepassivation layer 180 andexternal connectors 182. Backside processing of the base chip can include forming an inductor (e.g., inductor 190) and at least a portion of an isolation wall (e.g., isolation wall 192). - At
block 628, the bonded wafers are singulated (e.g., by sawing) to separate individual multi-chip devices that have been formed. Each of the multi-chip devices can be as shown inFIG. 1 . - While the foregoing is directed to specific examples, other and further examples may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (20)
1. A multi-chip device comprising:
a chip stack comprising a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate and a front side dielectric layer on a front side of the semiconductor substrate;
an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer of the first chip being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and
an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer of the first chip, the isolation wall comprising a through substrate via (TSV) through the semiconductor substrate of the first chip, the isolation wall being disposed around the inductor.
2. The multi-chip device of claim 1 , wherein the front side dielectric layer is an outermost dielectric layer in which metallization is disposed.
3. The multi-chip device of claim 1 , wherein the first chip is an input/output (I/O) chip.
4. The multi-chip device of claim 1 , wherein the semiconductor substrate comprises intrinsic silicon in a region of the semiconductor substrate corresponding with a position of the inductor.
5. The multi-chip device of claim 1 , wherein the semiconductor substrate of the first chip has a thickness less than or equal to 2.7 um.
6. The multi-chip device of claim 1 , wherein at least one of the plurality of chips comprises a processing integrated circuit.
7. The multi-chip device of claim 1 , further comprising a pattern ground shield (PGS) disposed in the front side dielectric layer of the first chip, wherein the isolation wall surrounds and is electrically connected to the PGS.
8. The multi-chip device of claim 1 , wherein the isolation wall further extends into a second chip bonded to the first chip.
9. The multi-chip device of claim 1 , wherein at least one chip of the plurality of chips further comprises:
one or more front side metallization layers disposed in the front side dielectric layer, the one or more front side metallization layers comprising a top metallization layer disposed distal from the semiconductor substrate of the respective chip; and
one or more backside metallization layers disposed in the backside dielectric layer, the one or more backside metallization layers comprising a bottom metallization layer disposed distal from the semiconductor substrate of the respective chip.
10. The multi-chip device of claim 1 , wherein the isolation wall extends through more than one of the plurality of chips.
11. A method for constructing a multi-chip device, the method comprising:
forming a stack of a plurality of chips comprising forming the plurality of chips, each chip comprising a semiconductor substrate and a front side dielectric layer on a front side of the semiconductor substrate, wherein forming a first chip of the plurality of chips includes:
forming an inductor disposed in a backside dielectric layer of the first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side; and
forming an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer of the first chip, the isolation wall comprising a through-substrate via (TSV) through the semiconductor substrate of the first chip, the isolation wall being disposed around the inductor.
12. The method of claim 11 , wherein the front side dielectric layer of the first chip is an outermost dielectric layer in which metallization is disposed.
13. The method of claim 11 , wherein the semiconductor substrate comprises intrinsic silicon in a region of the semiconductor substrate corresponding with a position of the inductor.
14. The method of claim 11 , wherein the semiconductor substrate has a thickness of less than or equal to 2.7 um.
15. The method of claim 11 , wherein the plurality of chips comprise Active-on-Active (AoA) chips.
16. The method of claim 11 , further comprising forming a pattern ground shield (PGS) disposed in the front side dielectric layer of the first chip, wherein the isolation wall surrounds and is electrically connected to the PGS.
17. The method of claim 11 , wherein the isolation wall further extends into a second chip bonded to the first chip.
18. The method of claim 11 , wherein the isolation wall extends through more than one of the plurality of chips.
19. A multi-chip device comprising:
a chip stack;
an inductor disposed in a backside dielectric layer of a first chip of the chip stack; and
an isolation wall extending from the backside dielectric layer of the first chip to a front side dielectric layer of the first chip, the isolation wall being disposed around the inductor.
20. The multi-chip device of claim 19 , further comprising a pattern ground shield (PGS) disposed in the front side dielectric layer of the first chip, wherein the isolation wall surrounds and is electrically connected to the PGS.
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US16/694,476 US11043470B2 (en) | 2019-11-25 | 2019-11-25 | Inductor design in active 3D stacking technology |
PCT/US2020/054891 WO2021108037A1 (en) | 2019-11-25 | 2020-10-09 | Inductor design in active 3d stacking technology |
KR1020227017951A KR20220106136A (en) | 2019-11-25 | 2020-10-09 | Inductor Design in Active 3D Stacking Technology |
JP2022530308A JP2023503150A (en) | 2019-11-25 | 2020-10-09 | Inductor design in active 3D stacking technology |
CN202080081181.9A CN114730754A (en) | 2019-11-25 | 2020-10-09 | Inductor design in active 3D stacking technology |
EP20800413.5A EP4066281A1 (en) | 2019-11-25 | 2020-10-09 | Inductor design in active 3d stacking technology |
TW109135716A TW202121640A (en) | 2019-11-25 | 2020-10-15 | Inductor design in active 3d stacking technology |
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US16/694,476 US11043470B2 (en) | 2019-11-25 | 2019-11-25 | Inductor design in active 3D stacking technology |
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US20220270973A1 (en) * | 2021-02-22 | 2022-08-25 | United Microelectronics Corp. | Bonded semiconductor structure and method for forming the same |
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US20220189921A1 (en) * | 2020-12-14 | 2022-06-16 | Advanced Micro Devices, Inc. | Stacked die circuit routing system and method |
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US20220270973A1 (en) * | 2021-02-22 | 2022-08-25 | United Microelectronics Corp. | Bonded semiconductor structure and method for forming the same |
US20220320044A1 (en) * | 2021-03-31 | 2022-10-06 | Taiwan Semiconductor Manufacturing Company Limited | Bonded wafer device structure and methods for making the same |
US11621248B2 (en) * | 2021-03-31 | 2023-04-04 | Taiwan Semiconductor Manufacturing Company Limited | Bonded wafer device structure and methods for making the same |
US11961826B2 (en) * | 2021-03-31 | 2024-04-16 | Taiwan Semiconductor Manufacturing Company Limited | Bonded wafer device structure and methods for making the same |
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CN114730754A (en) | 2022-07-08 |
KR20220106136A (en) | 2022-07-28 |
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EP4066281A1 (en) | 2022-10-05 |
JP2023503150A (en) | 2023-01-26 |
US11043470B2 (en) | 2021-06-22 |
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