US20210124117A1 - Waveguide crossings having arms shaped with a non-linear curvature - Google Patents
Waveguide crossings having arms shaped with a non-linear curvature Download PDFInfo
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- US20210124117A1 US20210124117A1 US16/663,696 US201916663696A US2021124117A1 US 20210124117 A1 US20210124117 A1 US 20210124117A1 US 201916663696 A US201916663696 A US 201916663696A US 2021124117 A1 US2021124117 A1 US 2021124117A1
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
- G02B6/125—Bends, branchings or intersections
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/12002—Three-dimensional structures
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
- G02B6/1228—Tapered waveguides, e.g. integrated spot-size transformers
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12035—Materials
- G02B2006/12061—Silicon
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12083—Constructional arrangements
- G02B2006/12097—Ridge, rib or the like
Definitions
- the present invention relates to photonics chips and, more specifically, to structures for a waveguide crossing and methods of fabricating a structure for a waveguide crossing.
- Photonics chips are used in many applications and systems including, but not limited to, data communication systems and data computation systems.
- a photonics chip integrates optical components, such as waveguides, optical switches, directional couplers, and bends, and electronic components, such as field-effect transistors, into a unified platform.
- layout area, cost, and operational overhead may be reduced by the integration of both types of components on the same chip.
- a waveguide crossing is building block used in photonics chips to provide paths for propagating optical signals.
- a waveguide crossing is an optical element in which two waveguide cores in a single layer intersect and directly cross.
- An ideal waveguide crossing may be designed with measures to provide high transmission in each straight path and low crosstalk to the corresponding crossing path.
- waveguide cores may unwantedly exhibit high insertion loss and high cross-talk.
- waveguide crossings possess large footprints that may hamper dense integration in a photonics chip.
- a structure in an embodiment of the invention, includes a waveguide crossing including a central section and an arm positioned between a waveguide core and the central section.
- the arm and the waveguide core are aligned along a longitudinal axis.
- the arm is coupled to the waveguide core at a first interface, and the arm is coupled to a portion of the central section at a second interface.
- the arm has a first width at the first interface, a second width at the second interface, and a third width between the first interface and the second interface.
- the third width is greater than the first width, and the third width greater than the second width.
- a structure in an embodiment of the invention, includes a first waveguide crossing having a first central section and a first plurality of arms connected to the first central section.
- the structure further includes a second waveguide crossing positioned over the first waveguide crossing.
- the second waveguide crossing includes a second central section and a second plurality of arms connected to the second central section.
- the first waveguide crossing is comprised of a first material
- the second waveguide crossing is comprised of a second material that is different in composition from the first material.
- a method includes patterning a layer of material to define a waveguide core and a waveguide crossing that includes a central section and an arm positioned between the waveguide core and the central section.
- the arm and the waveguide core are aligned along a longitudinal axis.
- the arm is coupled to the waveguide core at a first interface, and the arm is coupled to a portion of the central section at a second interface.
- the arm has a first width at the first interface, a second width at the second interface, and a third width between the first interface and the second interface.
- the third width is greater than the first width, and the third width is greater than the second width.
- FIG. 1 is a diagrammatic top view of a structure at an initial fabrication stage of a processing method in accordance with embodiments of the invention.
- FIG. 2 is an enlarged view of a portion of FIG. 1 .
- FIG. 3 is a cross-sectional view taken generally along line 3 - 3 in FIG. 1 .
- FIG. 4 is a cross-sectional view of the structure at a fabrication stage of the processing method subsequent to FIG. 3 .
- FIGS. 5-7 are cross-sectional views of structures in accordance with alternative embodiments of the invention.
- FIG. 8 is a cross-sectional view of a structure in accordance with alternative embodiments of the invention.
- FIG. 8A is a top view of a structure in which FIG. 8 is taken generally along line 8 - 8 and in which layers are omitted for purposes of clarity of description.
- FIG. 9 is a cross-sectional view of a structure in accordance with alternative embodiments of the invention.
- a structure 10 includes a waveguide crossing 12 , a waveguide core 14 and a waveguide core 16 that are coupled to respective arms 22 , 24 of the waveguide crossing 12 to respectively provide an input port and a through port, and a waveguide core 18 and a waveguide core 20 that are coupled to respective arms 26 , 28 of the waveguide crossing 12 to provide a cross port.
- the waveguide crossing 12 includes a central section 30 providing a junction that is arranged between the arms 22 , 24 of the waveguide crossing 12 along the longitudinal axis 15 , and also arranged between the arms 26 , 28 of the waveguide crossing 12 along the longitudinal axis 19 .
- Each of the arms 22 , 24 , 26 , 28 is coupled to a different portion of the central section 30 .
- the waveguide cores 14 , 16 and the arms 22 , 24 of the waveguide crossing 12 are aligned along a longitudinal axis 15
- the waveguide cores 18 , 20 and the arms 26 , 28 of the waveguide crossing 12 are aligned along a longitudinal axis 19 that is oriented transverse to the longitudinal axis 15 of the waveguide cores 14 , 16 .
- the longitudinal axes 15 , 19 may be oriented orthogonal to each other.
- the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 may be composed of single-crystal semiconductor material (e.g., single-crystal silicon).
- the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 may be formed by patterning a device layer of a silicon-on-insulator (SOI) wafer with lithography and etching processes that form an etch mask over the device layer and etch the masked device layer with an etching process, such as reactive ion etching (ME), in which the buried insulator layer 32 functions as an etch stop.
- SOI silicon-on-insulator
- the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 may be arranged on a buried insulator layer 32 of the SOI wafer.
- the buried insulator layer 32 may be composed of a dielectric material, such as silicon dioxide, and buried insulator layer 32 is arranged over a substrate 34 that may contain single-crystal semiconductor material (e.g., single-crystal silicon).
- the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 may have a ridge construction.
- the buried insulator layer 32 may operate as a lower cladding providing confinement for the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 of the structure 10 .
- Each of the arms 22 , 24 , 26 , 28 may have shapes with curvatures that are identical or substantially identical with respect to the central section 30 other than orientation along the respective longitudinal axis 15 , 19 .
- the arms 22 , 24 , 26 , 28 are subsequently discussed in connection with the arm 22 with an understanding that the subsequent discussion applies equally to the arms 24 , 26 , 28 .
- the arm 22 has an interface 36 with the waveguide core 14 defining an input to the arm 22 , and the arm 22 has an interface 38 with the central section 30 defining an output from the arm 22 .
- the arm 22 has a width, W1, at the interface 36 with the waveguide core 14 , a width, W2, at the interface 38 with the central section 30 , and a maximum width, Wmax, that is located along the longitudinal axis 15 between the interface 36 and the interface 38 .
- the location of the maximum width between the interfaces 36 , 38 differs from a conventional taper or inverse taper in which the maximum width occurs at either the beginning or end of the taper.
- the maximum width, Wmax is greater than the width, W1, at the interface 36 with the waveguide core 14 and the width, W2, at the interface 38 with the central section 30 .
- the central section 30 is square in shape with the width of each side equal to the width, W2.
- the arm 22 extends along a total length, L, along the longitudinal axis 15 between the interface 36 and the interface 38 .
- the arm 22 has a section positioned between the interface 36 and the location of the maximum width, Wmax.
- the total length, L is divided into a length, L1, of the section positioned between the location of the maximum width, Wmax, and the interface 36 and a length, L2, of the section positioned between the location of the maximum width, Wmax, and the interface 38 .
- the location of the maximum width, Wmax is asymmetrically positioned between the interface 36 and the interface 38 .
- the width, W1, at the interface 36 with the waveguide core 14 is less than the width, W2, at the interface 38 with the central section 30 , then the value of the length, L1 is greater than the value of the length, L2, such that the location of the maximum width, Wmax, is closer to the interface 38 with the central section 30 than to the interface 36 with the waveguide core 14 .
- the location of the maximum width, Wmax may be symmetrically positioned between the interface 36 and the interface 38 .
- the shape of the arm 22 has an envelope at its side surfaces 23 with a curvature at each of its side surfaces 23 that may be described by a non-linear function.
- the shape of the arm 22 has an envelope at its side surfaces 23 with a curvature at each of its side surfaces 23 that may be described by a cosine function.
- values may be calculated for the lengths L1 and L2 of the different sections of the arm 22 .
- the length, L1 is dependent on a ratio of the width, W1, to the width, Wmax, and the length, L2, is dependent on a ratio of the width, W2, to the width, Wmax.
- the absolute value of L1 is equal to (2L0/ ⁇ ) ⁇ arccos (W1/Wmax)
- the absolute value of L2 is equal to (2L0/ ⁇ ) ⁇ arccos (W2/Wmax).
- the total length, Ltotal, of the waveguide crossing 12 along the set of arms 22 , 24 between the interface 36 of the arm 22 with the waveguide core 14 and the interface 36 of the arm 24 with the waveguide core 16 is equal to (2 ⁇ L)+W2.
- the total length of the waveguide crossing 12 along the set of arms 26 , 28 between the interface 36 of the arm 26 with the waveguide core 18 and the interface 36 of the arm 28 with the waveguide core 20 is also equal to (2 ⁇ L)+W2. Consequently, the waveguide crossing 12 has a rotational symmetry of the order four (4).
- the waveguide crossing 12 has a compact footprint due to the non-linear curved shapes of the arms 22 , 24 , 26 , 28 .
- the waveguide crossing 12 may be characterized by low insertion loss, low cross-talk, low reflection, and low wavelength dependency also due to the non-linear curved shapes of the arms 22 , 24 , 26 , 28 .
- the waveguide crossing 12 may be optimized for the O-band (1260 nm to 1360 nm) and may be optimized for transmitting optical signals with transverse electric (TE) polarization.
- dielectric layers 40 , 42 , 44 , 46 composed of respective dielectric materials are sequentially formed in a layer stack over the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 .
- the dielectric layer 40 is arranged over the buried insulator layer 32
- the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 the dielectric layer 42 is arranged over the dielectric layer 40
- the dielectric layer 44 is arranged over the dielectric layer 42
- the dielectric layer 46 is arranged over the dielectric layer 44 .
- the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 are embedded or buried in the dielectric material of the dielectric layer 40 , which acts as lateral cladding.
- the dielectric layer 40 may be composed of a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition and planarized with, for example, chemical mechanical polishing to remove topography.
- the dielectric layer 42 may be composed of dielectric material, such as silicon dioxide, deposited by chemical vapor deposition or atomic layer deposition over the dielectric layer 40 .
- the dielectric layer 44 may be composed of dielectric material, such as silicon nitride, deposited by chemical vapor deposition or atomic layer deposition over the dielectric layer 42 .
- the dielectric layer 46 may be composed of dielectric material, such as silicon dioxide, deposited by chemical vapor deposition or atomic layer deposition over the dielectric layer 44 .
- the dielectric layers 42 , 44 , 46 may be planar layers arranged in the layer stack over the planarized top surface of the dielectric layer 40 .
- a dielectric layer 48 of a contact level is formed by middle-of-line processing over the dielectric layer 46 .
- the dielectric layer 48 may be composed of dielectric material, such as silicon dioxide, deposited by chemical vapor deposition using ozone and tetraethylorthosilicate (TEOS) as reactants.
- TEOS tetraethylorthosilicate
- a back-end-of-line stack is formed by back-end-of-line processing over the dielectric layer 48 and the structure 10 .
- the back-end-of-line stack 50 may include one or more interlayer dielectric layers composed of one or more dielectric materials, such as a carbon-doped silicon oxide, and metallization composed of, for example, copper, tungsten, and/or cobalt that is arranged in the one or more interlayer dielectric layers.
- the structure 10 in any of its embodiments described herein, may be integrated into a photonics chip 60 ( FIG. 1 ) that may include electronic components 52 and optical components 54 in addition to the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 .
- the electronic components 52 may include, for example, field-effect transistors that are fabricated by CMOS front-end-of-line (FEOL) processing using the device layer of the SOI wafer.
- FEOL front-end-of-line
- the device layer may be partially etched adjacent to sidewalls of the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 during patterning to define a slab layer 56 .
- the slab layer 56 which is in direct contact with the buried insulator layer 32 , is coupled to the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 .
- the slab layer 56 is thinner than the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 , which are masked during the patterning forming the slab layer 56 .
- the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 may have a rib construction due to the addition of the slab layer 56 .
- the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 may be composed of a different material and may be located over the dielectric layer 46 and embedded in dielectric layer 48 .
- the waveguide crossing 12 may be composed of a dielectric material, such as silicon nitride.
- the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 may be formed by depositing a layer of the dielectric material on the dielectric layer 46 , and then patterning the deposited layer with lithography and etching processes that lithographically form an etch mask over the deposited layer and etch the masked deposited layer with an etching process, such as reactive ion etching (RIE).
- RIE reactive ion etching
- the deposited layer may be partially etched adjacent to sidewalls of the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 during patterning to define a slab layer 58 .
- the slab layer 58 which is in direct contact with the dielectric layer 46 , is coupled to the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 .
- the slab layer 58 is thinner than the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 , which are masked during patterning.
- the waveguide crossing 12 and the waveguide cores 14 , 16 , 18 , 20 may have a rib construction due to the addition of the slab layer 58 .
- the structure 10 may further include a waveguide crossing 66 that is disposed over the waveguide crossing 12 .
- the arms 68 of the waveguide crossing 66 may be located in a vertical direction over (i.e., above in the y-direction) the arms 22 , 24 , 26 , 28 of the waveguide crossing 12 in a stacked relationship.
- the arms 68 of the waveguide crossing 66 may have the same shape as the arms 22 , 24 , 26 , 28 of the waveguide crossing 12 with interfaces similar to interfaces 36 , 38 , as well as a central section 70 that is similar to central section 30 of the waveguide crossing 12 .
- the arms 68 of the waveguide crossing 66 may terminate at respective ends 72 that are analogous to the interfaces 36 of the arms 22 , 24 , 26 , 28 of the waveguide crossing 12 and each ends 72 may terminate over one of the arms 22 , 24 , 26 , 28 of the waveguide crossing 12 .
- the waveguide crossing 66 may be composed of a material having a different composition than the material from which the waveguide crossing 12 is composed.
- the arms 68 of the waveguide crossing 66 may be composed of a dielectric material, such as silicon nitride, and the arms of the waveguide crossing 12 may be composed of a single-crystal semiconductor material, such as single-crystal silicon.
- the arms 68 of the waveguide crossing 66 may be composed of a polycrystalline semiconductor material (e.g., polycrystalline silicon), and the arms of the waveguide crossing 12 may be composed of a single-crystal semiconductor material, such as single-crystal silicon.
- the waveguide crossing 12 and the waveguide crossing 66 are composed of respective materials of different composition and define a bilayer or multiple-layer stack of the different materials.
- the addition of the waveguide crossing 66 over the waveguide crossing 12 may function to improve the performance of the waveguide crossing 12 .
- insertion loss may be reduced by the addition of the waveguide crossing 66 over the waveguide crossing 12 .
- the waveguide crossing 66 of FIG. 8 may be arranged over the waveguide crossing 12 of FIG. 6 or FIG. 7 . In alternative embodiments, the waveguide crossing 66 of FIG. 8 may be arranged beneath the waveguide crossing 12 of FIG. 6 or FIG. 7 . In alternative embodiments, the waveguide crossing 66 of FIG. 8 may be arranged beneath the waveguide crossing 12 of FIG. 6 or FIG. 7 , and the waveguide crossing 66 may be composed of a single-crystal semiconductor material, such as single-crystal silicon. In alternative embodiments, one or more waveguide crossings 66 may be arranged above and beneath the waveguide crossing 12 of FIG. 6 or FIG. 7 .
- the waveguide crossing 66 of FIG. 8 may be arranged over the waveguide crossing 66 of FIG. 9 such that both waveguide crossings 66 are arranged over the waveguide crossing 12 of FIG. 4 or FIG. 5 .
- an additional waveguide crossing (not shown) may be formed from the single-crystal semiconductor material of the device layer and may be arranged beneath the waveguide crossing 12 of FIG. 6 or FIG. 7 in addition to the waveguide crossing 66 of FIG. 8 to provide a three-layer layer stack.
- the waveguide crossing 66 of FIG. 8 and the waveguide crossing 66 of FIG. 9 may be added to the waveguide crossing 12 of FIG. 6 or FIG. 7 to provide a three-layer stack.
- the methods as described above are used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
- the end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
- references herein to terms modified by language of approximation such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified.
- the language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate +/ ⁇ 10% of the stated value(s).
- references herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference.
- the term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation.
- the terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined.
- the term “lateral” refers to a direction within the horizontal plane.
- a feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present.
- a feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent.
- a feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present.
- a feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present.
- a feature may be “directly on” or in “direct contact” with another feature if intervening features are absent.
- a feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present.
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Abstract
Description
- The present invention relates to photonics chips and, more specifically, to structures for a waveguide crossing and methods of fabricating a structure for a waveguide crossing.
- Photonics chips are used in many applications and systems including, but not limited to, data communication systems and data computation systems. A photonics chip integrates optical components, such as waveguides, optical switches, directional couplers, and bends, and electronic components, such as field-effect transistors, into a unified platform. Among other factors, layout area, cost, and operational overhead may be reduced by the integration of both types of components on the same chip.
- A waveguide crossing is building block used in photonics chips to provide paths for propagating optical signals. A waveguide crossing is an optical element in which two waveguide cores in a single layer intersect and directly cross. An ideal waveguide crossing may be designed with measures to provide high transmission in each straight path and low crosstalk to the corresponding crossing path. However, despite these measures, waveguide cores may unwantedly exhibit high insertion loss and high cross-talk. In addition, waveguide crossings possess large footprints that may hamper dense integration in a photonics chip.
- Improved structures for a waveguide crossing and methods of fabricating a structure for a waveguide crossing are needed.
- In an embodiment of the invention, a structure includes a waveguide crossing including a central section and an arm positioned between a waveguide core and the central section. The arm and the waveguide core are aligned along a longitudinal axis. The arm is coupled to the waveguide core at a first interface, and the arm is coupled to a portion of the central section at a second interface. The arm has a first width at the first interface, a second width at the second interface, and a third width between the first interface and the second interface. The third width is greater than the first width, and the third width greater than the second width.
- In an embodiment of the invention, a structure includes a first waveguide crossing having a first central section and a first plurality of arms connected to the first central section. The structure further includes a second waveguide crossing positioned over the first waveguide crossing. The second waveguide crossing includes a second central section and a second plurality of arms connected to the second central section. The first waveguide crossing is comprised of a first material, and the second waveguide crossing is comprised of a second material that is different in composition from the first material.
- In an embodiment of the invention, a method includes patterning a layer of material to define a waveguide core and a waveguide crossing that includes a central section and an arm positioned between the waveguide core and the central section. The arm and the waveguide core are aligned along a longitudinal axis. The arm is coupled to the waveguide core at a first interface, and the arm is coupled to a portion of the central section at a second interface. The arm has a first width at the first interface, a second width at the second interface, and a third width between the first interface and the second interface. The third width is greater than the first width, and the third width is greater than the second width.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.
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FIG. 1 is a diagrammatic top view of a structure at an initial fabrication stage of a processing method in accordance with embodiments of the invention. -
FIG. 2 is an enlarged view of a portion ofFIG. 1 . -
FIG. 3 is a cross-sectional view taken generally along line 3-3 inFIG. 1 . -
FIG. 4 is a cross-sectional view of the structure at a fabrication stage of the processing method subsequent toFIG. 3 . -
FIGS. 5-7 are cross-sectional views of structures in accordance with alternative embodiments of the invention. -
FIG. 8 is a cross-sectional view of a structure in accordance with alternative embodiments of the invention. -
FIG. 8A is a top view of a structure in whichFIG. 8 is taken generally along line 8-8 and in which layers are omitted for purposes of clarity of description. -
FIG. 9 is a cross-sectional view of a structure in accordance with alternative embodiments of the invention. - With reference to
FIGS. 1-3 and in accordance with embodiments of the invention, astructure 10 includes awaveguide crossing 12, awaveguide core 14 and awaveguide core 16 that are coupled torespective arms waveguide core 18 and awaveguide core 20 that are coupled torespective arms waveguide crossing 12 includes acentral section 30 providing a junction that is arranged between thearms longitudinal axis 15, and also arranged between thearms longitudinal axis 19. Each of thearms central section 30. Thewaveguide cores arms waveguide crossing 12 are aligned along alongitudinal axis 15, and thewaveguide cores arms waveguide crossing 12 are aligned along alongitudinal axis 19 that is oriented transverse to thelongitudinal axis 15 of thewaveguide cores longitudinal axes - The waveguide crossing 12 and the
waveguide cores waveguide cores insulator layer 32 functions as an etch stop. The waveguide crossing 12 and thewaveguide cores insulator layer 32 of the SOI wafer. The buriedinsulator layer 32 may be composed of a dielectric material, such as silicon dioxide, and buriedinsulator layer 32 is arranged over asubstrate 34 that may contain single-crystal semiconductor material (e.g., single-crystal silicon). The waveguide crossing 12 and thewaveguide cores insulator layer 32 may operate as a lower cladding providing confinement for the waveguide crossing 12 and thewaveguide cores structure 10. - Each of the
arms central section 30 other than orientation along the respectivelongitudinal axis arms arm 22 with an understanding that the subsequent discussion applies equally to thearms - The
arm 22 has aninterface 36 with thewaveguide core 14 defining an input to thearm 22, and thearm 22 has aninterface 38 with thecentral section 30 defining an output from thearm 22. Thearm 22 has a width, W1, at theinterface 36 with thewaveguide core 14, a width, W2, at theinterface 38 with thecentral section 30, and a maximum width, Wmax, that is located along thelongitudinal axis 15 between theinterface 36 and theinterface 38. The location of the maximum width between theinterfaces interface 36 with thewaveguide core 14 and the width, W2, at theinterface 38 with thecentral section 30. Thecentral section 30 is square in shape with the width of each side equal to the width, W2. - The
arm 22 extends along a total length, L, along thelongitudinal axis 15 between theinterface 36 and theinterface 38. Thearm 22 has a section positioned between theinterface 36 and the location of the maximum width, Wmax. The total length, L, is divided into a length, L1, of the section positioned between the location of the maximum width, Wmax, and theinterface 36 and a length, L2, of the section positioned between the location of the maximum width, Wmax, and theinterface 38. In an embodiment in which the width, W1, at theinterface 36 and the width, W2, at theinterface 38 are unequal, the location of the maximum width, Wmax, is asymmetrically positioned between theinterface 36 and theinterface 38. For example, if the width, W1, at theinterface 36 with thewaveguide core 14 is less than the width, W2, at theinterface 38 with thecentral section 30, then the value of the length, L1 is greater than the value of the length, L2, such that the location of the maximum width, Wmax, is closer to theinterface 38 with thecentral section 30 than to theinterface 36 with thewaveguide core 14. In an embodiment in which the width, W1, at theinterface 36 and the width, W2, at theinterface 38 are equal, the location of the maximum width, Wmax, may be symmetrically positioned between theinterface 36 and theinterface 38. - The shape of the
arm 22 has an envelope at itsside surfaces 23 with a curvature at each of itsside surfaces 23 that may be described by a non-linear function. In an embodiment, the shape of thearm 22 has an envelope at itsside surfaces 23 with a curvature at each of itsside surfaces 23 that may be described by a cosine function. Specifically, the width of the shape for thearm 22 as a function of position, x, along thelongitudinal axis 15 may be given by W(x)=Wmax·cos(πx/2L0) wherein L0 is the position along thelongitudinal axis 15 that the cosine curve converges at and crosses the longitudinal axis 15 (i.e., W=0). The maximum width, Wmax, of the curvature occurs at x=0. In an alternative embodiment, the width of the shape of thearm 22 as a function of position along thelongitudinal axis 15 may be described by a sine function W(x)=Wmax·sin(πx/2L) defining the curvature of the envelope. - Given a set of widths, W1, W2, Wmax, values may be calculated for the lengths L1 and L2 of the different sections of the
arm 22. The length, L1, is dependent on a ratio of the width, W1, to the width, Wmax, and the length, L2, is dependent on a ratio of the width, W2, to the width, Wmax. Specifically, the absolute value of L1 is equal to (2L0/π)·arccos (W1/Wmax), and the absolute value of L2 is equal to (2L0/π)·arccos (W2/Wmax). - The total length, Ltotal, of the waveguide crossing 12 along the set of
arms interface 36 of thearm 22 with thewaveguide core 14 and theinterface 36 of thearm 24 with thewaveguide core 16 is equal to (2·L)+W2. Similarly, the total length of the waveguide crossing 12 along the set ofarms interface 36 of thearm 26 with thewaveguide core 18 and theinterface 36 of thearm 28 with thewaveguide core 20 is also equal to (2·L)+W2. Consequently, the waveguide crossing 12 has a rotational symmetry of the order four (4). - The
waveguide crossing 12 has a compact footprint due to the non-linear curved shapes of thearms waveguide crossing 12 may be characterized by low insertion loss, low cross-talk, low reflection, and low wavelength dependency also due to the non-linear curved shapes of thearms waveguide crossing 12 may be optimized for the O-band (1260 nm to 1360 nm) and may be optimized for transmitting optical signals with transverse electric (TE) polarization. - With reference to
FIG. 4 in which like reference numerals refer to like features inFIG. 3 and at a subsequent fabrication stage,dielectric layers waveguide cores dielectric layer 40 is arranged over the buriedinsulator layer 32, the waveguide crossing 12 and thewaveguide cores dielectric layer 42 is arranged over thedielectric layer 40, thedielectric layer 44 is arranged over thedielectric layer 42, and thedielectric layer 46 is arranged over thedielectric layer 44. Thewaveguide crossing 12 and thewaveguide cores dielectric layer 40, which acts as lateral cladding. - The
dielectric layer 40 may be composed of a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition and planarized with, for example, chemical mechanical polishing to remove topography. Thedielectric layer 42 may be composed of dielectric material, such as silicon dioxide, deposited by chemical vapor deposition or atomic layer deposition over thedielectric layer 40. Thedielectric layer 44 may be composed of dielectric material, such as silicon nitride, deposited by chemical vapor deposition or atomic layer deposition over thedielectric layer 42. Thedielectric layer 46 may be composed of dielectric material, such as silicon dioxide, deposited by chemical vapor deposition or atomic layer deposition over thedielectric layer 44. The dielectric layers 42, 44, 46 may be planar layers arranged in the layer stack over the planarized top surface of thedielectric layer 40. - A
dielectric layer 48 of a contact level is formed by middle-of-line processing over thedielectric layer 46. Thedielectric layer 48 may be composed of dielectric material, such as silicon dioxide, deposited by chemical vapor deposition using ozone and tetraethylorthosilicate (TEOS) as reactants. - A back-end-of-line stack, generally indicated by
reference numeral 50, is formed by back-end-of-line processing over thedielectric layer 48 and thestructure 10. The back-end-of-line stack 50 may include one or more interlayer dielectric layers composed of one or more dielectric materials, such as a carbon-doped silicon oxide, and metallization composed of, for example, copper, tungsten, and/or cobalt that is arranged in the one or more interlayer dielectric layers. - The
structure 10, in any of its embodiments described herein, may be integrated into a photonics chip 60 (FIG. 1 ) that may includeelectronic components 52 andoptical components 54 in addition to the waveguide crossing 12 and thewaveguide cores electronic components 52 may include, for example, field-effect transistors that are fabricated by CMOS front-end-of-line (FEOL) processing using the device layer of the SOI wafer. - With reference to
FIG. 5 in which like reference numerals refer to like features inFIG. 2 and in accordance with alternative embodiments of the invention, the device layer may be partially etched adjacent to sidewalls of the waveguide crossing 12 and thewaveguide cores slab layer 56. Theslab layer 56, which is in direct contact with the buriedinsulator layer 32, is coupled to the waveguide crossing 12 and thewaveguide cores slab layer 56 is thinner than the waveguide crossing 12 and thewaveguide cores slab layer 56. Thewaveguide crossing 12 and thewaveguide cores slab layer 56. - With reference to
FIG. 6 and in accordance with alternative embodiments of the invention, the waveguide crossing 12 and thewaveguide cores dielectric layer 46 and embedded indielectric layer 48. In an embodiment, the waveguide crossing 12 may be composed of a dielectric material, such as silicon nitride. Thewaveguide crossing 12 and thewaveguide cores dielectric layer 46, and then patterning the deposited layer with lithography and etching processes that lithographically form an etch mask over the deposited layer and etch the masked deposited layer with an etching process, such as reactive ion etching (RIE). - With reference to
FIG. 7 in which like reference numerals refer to like features inFIG. 6 and in accordance with alternative embodiments of the invention, the deposited layer may be partially etched adjacent to sidewalls of the waveguide crossing 12 and thewaveguide cores slab layer 58. Theslab layer 58, which is in direct contact with thedielectric layer 46, is coupled to the waveguide crossing 12 and thewaveguide cores slab layer 58 is thinner than the waveguide crossing 12 and thewaveguide cores waveguide crossing 12 and thewaveguide cores slab layer 58. - With reference to
FIGS. 8, 8A in which like reference numerals refer to like features inFIG. 4 and in accordance with alternative embodiments of the invention, thestructure 10 may further include a waveguide crossing 66 that is disposed over thewaveguide crossing 12. Thearms 68 of the waveguide crossing 66 may be located in a vertical direction over (i.e., above in the y-direction) thearms arms 68 of the waveguide crossing 66 may have the same shape as thearms interfaces central section 70 that is similar tocentral section 30 of thewaveguide crossing 12. Thearms 68 of the waveguide crossing 66 may terminate at respective ends 72 that are analogous to theinterfaces 36 of thearms arms waveguide crossing 12. - The
waveguide crossing 66 may be composed of a material having a different composition than the material from which the waveguide crossing 12 is composed. In an embodiment, thearms 68 of the waveguide crossing 66 may be composed of a dielectric material, such as silicon nitride, and the arms of the waveguide crossing 12 may be composed of a single-crystal semiconductor material, such as single-crystal silicon. In an alternative embodiment and as shown inFIG. 9 , thearms 68 of the waveguide crossing 66 may be composed of a polycrystalline semiconductor material (e.g., polycrystalline silicon), and the arms of the waveguide crossing 12 may be composed of a single-crystal semiconductor material, such as single-crystal silicon. - Generally, the waveguide crossing 12 and the waveguide crossing 66 are composed of respective materials of different composition and define a bilayer or multiple-layer stack of the different materials. The addition of the waveguide crossing 66 over the waveguide crossing 12 may function to improve the performance of the
waveguide crossing 12. For example, insertion loss may be reduced by the addition of the waveguide crossing 66 over thewaveguide crossing 12. - In alternative embodiments, the waveguide crossing 66 of
FIG. 8 may be arranged over the waveguide crossing 12 ofFIG. 6 orFIG. 7 . In alternative embodiments, the waveguide crossing 66 ofFIG. 8 may be arranged beneath the waveguide crossing 12 ofFIG. 6 orFIG. 7 . In alternative embodiments, the waveguide crossing 66 ofFIG. 8 may be arranged beneath the waveguide crossing 12 ofFIG. 6 orFIG. 7 , and the waveguide crossing 66 may be composed of a single-crystal semiconductor material, such as single-crystal silicon. In alternative embodiments, one ormore waveguide crossings 66 may be arranged above and beneath the waveguide crossing 12 ofFIG. 6 orFIG. 7 . - In alternative embodiments, the waveguide crossing 66 of
FIG. 8 may be arranged over the waveguide crossing 66 ofFIG. 9 such that bothwaveguide crossings 66 are arranged over the waveguide crossing 12 ofFIG. 4 orFIG. 5 . In alternative embodiments, an additional waveguide crossing (not shown) may be formed from the single-crystal semiconductor material of the device layer and may be arranged beneath the waveguide crossing 12 ofFIG. 6 orFIG. 7 in addition to the waveguide crossing 66 ofFIG. 8 to provide a three-layer layer stack. In alternative embodiments, the waveguide crossing 66 ofFIG. 8 and the waveguide crossing 66 ofFIG. 9 may be added to the waveguide crossing 12 ofFIG. 6 orFIG. 7 to provide a three-layer stack. - The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
- References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate +/−10% of the stated value(s).
- References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane.
- A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
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US8644661B2 (en) | 2011-10-26 | 2014-02-04 | Alcatel Lucent | Photonic integrated circuit with a waveguide crossing structure |
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US9817185B2 (en) * | 2016-01-21 | 2017-11-14 | The Governing Council Of The University Of Toronto | Photonic platform having light-transferring interlayer transitions |
US10620371B2 (en) | 2016-03-05 | 2020-04-14 | Huawei Technologies Canada Co., Ltd. | Waveguide crossing having rib waveguides |
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