US20210067166A1

US20210067166A1 - Multiphase injection locked sub-sampling phase locked loop (pll) circuit

Info

Publication number: US20210067166A1
Application number: US16/839,124
Authority: US
Inventors: Xiong Liu; Chih-Wei Yao
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2019-08-28
Filing date: 2020-04-03
Publication date: 2021-03-04
Also published as: KR20210028074A; TW202110094A; CN112448716A; US11115005B2; US20210067145A1; KR20210027050A

Abstract

A system, method and electronic device are provided. The system includes a shared fractional-N phase-lock loop (PLL), a ring oscillator circuit (OSC), and a multiphase injection pulse generator configured to receive an input signal having a first frequency from the shared fraction-N PLL and generate injection pulses for the OSC based on the input signal.

Description

PRIORITY

This application is based on and claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application filed on Aug. 28, 2019 in the United States Patent and Trademark Office and assigned Ser. No. 62/892,862, the entire contents of which are incorporated herein by reference.

FIELD

The present disclosure generally relates to a wireless communication system. In particular, the present disclosure relates to a multiphase injection locked sub-sampling phase locked loop (PLL) circuit.

BACKGROUND

A typical injection locked phase-locked loop (PLL) for an LO IQ multiplier includes a pulse generation block that injects a pulse once (1× at rising edge), at one stage output of a ring oscillator. An injection action is achieved via shorting the switch by a signal. With increased injection, the phase noise improves. A PLL has components/circuits including a reference clock, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), multiple buffers that contribute to the total phase noise.

SUMMARY

According to one embodiment, a system is provided. The system includes a shared fractional-N phase-lock loop (PLL), a ring oscillator circuit (OSC), and a multiphase injection pulse generator configured to receive an input signal having a first frequency from the shared fraction-N PLL and generate injection pulses for the OSC based on the input signal.
According to one embodiment, a method is provided. The method includes generating, by a shared fractional-N PLL an input signal having a first frequency, receiving, by a multiphase injection pulse generator, the input signal having the first frequency, and generating, by the multiphase injection pulse generator, injection pulses for a OSC based on the received input signal.
According to one embodiment, an electronic device is provided. The electronic device includes at least one receiver, a shared fractional-N PLL, an OSC, a multiphase injection pulse generator, and a processor configured to receive, from the shared fractional-N PLL, an input signal having a first frequency and generate, by the multiphase injection pulse generator, injection pulses for the OSC based on the input signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a diagram of an injection locked PLL based LO IQ multiplier, according to an embodiment;

FIG. 2 illustrates a diagram of a ring oscillator, according to an embodiment;

FIG. 3 illustrates a diagram of a multiphase injection locked PLL based LO IQ multiplier, according to an embodiment;

FIG. 4 illustrates a graph of phase noise, according to an embodiment;

FIG. 5 illustrates a diagram of a sub-integer multiphase injection locked PLL based LO IQ multiple for a transceiver, according to an embodiment;

FIG. 6 illustrates another diagram of a multiphase injection locked PLL based LOIQ multiplier, according to an embodiment;

FIG. 7 illustrates a graph of control voltage and injections;

FIG. 8 illustrates a graph of 1× injection, according to an embodiment;

FIG. 9 illustrates a graph of 2× injection, according to an embodiment;

FIG. 10 illustrates a graph of 4× injection and multiplication by ¾, according to an embodiment;

FIG. 11 illustrates a graph of 4× injection and multiplication by 5/4, according to an embodiment;

FIG. 12 illustrates a graph of 8× injection and multiplication by ⅝, according to an embodiment;

FIG. 13 illustrates a graph of 8× injection and multiplication by ⅞, according to an embodiment;

FIG. 14 illustrates a graph of 8× injection and multiplication by 9/8, according to an embodiment;

FIG. 15 illustrates a graph of 8× injection and multiplication by 11/8, according to an embodiment;

FIG. 16 illustrates a diagram of an injection locking sequence, according to an embodiment;

FIG. 17 illustrates a diagram of a global pulse generator, according to an embodiment; and

FIG. 18 illustrates a block diagram of an electronic device in a network environment, according to one embodiment.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that the same elements will be designated by the same reference numerals although they are shown in different drawings. In the following description, specific details such as detailed configurations and components are merely provided to assist with the overall understanding of the embodiments of the present disclosure. Therefore, it should be apparent to those skilled in the art that various changes and modifications of the embodiments described herein may be made without departing from the scope of the present disclosure. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness. The terms described below are terms defined in consideration of the functions in the present disclosure, and may be different according to users, intentions of the users, or customs. Therefore, the definitions of the terms should be determined based on the contents throughout this specification.
The present disclosure may have various modifications and various embodiments, among which embodiments are described below in detail with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the embodiments, but includes all modifications, equivalents, and alternatives within the scope of the present disclosure.
Although the terms including an ordinal number such as first, second, etc. may be used for describing various elements, the structural elements are not restricted by the terms. The terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first structural element may be referred to as a second structural element. Similarly, the second structural element may also be referred to as the first structural element. As used herein, the term “and/or” includes any and all combinations of one or more associated items.
The terms used herein are merely used to describe various embodiments of the present disclosure but are not intended to limit the present disclosure. Singular forms are intended to include plural forms unless the context clearly indicates otherwise. In the present disclosure, it should be understood that the terms “include” or “have” indicate existence of a feature, a number, a step, an operation, a structural element, parts, or a combination thereof, and do not exclude the existence or probability of the addition of one or more other features, numerals, steps, operations, structural elements, parts, or combinations thereof.
Unless defined differently, all terms used herein have the same meanings as those understood by a person skilled in the art to which the present disclosure belongs. Terms such as those defined in a generally used dictionary are to be interpreted to have the same meanings as the contextual meanings in the relevant field of art, and are not to be interpreted to have ideal or excessively formal meanings unless clearly defined in the present disclosure.
The electronic device according to one embodiment may be one of various types of electronic devices. The electronic devices may include, for example, a portable communication device (e.g., a smart phone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to one embodiment of the disclosure, an electronic device is not limited to those described above.
The terms used in the present disclosure are not intended to limit the present disclosure but are intended to include various changes, equivalents, or replacements for a corresponding embodiment. With regard to the descriptions of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. A singular form of a noun corresponding to an item may include one or more of the things, unless the relevant context clearly indicates otherwise. As used herein, each of such phrases as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C,” may include all possible combinations of the items enumerated together in a corresponding one of the phrases. As used herein, terms such as “1^st,” “2nd,” “first,” and “second” may be used to distinguish a corresponding component from another component, but are not intended to limit the components in other aspects (e.g., importance or order). It is intended that if an element (e.g., a first element) is referred to, with or without the term “operatively” or “communicatively”, as “coupled with,” “coupled to,” “connected with,” or “connected to” another element (e.g., a second element), it indicates that the element may be coupled with the other element directly (e.g., wired), wirelessly, or via a third element.
As used herein, the term “module” may include a unit implemented in hardware, software, or firmware, and may interchangeably be used with other terms, for example, “logic,” “logic block,” “part,” and “circuitry.” A module may be a single integral component, or a minimum unit or part thereof, adapted to perform one or more functions. For example, according to one embodiment, a module may be implemented in a form of an application-specific integrated circuit (ASIC).
The present disclosure provides a system and method to generate local oscillator (LO) in-phase/quadrature (IQ) signals for wireless receivers while providing program ability to avoid spur and pulling issues.
FIG. 1 illustrates a diagram of an injection locked PLL based LO IQ multiplier, according to an embodiment. An injection locked PLL based LO IQ multiplier 100 includes a shared fractional-N PLL 102 and an injection locked PLL 101. The injection locked PLL lxx includes an injection pulse generator 104, and PFD-CP 108, a low pass filter (LPF) 110, a ring oscillator (OSC) 112 and a feedback divider (DivN) 114. The injection pulse generation block 104 injects a pulse once (2× at the rising edge) at one stage output of the OSC 112. A PLL is a control system that generates an output signal whose phase is related to the phase of an input signal. There are several different types; the simplest is an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of the input periodic signal, adjusting the oscillator to keep the phases matched.
FIG. 2 illustrates a diagram of a differential ring oscillator 200, according to an embodiment. A differential OSC 200 includes a first differential stage 201, a second differential stage 202, a third differential stage 204 and a fourth differential stage 206. The injection action is achieved by shorting the switch 208 by a signal Vinj1.
FIG. 3 illustrates a diagram of a multiphase injection locked PLL based LO IQ, according to an embodiment. The multiphase injection locked PLL based LO IQ may be high bandwidth. With increased injection, the phase noise may be improved. A multiphase injection locked PLL 300 includes a shared fractional-N PLL 302 and a multiphase injection locked PLL 303. The multiphase injection locked PLL 303 includes a multiphase injection pulse generator 304, a sub-sampling phase detector (SSPD) 306, an LPF 308 and an OSC 310. To improve the phase noise, the injection rate can be doubled at both the rising edge crossover and the falling edge crossover. The injection can be performed at each stage of the OSC 310 (i.e., 8× injections).
FIG. 4 illustrates a graph of phase noise, according to an embodiment. As shown in graph 400, the phase noise improves as the number of injections increases.
FIG. 5 illustrates a diagram of a sub-integer multiphase injection locked PLL based LO IQ for a transceiver, according to an embodiment. A transceiver 500 includes a shared fractional-N PLL 502 and multiple receivers RX1 504, RX2 506 to RXN 508 and multiple LOIQ blocks 510, 512 to 514. The transceiver 500 may be a transceiver used for any wireless technology, including cellular technology (e.g., 4^thgeneration (4G), 5^thgeneration (5G)), and Wi-Fi. Each LOIQ block (e.g., 510 a) includes a multiphase injection pulse generator 516, and a SSPD 518, a LPF 520 and an OSC 522. Each receiver (e.g., 504 a) receives I and Q signals from each LOIQ block and processes the I and Q signals in a mixer 524 to mix the I/Q signals with the RF signal that is amplified by the LNA to downconvert the RF signal to an intermediate frequency that is further processed with an analog base band (ABB) signal 526 and an analog to digital converter (ADC) 528 to produce a signal which is run through a low noise amplifier 530 and the RF signal is produced. Table 1 shows supported LO frequency (Flo) and corresponding standards (e.g., sub-6 GHz New Radio (NR), ultra high band (UHB), and License Assisted Access (LAA)).

TABLE 1

Standard	Sub-6 GHz NR	UHB	LAA

Flo(MHz)	3300-4200	4400-5000	3400-3800	5150-5925
N/M Ratio	3/4, 7/8, 5/8	9/8, 11/8, 5/4	3/4, 7/8, 5/8	9/8, 11/8, 5/4

FIG. 6 illustrates another diagram of a multiphase injection locked PLL based LOIQ multiplier, according to an embodiment. A multiphase injection locked PLL based LOIQ multiplier 600 includes a fractional-N PLL 601 and a multiphase injection locked PLL 603. The multiphase injection locked PLL 603 includes a buffer 607, and a OSC 605 that includes a first differential stage 602, a second differential stage 604, a third differential stage 606, and a fourth differential stage 608. A multimode multiphase pulse generator 610 provides each injection (INJ0 through INJ3) to a respective differential stage of the OSC 605. 609 and 611 are output buffers to each next stage. The multiphase injection locked PLL 603 further includes a sampler 612 that receives a sample signal from the multimode multiphase pulse generator 610 and samples the signal from the OSC 605. The signals from the sampler 612 are sent to a voltage-to-current generator (Gm) 614 which is then sent to a LPF 616. Furthermore, a DivN block 618 samples an output of the OSC that divides down the frequency of the OSC frequency to the reference voltage frequency, and passes the signal to a phase frequency detector (PFD) 620 that generates a voltage signal that represents the difference in phase between the output of DivN and REF (after buffer). The outputs of the Gm 614 and the PFD 620 are passed to a DivM function 621 and are then passed to the LPF 616 To switch between different modes, there is no physical connection change. All modes are included in the pulse generator 610 and the pulse generator 610 output is different across different modes, as shown in Table 2, according to one embodiment.

TABLE 2

INJECTION
MODE	INJ0	INJ1	INJ2	INJ3

X1	Active, and same	Always	0	Always 0	Always 0
	freq as SAMP pulse
X2	Active, 2x	Always 0	Always 0	Always 0
	freq as SAMP pulse
X4	Active, 2x	Always 0	Active, 2x	Always 0
	freq as SAMP pulse		freq as SAMP pulse
X8	Active, 2x	Active, 2x	Active, 2x	Active, 2x
	freq as SAMP pulse	freq as SAMP pulse	freq as SAMP pulse	freq as SAMP pulse

FIG. 7 illustrates a graph of control voltage and injections. FIG. 7 shows the sequence of injection locking. Since injection locking is a “fragile” or sensitive operation, the system determines a correct time to start.
FIG. 8 illustrates a graph of 1× injection, according to an embodiment. As shown in graph 800, an injection signal INJ0 includes an injection pulse 802 applied at a rising edge of an input PH0 and a corresponding falling edge of a complementary input PH4 of a first differential stage of a differential ring oscillator. Although PH4 is not illustrated in FIG. 8, it is understood that PH4's timing waveform is complementary to PH0. It is appreciated that the injection pulse may be performed at the rising edge of any differential stage of the differential ring oscillator, without deviating from the scope of the present disclosure.
FIG. 9 illustrates a graph of 2× injection, according to an embodiment. As shown in graph 900, an injection signal INJ0 includes a first injection pulse 902 at a rising edge of a input PH0 and at a corresponding falling edge of a complementary input PH4 of a first differential stage of a differential ring oscillator; and a second injection pulse 904 at a falling edge of PH0 and at a corresponding rising edge of PH4. Although PH4 is not illustrated in FIG. 9, it is understood that PH4's timing waveform is complementary to PH0. As shown in graph 900, every four input clock cycle periods is equal to three ring oscillator periods.
FIG. 10 illustrates a graph of 4× injection and multiplication by ¾, according to an embodiment. As shown in graph 1000, a first injection signal INJ0 includes a first injection pulse 1002 applied at a rising edge of an input PH0 and a corresponding falling edge of a complementary input PH4 of a first differential stage of a differential ring oscillator. A second injection signal INJ includes a second injection pulse 1004 applied at a falling edge of an input PH2 and a corresponding rising edge of a complementary input PH6 of a third differential stage of the differential ring oscillator. The first injection signal INJ0 further includes a third injection pulse 1006 applied at a falling edge of PH0 and at a rising edge of PH4. The second injection signal INJ2 further includes a fourth injection pulse 1008 applied at a rising edge of PH2 and at a corresponding falling edge of PH6. Although PH4 and PH6 are not illustrated in FIG. 10, it is understood that PH4 and PH6's timing waveforms are complementary to PH0 and PH2 respectively. One injection pulse INJ0 is at an even cycle while the other injection pulse INJ2 is at an odd cycle. Every four input clock cycle periods equals three ring oscillator periods.
FIG. 11 illustrates a graph of 4× injection and multiplication by 5/4, according to an embodiment. As shown in graph 1100, a first injection signal INJ0 includes a first injection pulse 1102 applied at a rising edge of an input PH0 and a corresponding falling edge of a complementary input PH4 of a first differential stage of a differential ring oscillator. A second injection signal INJ2 includes a second injection pulse 1104 applied at a rising edge of an input PH2 and at a corresponding falling edge of a complementary input PH6 of a third differential stage of the differential ring oscillator. The first injection signal INJ0 further includes a third injection pulse 1106 applied at a falling edge of PH0 and at a corresponding rising edge of PH4. The second injection signal INJ2 further includes a fourth injection pulse 1108 applied at a falling edge of PH2 and at a corresponding rising edge of PH6. Every five input clock cycle periods equals three ring oscillator periods. Although PH4 and PH6 are not illustrated in FIG. 11, it is understood that PH4 and PH6's timing waveforms are complementary to PH0 and PH2 respectively.
FIG. 12 illustrates a graph of 8× injection and multiplication by ⅝, according to an embodiment. Every eight input clock cycle periods equals five ring oscillator periods. As shown in graph 1200, a first injection signal INJ0 includes a first injection pulse 1202 applied at a rising edge of an input PH0 and at a corresponding falling edge of a complementary input PH4 of a first differential stage of a differential ring oscillator. A second injection signal INJ1 includes a second injection pulse 1204 applied at a falling edge of an input PH1 and at a corresponding rising edge of a complementary input PH5 of a second differential stage of the differential ring oscillator. A third injection signal INJ2 includes a third injection signal 1206 applied at a rising edge of an input PH2 and at a corresponding falling edge of a complementary input PH6 of a third differential stage of the differential ring oscillator. A fourth injection signal INJ3 includes a fourth injection signal 1208 applied at a rising edge of an input PH3 and at a corresponding falling edge of a complementary input PH7 of a fourth differential stage of the differential ring oscillator. The first injection signal INJ0 further includes a fifth injection 1210 applied at a falling edge of PH0 and at a corresponding rising edge of PH4. The second injection signal INJ1 further includes a sixth injection 1212 applied at a rising edge of PH1 and at a corresponding falling edge of PH5. The third injection signal INJ2 further includes a seventh injection 1214 applied at a falling edge of PH2 and at a corresponding rising edge of PH6. The fourth injection signal INJ3 further includes an eighth injection signal 1216 applied at a rising edge of PH3 and at a corresponding falling edge of PH7. Although PH4-PH7 are not illustrated in FIG. 12, it is understood that PH4-PH7's timing waveforms are complementary to PH0-PH3 respectively.
FIG. 13 illustrates a graph of 8× injection and multiplication by ⅞, according to an embodiment. Every eight input clock cycle periods equals seven ring oscillator periods. As shown in graph 1300, the first injection signal INJ0 includes a first injection pulse 1302 applied at a rising edge of an input PH0 and at a corresponding falling edge of a complementary input PH4 of a first differential stage of a differential ring oscillator. A second injection signal INJ1 includes a second injection pulse 1304 applied at a falling edge of input PH3 and at a corresponding rising edge of a complementary input PH7 of a second differential stage of the differential ring oscillator. A third injection signal INJ2 includes a third injection signal 1306 applied at a falling edge of an input PH2 and at a corresponding rising edge of a complementary input PH6 of a third differential stage of the differential ring oscillator. A fourth injection signal INJ3 includes a fourth injection signal 1308 applied at a falling edge of PH1 and at a corresponding rising edge of a complementary input PH5 of a fourth differential stage of the differential ring oscillator. The first injection signal INJ0 includes the fifth injection 1310 applied at a falling edge of PH0 and at a corresponding rising edge of PH4. The second injection signal INJ1 includes a sixth injection 1312 applied at a rising edge of PH3 and a corresponding falling edge of PH7 The third injection signal INJ3 includes a seventh injection 1314 applied at a rising edge of PH2 and at a corresponding falling edge of PH6. The fourth injection signal INJ3 includes an eighth injection 1316 applied at a rising edge of PH1 and at a corresponding falling edge of PH5. Although PH4-PH7 are not illustrated in FIG. 13, it is understood that PH4-PH7's timing waveforms are complementary to PH0-PH3 respectively.
FIG. 14 illustrates a graph of 8× injection and multiplication by 9/8, according to an embodiment. Every eight input clock cycle periods equals nine ring oscillator periods. As shown in graph 1400, the first injection signal INJ0 includes a first injection pulse 1402 applied at a rising edge of input PH0 and a corresponding falling edge of a complementary input PH4 of a first differential stage of a differential ring oscillator. A second injection signal INJ1 includes a second injection pulse 1404 applied at a rising edge of input PH1 and at a corresponding falling edge of a complementary input PH5 of a second differential stage of the differential ring oscillator. A third injection signal INJ2 includes a third injection pulse 1406 applied at a rising edge of input PH2 and at a corresponding falling edge of a complementary input PH6 of a third differential stage of the differential ring oscillator. A fourth injection signal INJ3 includes a fourth injection pulse 1408 applied at a rising edge of input PH3 and at a corresponding falling edge of a complementary input PH7 of a fourth differential stage of the differential ring oscillator. The first injection signal INJ0 further includes a fifth injection 1410 applied at a falling edge of PH0 and at a corresponding rising edge of PH4. The second injection signal INJ1 further includes a sixth injection 1412 applied at a rising edge of PH1 and at a corresponding falling edge of PH5. The third injection signal INJ2 further includes a seventh injection 1414 applied at a falling edge of PH2 and at a corresponding rising edge of PH6. The fourth injection signal INJ3 further includes an eighth injection signal 1416 applied at a rising edge of PH3 and at a corresponding falling edge of PH7. Although PH4-PH7 are not illustrated in FIG. 14, it is understood that PH4-PH7's timing waveforms are complementary to PH0-PH3 respectively
FIG. 15 illustrates a graph of 8× injection and multiplication by 11/8, according to an embodiment. Every eight input clock cycle periods equals eleven ring oscillator periods. As shown in graph 1500, the first injection signal INJ0 includes a first injection pulse 1502 applied at a rising edge of an input PH0 and at a corresponding falling edge of a complementary input PH4 of a first differential stage of a differential ring oscillator. A second injection signal INJ1 includes a second injection pulse 1504 applied at a rising edge of input PH3 and at a corresponding falling edge of a complementary input PH7 of a second differential stage of the differential ring oscillator. A third injection signal INJ2 includes a third injection signal 1506 applied at a falling edge of an input PH2 and at a corresponding rising edge of a complementary input PH6 of a third differential stage of the differential ring oscillator. A fourth injection signal INJ3 includes a fourth injection signal 1508 applied at a rising edge of PH1 and at a corresponding falling edge of a complementary input PH5 of a fourth differential stage of the differential ring oscillator. The first injection signal INJ0 includes the fifth injection 1510 applied at a falling edge of PH0 and at a corresponding rising edge of PH4. The second injection signal INJ1 includes a sixth injection 1512 applied at a falling edge of PH3 and a corresponding rising edge of PH7 The third injection signal INJ3 includes a seventh injection 1514 applied at a rising edge of PH2 and at a corresponding falling edge of PH6. The fourth injection signal INJ3 includes an eighth injection 1516 applied at a falling edge of PH1 and at a corresponding rising edge of PH5. Although PH4-PH7 are not illustrated in FIG. 15, it is understood that PH4-PH7's timing waveforms are complementary to PH0-PH3 respectively
FIG. 16 illustrates a diagram of an injection locking sequence, according to an embodiment. At 1602, the present system performs a frequency locked loop (FLL) lock. At 1604, the system enables the sub-sampling PLL. At 1606, the injections start. The sub-sampling is used to utilize the high gain in the sampler and achieve lower phase noise. Due to the limited tracking range, the FLL is used to help the sub-sampling PLL achieve the lock. After the sub-sampling PLL locks, the injections start and is the main method to ensure the output if a clock that closely tracks the input reference clock and thus low phase noise. Table 3 shows an example injection rate and sampling pulses.

TABLE 3

SSPLL m	SSPLLDI	Inj mode	SAMPMO	INJ_MOD	FLL FB Div

fchannel(MHz)
fvco (MHz)
fdco SS-PLL ratio = 3/2 (MHz)	½	2.000	1x, 2x	0	0, 1	3
fdco SS-PLL ratio = 9/8 (MHz)	⅛	8.000	1x, 2x, 4x, 8x	2	0, 1, 2, 3	9
fdco SS-PLL ratio = 11/8 (MHz)	⅛	8.000	1x, 2x, 4x, 8x	2	0, 1, 2, 3	11
fdco SS-PLL ratio = 5/4 (MHz)	¼	4.000	1x, 2x, 4x	1	0, 1, 2	5
fdco SS-PLL ratio = 3/4 (MHz)	¼	4.000	1x, 2x, 4x	1	0, 1, 2	3
fdco SS-PLL ratio = 7/8 (MHz)	⅛	8.000	1x, 2x, 4x, 8x	2	0, 1, 2, 3	7
fdco SS-PLL ratio = 5/8 (MHz)	⅛	8.000	1x, 2x, 4x, 8x	2	0, 1, 2, 3	5

indicates data missing or illegible when filed

FIG. 17 illustrates a diagram of a global pulse generator, according to an embodiment. FIG. 17 shows an example of the multiphase injection pulse generation block 304 (FIG. 3). The pulse generation block 1702 received an input clock from a shared PLL (block 302/502) and generates multiple pulses (e.g., INJ0/INJ1/INJ3/INJ/SAMP of FIG. 6). To implement these functions, the system includes a state machine 1704 to decode for different injection ratios (i.e., 2×/4×/8×, etc.), a pipelined gating logic block 1706 to generate a global pulse and gating logic to selectively pass the global pulses to 5 outputs 1710-1718 (i.e., SAMP/INJ0/INJ1/INJ2/INJ3).
FIG. 18 illustrates a block diagram of an electronic device 1801 in a network environment 1800, according to one embodiment. Referring to FIG. 18, the electronic device 1801 in the network environment 1800 may communicate with another electronic device 1802 via a first network 1898 (e.g., a short-range wireless communication network), or another electronic device 1804 or a server 1808 via a second network 1899 (e.g., a long-range wireless communication network). The electronic device 1801 may also communicate with the electronic device 1804 via the server 1808. The electronic device 1801 may include a processor 1820, a memory 1830, an input device 1850, a sound output device 1855, a display device 1860, an audio module 1870, a sensor module 1876, an interface 1877, a haptic module 1879, a camera module 1880, a power management module 1888, a battery 1889, a communication module 1890, a subscriber identification module (SIM) 1896, or an antenna module 1897. In one embodiment, at least one (e.g., the display device 1860 or the camera module 1880) of the components may be omitted from the electronic device 1801, or one or more other components may be added to the electronic device 1801. In one embodiment, some of the components may be implemented as a single integrated circuit (IC). For example, the sensor module 1876 (e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) may be embedded in the display device 1860 (e.g., a display).
The processor 1820 may execute, for example, software (e.g., a program 1840) to control at least one other component (e.g., a hardware or a software component) of the electronic device 1801 coupled with the processor 1820, and may perform various data processing or computations. As at least part of the data processing or computations, the processor 1820 may load a command or data received from another component (e.g., the sensor module 1876 or the communication module 1890) in volatile memory 1832, process the command or the data stored in the volatile memory 1832, and store resulting data in non-volatile memory 1834. The processor 1820 may include a main processor 1821 (e.g., a central processing unit (CPU) or an application processor (AP)), and an auxiliary processor 1823 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that is operable independently from, or in conjunction with, the main processor 1821. Additionally or alternatively, the auxiliary processor 1823 may be adapted to consume less power than the main processor 1821, or execute a particular function. The auxiliary processor 1823 may be implemented as being separate from, or a part of, the main processor 1821.
The auxiliary processor 1823 may control at least some of the functions or states related to at least one component (e.g., the display device 1860, the sensor module 1876, or the communication module 1890) among the components of the electronic device 1801, instead of the main processor 1821 while the main processor 1821 is in an inactive (e.g., sleep) state, or together with the main processor 1821 while the main processor 1821 is in an active state (e.g., executing an application). According to one embodiment, the auxiliary processor 1823 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module 1880 or the communication module 1890) functionally related to the auxiliary processor 1823.
The memory 1830 may store various data used by at least one component (e.g., the processor 1820 or the sensor module 1876) of the electronic device 1801. The various data may include, for example, software (e.g., the program 1840) and input data or output data for a command related thereto. The memory 1830 may include the volatile memory 1832 or the non-volatile memory 1834.
The program 1840 may be stored in the memory 1830 as software, and may include, for example, an operating system (OS) 1842, middleware 1844, or an application 1846.
The input device 1850 may receive a command or data to be used by other component (e.g., the processor 1820) of the electronic device 1801, from the outside (e.g., a user) of the electronic device 1801. The input device 1850 may include, for example, a microphone, a mouse, or a keyboard.
The sound output device 1855 may output sound signals to the outside of the electronic device 1801. The sound output device 1855 may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as playing multimedia or recording, and the receiver may be used for receiving an incoming call. According to one embodiment, the receiver may be implemented as being separate from, or a part of, the speaker.
The display device 1860 may visually provide information to the outside (e.g., a user) of the electronic device 1801. The display device 1860 may include, for example, a display, a hologram device, or a projector and control circuitry to control a corresponding one of the display, hologram device, and projector. According to one embodiment, the display device 1860 may include touch circuitry adapted to detect a touch, or sensor circuitry (e.g., a pressure sensor) adapted to measure the intensity of force incurred by the touch.
The audio module 1870 may convert a sound into an electrical signal and vice versa. According to one embodiment, the audio module 1870 may obtain the sound via the input device 1850, or output the sound via the sound output device 1855 or a headphone of an external electronic device 1802 directly (e.g., wired) or wirelessly coupled with the electronic device 1801.
The sensor module 1876 may detect an operational state (e.g., power or temperature) of the electronic device 1801 or an environmental state (e.g., a state of a user) external to the electronic device 1801, and then generate an electrical signal or data value corresponding to the detected state. The sensor module 1876 may include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.
The interface 1877 may support one or more specified protocols to be used for the electronic device 1801 to be coupled with the external electronic device 1802 directly (e.g., wired) or wirelessly. According to one embodiment, the interface 1877 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.
A connecting terminal 1878 may include a connector via which the electronic device 1801 may be physically connected with the external electronic device 1802. According to one embodiment, the connecting terminal 1878 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).
The haptic module 1879 may convert an electrical signal into a mechanical stimulus (e.g., a vibration or a movement) or an electrical stimulus which may be recognized by a user via tactile sensation or kinesthetic sensation. According to one embodiment, the haptic module 1879 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.
The camera module 1880 may capture a still image or moving images. According to one embodiment, the camera module 1880 may include one or more lenses, image sensors, image signal processors, or flashes.
The power management module 1888 may manage power supplied to the electronic device 1801. The power management module 1888 may be implemented as at least part of, for example, a power management integrated circuit (PMIC).
The battery 1889 may supply power to at least one component of the electronic device 1801. According to one embodiment, the battery 1889 may include, for example, a primary cell which is not rechargeable, a secondary cell which is rechargeable, or a fuel cell.
The communication module 1890 may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 1801 and the external electronic device (e.g., the electronic device 1802, the electronic device 1804, or the server 1808) and performing communication via the established communication channel. The communication module 1890 may include one or more communication processors that are operable independently from the processor 1820 (e.g., the AP) and supports a direct (e.g., wired) communication or a wireless communication. According to one embodiment, the communication module 1890 may include a wireless communication module 1892 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 1894 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules may communicate with the external electronic device via the first network 1898 (e.g., a short-range communication network, such as Bluetooth™, wireless-fidelity (Wi-Fi) direct, or a standard of the Infrared Data Association (IrDA)) or the second network 1899 (e.g., a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., LAN or wide area network (WAN)). These various types of communication modules may be implemented as a single component (e.g., a single IC), or may be implemented as multiple components (e.g., multiple ICs) that are separate from each other. The wireless communication module 1892 may identify and authenticate the electronic device 1801 in a communication network, such as the first network 1898 or the second network 1899, using subscriber information (e.g., international mobile subscriber identity (IMSI)) stored in the subscriber identification module 1896.
The antenna module 1897 may transmit or receive a signal or power to or from the outside (e.g., the external electronic device) of the electronic device 1801. According to one embodiment, the antenna module 1897 may include one or more antennas, and, therefrom, at least one antenna appropriate for a communication scheme used in the communication network, such as the first network 1898 or the second network 1899, may be selected, for example, by the communication module 1890 (e.g., the wireless communication module 1892). The signal or the power may then be transmitted or received between the communication module 1890 and the external electronic device via the selected at least one antenna.
At least some of the above-described components may be mutually coupled and communicate signals (e.g., commands or data) therebetween via an inter-peripheral communication scheme (e.g., a bus, a general purpose input and output (GPIO), a serial peripheral interface (SPI), or a mobile industry processor interface (MIPI)).
According to one embodiment, commands or data may be transmitted or received between the electronic device 1801 and the external electronic device 1804 via the server 1808 coupled with the second network 1899. Each of the electronic devices 1802 and 1804 may be a device of a same type as, or a different type, from the electronic device 1801. All or some of operations to be executed at the electronic device 1801 may be executed at one or more of the external electronic devices 1802, 1804, or 1808. For example, if the electronic device 1801 should perform a function or a service automatically, or in response to a request from a user or another device, the electronic device 1801, instead of, or in addition to, executing the function or the service, may request the one or more external electronic devices to perform at least part of the function or the service. The one or more external electronic devices receiving the request may perform the at least part of the function or the service requested, or an additional function or an additional service related to the request, and transfer an outcome of the performing to the electronic device 1801. The electronic device 1801 may provide the outcome, with or without further processing of the outcome, as at least part of a reply to the request. To that end, a cloud computing, distributed computing, or client-server computing technology may be used, for example.
One embodiment may be implemented as software (e.g., the program 1840) including one or more instructions that are stored in a storage medium (e.g., internal memory 1836 or external memory 1838) that is readable by a machine (e.g., the electronic device 1801). For example, a processor of the electronic device 1801 may invoke at least one of the one or more instructions stored in the storage medium, and execute it, with or without using one or more other components under the control of the processor. Thus, a machine may be operated to perform at least one function according to the at least one instruction invoked. The one or more instructions may include code generated by a complier or code executable by an interpreter. A machine-readable storage medium may be provided in the form of a non-transitory storage medium. The term “non-transitory” indicates that the storage medium is a tangible device, and does not include a signal (e.g., an electromagnetic wave), but this term does not differentiate between where data is semi-permanently stored in the storage medium and where the data is temporarily stored in the storage medium.
According to one embodiment, a method of the disclosure may be included and provided in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a compact disc read only memory (CD-ROM)), or be distributed (e.g., downloaded or uploaded) online via an application store (e.g., Play Store™), or between two user devices (e.g., smart phones) directly. If distributed online, at least part of the computer program product may be temporarily generated or at least temporarily stored in the machine-readable storage medium, such as memory of the manufacturer's server, a server of the application store, or a relay server.
According to one embodiment, each component (e.g., a module or a program) of the above-described components may include a single entity or multiple entities. One or more of the above-described components may be omitted, or one or more other components may be added. Alternatively or additionally, a plurality of components (e.g., modules or programs) may be integrated into a single component. In this case, the integrated component may still perform one or more functions of each of the plurality of components in the same or similar manner as they are performed by a corresponding one of the plurality of components before the integration. Operations performed by the module, the program, or another component may be carried out sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations may be executed in a different order or omitted, or one or more other operations may be added.
Although certain embodiments of the present disclosure have been described in the detailed description of the present disclosure, the present disclosure may be modified in various forms without departing from the scope of the present disclosure. Thus, the scope of the present disclosure shall not be determined merely based on the described embodiments, but rather determined based on the accompanying claims and equivalents thereto.

Claims

What is claimed is:

1. A system, comprising:

a shared fractional-N phase-lock loop (PLL);

a ring oscillator circuit (OSC); and

a multiphase injection pulse generator configured to receive an input signal having a first frequency from the shared fraction-N PLL and generate injection pulses for the OSC based on the input signal.

2. The system of claim 1, wherein the OSC includes a plurality of stages;

3. The system of claim 2, wherein the multiphase injection pulse generator is further configured to generate a first set of injection pulses for each of the stages of the OSC.

4. The system of claim 3, wherein the multiphase injection pulse generator is further configured to generate a second set of injection pulses for each of the stages of the OSC.

5. The system of claim 1, further comprising a frequency and phase stabilization loop configured to synchronize stages of the OSC to the generated injection pulses.

6. The system of claim 1, wherein the generated injection pulses are performed at a rising edge of the OSC.

7. The system of claim 1, wherein the generated injection pulses are performed at a falling edge of the OSC.

8. A method, comprising:

generating, by a shared fractional-N phase-lock loop (PLL) an input signal having a first frequency;

receiving, by a multiphase injection pulse generator, the input signal having the first frequency; and

generating, by the multiphase injection pulse generator, injection pulses for a ring oscillator circuit (OSC) based on the received input signal.

9. The method of claim 8, wherein the OSC includes a plurality of stages;

10. The method of claim 9, further comprising generating, by the multiphase injection pulse generator, a first set of injection pulses for each of the stages of the OSC.

11. The method of claim 10, further generating, by the multiphase injection pulse generator a second set of injection pulses for each of the stages of the OSC.

12. The method of claim 8, further comprising synchronizing, by a frequency and phase stabilization loop, stages of the OSC to the generated injection pulses.

13. The method of claim 8, wherein the generated injection pulses are performed at a rising edge of the OSC.

14. The method of claim 8, wherein the generated injection pulses are performed at a falling edge of the OSC.

15. A electronic device, comprising:

at least one receiver;

a shared fractional-N phase-lock loop (PLL);

a ring oscillator circuit (OSC);

a multiphase injection pulse generator; and

a processor configured to receive, from the shared fractional-N PLL, an input signal having a first frequency and generate, by the multiphase injection pulse generator, injection pulses for the OSC based on the input signal.

16. The electronic device of claim 15, wherein the OSC includes a plurality of stages;

17. The electronic device of claim 16, wherein the processor is further configured to generate, by the multiphase injection pulse generator, a first set of injection pulses for each of the stages of the OSC.

18. The electronic device of claim 17, wherein the processor is further configured to generate, by the multiphase injection pulse generator, a second set of injection pulses for each of the stages of the OSC.

19. The electronic device of claim 15, further comprising a frequency and phase stabilization loop, wherein the processor is further configured to, by the frequency and phase stabilization loop, synchronize stages of the OSC to the generated injection pulses.

20. The electronic device of claim 15, wherein the generated injection pulses are performed at a rising edge of the OSC.