US20210064117A1

US20210064117A1 - Optimizing power usage by factoring processor architectural events to pmu

Info

Publication number: US20210064117A1
Application number: US17/097,325
Authority: US
Inventors: Yen-Cheng Liu; P. Keong Or; Krishnakanth V. Sistla; Ganapati Srinivasa
Original assignee: Intel Corp
Current assignee: Tahoe Research Ltd
Priority date: 2006-12-29
Filing date: 2020-11-13
Publication date: 2021-03-04
Also published as: US8473766B2; US9367112B2; US20130254572A1; US20150127962A1; CN101266515A; US8117478B2; US8966299B2; US8700933B2; JP2008165797A; US20120089850A1; US8412970B2; US20170017292A1; US11144108B2; CN101266515B; US20140164799A1; US20170017286A1; CN102200828B; US20130031400A1; US20080162972A1; US20230251702A1

Abstract

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 15/281,587, filed Sep. 30, 2016, which is a continuation of application Ser. No. 14/972,765, filed Dec. 17, 2015, which is a continuation of application Ser. No. 14/598,454, filed Jan. 16, 2015 (now U.S. Pat. No. 9,367,112 issued Jun. 14, 2016), which is a continuation of application Ser. No. 14/182,385, filed Feb. 18, 2014 (now U.S. Pat. No. 8,966,299 issued Feb. 24, 2015), which is a continuation of application Ser. No. 13/787,085, filed Mar. 6, 2013 (now U.S. Pat. No. 8,700,933 issued Apr. 15, 2014), which is a continuation of application Ser. No. 13/329,700, filed Dec. 19, 2011 (now U.S. Pat. No. 8,412,970 issued Apr. 2, 2013), which is a continuation of application Ser. No. 11/618,477, filed Dec. 29, 2006 (now U.S. Pat. No. 8,117,478 issued Feb. 14, 2012), all of which are herein incorporated by reference.

BACKGROUND ART

Processor power consumption has become a major issue in recent years. The current trend of processor design to multi-core architecture as eased the pressure on power consumption. However, power consumption still grows linearly with the number of cores being designed.
Recent developments in technology have provided new opportunities to further optimize power consumptions. However, these technologies still have several downsides. Specifically, within the new technologies, OS does not understand how effectively the workload is running in the hardware and the associated power cost in the hardware. Secondly, OS interaction is very slow to react. Thirdly, the current OS do not control performance power state per core. Finally, turbo mode only takes thermal and sensor feedback, it does take into account the cores higher performance requirement.

BRIEF DESCRIPTION OF THE DRAWINGS

Various features of the invention will be apparent from the following description of preferred embodiments as illustrated in the accompanying drawings, in which like reference numerals generally refer to the same parts throughout the drawings. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the inventions.

FIG. 1 illustrates a diagram of a thermal sensor and architecture events connection to a PCU in accordance with one embodiment of the invention.

FIG. 2 illustrates a flow chart of a method for architecture event power controller in accordance with one embodiment of the invention.

FIG. 3 is a block diagram of computer system in accordance with an embodiment of the invention.

FIG. 4 is a block diagram of a computing system arranged in a point-to-point configuration, according to one embodiment of the invention.

DETAILED DESCRIPTION

In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of the invention. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the invention may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
Some of the embodiments discussed herein may be utilized to perform event handling operations. In an embodiment, an “event” refers to a condition that may or may not require some action to be taken by logic. Furthermore, events may be classified into different types based on the action that is to be taken.
In one embodiment, and “architectural event” refers to an event or condition that may be monitored (e.g., by programming information corresponding to the architectural event into a state). In an embodiment, software may configure a channel to monitor certain architectural event which may not otherwise be observable by software and/or hardware. In an embodiment, an architectural event may generally refer to an event or condition that occurs within processing resources or other logic present on the same integrated circuit chip as a processor.
In an embodiment, architecture events are one factor for making power management decisions. Architecture events are widely used for software performance optimization. By factoring in architecture events for making power management decisions, the embodiment may effectively detect core execution condition that neither OS nor turbo mode can currently detect.
One embodiment provides additional value to a power control unit (PCU) to make appropriate power decisions using existing designs. The PCU handles thermal events, schedules/manages per core's frequency increase/decrease. In the embodiment, logic is added in the PCU. The PCU then takes feedback from counters to assist in making decisions to scale up a particular core.
Architecture events inside a processor are usually detected by a series of physical counters implemented in different areas of the processor. These counters maybe referred to as EMON counters. EMON counters are performance monitoring counters that reside in each function unit that counts the number of specific events that has occurred during a period of time.
There may be public EMON counters and private EMON counters. Public EMON counters are those accessible by vendors and users, while private EMON counters are used internally for debugging. Both public and private EMON counters may be used for software and hardware tuning. EMON counters are very useful tools to understand the application behavior and how effective the current application is doing inside the processor.
Instruction retried is one type of EMON counter. By knowing instruction retired per cycle, the system knows how fast the current application is executing inside the processor. More instruction retired per cycle, the better performance the application is getting.
Another type EMON counter is a MLC/LLC cache miss. Programs experience lots of MLC/LLC cache miss usually means they require higher BW to system interconnect. It also means the program will not be effectively executing instruction since most of time the problem will be stalled waiting for data return.
Branch Misprediction is also a type of EMON counter. This is a good indicator to show that the core is not doing lots of “useful” work since it is working on the wrong branch of instruction stream.
TLB miss is also a type of EMON counter. Similar to MLC/LLC miss, a TLB miss usually means stalling the core until data has returned.
There are many more counters defined in any processor. For example, Intel's P4 processor contains more than 200 counters. Some of the counters are for performance tuning while others are for debug/validation purposes. The four counters mentioned above, instruction retired, MLC/LLC cache miss, branch misprediction and TLB miss are crucial to the power management discussed here within.
However, it should be noted that the present disclosure is not limited to the above identified counters. Rather, the present disclosure may take as many architectural events as needed. The present system utilizes a push bus mechanism that can connect all counters serially on the same bus since these counters do not require high bandwidth or high refresh rate.
FIG. 1 illustrates a diagram of a thermal sensor and architecture events connection 100 to a PCU in accordance with one embodiment of the invention. FIG. 1 illustrates a processor with eight cores 105 and four shared last level caches (LLC) 107. It should be noted that the eight cores and four shared LLCs are shown for illustrative purposes only. Any number of cores or LLCs may be used for this embodiment. A functional unit 110 is shared among the cores 105. The PCU 115 is one of the units to be shared by the cores 105.
The dark squares in the cores 105 represent thermal sensors 120. The cores 105 have thermal sensors 120 to prevent over heating of the cores 105. A serial push bus 125 connects all the sensors 120 on the bus. The push bus 125 may have various branches. A first branch 127 of the push bus 125 may take up to 96 time slots, where each time slot is reserved for one of the thermal sensors 120. There is at least one branch 127 of the push bus 125 in each core 105. Each branch 127 of the push bus 105 may monitor one core 105 with all the thermal sensors 120. All the data collected from the thermal sensors 120 by the push bus 125 is then sent to the PCU 115.
A similar approach is made to monitor architectural events by linking different counters via the same serial push bus mechanism and each counter having a designated time slot. The light squares are EMON counters 130. The dotted line 135 is another branch of the serial push bus. The second branch 135 of the push bus 125 may take up to 96 time slots, where each time slot is reserved for one of the EMON counters. There is at least one branch 135 of the push bus 125 in each core 105. Each branch 135 of the push bus 125 may monitor one core 105 with all the EMON counters 130. All the data collected from the EMON counters 130 by the push bus 125 is then sent to the PCU 115.
The PCU 115 may have very low sampling rate to retrieve information from the push bus 125 which is one reason why all the sensors may share a narrow bus. The serial push bus 125 may not be more than 10 bits wide and runs a low sampling rate. Due to this, there is no high bandwidth requirement to monitor these events. Sampling the counters every 1000 cycles may be sufficient. The sampling frequency should be tuned with the thermal sensors so that PCU 115 decisions may be made coherent between architectural events 130 and thermal sensors 120.
FIG. 2 illustrates a flow chart of a method 200 for architecture event power controller in accordance with one embodiment of the invention. The method 200 begins when the system is in idle mode 205. When each timer interval is reached, architectural event power optimization logic (AEPOL) examines the counts and decides whether a power up or power down sequence should be initiated 210.
For a power up sequence, AEPOL queries PCU 115 to determine if turbo mode is available 215. If turbo mode is not available, meaning no reserve power is available, AEPOL goes back to idle mode 205 until the next timer interval arrives. If turbo mode is available, AEPOL initiates a power up sequence 220. Once the power up sequence is completed AEPOL goes into idle mode 205 until the next timer interval.
For a power down sequence, AEPOL notifies PCU 115 to initiate power down sequence 225. Once power down sequence is completed, AEPOL goes to idle mode 205 until the next timer interval.
The AEPOL referred to in FIG. 2 is implemented per core. The logic may constantly monitor architectural events to ensure cores are running in it optimal power/performance state.
In one embodiment, architecture event counts of interest are counted and sent to the PCU 115. PCU 115 then analyzes the counts it receives from each counter and determines whether it should power up or power down a particular core 105. In one embodiment, if a system interconnect (shared cache, bus control logic, on-die memory control, etc.) also supports power scaling, the same mechanism may be used to scale system interconnect logic.
In an embodiment, all EMON counters 130 monitored should be referenced together to better understand AEPOL behavior. For example, low instruction retired per cycle (IPC) count does not mean core is not running effectively unless we know it also suffers high cache miss or high branch misprediction.
As shown in Table 1 below, the architecture events of interests are grouped together to make decisions. A threshold count for each architecture event counter is also defined. The threshold value is defined based on performance studies for a particular architecture, as performance may differ depending on the architecture of the system. In Table 1, if all related architecture counters are low, this suggests that the system does not suffer from any system bound actions. Therefore, scaling up the frequency on the core does help increasing the performance of the application. On the other hand, if the core is suffering rather high counts of MLC/LLC misses, there will be no benefit to increase core frequency since the performance is bounded by access latency to an off-chip component. In this situation, the system should scale down the core frequency and divert the saved power to other cores that may be doing useful work.
Therefore, AEPOL allows for an intelligent decision making on when to turn on turbo where performance will benefit and can be observed and it lowers the power dissipation with fine tuning performance power state on cores that are stalling on instruction

TABLE 1

PCU decision tree per core based on architectural event counters

Architectural	Count	Count	Count	Count	Count	Count
Events	threshold	threshold	threshold	threshold	threshold	threshold

Inst. Retired	Low	high	low	low	low	low
MLC Miss	low	don't care	high	high	low	low
LLC Miss	low	don't care	high	low	don't care	low
TLB Miss	low	don't care	don't care	don't care	don't care	high
Branch Miss	low	don't care	don't care	don't care	high	don't care
Final Decision	Power UP	Powr UP	Power Down	Power Down	Power Up	Power Down

There can be many more scenarios or other useful architectural event counters that can do finer grain control of the core power usage and the AEPOL logic is applicable to all these situations.
With AEPOL optimization, the system is given a smarter way to utilize the available power to the processor. In future processor design where power aware architecture must exist across the board, AEPOL not only provides a way to conserve energy when it is not needed, it also provides opportunity to optimize performance further within the same power budget. This mechanism opens a whole new range of opportunity for finer grain hardware tuning.
FIG. 3 illustrates a block diagram of a computing system 300 in accordance with an embodiment of the invention. The computing system 300 may include one or more central processing units(s) (CPUs) 31 or processors that communicate via an interconnection network (or bus) 49. The processors 31 may be any type of a processor such as a general purpose processor, a network processor (that processes data communicated over a computer network 48, or other types of a processor (including a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC). Moreover, the processors 31 may have a single or multiple core design. The processors 31 with a multiple core design may integrate different types of processor cores on the same integrated circuit (IC) die. Also, the processors 31 may utilize the embodiments discussed with references to FIGS. 1 and 2. For example, one or more of the processors 31 may include one or more processor cores 32. Also, the operations discussed with reference to FIGS. 1 and 2 may be performed by one or more components of the system 300.
A chipset 33 may also communicate with the interconnection network 49. The chipset 33 may include a memory control hub (MCH) 34. The MCH 34 may include a memory controller 36 that communicates with a memory 41. The memory 41 may store data and sequences of instructions that are executed by the CPU 31, or any other device included in the computing system 300. In one embodiment of the invention, the memory 41 may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM, (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or the like. Nonvolatile memory may also be utilized such as a hard disk. Additional devices may communicate via the interconnection network 49, such as multiple CPUs and/or multiple system memories.
The MCH 34 may also include a graphics interface 37 that communicates with a graphics accelerator 42. In one embodiment of the invention, the graphics interface 37 may communicate with the graphics accelerator 42 via an accelerated graphics port (AGP). In an embodiment of the invention, a display (such as a flat panel display) may communicate with the graphics interface 37 through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as a video memory or system memory into display signals that are interpreted and displayed by the display. The display signals produced by the display device may pass through various control devices before being interpreted by and subsequently displayed on the display.
A hub interface 51 may allow the MCH 34 to communicate with an input/output control hub (ICH) 38. The ICH 38 may provide an interface to I/O devices that communicate with components of the computing system 300. The ICH 38 may communicate with a bus 47 through a peripheral bridge (or controller) 39, such as a peripheral component interconnect (PCI) bridge, a universal serial bus (USB) controller, or the like. The bridge 39 may provide a data path between the CPU 31 and peripheral devices. Other types of topologies may be utilized. Also, multiple buses may communicate with the ICH 38, e.g. through multiple bridges or controllers. Moreover, other peripheral in communication with the ICH 38 may include, in various embodiments of the invention, integrated drive electronics (IDE) or small computer system interfaces (SCSI) hard drive(s), USB ports, a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), or the like.
The bus 47 may communicate with an audio device 43, one or more disk drive(s) 44, and a network interface device 46 (which communicates with the computer network 48). Other devices may be in communication with the bus 47. Also, various components (such as the network interface device 46) may be in communication with the MCH 34 in some embodiments of the invention. In addition, the processor 31 and the MCH 34 may be combined to form a single chip. Furthermore, the graphics accelerator 42 may be included within the MCH 34 in other embodiments of the invention.
Furthermore, the computing system 300 may include volatile and/or nonvolatile memory (or storage). For example, nonvolatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive (e.g., 44) a floppy disk, a compact disk ROM (CD-ROM), a digital versatile disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media capable of storing electronic instructions and/or data.
FIG. 4 illustrates a computing system 400 that is arranged in a point-to-point (PtP) configuration, according to an embodiment of the invention. In particular, FIG. 4 shows a system where processors, memory, and input/output devices are interconnected by a number of point to point interfaces. The operations discussed with reference to FIGS. 1-3 may be performed by one or more components of the system 400.
As illustrated in FIG. 4, the system 400 may include several processors, of which only two, processors 5, 10 are shown for clarity. The processors 5, 10 may each include a local memory controller hub (MCH) 15, 20 to allow communication with memories 15, 20. The memories 15, and/or 20 may store various data such as those discussed with reference to the memory 512.
The processors 5, 10 may be any type of a processor such as those discussed with reference to the processors 31 of FIG. 3. The processors 5, 10 may exchange data via a point-to-point interface 93 using PtP interface circuits 40 and 45, respectively. The processors 5, 10 may each exchange data with a chipset 50 via individual PtP interfaces 55, 60 using point to point interface circuits 65, 70, 75, 80. The chipset 50 may also exchange data with a high-performance graphics circuit 37 via a high performance graphic interface 97, using a PtP interface circuit 90.
At least one embodiment of the invention may be provided within the processors 5, 10. For example, one or more of the processor core (s) 32 may be located within the processors 5, 10. Other embodiments of the invention, however, may exist in other circuits, logic units, or devices with the system 400 of FIG. 6. Furthermore, other embodiments of the invention may be distributed throughout several circuits, logic units, or devices illustrated in FIG. 4.
The chipset 50 may communicate with a bus 16 using a PtP interface circuit 95. The bus 16 may have one or more devices that communicate with it, such as a bus bridge 18 and I/O devices 14. Via a bus 20, the bus bridge 14 may be in communication with other devices such as a keyboard/mouse 22, communication devices 26 (such as modems, network interface devices, etc. that may be in communication with the computer network 48), audio I/O devices, and/or a data storage device 28. The data storage device 28 may store code 30 that may be executed by the processors 5 and/or 10.
In various embodiments of the invention, the operations discussed herein, e.g., with reference to FIGS. 1-4 may be implemented by hardware (e.g., circuitry), software, firmware, microcode, or combinations thereof, which may be provided as a computer program product, e.g., including a machine readable or computer readable medium having stored thereon instructions (or software procedures) used to program a computer to perform a process discussed herein. Also, the term “logic” may include, by way of example, software, hardware, or combinations of software and hardware. The machine readable medium may include a storage device such as those discussed with respect to FIGS. 1-4.
Additionally, such computer readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (.g., a bus, a modem, or a network connection). Accordingly, herein, a carrier wave shall be regarded as comprising a machine readable medium.
Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.
Also, in the description and claims, the term “coupled” and “connected”, along with their derivatives, may be used. In some embodiments of the invention, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.
Thus, although embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.

Claims

What is claimed is:

1. A processor comprising:

a plurality of cores including a first core of a first core type and a second core of a second core type, wherein the first core and second core are able to operate concurrently at different frequencies in different power states;

a plurality of thermal sensors to provide thermal data, including at least a first thermal sensor to provide first thermal data for the first core and at least a second thermal sensor to provide second thermal data for the second core;

a plurality of counters integral to the first core, each counter to count a number of occurrences of an architectural event, the plurality of counters including a first counter to count a number of instructions retired, a second counter to count last level cache misses, a third counter to count translation lookaside buffer (TLB) misses, and a fourth counter to count branch mispredictions;

a system interconnect coupled to the plurality of cores, the system interconnect able to operate in a plurality of different power states; and

a power controller coupled to the system interconnect, the power controller to control the power states of the first core and the second core in accordance with the thermal data.

2. The processor of claim 1 wherein the power controller to control the power states of the interconnect in accordance with the thermal data.

3. The processor of claim 2 wherein the power controller is to control the power states of the system interconnect, the first core, and the second core in accordance with a specified power limit.

4. The processor of claim 1 wherein the power controller is to attempt to optimize performance within a specified thermal budget.

5. The processor of claim 2 wherein the first core is to operate at a first frequency in a first power state, the second core is to operate at a second frequency in a second power state, and the system interconnect is to operate at a third frequency in a third power state.

6. The processor of claim 4 further comprising:

a third thermal sensor in combination with the first thermal sensor to provide the first thermal data for the first core.

7. The processor of claim 1 further comprising:

a functional unit coupled to the plurality of cores over the system interconnect; and

a cache shared by the plurality of cores.

8. The processor of claim 7, further comprising:

a memory controller coupled to the system interconnect and a system memory device.

9. The processor of claim 8, further comprising:

a network interface coupled to the system interconnect;

a flash memory coupled to the interconnect; and

a display coupled to the system interconnect.

10. The processor of claim 1, wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on the first thermal data and/or the second thermal data.

11. The processor of claim 1 wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on current power states of the plurality of cores and the power limit.

12. The processor of claim 1 wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on performance data determined from one or more of the plurality of counters.

13. The processor of claim 1 wherein the plurality of counters integral to the first core comprise a first plurality of counters, the processor further comprising: a second plurality of counters integral to the second core, each counter of the second plurality of counters to count a number of occurrences of one of the architectural events, the second plurality of counters including a fifth counter to count a number of instructions retired, a sixth counter to count last level cache misses, a seventh counter to count translation lookaside buffer (TLB) misses, and an eighth counter to count branch mispredictions.

14. A method comprising:

operating a plurality of cores at a plurality of different frequencies associated with different power states, the plurality of cores including a first core of a first core type and a second core of a second core type;

providing thermal data from a plurality of thermal sensors, including providing first thermal data from a first thermal sensor associated with the first core and providing second thermal data from a second thermal sensor associated with the second core;

counting, by a plurality of counters integral to the first core, a corresponding number of occurrences of architectural events, the plurality of counters including a first counter to count a number of instructions retired, a second counter to count last level cache misses, a third counter to count translation lookaside buffer (TLB) misses, and a fourth counter to count branch mispredictions;

operating a system interconnect coupled to the plurality of cores in a plurality of different power states; and

controlling, by a power controller coupled to the system interconnect, the power states of the first core and the second core in accordance with the thermal data.

15. The method of claim 14 further comprising:

controlling, by the power controller, the power states of the interconnect in accordance with the thermal data.

16. The method of claim 15 further comprising:

controlling, by the power controller, the power states of the system interconnect, the first core, and the second core in accordance with a specified power limit.

17. The method of claim 14 wherein controlling further comprises:

attempting to optimize performance within a specified thermal budget.

18. The method of claim 15 wherein the first core is to operate at a first frequency in a first power state, the second core is to operate at a second frequency in a second power state, and the system interconnect is to operate at a third frequency in a third power state.

19. The method of claim 17 further comprising:

providing a portion of the first thermal data from a third thermal sensor associated with the first core.

20. The method of claim 14 wherein a functional unit is coupled to the plurality of cores over the system interconnect and a cache is shared by the plurality of cores.

21. The method of claim 20, wherein a memory controller is coupled to the system interconnect and a system memory device.

22. The method of claim 21, wherein a network interface is coupled to the system interconnect, a flash memory is coupled to the interconnect, and a display is coupled to the system interconnect.

23. The method of claim 14, wherein controlling further comprises the power controller determining whether to modify a power state of one of the plurality of cores based on the first thermal data and/or the second thermal data.

24. The method of claim 23 wherein controlling further comprises the power controller determining whether to modify a power state of one of the plurality of cores based on current power states of the plurality of cores and the power limit.

25. The method of claim 14 wherein controlling further comprises the power controller determining whether to modify a power state of one of the plurality of cores based on performance data determined from one or more of the plurality of counters.

26. The method of claim 14 wherein the plurality of counters comprise a first plurality of counters, the method further comprising:

counting, by a second plurality of counters integral to the second core, a corresponding number of occurrences of architectural events, the plurality of counters including a first counter to count a number of instructions retired, a second counter to count last level cache misses, a third counter to count translation lookaside buffer (TLB) misses, and a fourth counter to count branch mispredictions.

27. A system comprising:

a system memory to store program code and data; and

a processor coupled to the memory, the processor comprising:

a plurality of counters integral to the first core, each counter to count a number of occurrences of one of the architectural events, the plurality of counters including a first counter to count a number of instructions retired, a second counter to count last level cache misses, a third counter to count translation lookaside buffer (TLB) misses, and a fourth counter to count branch mispredictions;

28. The system of claim 27 wherein the power controller to control the power states of the interconnect in accordance with the thermal data.

29. The system of claim 28 wherein the power controller is to control the power states of the system interconnect, the first core, and the second core in accordance with a specified power limit.

30. The system of claim 27 wherein the power controller is to attempt to optimize performance within a specified thermal budget.

31. The system of claim 28 wherein the first core is to operate at a first frequency in a first power state, the second core is to operate at a second frequency in a second power state, and the system interconnect is to operate at a third frequency in a third power state.

32. The system of claim 30 further comprising:

33. The system of claim 27 further comprising:

a cache shared by the plurality of cores.

34. The system of claim 33, further comprising:

a memory controller coupled to the system interconnect and the system memory.

35. The system of claim 34, further comprising:

a network interface coupled to the system interconnect;

a flash memory coupled to the interconnect; and

a display coupled to the system interconnect.

36. The system of claim 27, wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on the first thermal data and/or the second thermal data.

37. The system of claim 27 wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on current power states of the plurality of cores and the power limit.

38. The system of claim 27 wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on performance data determined from one or more of the plurality of counters.

39. The system of claim 27 wherein the plurality of counters integral to the first core comprise a first plurality of counters, the system further comprising: a second plurality of counters integral to the second core, each counter of the second plurality of counters to count a number of occurrences of one of the architectural events, the second plurality of counters including a fifth counter to count a number of instructions retired, a sixth counter to count last level cache misses, a seventh counter to count translation lookaside buffer (TLB) misses, and an eighth counter to count branch mispredictions.