US20200395298A1 - Semiconductor device, associated method and layout - Google Patents
Semiconductor device, associated method and layout Download PDFInfo
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- US20200395298A1 US20200395298A1 US16/442,251 US201916442251A US2020395298A1 US 20200395298 A1 US20200395298 A1 US 20200395298A1 US 201916442251 A US201916442251 A US 201916442251A US 2020395298 A1 US2020395298 A1 US 2020395298A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5221—Crossover interconnections
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Abstract
A semiconductor device includes gate strips, first metal strips and second metal strips. The first metal strips are formed above the gate strips. The first metal strips are co-planar, and each first metal strip and one of the gate strips are crisscrossed. The second metal strips are formed above the first metal strips. The second metal strips are co-planar, and each second metal strip and one of the first metal strips are crisscrossed. One first metal strip connects to one gate strip crossing underneath by a first contact via without connecting to one second metal strip crossing over. A length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one first metal strips is smaller than two and a half times as the length between two adjacent gate strips.
Description
- Due to complex process rules, the lack of routing resource is a challenge for the design of integrated circuit (IC), especially in the advance process. In order to own good pin access ability for achieving smaller chip area and better performance, a novel design is required.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 is a diagram illustrating a cross-sectional perspective of a part of a semiconductor device in accordance with an embodiment of the present disclosure. -
FIG. 2 is a diagram illustrating a top view of gate strips, metal strips in the metal layers M0 and M1 in a semiconductor device in accordance with an embodiment of the present disclosure. -
FIG. 3 is a diagram illustrating a top view of the gate strips and the strips in the metal layer M1 in semiconductor device in accordance with an embodiment of the present disclosure. -
FIGS. 4A and 4B are diagrams illustrating a top view of the gate strips and a strip in the metal layer M0 in a semiconductor device in accordance with an embodiment of the present disclosure. -
FIGS. 5A and 5B are diagrams illustrating a pattern of the gate strips, and the strips in the metal layer M0 in a semiconductor device in according with an embodiment of the present disclosure. -
FIGS. 6A and 6B are diagrams illustrating a pattern of the gate strips, and the strips in the metal layer M0 in a semiconductor device in according with another embodiment of the present disclosure. -
FIGS. 7 to 12 are diagrams illustrating a top view of a part of a circuit layout in a semiconductor device in accordance with an embodiment of the present disclosure. -
FIG. 13 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present disclosure. -
FIG. 14 is a diagram illustrating a system according to an embodiment of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the term “about” generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term “about” means within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.
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FIG. 1 is a diagram illustrating a cross-sectional perspective of a part of asemiconductor device 10 in accordance with an embodiment of the present disclosure. Thesemiconductor device 10 includes a substrate SUB, agate layer 110 and a plurality of metal layers M0, M1, . . . , MN. The substrate SUB includes twodoping regions doping region gate layer 110 includes a plurality of gate strips such as thegate strip 130 shown inFIG. 1 Each gate strip is configured to be a gate terminal of the transistor. In some embodiments, each gate strip is made of conductive material such as copper, aluminum, tungsten, or the alloy of the aforementioned materials. In some embodiments, each gate strip is made of polysilicon. It should be noted that the material of each gate strip is not limited by the present disclosure. - The metal layers M0, M1, . . . , MN constitute an interconnection metal layer of the
semiconductor device 10. The metal layer M0 is the bottom layer in the interconnection metal layer, then the metal layer M1, and so on. The metal layer M0 includes a plurality of metal strips such as thestrips FIG. 1 . Thestrips drain regions strips 143 connects to thegate strip 130 via a contact via VG. The plurality of metal strips such as thestrips strip 144 is configured to receive a reference voltage, and not connected to either the source/drain region or the gate terminal. In other words, the connections between the metal layer M0 and the source/drain region and thegate layer 110 depends on the practical design. - The metal layer M1 is disposed above the metal layer M0. The metal layer M1 includes a plurality of metal strips such as the
strips FIG. 1 . In some embodiments, the strips in the metal layer M1 are connected to the strips in the metal M0 via contact vias. For example, thestrips strips -
FIG. 2 is a diagram illustrating a top view of gate strips, metal strips in the metal layers M0 and M1 in thesemiconductor device 10 in accordance with an embodiment of the present disclosure. As shown in the sub-diagram (A) ofFIG. 2 , the gate strips G1, G2, G3 and G4 extend in a first direction, for example, y-direction from a top view. As shown in the sub-diagram (B) ofFIG. 2 , the strips in the metal layer M0 extend in a second direction, for example, x-direction from a top view. In other words, the strips in the metal layer M0 and the gate strips are crisscrossed from a top view. As shown in the sub-diagram (C) ofFIG. 2 , the strips in the metal layer M1 extends in the first direction, for example, y-direction. In other words, the strips in the metal layer M1 and the strip in the metal M0 are crisscrossed from a top view. However, this is only for illustrative purpose, in other embodiments, the strips in the metal layer M0 extends in the first direction same as the gate strips G1, G2, G3 and G4. -
FIG. 3 is a diagram illustrating a top view of the gate strips and the strips in the metal layer M1 in thesemiconductor device 10 in accordance with an embodiment of the present disclosure. As shown in the sub-diagram (A) ofFIG. 3 , a length L1 (or so-called a poly pitch) between two adjacent gate strips (e.g., the gate strips G1 and G2) is twice as a length L2 (or so-called a M1 pitch) between two adjacent strips (e.g., 301 and 302) in the metal layer M1. With such configurations, the circuit design becomes more flexible due to the ratio between the poly pitch and the M1 pitch is integer (i.e., 2:1). Accordingly, the pin access point configured to be an input terminal or an output terminal of a circuit can be increased, and the routing resource can be greatly released. In addition, due to the lack of routing resource is improved, the chip area can be reduced. - As mentioned in the embodiment of
FIG. 2 , the strips in the metal layer M0 can extend in the same direction as the gate strips. With such configurations, the length between two adjacent gate strips, e.g., the gate strips G1 and G2, is twice as a length (or so-called M0 pitch) between two adjacent strip in the metal layer M0. - It should be noted that, to facilitate the manufacturing process, the length between two adjacent gate strips, e.g., the gate strips G1 and G2, is not required to be exactly twice as the length between two adjacent strips in the metal layer M1. As shown in the sub-diagram (B) of
FIG. 3 , the length between thestrips strips - The process of manufacturing the strips in the metal layer M1 can utilize double patterning technique, that is, two photolithography operations are performed upon the same layer. More specifically, a mask for the photolithography operation is fabricated first. Next, a first photolithography operation is executed on a dielectric layer with the fabricated mask, and a first patterned mask is generated. The first patterned mask includes a plurality of strip-shaped openings. The strip-shaped openings are prepared for the
strips FIG. 3 , that is, a length between two adjacent strip-shaped openings equals to the length between two adjacent gate strips. Next, a conductive material is filled into the strip-shaped openings to generate thestrips FIG. 3 , and a transition patterned mask is generated. Next, a second photolithography operation is executed upon the transition patterned mask to generate a second patterned mask. The second patterned mask includes a plurality of strip-shaped openings. The plurality of strip-shaped openings are prepared for thestrips FIG. 3 , that is, a length between two adjacent strip-shaped openings equals to the length between two adjacent gate strips. Next, a conductive material is filled into the strip-shaped openings to generate thestrips FIG. 3 . Accordingly, thestrips 301 to 307 in the metal layer M1 are generated. - It should be noted that for the upper metal layers (e.g., the metal layers M2 to MN) in the
semiconductor device 10, masks for the following photolithography operations are fabricated. Those skilled in the art should readily understand the following photolithography operations for manufacturing the upper metal layers, the detailed description is omitted here for brevity. -
FIGS. 4A and 4B are diagrams illustrating a pattern of the gate strips, the strips in the metal layers M0 and M1 in thesemiconductor device 10 in according with an embodiment of the present disclosure. In this embodiment, astrip 401 in the metal layer M1 crosses over astrip 402 in the metal layer M2. Thestrip 401 in the metal layer M1 connects to two other strips in the metal layer M0 by contact vias V0 1 and V0 2. Thestrip 402 in the metal layer M0 crosses over gate strips G1 and G2, and a length L3 of thestrip 402 is smaller than two and a half times as the length L1 between two adjacent gate strips (e.g., G1 and G2). With such configurations, when thestrip 402 is configured to receive an input signal or output an output signal of a standard cell, thestrip 402 can be configured to be an access point without connecting to the upper metal layer (e.g., thestrip 401 or any other strip in the metal layer M1 crossing over the strip 402). In other words, thestrips 402 is configured to be a M0 pin. When thestrips 402 is configured to be a M0 pin, it connects to a gate strip crossing underneath via a contact via. For example, as shown inFIG. 4A , thestrip 402 connects to the gate strip G1 crossing underneath via a contact via VG1. For another example, as shown inFIG. 4B , thestrip 402 connects to the gate strip G2 crossing underneath via a contact via VG2. -
FIGS. 5A and 5B are diagrams illustrating a pattern of the gate strips, and the strips in the metal layer M0 in thesemiconductor device 10 in according with an embodiment of the present disclosure. As shown inFIG. 5A , twoadjacent strips strips strip 501 is as long as thestrip 502, and the length L4 of thestrips strips strips strips strips FIG. 5A , thestrip 501 connects to the gate strip G1 crossing underneath via a contact via VG1 while thestrip 502 connects to the gate strip G2 crossing underneath via a contact via VG2. For another example, as shown inFIG. 5B , thestrip 501 connects to the gate strip G2 crossing underneath via a contact via VG3 while thestrip 502 connects to the gate strip G1 crossing underneath via a contact via VG4. -
FIGS. 6A and 6B are diagrams illustrating a pattern of the gate strips, and the strips in the metal layer M0 in thesemiconductor device 10 in according with another embodiment of the present disclosure. As shown inFIG. 6A , twoadjacent strips strips strip 601 is smaller than two and a half times as the length L1 between two adjacent gate strips (e.g., G1 and G2). In contrary, a length L6 of thestrip 602 is not smaller (i.e., greater or equal) than two and a half times as the length L1 between two adjacent gate strips (e.g., G1 and G2). - With such configurations, when each of the
strips strips strips strips - For example, as shown in
FIG. 6A , thestrip 601 connects to the gate strip G1 crossing underneath via a contact via VG1 while thestrip 602 connects to the gate strip G2 crossing underneath via a contact via VG2. For another example, as shown inFIG. 6B , thestrip 601 connects to the gate strip G2 crossing underneath via a contact via VG3 while thestrip 602 connects to the gate strip G1 crossing underneath via a contact via VG4. -
FIG. 7 is a diagram illustrating a top view of a part of acircuit layout 70 in thesemiconductor device 10 in accordance with an embodiment of the present disclosure. In this embodiment, thecircuit layout 70 represents an And-Or-Inverter (AOI) logic standard cell. More specifically,circuit layout 70 is an AOI211 standard cell, wherein the AOI211 standard cell means two inputs are received by an AND gate logic while two other inputs and the output of the AND gate are received by an NOR gate logic. Thecircuit layout 70 is stored on a non-transitory computer-readable medium, for example, on a Taiwan Semiconductor Manufacturing Company (TSMC) cell library. When thesemiconductor device 10 is designed, thecircuit layout 70 is retrieved from the cell library. - The
circuit layout 70 includes a plurality of gate strips, e.g., the gate strips 707 and 708, wherein each of the gate strips can be implemented by the gate strip mentioned in the embodiment ofFIG. 1 . Each of the gate strips extends in a first direction, for example, y-direction. - The
circuit layout 70 further includes a plurality of metal strips in the metal layer M0, e.g., thestrips circuit layout 70 further includes ametal strip 701 in the metal layer M1. Themetal strip 701 extends in the first direction same as the gate strips 707 and 708. - The
strip 701 in the metal layer M1 crosses over thestrip 702 in the metal layer M0, and thestrip 701 connects to twostrips strip 702 in the metal layer M0 is smaller than two and a half times as the length between two adjacent gate strips. Following the pattern mentioned in the embodiment ofFIG. 4 , when thestrip 702 is configured to receive an input signal or output an output signal of the AOI211 standard cell, thestrip 702 is configured to be a M0 pin, and not connected to any metal strip crossing over. When thestrip 702 is configured to be a M0 pin, it connects to a gate strip crossing underneath (e.g., the gate strip 707) by a contact via VG5. - Except the
strip 702 in the metal layer M2, the circuit layout further includesstrips strip 711 in the metal layer M2 connects to agate strip 714 crossing underneath by a contact via VG6, thestrip 712 in the metal layer M2 connects to agate strip 715 crossing underneath by a contact via VGA, and thestrip 713 in the metal layer M2 connects to agate strip 716 crossing underneath by a contact via VG8. A length between thestrips circuit layout 70. In this embodiment, the cell height CH is about 60 to 150 nanometer(nm). -
FIG. 8 is a diagram illustrating a top view of a part of acircuit layout 80 in thesemiconductor device 10 in accordance with another embodiment of the present disclosure. In this embodiment, thecircuit layout 80 represents another AOI211 logic standard cell. Thecircuit layout 80 is stored on a non-transitory computer-readable medium, for example, on a TSMC cell library. When thesemiconductor device 10 is designed, thecircuit layout 80 is retrieved from the cell library. - The
circuit layout 80 includes a plurality of gate strips, e.g., the gate strips 807 and 808, wherein each of the gate strips can be implemented by the gate strip mentioned in the embodiment ofFIG. 1 . Each of the gate strips extends in a first direction, for example, y-direction. - The
circuit layout 80 further includes a plurality of metal strips in the metal layer M0, e.g., thestrips circuit layout 80 further includes ametal strip 801 in the metal layer M1. Themetal strip 801 extends in the first direction same as the gate strips 807 and 808. - The
strip 801 in the metal layer M1 crosses over thestrip 802 in the metal layer M0, and thestrip 801 connects to twostrips strip 802 in the metal layer M0 is smaller than two and a half times as the length between two adjacent gate strips. Following the pattern mentioned in the embodiment ofFIG. 4 , when thestrip 802 is configured to receive an input signal or output an output signal of the AOI211 standard cell, thestrip 802 is configured to be a M0 pin, and not connected to any metal strip crossing over. When thestrip 802 is configured to be a M0 pin, it connects to a gate strip crossing underneath (e.g., the gate strip 807) by a contact via VG5. - Except the
strip 802 in the metal layer M2, the circuit layout further includesstrips strip 811 in the metal layer M2 connects to agate strip 814 crossing underneath by a contact via VG6, thestrip 812 in the metal layer M2 connects to agate strip 815 crossing underneath by a contact via VG7, and thestrip 813 in the metal layer M2 connects to agate strip 816 crossing underneath by a contact via VG8. A length between thestrips circuit layout 80. In this embodiment, the cell height CH is about 60 to 150 nanometer(nm). -
FIG. 9 is a diagram illustrating a top view of a part of acircuit layout 90 in thesemiconductor device 10 in accordance with another embodiment of the present disclosure. In this embodiment, thecircuit layout 90 represents an AOI22 logic standard cell, wherein the AOI22 standard cell means two inputs are received by an AND gate logic while two other inputs are received by another AND gate, and the outputs of both AND gates are received by an NOR gate logic. Thecircuit layout 90 is stored on a non-transitory computer-readable medium, for example, on a TSMC cell library. When thesemiconductor device 10 is designed, thecircuit layout 90 is retrieved from the cell library. - The
circuit layout 90 includes a plurality of gate strips, e.g., the gate strips 907 and 908, wherein each of the gate strips can be implemented by the gate strip mentioned in the embodiment ofFIG. 1 . Each of the gate strips extends in a first direction, for example, y-direction. - The
circuit layout 90 further includes a plurality of metal strips in the metal layer M0, e.g., thestrips circuit layout 90 further includes ametal strip 901 in the metal layer M1. Themetal strip 901 extends in the first direction same as the gate strips 907 and 908. - The
strip 901 in the metal layer M1 crosses over thestrip 902 in the metal layer M0, and connects to twostrips strip 902 in the metal layer M0 is smaller than two and a half times as the length between two adjacent gate strips. Following the pattern mentioned in the embodiment ofFIG. 4 , when thestrip 902 is configured to receive an input signal or output an output signal of the AOI22 standard cell, thestrip 902 is configured to be a M0 pin, and not connected to any metal strip crossing over. When thestrip 902 is configured to be a M0 pin, it connects to a gate strip crossing underneath (e.g., the gate strip 907) by a contact via VG5. - Except the
strip 902 in the metal layer M2, the circuit layout further includesstrips strip 911 in the metal layer M2 connects to agate strip 914 crossing underneath by a contact via VG6, thestrip 912 in the metal layer M2 connects to agate strip 915 crossing underneath by a contact via VG7, and thestrip 913 in the metal layer M2 connects to agate strip 916 crossing underneath by a contact via VG8. A length between thestrips circuit layout 90. In this embodiment, the cell height CH is about 60 to 150 nanometer(nm). -
FIG. 10 is a diagram illustrating a top view of a part of acircuit layout 100 in thesemiconductor device 10 in accordance with another embodiment of the present disclosure. In this embodiment, thecircuit layout 100 represents another AOI22 logic standard cell. Thecircuit layout 100 is stored on a non-transitory computer-readable medium, for example, on a TSMC cell library. When thesemiconductor device 10 is designed, thecircuit layout 100 is retrieved from the cell library. - The
circuit layout 100 includes a plurality of gate strips, e.g., the gate strips 1007 and 1008, wherein each of the gate strips can be implemented by the gate strip mentioned in the embodiment ofFIG. 1 . Each of the gate strips extends in a first direction, for example, y-direction. - The
circuit layout 100 further includes a plurality of metal strips in the metal layer M0, e.g., thestrips circuit layout 100 further includes ametal strip 1001 in the metal layer M1. Themetal strip 1001 extends in the first direction same as the gate strips 1007 and 1008. - The
strip 1001 in the metal layer M1 crosses over thestrip 1002 in the metal layer M0, and connects to twostrips strip 1002 in the metal layer M0 is smaller than two and a half times as the length between two adjacent gate strips. Following the pattern mentioned in the embodiment ofFIG. 4 , when thestrip 1002 is configured to receive an input signal or output an output signal of the AOI22 standard cell, thestrip 1002 is configured to be a M0 pin, and not connected to any metal strip crossing over. When thestrip 1002 is configured to be a M0 pin, it connects to a gate strip crossing underneath (e.g., the gate strip 1007) by a contact via VG5. - Except the
strip 1002 in the metal layer M2, the circuit layout further includesstrips strip 1011 in the metal layer M2 connects to agate strip 1014 crossing underneath by a contact via VG6, thestrip 1012 in the metal layer M2 connects to agate strip 1015 crossing underneath by a contact via VG7, and thestrip 1013 in the metal layer M2 connects to agate strip 1016 crossing underneath by a contact via VG8. A length between thestrips circuit layout 100. In this embodiment, the cell height CH is about 60 to 150 nanometer(nm). -
FIG. 11 is a diagram illustrating a top view of a part of acircuit layout 1100 in thesemiconductor device 10 in accordance with another embodiment of the present disclosure. Thecircuit layout 1100 includes a plurality of gate strips, e.g., the gate strips 1105 and 1106, wherein each of the gate strips can be implemented by the gate strip mentioned in the embodiment ofFIG. 1 . Each of the gate strips extends in a first direction, for example, y-direction. The circuit layout can be an AN4D1 standard cell stored on a non-transitory computer-readable medium, for example, on a TSMC cell library. When thesemiconductor device 10 is designed, thecircuit layout 1100 is retrieved from the cell library. - The
circuit layout 1100 further includes a plurality of metal strips in the metal layer M0, e.g., thestrips circuit layout 1100 further includes ametal strip 1107 in the metal layer M1. Themetal strip 1107 extends in the first direction same as the gate strips 1105 and 1106. - The
adjacent strips strips FIG. 5 , when each of thestrips circuit layout 1100, each of thestrips strips strips circuit layout 1100. In this embodiment, the cell height CH is about 60 to 150 nanometer(nm). -
FIG. 12 is a diagram illustrating a top view of a part of acircuit layout 1200 in thesemiconductor device 10 in accordance with another embodiment of the present disclosure. Thecircuit layout 1200 includes a plurality of gate strips, e.g., the gate strips 1205 and 1206, wherein each of the gate strips can be implemented by the gate strip mentioned in the embodiment ofFIG. 1 . Each of the gate strips extends in a first direction, for example, y-direction. The circuit layout can be an ND4D1 standard cell stored on a non-transitory computer-readable medium, for example, on a TSMC cell library. When thesemiconductor device 10 is designed, thecircuit layout 1200 is retrieved from the cell library. - The
circuit layout 1200 further includes a plurality of metal strips in the metal layer M0, e.g., thestrips circuit layout 1200 further includes ametal strip 1207 in the metal layer M1. Themetal strip 1207 extends in the first direction same as the gate strips 1205 and 1206. - The
adjacent strips strip 1201 is smaller than two and a half times as the length between two adjacent gate strips, while the length of thestrips 1202 is greater than two and a half times as the length between two adjacent gate strips. Following the pattern mentioned in the embodiment ofFIG. 6 , when each of thestrips circuit layout 1200, each of thestrips strips strips circuit layout 1200. In this embodiment, the cell height CH is about 60 to 150 nanometer(nm). -
FIG. 13 is a flowchart illustrating a method 1300 of manufacturing a semiconductor device in accordance with an embodiment of the present disclosure. Provided that the results are substantially the same, the steps shown inFIG. 13 are not required to be executed in the exact order. The method 1300 is summarized as follow. - Step 1301: a plurality of gate strips are formed.
- Step 1302: a plurality of first contact vias connecting to a part of the gate strips are formed.
- Step 1303: a plurality of first metal strips are formed above the plurality of gate strips, wherein each first metal strip and one of the gate strips are crisscrossed from top view.
- Step 1304: one of the first metal strips is connected to one of the first contact vias.
- Step 1305: a plurality of second contact vias are formed above a part of the first metal strips excluding said one of the first metal strips.
- Step 1306: a plurality of second metal strips are formed above the plurality of first metal strips, wherein each second metal strip and one of the first metal strips are crisscrossed from top view.
- Those skilled in the art should readily understand the detail of the method 1300 after reading the embodiments of
FIG. 1 toFIG. 12 . The detailed description is omitted here for brevity. -
FIG. 14 is a diagram illustrating asystem 1400 according to an embodiment of the present disclosure. Thesystem 1400 includes astorage device 1401, e.g., a memory, and aprocessor 1402. Thestorage device 1401 is arranged to store a program code PROG. When the program code PROG is executed by theprocessor 1402, thesystem 1400 execute the layout implementation mentioned in the embodiments ofFIGS. 1 to 12 , and controls thefabrication tools 1500 to physical implementation to fabricate the layouts. Those skilled in the art should readily understand the operation of thefabrication tools 1500 after reading the embodiments ofFIG. 1 toFIG. 13 . The detailed description is omitted here for brevity. - In some embodiments, a semiconductor device is disclosed. The semiconductor device includes a plurality of gate strips, a plurality of first metal strips and a plurality of second metal strips. Each gate strip is arranged to be a gate terminal of a transistor. The plurality of first metal strips are formed above the plurality of gate strips, wherein the plurality of first metal strips are co-planar, and each first metal strip and one of the gate strips are crisscrossed from top view. The plurality of second metal strips are formed above the first metal strips, wherein the plurality of second metal strips are co-planar, and each second metal strip and one of the first metal strips are crisscrossed from top view. One of the first metal strips connects to one of gate strips crossing underneath by a first contact via without connecting to one of second metal strips crossing over. A length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.
- In some embodiments, a method of manufacturing a semiconductor device is disclosed. The method includes: forming a plurality of gate strips, wherein each gate strip is arranged to be a gate terminal of a transistor; forming a plurality of first contact vias connecting to a part of the gate strips; forming a plurality of first metal strips above the plurality of gate strips, wherein the plurality of first metal strips are co-planar, and each first metal strip and one of the gate strips are crisscrossed from top view; connecting one of the first metal strips to one of the first contact vias; forming a plurality of second contact vias above a part of the first metal strips excluding said one of the first metal strips; forming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, and each second metal strip and one of the first metal strips are crisscrossed from top view; fabricating masks for manufacturing the semiconductor device; and manufacturing the semiconductor device based on the fabricated masks; wherein a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.
- In some embodiments, a layout of an integrated circuit (IC) is disclosed. The layout is stored on a non-transitory computer-readable medium, and includes: a plurality of gate strips, a plurality of first metal strips and a plurality of first metal strips. Each gate strip is arranged to be a gate terminal of a transistor. The plurality of first metal strips are formed above the plurality of gate strips, wherein the plurality of first metal strips are co-planar, and each first metal strip and one of the gate strips are crisscrossed from top view. The plurality of second metal strips are formed above the first metal strips, wherein the plurality of second metal strips are co-planar, and each second metal strip and one of the first metal strips are crisscrossed from top view. One of the first metal strips connects to one of gate strips crossing underneath by a first contact via without connecting to one of second metal strips crossing over. A length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.
Claims (21)
1. A semiconductor device, comprising:
a plurality of gate strips, wherein each gate strip is arranged to be a gate terminal of a transistor;
a plurality of first metal strips, formed above the plurality of gate strips, wherein the plurality of first metal strips are co-planar, and each first metal strip and one of the gate strips are crisscrossed from top view; and
a plurality of second metal strips, formed above the first metal strips, wherein the plurality of second metal strips are co-planar, and each second metal strip and one of the first metal strips are crisscrossed from top view;
wherein one of the first metal strips connects to one of gate strips crossing underneath by a first contact via without connecting to one of second metal strips crossing over;
wherein a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.
2. The semiconductor device of claim 1 , wherein one of the second metal strips connects to two first metal strips by respective a second contact via and a third contact via, and said two first metal strips exclude said one of the first metal strips; wherein said one of the second metal strips crosses said one of the first metal strips from top view.
3. The semiconductor device of claim 1 , wherein another one of the first metal strips connects to another one of the gate strips via a second contact via without connecting to one of the second metal strips crossing over.
4. The semiconductor device of claim 3 , wherein said another one of the first metal strips is next to said one of the first metal strips.
5. The semiconductor device of claim 4 , wherein a length of said another one of the first metal strip is smaller than two and a half times as the length between two adjacent gate strips.
6. The semiconductor device of claim 1 , wherein two of the first metal strips receive respective a first reference voltage and a second reference voltage, four other first metal strips are arranged between said two of the first metal strips in parallel.
7. The semiconductor device of claim 6 , wherein a length between said two of the first metal strips ranges from about 60 to 150 nanometer(nm).
8-15. (canceled)
16. A layout of an integrated circuit (IC), wherein the layout is stored on a non-transitory computer-readable medium, comprising:
a plurality of gate strips, wherein each gate strip is arranged to be a gate terminal of a transistor;
a plurality of first metal strips, formed above the plurality of gate strips, wherein each first metal strip and one of the gate strips are crisscrossed from top view; and
a plurality of second metal strips, formed above the first metal strips, wherein each second metal strip and one of the first metal strips are crisscrossed from top view;
wherein one of the first metal strips connects to one of gate strips crossing underneath by a first contact via without connecting to one of second metal strips crossing over;
wherein a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.
17. The layout of claim 16 , wherein one of the second metal strips connects to two first metal strips by respective a second contact via and a third contact via, and said two first metal strips exclude said one of the first metal strips;
wherein said one of the second metal strips crosses said one of the first metal strips from top view.
18. The layout of claim 16 , wherein another one of the first metal strips connects to another one of the gate strips via a second contact via without connecting to one of the second metal strips crossing over.
19. The layout of claim 18 , wherein said another one of the first metal strips is next to said one of the first metal strips.
20. The layout of claim 19 , wherein a length of said another one of the first metal strip is smaller than two and a half times as the length between two adjacent gate strips.
21. The layout of claim 20 , wherein two of the first metal strips receive respective a first reference voltage and a second reference voltage, four other first metal strips are arranged between said two of the first metal strips in parallel.
22. The layout of claim 21 , wherein a length between said two of the first metal strips ranges from about 60 to 150 nanometer(nm).
23. A layout of an integrated circuit (IC), wherein the layout is stored on a non-transitory computer-readable medium, comprising:
a first patterned layer, including a plurality of gate strips equally disposed and extending in a first direction, wherein every two immediately adjacent gate strip are distanced from a first length;
a first conductive layer above the first patterned layer, including:
a first conductive pattern, extending in a second direction and including a first row and a second row crossing over the plurality of gate strips;
a second conductive pattern, extending in the second direction and disposed between the first row and the second row, wherein the second conductive pattern connects to one of the plurality of gate strips; and
a second conductive layer above the first conductive layer, including a plurality of conductive strips equally disposed and extending in the first direction, wherein every two immediately adjacent conductive strip are distanced from a second length, and the first length is twice as the second length;
wherein the second conductive pattern is free from connecting to the second conductive layer, and a length of the second conductive pattern in the second direction is smaller than two and a half times as the first length.
24. The layout of claim 23 , wherein the second conductive pattern includes a first conductive strip and a second conductive strip immediately adjacent to the first conductive strip, and the first conductive strip is connected to one of the gate strips and the second conductive strip is connected to another one of the gate strips.
25. The layout of claim 24 , wherein one of the plurality of conductive strips in the second conductive layer crosses over the first conductive strip from a top view and is free from crossing over the second conductive strip from the top view.
26. The layout of claim 25 , wherein the first conductive layer further includes a third conductive pattern disposed between the first row and the second conductive pattern, and said one of the plurality of conductive strips is connected to the third conductive pattern.
27. The layout of claim 23 , wherein the first row and the second row receive respective a first reference voltage and a second reference voltage.
28. The layout of claim 28 , wherein a length between the first row and the second row ranges from about 60 to 150 nanometer(nm).
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/442,251 US10867917B1 (en) | 2019-06-14 | 2019-06-14 | Semiconductor device, associated method and layout |
TW108146776A TW202046376A (en) | 2019-06-14 | 2019-12-19 | Semiconductor device, associated method and layout |
CN202010120919.XA CN112086449A (en) | 2019-06-14 | 2020-02-26 | Semiconductor device, method of manufacturing semiconductor device, and layout of integrated circuit |
US17/115,422 US11569167B2 (en) | 2019-06-14 | 2020-12-08 | Method of manufacturing semiconductor device |
US18/066,292 US11923301B2 (en) | 2019-06-14 | 2022-12-15 | Method of manufacturing semiconductor device |
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US16/442,251 US10867917B1 (en) | 2019-06-14 | 2019-06-14 | Semiconductor device, associated method and layout |
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US10867917B1 US10867917B1 (en) | 2020-12-15 |
US20200395298A1 true US20200395298A1 (en) | 2020-12-17 |
Family
ID=73735072
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US16/442,251 Active US10867917B1 (en) | 2019-06-14 | 2019-06-14 | Semiconductor device, associated method and layout |
US17/115,422 Active 2040-02-03 US11569167B2 (en) | 2019-06-14 | 2020-12-08 | Method of manufacturing semiconductor device |
US18/066,292 Active US11923301B2 (en) | 2019-06-14 | 2022-12-15 | Method of manufacturing semiconductor device |
Family Applications After (2)
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US17/115,422 Active 2040-02-03 US11569167B2 (en) | 2019-06-14 | 2020-12-08 | Method of manufacturing semiconductor device |
US18/066,292 Active US11923301B2 (en) | 2019-06-14 | 2022-12-15 | Method of manufacturing semiconductor device |
Country Status (3)
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US (3) | US10867917B1 (en) |
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Families Citing this family (2)
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KR20210137276A (en) * | 2020-05-07 | 2021-11-17 | 삼성전자주식회사 | Semiconductor device |
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US10867917B1 (en) * | 2019-06-14 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device, associated method and layout |
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- 2019-06-14 US US16/442,251 patent/US10867917B1/en active Active
- 2019-12-19 TW TW108146776A patent/TW202046376A/en unknown
-
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- 2020-02-26 CN CN202010120919.XA patent/CN112086449A/en active Pending
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Also Published As
Publication number | Publication date |
---|---|
US11569167B2 (en) | 2023-01-31 |
US20230115672A1 (en) | 2023-04-13 |
TW202046376A (en) | 2020-12-16 |
CN112086449A (en) | 2020-12-15 |
US20210091000A1 (en) | 2021-03-25 |
US10867917B1 (en) | 2020-12-15 |
US11923301B2 (en) | 2024-03-05 |
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