US20200373436A1 - Structure of memory device and fabrication method thereof - Google Patents
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- US20200373436A1 US20200373436A1 US16/452,311 US201916452311A US2020373436A1 US 20200373436 A1 US20200373436 A1 US 20200373436A1 US 201916452311 A US201916452311 A US 201916452311A US 2020373436 A1 US2020373436 A1 US 2020373436A1
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- 230000005641 tunneling Effects 0.000 claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- 239000003990 capacitor Substances 0.000 description 15
- 230000000694 effects Effects 0.000 description 5
- 238000009413 insulation Methods 0.000 description 3
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42344—Gate electrodes for transistors with charge trapping gate insulator with at least one additional gate, e.g. program gate, erase gate or select gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
Definitions
- the present invention relates to a semiconductor fabrication technology, and more particularly to a structure of a memory device and a fabrication method thereof.
- a non-volatile memory is almost a necessity in digital electronic products.
- Digital electronic products such as computers, mobile phones, cameras, and video recorders are also indispensable products in daily life. Therefore, the non-volatile memory is generally required.
- the non-volatile memory is, for example, a flash memory including a control gate and a floating gate. Since the data stored in the memory is frequently changed according to actual operations, in addition to the operations of writing and reading, the operation of erasing data is often performed. Therefore, the efficiency of erasing data also affects the overall performance of the memory.
- the structure of the flash memory is also continuing to be developed in order to improve the overall performance of the memory.
- the present invention provides a structure of a memory device and a fabrication method thereof.
- the memory device is a structure based on a structure including a control gate and a floating gate, which can reduce the capacitance value between the floating gate and an erase gate and increase the capacitance value between the floating gate and a substrate, thereby improving the efficiency of erasing data.
- the present invention provides a structure of a memory device, including a tunneling layer disposed on a substrate.
- a first oxide-nitride-oxide (ONO) layer is disposed on the substrate abutting to the tunneling layer.
- a floating gate is disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer.
- a second ONO layer is disposed on the floating gate.
- a control gate is disposed on the second ONO layer.
- An isolation layer is disposed on first sidewalls of the floating gate and sidewalls of the control gate.
- An erase gate is disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.
- the structure of the memory device further includes a vertical dielectric layer on second sidewalls of the side portion of the floating gate, wherein the second sidewalls abut to a shallow trench isolation structure and are merged with the first ONO layer.
- the vertical dielectric layer occupies a space to reduce a width of the floating gate.
- the vertical dielectric layer includes an oxide layer and a nitride layer stacked on the second sidewalls.
- the isolation layer includes a first portion disposed on the first sidewalls of the floating gate and a second portion disposed on the sidewalls of the control gate.
- the first portion of the isolation layer is an oxide layer
- the second portion of the isolation layer is a third ONO layer.
- control gate does not completely cover over the side portion of the floating gate.
- the erase gate includes a protruding portion at a top region, covering over the side portion of the floating gate and isolated by a portion of the isolation layer.
- the substrate includes: active lines extending in a first direction; and shallow trench isolation lines to isolate the active lines.
- the control gate is a control gate line and the erase gate is an erase gate line, and the control gate and the erase gate extend in a second direction perpendicular to the first direction.
- the substrate includes a P-type well region and an N-type well region in the P-type well region, wherein the floating gate covers over the P-type well region and the N-type well region, and the erase gate covers over the N-type well region.
- the present invention also provides a method of fabricating a memory device, including: a tunneling layer is formed on a substrate. The method further includes that a first oxide/nitride/oxide (ONO) layer abutting to the tunneling layer is formed on the substrate.
- a floating gate is formed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer.
- a second ONO layer is formed on the floating gate.
- a control gate is formed on the second ONO layer.
- An isolation layer is formed on first sidewalls of the floating gate and sidewalls of the control gate.
- An erase gate is formed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.
- the method of fabricating the memory device further includes that a vertical dielectric layer is formed on second sidewalls of the side portion of the floating gate.
- the second sidewalls abut to a shallow trench isolation structure and are merged with the first ONO layer.
- the vertical dielectric layer occupies a space to reduce a width of the floating gate.
- the vertical dielectric layer includes an oxide layer and a nitride layer stacked on the second sidewalls.
- the formed isolation layer includes a first portion disposed on the first sidewalls of the floating gate and a second portion disposed on the sidewalls of the control gate.
- the first portion of the isolation layer is an oxide layer
- the second portion of the isolation layer is a third ONO layer.
- control gate does not completely cover over the side portion of the floating gate.
- the erase gate includes a protruding portion at a top region, covering over the side portion of the floating gate and isolated by a portion of the isolation layer.
- the formed substrate includes: active lines extending in a first direction; and shallow trench isolation lines to isolate the active lines.
- the control gate is a control gate line and the erase gate is an erase gate line, and the control gate and the erase gate extend in a second direction perpendicular to the first direction.
- the substrate includes a P-type well region and an N-type well region in the P-type well region, wherein the floating gate covers over the P-type well region and the N-type well region, and the erase gate covers over the N-type well region.
- FIG. 1A is a layout view of a memory device in accordance with the present invention.
- FIG. 1B is a cross-sectional view of the memory device in accordance with the present invention taken along cutting line A-A′ of FIG. 1A .
- FIG. 2 is a layout view of a memory device in accordance with one embodiment of the present invention.
- FIG. 3 is a cross-sectional and three-dimensional view of the memory device 2 taken along cutting line I-I′ of FIG. 2 in accordance with one embodiment of the present invention.
- FIG. 4 is a top view of a floating gate of a memory device in accordance with one embodiment of the present invention.
- FIG. 5 is a cross-sectional view of the memory device taken along cutting line II-II′ of FIG. 2 in accordance with one embodiment of the present invention.
- FIG. 6 is a cross-sectional view of the memory device taken along the cutting line I-I′ of FIG. 2 in accordance with one embodiment of the present invention.
- FIG. 7 is a partial enlarged view of a memory device in accordance with one embodiment of the present invention.
- FIG. 8 is a schematic view showing the capacitive effect of a memory device between a floating gate and a substrate in FIG. 7 in accordance with one embodiment of the present invention.
- FIG. 9 is a flow chart of a method of fabricating a memory device in accordance with one embodiment of the present invention.
- the present invention relates to a structure of a memory device and a fabrication method thereof.
- the memory device is a structure based on a structure including a control gate and a floating gate.
- the structure of the memory device provided by the present invention can reduce the capacitance value between the floating gate and the erase gate and increase the capacitance value between the floating gate and the substrate, thereby improving the efficiency of erasing data.
- the present invention proposes to look into the possible drawbacks of the structure of the memory before proposing improvements to the structure of the memory device.
- FIG. 1A is a drawing, schematically illustrating a layout view of a memory device in accordance with the present invention.
- FIG. 1B is a drawing, schematically illustrating a cross-sectional view of the memory device in accordance with the present invention taken along cutting line A-A′ of FIG. 1A .
- memory cells of the memory device 60 are distributed in arrays. From the top view layout, a plurality of active lines 80 on a substrate 100 extends in a first direction as an active region of a component. The memory cells of the memory device 60 are fabricated on the region of the active lines 80 of the substrate 100 .
- a plurality of shallow trench isolation structures 70 is also formed on the substrate 100 to isolate the active lines 80 .
- the memory device 60 further includes a floating gate 112 , a control gate 114 , and an erase gate 110 , which are also linear structures extending in a second direction that is perpendicular to the first direction.
- the control gate 114 and the erase gate 110 of FIG. 1B correspond to the control gates 114 and CG and the erase gates 110 and EG of FIG. 1A .
- word lines 108 and WL are on the other side of the control gates 114 and CG.
- the intersection region of the active line 80 and the control gates 114 and CG has the floating gate 112 and constitutes a memory cell of the memory device 60 .
- the region of the active line 80 of the substrate 100 is formed with a P-type well region which is a doped region of the substrate 100 .
- an N-type well region 104 is formed corresponding to the erase gate 100
- an N-type doped region 105 with a large concentration is formed in the substrate 100 below the erase gate 110 , and is used as a selection line.
- An N-type doped region 102 to be connected to a bit line is also formed at both ends of the active line.
- An oxide layer 102 is first formed on the substrate.
- a portion of the oxide layer 102 corresponding to the floating gate 112 also serves as a tunneling layer.
- the oxide layer 106 also provides the floating gate 112 and a gate insulation layer of the substrate 100 opposite to the erase gate 100 .
- the floating gate 112 and the control gate 114 are stacked on the oxide layer 102 .
- An oxide/nitride/oxide (ONO) layer 116 is arranged between the floating gate 112 and the control gate 114 .
- the gate insulation layer between the floating gate 112 and the substrate 100 is provided by a portion of the oxide layer 102 .
- the sidewalls of the control gate 114 comprise an isolation layer 118 , such as an ONO structure, to isolate the upper portion of the erase gate 110 .
- the gate insulation layer between the erase gate 110 and the substrate 100 is also provided by a portion of the oxide layer 102 .
- the lower portion of the erase gate 110 is also isolated by the oxide layer 120 from the floating gate 112 .
- the top of the control gate 114 also comprises an oxide layer and a nitride layer as a protective mask layer 124 .
- the sidewalls of the mask layer 124 in the present embodiment are covered by the oxide layer.
- the sidewalls of the mask layer 124 may also extend from the isolation layer 118 , also being an ONO structure.
- the present invention is not limited to the embodiments provided.
- a capacitor C eg-fg exists between the erase gate 110 and the floating gate 112
- another capacitor C fg-sub also exists between the floating gate 112 and the substrate 100 .
- the present invention looks into, for example, the structure of FIG. 1B and finds that the smaller the capacitance value of the capacitor C eg-fg , the better the erasing efficiency. In addition, the larger the capacitance value of the capacitor C fg-sub , the better the erasing efficiency.
- the present invention further provides a further design of the memory device to at least reduce the capacitance value of the capacitor C eg-fg and increase the capacitance value of the capacitor C fg-sub . In this way, at least the performance of the memory device on the erasing operation can be improved.
- FIG. 2 is a drawing, schematically illustrating a layout view of the memory device in accordance with one embodiment of the present invention.
- the layout of the memory device is similar to that described in FIG. 1B , but the structure of the floating gate 112 is further adjusted.
- the cross-sectional structure corresponding to cutting lines I-I′ and II-II′ is described in detail below.
- FIG. 3 is a drawing, schematically illustrating a cross-sectional and three-dimensional view of the memory device taken along the cutting line I-I′ of FIG. 2 in accordance with one embodiment of the present invention.
- a plurality of active lines 80 are formed on the substrate 100 .
- a plurality of shallow trench isolation structures 70 is also formed on the substrate 100 to isolate the active lines 80 .
- the active line 80 is a doped region in the substrate 100 .
- An oxide layer 106 is formed on the active line 80 .
- the basic structure of the floating gate 112 , the control gate 114 , the erase gate 110 , and the like of the memory device is similar to that of FIG. 1B , and an ONO layer 116 is arranged between the floating gate 112 and the control gate 114 . Parts similar to those of FIG. 1B will be omitted herein. In addition, other components of the same reference numerals will be omitted herein.
- an ONO layer 200 is formed between the erase gate 110 and the substrate 100 to replace a portion of the oxide layer 106 .
- the ONO layer 200 also extends to the side portion of the floating gate 112 .
- the isolation layer 118 and the isolation layer 120 may be integrated into two portions of the isolation layer 121 at the sidewalls of the floating gate 112 and the control gate to achieve an isolation effect.
- the side portion of the floating gate 112 is, for example, corresponding to the region covered by the upper portion of the erase gate 110 .
- the cutting line II-II′ indicated in FIG. 2 is shown in FIG. 3 to pass through the side portion of the floating gate 112 , so that the structural relationship between the ONO layer 200 and the floating gate 112 is clearly described.
- the floating gate 112 is provided corresponding to the region of the memory cell, and is used for controlling stored charges to conduct the operation on the memory cell. In other words, the floating gate 112 is not a linearly extending structure.
- FIG. 4 is a drawing, schematically illustrating a top view of a floating gate of a memory device in accordance with one embodiment of the present invention.
- the floating gate 112 is substantially rectangular or square in geometry as viewed from above.
- the sidewalls 112 B of the floating gate 112 are protected by an oxide layer 102 .
- the ONO layer 200 also extends to the side portion of the floating gate 112 , in one embodiment, the other pair of sidewalls 112 A of the floating gate 112 are also covered, for example, by the ONO layer 200 .
- FIG. 4 is a drawing, schematically illustrating a top view of a floating gate of a memory device in accordance with one embodiment of the present invention.
- the floating gate 112 is substantially rectangular or square in geometry as viewed from above.
- the sidewalls 112 B of the floating gate 112 are protected by an oxide layer 102 .
- the ONO layer 200 also extends to the side portion of the floating gate 112
- a dielectric material covering the sidewalls 112 A of the floating gate 112 may generally be a vertical dielectric layer 202 . Since the ONO layer 200 occupies the space, the width of the subsequently formed floating gate 112 at the side portion is reduced. Thus, the area between the floating gate 112 and the erase gate 110 is reduced, and the capacitor C eg-fg generated by the relative has a small capacitance value. After the research of the present invention, the present invention finds that the capacitor C eg-fg with a smaller capacitance value is advantageous for the erasing operation of the memory device.
- the capacitance value of the capacitor C fg-sub is also increased, which is also advantageous for the erasing operation of the memory device. Embodiments are provided below to describe the generation mechanism of the capacitor in more detail.
- FIG. 5 is a drawing, schematically illustrating a cross-sectional view of the memory device taken along the cutting line II-II′ of FIG. 2 in accordance with one embodiment of the present invention.
- the floating gate 112 along the cutting line II-II′ in FIG. 2 is on the active line 80 of the substrate.
- the active line 80 is isolated by a shallow trench isolation structure 70 .
- the active line 80 comprises the ONO layer 200 thereon.
- the floating gate 112 is formed on the ONO layer 200 .
- the upper surface of the floating gate 112 comprises an ONO layer 116 that extends in another direction.
- the control gate 114 also extends in the another direction and is formed on the ONO layer 116 .
- the ONO layer 200 of the present invention is also formed on the sidewalls 112 A of the side portion of the floating gate 112 .
- the portion of the sidewalls 112 A may be considered as the vertical dielectric layer 202 in terms of general effect of adjusting the capacitance value. That is, the vertical dielectric layer 202 may not be an ONO structure as the ONO layer 200 .
- the vertical dielectric layer 202 may include, for example, an oxide layer and a nitride layer. The stack of vertical dielectric layers 202 can be formed correspondingly by the employed fabricating process.
- the vertical dielectric layer 202 is formed first, and then the floating gate 112 is filled, so that the floating gate 112 is surrounded and occupied by the vertical dielectric layer 202 and thus recessed at the side portion.
- the thickness of the vertical dielectric layer 202 is increased, the width of the floating gate 112 is reduced, and the capacitance value generated is also reduced, which is advantageous for the erasing operation.
- FIG. 6 is a drawing, schematically illustrating a cross-sectional view of the memory device taken along the cutting line I-I′ of FIG. 2 in accordance with one embodiment of the present invention.
- the structure of the memory device 90 is the same as the cross-sectional structure of the end face of FIG. 3 .
- the sidewall of the mask layer 124 may be a general oxide layer, and does not need to extend from the isolation layer 118 , or substantially change the formation of the ONO layer 200 and the vertical dielectric layer 202 .
- the sidewalls 112 B of the side portion of the floating gate 112 are isolated by the isolation layer 120 from the lower portion of the erase gate 110 .
- the ONO layer 200 produces a capacitance effect between the floating gate 112 and the substrate 100 .
- FIG. 7 is a drawing, schematically illustrating a partial enlarged view of a memory device in accordance with one embodiment of the present invention.
- FIG. 8 is a drawing, schematically illustrating a schematic view showing the capacitive effect of the memory device between the floating gate and the substrate in FIG. 7 in accordance with one embodiment of the present invention.
- the ONO layer 200 extends to the side portion of the floating gate 112 and is located between the floating gate 112 and the substrate 100 to constitute an equivalent capacitor 304 .
- the oxide layer 106 between the floating gate 112 and the substrate 100 constitutes an equivalent capacitor 302 .
- the capacitor 302 is connected in parallel with the capacitor 304 . Since the ONO layer 200 provides a larger average dielectric constant value, a larger capacitance value is produced. In terms of a circuit, the total capacitance value of the capacitor C fg-sub increases, which is advantageous for the erasing operation.
- FIG. 9 a drawing, schematically illustrating is a flow chart of a method of fabricating the memory device in accordance with one embodiment of the present invention.
- the present invention also provides a method of fabricating the memory device, including: a tunneling layer is formed on a substrate as shown in step S 100 .
- the method further includes step S 102 in which a first oxide/nitride/oxide layer abutting to the tunneling layer is formed on the substrate.
- step S 104 a floating gate is formed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer.
- a second ONO layer is formed on the floating gate.
- a control gate is formed on the second ONO layer.
- step S 110 an isolation layer is formed on first sidewalls of the floating gate and sidewalls of the control gate.
- step S 112 an erase gate is formed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.
- the method of fabricating the memory device further includes that a vertical dielectric layer 202 is formed on sidewalls 112 A of the side portion of the floating gate 112 .
- the sidewalls 112 A abut to a shallow trench isolation structure 70 and are merged with the ONO layer 200 .
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Abstract
Description
- This application claims the priority benefit of Chinese patent application serial no. 201910418713.2, filed on May 20, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
- The present invention relates to a semiconductor fabrication technology, and more particularly to a structure of a memory device and a fabrication method thereof.
- A non-volatile memory is almost a necessity in digital electronic products. Digital electronic products such as computers, mobile phones, cameras, and video recorders are also indispensable products in daily life. Therefore, the non-volatile memory is generally required.
- The non-volatile memory is, for example, a flash memory including a control gate and a floating gate. Since the data stored in the memory is frequently changed according to actual operations, in addition to the operations of writing and reading, the operation of erasing data is often performed. Therefore, the efficiency of erasing data also affects the overall performance of the memory.
- The structure of the flash memory is also continuing to be developed in order to improve the overall performance of the memory.
- The present invention provides a structure of a memory device and a fabrication method thereof. The memory device is a structure based on a structure including a control gate and a floating gate, which can reduce the capacitance value between the floating gate and an erase gate and increase the capacitance value between the floating gate and a substrate, thereby improving the efficiency of erasing data.
- In one embodiment, the present invention provides a structure of a memory device, including a tunneling layer disposed on a substrate. A first oxide-nitride-oxide (ONO) layer is disposed on the substrate abutting to the tunneling layer. A floating gate is disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. A second ONO layer is disposed on the floating gate. A control gate is disposed on the second ONO layer. An isolation layer is disposed on first sidewalls of the floating gate and sidewalls of the control gate. An erase gate is disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.
- In one embodiment, the structure of the memory device further includes a vertical dielectric layer on second sidewalls of the side portion of the floating gate, wherein the second sidewalls abut to a shallow trench isolation structure and are merged with the first ONO layer.
- In one embodiment, for the structure of the memory device, the vertical dielectric layer occupies a space to reduce a width of the floating gate.
- In one embodiment, for the structure of the memory device, the vertical dielectric layer includes an oxide layer and a nitride layer stacked on the second sidewalls.
- In one embodiment, for the structure of the memory device, the isolation layer includes a first portion disposed on the first sidewalls of the floating gate and a second portion disposed on the sidewalls of the control gate.
- In one embodiment, for the structure of the memory device, the first portion of the isolation layer is an oxide layer, and the second portion of the isolation layer is a third ONO layer.
- In one embodiment, for the structure of the memory device, the control gate does not completely cover over the side portion of the floating gate.
- In one embodiment, for the structure of the memory device, the erase gate includes a protruding portion at a top region, covering over the side portion of the floating gate and isolated by a portion of the isolation layer.
- In one embodiment, for the structure of the memory device, the substrate includes: active lines extending in a first direction; and shallow trench isolation lines to isolate the active lines. The control gate is a control gate line and the erase gate is an erase gate line, and the control gate and the erase gate extend in a second direction perpendicular to the first direction.
- In one embodiment, for the structure of the memory device, the substrate includes a P-type well region and an N-type well region in the P-type well region, wherein the floating gate covers over the P-type well region and the N-type well region, and the erase gate covers over the N-type well region.
- In one embodiment, the present invention also provides a method of fabricating a memory device, including: a tunneling layer is formed on a substrate. The method further includes that a first oxide/nitride/oxide (ONO) layer abutting to the tunneling layer is formed on the substrate. A floating gate is formed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. A second ONO layer is formed on the floating gate. A control gate is formed on the second ONO layer. An isolation layer is formed on first sidewalls of the floating gate and sidewalls of the control gate. An erase gate is formed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.
- In one embodiment, the method of fabricating the memory device further includes that a vertical dielectric layer is formed on second sidewalls of the side portion of the floating gate. The second sidewalls abut to a shallow trench isolation structure and are merged with the first ONO layer.
- In one embodiment, for the method of fabricating the memory device, the vertical dielectric layer occupies a space to reduce a width of the floating gate.
- In one embodiment, for the method of fabricating the memory device, the vertical dielectric layer includes an oxide layer and a nitride layer stacked on the second sidewalls.
- In one embodiment, for the method of fabricating the memory device, the formed isolation layer includes a first portion disposed on the first sidewalls of the floating gate and a second portion disposed on the sidewalls of the control gate.
- In one embodiment, for the method of fabricating the memory device, the first portion of the isolation layer is an oxide layer, and the second portion of the isolation layer is a third ONO layer.
- In one embodiment, for the method of fabricating the memory device, the control gate does not completely cover over the side portion of the floating gate.
- In one embodiment, for the method of fabricating the memory device, the erase gate includes a protruding portion at a top region, covering over the side portion of the floating gate and isolated by a portion of the isolation layer.
- In one embodiment, for the method of fabricating the memory device, the formed substrate includes: active lines extending in a first direction; and shallow trench isolation lines to isolate the active lines. The control gate is a control gate line and the erase gate is an erase gate line, and the control gate and the erase gate extend in a second direction perpendicular to the first direction.
- In one embodiment, for the method of fabricating the memory device, the substrate includes a P-type well region and an N-type well region in the P-type well region, wherein the floating gate covers over the P-type well region and the N-type well region, and the erase gate covers over the N-type well region.
- The accompanying drawings are included to provide a further understanding of the present invention. The accompanying drawings are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments of the present invention, and serve to explain the principles of the present invention together with the description.
-
FIG. 1A is a layout view of a memory device in accordance with the present invention. -
FIG. 1B is a cross-sectional view of the memory device in accordance with the present invention taken along cutting line A-A′ ofFIG. 1A . -
FIG. 2 is a layout view of a memory device in accordance with one embodiment of the present invention. -
FIG. 3 is a cross-sectional and three-dimensional view of the memory device 2 taken along cutting line I-I′ ofFIG. 2 in accordance with one embodiment of the present invention. -
FIG. 4 is a top view of a floating gate of a memory device in accordance with one embodiment of the present invention. -
FIG. 5 is a cross-sectional view of the memory device taken along cutting line II-II′ ofFIG. 2 in accordance with one embodiment of the present invention. -
FIG. 6 is a cross-sectional view of the memory device taken along the cutting line I-I′ ofFIG. 2 in accordance with one embodiment of the present invention. -
FIG. 7 is a partial enlarged view of a memory device in accordance with one embodiment of the present invention. -
FIG. 8 is a schematic view showing the capacitive effect of a memory device between a floating gate and a substrate inFIG. 7 in accordance with one embodiment of the present invention. -
FIG. 9 is a flow chart of a method of fabricating a memory device in accordance with one embodiment of the present invention. - The present invention relates to a structure of a memory device and a fabrication method thereof. In one embodiment, the memory device is a structure based on a structure including a control gate and a floating gate. The structure of the memory device provided by the present invention can reduce the capacitance value between the floating gate and the erase gate and increase the capacitance value between the floating gate and the substrate, thereby improving the efficiency of erasing data.
- The present invention is illustrated by the following embodiments, but the present invention is not limited to the embodiments. These embodiments can also be combined with each other.
- The present invention proposes to look into the possible drawbacks of the structure of the memory before proposing improvements to the structure of the memory device.
-
FIG. 1A is a drawing, schematically illustrating a layout view of a memory device in accordance with the present invention.FIG. 1B is a drawing, schematically illustrating a cross-sectional view of the memory device in accordance with the present invention taken along cutting line A-A′ ofFIG. 1A . According toFIG. 1A andFIG. 1B , memory cells of thememory device 60 are distributed in arrays. From the top view layout, a plurality ofactive lines 80 on asubstrate 100 extends in a first direction as an active region of a component. The memory cells of thememory device 60 are fabricated on the region of theactive lines 80 of thesubstrate 100. A plurality of shallowtrench isolation structures 70 is also formed on thesubstrate 100 to isolate theactive lines 80. Thememory device 60 further includes a floatinggate 112, acontrol gate 114, and an erasegate 110, which are also linear structures extending in a second direction that is perpendicular to the first direction. Thecontrol gate 114 and the erasegate 110 ofFIG. 1B correspond to thecontrol gates 114 and CG and the erasegates 110 and EG ofFIG. 1A . Furthermore,word lines 108 and WL are on the other side of thecontrol gates 114 and CG. The intersection region of theactive line 80 and thecontrol gates 114 and CG has the floatinggate 112 and constitutes a memory cell of thememory device 60. - As can be seen more clearly from
FIG. 1B , the region of theactive line 80 of thesubstrate 100 is formed with a P-type well region which is a doped region of thesubstrate 100. In the P-type well region, an N-type well region 104 is formed corresponding to the erasegate 100, and in the N-type well region 104, an N-type dopedregion 105 with a large concentration is formed in thesubstrate 100 below the erasegate 110, and is used as a selection line. An N-type dopedregion 102 to be connected to a bit line is also formed at both ends of the active line. - An
oxide layer 102 is first formed on the substrate. A portion of theoxide layer 102 corresponding to the floatinggate 112 also serves as a tunneling layer. On the other hand, theoxide layer 106 also provides the floatinggate 112 and a gate insulation layer of thesubstrate 100 opposite to the erasegate 100. The floatinggate 112 and thecontrol gate 114 are stacked on theoxide layer 102. An oxide/nitride/oxide (ONO)layer 116 is arranged between the floatinggate 112 and thecontrol gate 114. The gate insulation layer between the floatinggate 112 and thesubstrate 100 is provided by a portion of theoxide layer 102. The sidewalls of thecontrol gate 114 comprise anisolation layer 118, such as an ONO structure, to isolate the upper portion of the erasegate 110. The gate insulation layer between the erasegate 110 and thesubstrate 100 is also provided by a portion of theoxide layer 102. The lower portion of the erasegate 110 is also isolated by theoxide layer 120 from the floatinggate 112. As needed, the top of thecontrol gate 114 also comprises an oxide layer and a nitride layer as aprotective mask layer 124. The sidewalls of themask layer 124 in the present embodiment are covered by the oxide layer. However, in another embodiment, the sidewalls of themask layer 124 may also extend from theisolation layer 118, also being an ONO structure. The present invention is not limited to the embodiments provided. - For the structure of the memory device of
FIG. 1B . In the data erasing operation, a capacitor Ceg-fg exists between the erasegate 110 and the floatinggate 112, and another capacitor Cfg-sub also exists between the floatinggate 112 and thesubstrate 100. - The present invention looks into, for example, the structure of
FIG. 1B and finds that the smaller the capacitance value of the capacitor Ceg-fg, the better the erasing efficiency. In addition, the larger the capacitance value of the capacitor Cfg-sub, the better the erasing efficiency. - In one embodiment, the present invention further provides a further design of the memory device to at least reduce the capacitance value of the capacitor Ceg-fg and increase the capacitance value of the capacitor Cfg-sub. In this way, at least the performance of the memory device on the erasing operation can be improved.
-
FIG. 2 is a drawing, schematically illustrating a layout view of the memory device in accordance with one embodiment of the present invention. According toFIG. 2 , the layout of the memory device is similar to that described inFIG. 1B , but the structure of the floatinggate 112 is further adjusted. In order to be able to understand the more detailed structure, the cross-sectional structure corresponding to cutting lines I-I′ and II-II′ is described in detail below. -
FIG. 3 is a drawing, schematically illustrating a cross-sectional and three-dimensional view of the memory device taken along the cutting line I-I′ ofFIG. 2 in accordance with one embodiment of the present invention. According toFIG. 2 andFIG. 3 , a plurality ofactive lines 80 are formed on thesubstrate 100. A plurality of shallowtrench isolation structures 70 is also formed on thesubstrate 100 to isolate theactive lines 80. Theactive line 80 is a doped region in thesubstrate 100. Anoxide layer 106 is formed on theactive line 80. - In one embodiment, the basic structure of the floating
gate 112, thecontrol gate 114, the erasegate 110, and the like of the memory device is similar to that ofFIG. 1B , and anONO layer 116 is arranged between the floatinggate 112 and thecontrol gate 114. Parts similar to those ofFIG. 1B will be omitted herein. In addition, other components of the same reference numerals will be omitted herein. - The further features of the present invention are described below in accordance with an embodiment. In the present invention, an
ONO layer 200 is formed between the erasegate 110 and thesubstrate 100 to replace a portion of theoxide layer 106. TheONO layer 200 also extends to the side portion of the floatinggate 112. Theisolation layer 118 and theisolation layer 120 may be integrated into two portions of theisolation layer 121 at the sidewalls of the floatinggate 112 and the control gate to achieve an isolation effect. In one embodiment, the side portion of the floatinggate 112 is, for example, corresponding to the region covered by the upper portion of the erasegate 110. - The cutting line II-II′ indicated in
FIG. 2 is shown inFIG. 3 to pass through the side portion of the floatinggate 112, so that the structural relationship between theONO layer 200 and the floatinggate 112 is clearly described. The floatinggate 112 is provided corresponding to the region of the memory cell, and is used for controlling stored charges to conduct the operation on the memory cell. In other words, the floatinggate 112 is not a linearly extending structure. -
FIG. 4 is a drawing, schematically illustrating a top view of a floating gate of a memory device in accordance with one embodiment of the present invention. According toFIG. 4 , in one embodiment, the floatinggate 112 is substantially rectangular or square in geometry as viewed from above. The sidewalls 112B of the floatinggate 112 are protected by anoxide layer 102. However, since theONO layer 200 also extends to the side portion of the floatinggate 112, in one embodiment, the other pair ofsidewalls 112A of the floatinggate 112 are also covered, for example, by theONO layer 200. In one embodiment, as shown inFIG. 5 , which will be described later, a dielectric material covering thesidewalls 112A of the floatinggate 112 may generally be avertical dielectric layer 202. Since theONO layer 200 occupies the space, the width of the subsequently formed floatinggate 112 at the side portion is reduced. Thus, the area between the floatinggate 112 and the erasegate 110 is reduced, and the capacitor Ceg-fg generated by the relative has a small capacitance value. After the research of the present invention, the present invention finds that the capacitor Ceg-fg with a smaller capacitance value is advantageous for the erasing operation of the memory device. In addition, since theONO layer 200 also extends below the floatinggate 112, the capacitance value of the capacitor Cfg-sub is also increased, which is also advantageous for the erasing operation of the memory device. Embodiments are provided below to describe the generation mechanism of the capacitor in more detail. -
FIG. 5 is a drawing, schematically illustrating a cross-sectional view of the memory device taken along the cutting line II-II′ ofFIG. 2 in accordance with one embodiment of the present invention. According toFIG. 5 , in one embodiment, the floatinggate 112 along the cutting line II-II′ inFIG. 2 is on theactive line 80 of the substrate. Theactive line 80 is isolated by a shallowtrench isolation structure 70. Theactive line 80 comprises theONO layer 200 thereon. The floatinggate 112 is formed on theONO layer 200. The upper surface of the floatinggate 112 comprises anONO layer 116 that extends in another direction. Thecontrol gate 114 also extends in the another direction and is formed on theONO layer 116. - In one embodiment, the
ONO layer 200 of the present invention is also formed on thesidewalls 112A of the side portion of the floatinggate 112. The portion of thesidewalls 112A may be considered as thevertical dielectric layer 202 in terms of general effect of adjusting the capacitance value. That is, thevertical dielectric layer 202 may not be an ONO structure as theONO layer 200. In one embodiment, thevertical dielectric layer 202 may include, for example, an oxide layer and a nitride layer. The stack of verticaldielectric layers 202 can be formed correspondingly by the employed fabricating process. Thevertical dielectric layer 202 is formed first, and then the floatinggate 112 is filled, so that the floatinggate 112 is surrounded and occupied by thevertical dielectric layer 202 and thus recessed at the side portion. As the thickness of thevertical dielectric layer 202 is increased, the width of the floatinggate 112 is reduced, and the capacitance value generated is also reduced, which is advantageous for the erasing operation. -
FIG. 6 is a drawing, schematically illustrating a cross-sectional view of the memory device taken along the cutting line I-I′ ofFIG. 2 in accordance with one embodiment of the present invention. According toFIG. 6 , the structure of thememory device 90 is the same as the cross-sectional structure of the end face ofFIG. 3 . In one embodiment, as described above, the sidewall of themask layer 124 may be a general oxide layer, and does not need to extend from theisolation layer 118, or substantially change the formation of theONO layer 200 and thevertical dielectric layer 202. The sidewalls 112B of the side portion of the floatinggate 112 are isolated by theisolation layer 120 from the lower portion of the erasegate 110. - In the
region 300 indicated, theONO layer 200 produces a capacitance effect between the floatinggate 112 and thesubstrate 100. -
FIG. 7 is a drawing, schematically illustrating a partial enlarged view of a memory device in accordance with one embodiment of the present invention.FIG. 8 is a drawing, schematically illustrating a schematic view showing the capacitive effect of the memory device between the floating gate and the substrate inFIG. 7 in accordance with one embodiment of the present invention. - According to
FIG. 7 andFIG. 8 , theONO layer 200 extends to the side portion of the floatinggate 112 and is located between the floatinggate 112 and thesubstrate 100 to constitute anequivalent capacitor 304. In addition, theoxide layer 106 between the floatinggate 112 and thesubstrate 100 constitutes anequivalent capacitor 302. Thecapacitor 302 is connected in parallel with thecapacitor 304. Since theONO layer 200 provides a larger average dielectric constant value, a larger capacitance value is produced. In terms of a circuit, the total capacitance value of the capacitor Cfg-sub increases, which is advantageous for the erasing operation. - Features of the present invention are described below in terms of a semiconductor fabrication process.
FIG. 9 a drawing, schematically illustrating is a flow chart of a method of fabricating the memory device in accordance with one embodiment of the present invention. - According to
FIG. 9 , in one embodiment, the present invention also provides a method of fabricating the memory device, including: a tunneling layer is formed on a substrate as shown in step S100. The method further includes step S102 in which a first oxide/nitride/oxide layer abutting to the tunneling layer is formed on the substrate. In step S104, a floating gate is formed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. In step S106, a second ONO layer is formed on the floating gate. In step S108, a control gate is formed on the second ONO layer. In step S110, an isolation layer is formed on first sidewalls of the floating gate and sidewalls of the control gate. In step S112, an erase gate is formed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer. - In one embodiment, the method of fabricating the memory device further includes that a
vertical dielectric layer 202 is formed onsidewalls 112A of the side portion of the floatinggate 112. Thesidewalls 112A abut to a shallowtrench isolation structure 70 and are merged with theONO layer 200. - Finally, it should be noted that the above embodiments are only used to illustrate instead of limiting the technical solutions of the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions described in the foregoing embodiments may be modified or equivalently substituted for some or all of the technical features. These modifications and substitutions do not depart from the scope of the technical solutions of the embodiments of the present invention.
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Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4958321A (en) * | 1988-09-22 | 1990-09-18 | Advanced Micro Devices, Inc. | One transistor flash EPROM cell |
KR100232235B1 (en) * | 1996-11-15 | 1999-12-01 | 김영환 | Non-volatile memory device |
US6461915B1 (en) | 1999-09-01 | 2002-10-08 | Micron Technology, Inc. | Method and structure for an improved floating gate memory cell |
US6486029B1 (en) * | 2000-03-16 | 2002-11-26 | Advanced Micro Devices, Inc. | Integration of an ion implant hard mask structure into a process for fabricating high density memory cells |
EP1313149A1 (en) * | 2001-11-14 | 2003-05-21 | STMicroelectronics S.r.l. | Process for fabricating a dual charge storage location memory cell |
US7164167B2 (en) * | 2001-11-21 | 2007-01-16 | Sharp Kabushiki Kaisha | Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus |
JP4647175B2 (en) * | 2002-04-18 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
US6992929B2 (en) * | 2004-03-17 | 2006-01-31 | Actrans System Incorporation, Usa | Self-aligned split-gate NAND flash memory and fabrication process |
US7335941B2 (en) * | 2004-07-14 | 2008-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Uniform channel programmable erasable flash EEPROM |
US7928499B2 (en) * | 2007-03-07 | 2011-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Profile of flash memory cells |
US7700473B2 (en) * | 2007-04-09 | 2010-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gated semiconductor device and method of fabricating same |
JP2010050208A (en) * | 2008-08-20 | 2010-03-04 | Renesas Technology Corp | Semiconductor device |
KR101149044B1 (en) * | 2009-04-30 | 2012-05-24 | 에스케이하이닉스 주식회사 | Non-volatile memory device and method for fabricating the same |
US8780628B2 (en) * | 2011-09-23 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit including a voltage divider and methods of operating the same |
US8878281B2 (en) * | 2012-05-23 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for non-volatile memory cells |
US9431256B2 (en) * | 2013-07-11 | 2016-08-30 | United Microelectronics Corp. | Semiconductor device and manufacturing method thereof |
US9287282B2 (en) | 2014-01-28 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a logic compatible flash memory |
CN105655338A (en) * | 2014-12-04 | 2016-06-08 | 联华电子股份有限公司 | Non-volatile memory cell and manufacturing method thereof |
US9673204B2 (en) | 2014-12-29 | 2017-06-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
US9379121B1 (en) * | 2015-01-05 | 2016-06-28 | Silicon Storage Technology, Inc. | Split gate non-volatile flash memory cell having metal gates and method of making same |
TWI588992B (en) * | 2015-01-13 | 2017-06-21 | Xinnova Tech Ltd | Non-volatile memory components and methods of making the same |
US9859291B2 (en) * | 2015-08-03 | 2018-01-02 | Iotmemory Technology Inc. | Non-volatile memory and manufacturing method thereof |
TWI643315B (en) * | 2015-10-15 | 2018-12-01 | 聯華電子股份有限公司 | Semiconductor structure and manufacturing method thereof |
US9837425B2 (en) * | 2016-04-19 | 2017-12-05 | United Microelectronics Corp. | Semiconductor device with split gate flash memory cell structure and method of manufacturing the same |
US10276587B2 (en) * | 2016-05-27 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | NVM memory HKMG integration technology |
US9929167B2 (en) | 2016-07-13 | 2018-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10103156B2 (en) * | 2017-02-16 | 2018-10-16 | Globalfoundries Singapore Pte. Ltd. | Strap layout for non-volatile memory device |
US10269815B2 (en) * | 2017-04-27 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10192874B2 (en) * | 2017-06-19 | 2019-01-29 | United Microelectronics Corp. | Nonvolatile memory cell and fabrication method thereof |
US9911847B1 (en) * | 2017-07-12 | 2018-03-06 | United Microelectronics Corp. | Non-volatile memory device and manufacturing method thereof |
US10242996B2 (en) * | 2017-07-19 | 2019-03-26 | Cypress Semiconductor Corporation | Method of forming high-voltage transistor with thin gate poly |
US10879250B2 (en) * | 2017-08-29 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure for memory device and method for forming the same |
FR3071355B1 (en) * | 2017-09-20 | 2019-08-30 | Stmicroelectronics (Rousset) Sas | MEMORY CELL-COMPACT EEPROM |
US10950703B2 (en) * | 2017-11-07 | 2021-03-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure for memory device and method for forming the same |
US10622073B2 (en) * | 2018-05-11 | 2020-04-14 | Texas Instruments Incorporated | Integrated circuit including vertical capacitors |
US10679699B2 (en) * | 2018-07-30 | 2020-06-09 | Stmicroelectronics (Rousset) Sas | Non-volatile memory with double capa implant |
-
2019
- 2019-05-20 CN CN201910418713.2A patent/CN111968983B/en active Active
- 2019-06-25 US US16/452,311 patent/US10868197B1/en active Active
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