US20200365500A1 - Wiring structure and method for manufacturing the same - Google Patents
Wiring structure and method for manufacturing the same Download PDFInfo
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- US20200365500A1 US20200365500A1 US16/410,872 US201916410872A US2020365500A1 US 20200365500 A1 US20200365500 A1 US 20200365500A1 US 201916410872 A US201916410872 A US 201916410872A US 2020365500 A1 US2020365500 A1 US 2020365500A1
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- conductive structure
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- dielectric layer
- circuit layer
- peripheral surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/061—Lamination of previously made multilayered subassemblies
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
Abstract
A wiring structure includes an upper conductive structure, a lower conductive structure, a lower encapsulant and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The lower encapsulant surrounds a lateral peripheral surface of the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.
Description
- The present disclosure relates to a wiring structure and a manufacturing method, and to a wiring structure including at least two conductive structures attached or bonded together by an intermediate layer, and a method for manufacturing the same.
- Along with the rapid development in electronics industry and the progress of semiconductor processing technologies, semiconductor chips are integrated with an increasing number of electronic components to achieve improved electrical performance and additional functions. Accordingly, the semiconductor chips are provided with more input/output (I/O) connections. To manufacture semiconductor packages including semiconductor chips with an increased number of I/O connections, circuit layers of semiconductor substrates used for carrying the semiconductor chips may correspondingly increase in size. Thus, a thickness and a warpage of a semiconductor substrate may correspondingly increase, and a yield of the semiconductor substrate may decrease.
- In some embodiments, a wiring structure includes: (a) an upper conductive structure including at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer; (b) a lower conductive structure including at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer; (c) a lower encapsulant surrounding a lateral peripheral surface of the lower conductive structure; and (d) an intermediate layer disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure.
- In some embodiments, a method for manufacturing a wiring structure includes: (a) providing a lower substrate including at least one lower conductive structure, wherein the lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (b) providing a plurality of upper strips, wherein each of the upper strips includes at least one upper conductive structure, and the upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (c) attaching the upper strips to the lower substrate side by side, wherein a position of the upper conductive structure of the upper strip corresponds to a position of the lower conductive structure of the lower substrate; (d) electrically connecting the upper conductive structure of the upper strip and the lower conductive structure of the lower substrate; and (e) conducting a singulation process to form a plurality of wiring structures.
- In some embodiments, a method for manufacturing a wiring structure includes: (a) providing a plurality of lower conductive structures, wherein each of the lower conductive structures includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (b) forming a lower encapsulant to encapsulate a plurality of known good lower conductive structures to form a lower module; (c) providing a plurality of upper conductive structures, wherein each of the upper conductive structures includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer of the upper conductive structure; (d) attaching the upper conductive structures to the known good lower conductive structures of the lower module respectively; and electrically connecting the upper conductive structures and the known good lower conductive structures of the lower module; and (f) conducting a singulation process to form a plurality of wiring structures.
- Aspects of some embodiments of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It is noted that various structures may not be drawn to scale, and dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 illustrates a perspective view of a wiring structure according to some embodiments of the present disclosure. -
FIG. 2 illustrates a top view of the wiring structure ofFIG. 1 . -
FIG. 3 illustrates an exploded view of the wiring structure ofFIG. 1 . -
FIG. 4 illustrates a cross-sectional view of a portion of the wiring structure ofFIG. 1 . -
FIG. 5 illustrates a cross-sectional view of a wiring structure according to some embodiments of the present disclosure. -
FIG. 6 illustrates a cross-sectional view of a wiring structure according to some embodiments of the present disclosure. -
FIG. 7 illustrates a cross-sectional view of a wiring structure according to some embodiments of the present disclosure. -
FIG. 8 illustrates a cross-sectional view of a wiring structure according to some embodiments of the present disclosure. -
FIG. 9 illustrates a cross-sectional view of a wiring structure according to some embodiments of the present disclosure. -
FIG. 10 illustrates a cross-sectional view of a wiring structure according to some embodiments of the present disclosure. -
FIG. 11 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 12 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 13 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 14 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 15 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 16 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 17 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 18 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 19 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 20 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 21 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 22 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 23 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 24 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 25 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 26 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 27 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 28 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 29 illustrates one or more stages of an example of a method for manufacturing wiring structure according to some embodiments of the present disclosure. -
FIG. 30 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 31 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 32 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 33 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 34 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 35 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 36 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 37 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 38 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 39 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 40 illustrates one or more stages of an example of a method for manufacturing wiring structure according to some embodiments of the present disclosure. -
FIG. 41 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 42 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 43 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 44 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 45 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 46 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 47 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 48 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 49 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 50 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 51 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 52 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 53 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 54 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 55 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 56 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 57 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 58 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 59 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 60 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 61 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 62 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 63 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 64 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. -
FIG. 65 illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. - Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
- The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- To meet the specification of increasing I/O counts, a number of dielectric layers of a substrate should increase. In some comparative embodiments, a manufacturing process of a core substrate may include the following stages. Firstly, a core with two copper foils disposed on two sides thereof is provided. Then, a plurality of dielectric layers and a plurality of circuit layers are formed or stacked on the two copper foils. One circuit layer may be embedded in one corresponding dielectric layer. Therefore, the core substrate may include a plurality of stacked dielectric layers and a plurality of circuit layers embedded in the dielectric layers on both sides of the core. Since a line width/line space (L/S) of the circuit layers of such core substrate may be greater than or equal to 10 micrometers (μm)/10 μm, the number of the dielectric layers of such core substrate is relatively large. Although the manufacturing cost of such core substrate is low, the manufacturing yield for the circuit layers and the dielectric layers of such core substrate is also low, and, thus, the yield of such core substrate is low. In addition, each dielectric layer is relatively thick, and, thus, such core substrate is relatively thick. In some comparative embodiments, if a package has 10000 I/O counts, such core substrate may include twelve layers of circuit layers and dielectric layers. The manufacturing yield for one layer (including one circuit layer and one dielectric layer) of such core substrate may be 90%. Thus, the yield of such core substrate may be (0.9)12=28.24%. In addition, warpage of the twelve layers of circuit layers and dielectric layers may be accumulated, and, thus, the top several layers may have severe warpage. As a result, the yield of such core substrate may be further reduced.
- To address the above concerns, in some comparative embodiments, a coreless substrate is provided. The coreless substrate may include a plurality of dielectric layers and a plurality of fan-out circuit layers. In some embodiments, a manufacturing process of a coreless substrate may include the following stages. Firstly, a carrier is provided. Then, a plurality of dielectric layers and a plurality of fan-out circuit layers are formed or stacked on a surface of the carrier. One fan-out circuit layer may be embedded in one corresponding dielectric layer. Then, the carrier is removed. Therefore, the coreless substrate may include a plurality of stacked dielectric layers and a plurality of fan-out circuit layers embedded in the dielectric layers. Since a line width/line space (L/S) of the fan-out circuit layers of such coreless substrate may be less than or equal to 2 μm/2 μm, the number of the dielectric layers of such coreless substrate can be reduced. Further, the manufacturing yield for the fan-out circuit layers and the dielectric layers of such coreless substrate is high. For example, the manufacturing yield for one layer (including one fan-out circuit layer and one dielectric layer) of such coreless substrate may be 99%. However, the manufacturing cost of such coreless substrate is relatively high.
- At least some embodiments of the present disclosure provide for a wiring structure which has an advantageous compromise of yield and manufacturing cost. In some embodiments, the wiring structure includes an upper conductive structure and a lower conductive structure bonded to the upper conductive structure through an intermediate layer. At least some embodiments of the present disclosure further provide for techniques for manufacturing the wiring structure.
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FIG. 1 illustrates a perspective view of awiring structure 1 according to some embodiments of the present disclosure.FIG. 2 illustrates a top view of thewiring structure 1 ofFIG. 1 .FIG. 3 illustrates an exploded view of thewiring structure 1 ofFIG. 1 .FIG. 4 illustrates a cross-sectional view of a portion of thewiring structure 1 ofFIG. 1 . Thewiring structure 1 includes a plurality ofupper strips 2, alower substrate 3, anintermediate layer 12 and at least one upper through via 14. - As shown in
FIG. 1 toFIG. 3 , theupper strips 2 are disposed on thelower substrate 3 side by side. In some embodiments, theupper strips 2 are attached to thelower substrate 3 through theintermediate layer 12. Each of theupper strips 2 includes at least one upperconductive structure 2 a. For example, each of theupper strips 2 may include a plurality of upperconductive structures 2 a arranged in a row. It is noted that theupper strip 2 is in a strip type before a singulation process, and may be also referred to as an upper conductive structure. The upperconductive structure 2 a may be a die unit after a singulation process. - As shown in
FIG. 4 , the upperconductive structure 2 a includes at least one dielectric layer (including, for example, two first dielectric layers 20 and a second dielectric layer 26) and at least one circuit layer (including, for example, three first circuit layers 24 and asecond circuit layer 28 formed of a metal, a metal alloy, or other conductive material) in contact with the dielectric layer (e.g., the first dielectric layers 20 and the second dielectric layer 26). In some embodiments, the upperconductive structure 2 a may be similar to a coreless substrate. The upperconductive structure 2 a may be also referred to as “a stacked structure” or “a high-density conductive structure” or “a high-density stacked structure”. The circuit layer (including, for example, the three circuit layers 24) of the upperconductive structure 2 a may be also referred to as “a high-density circuit layer”. In some embodiments, a density of a circuit line (including, for example, a trace or a pad) of the high-density circuit layer is greater than a density of a circuit line of a low-density circuit layer. That is, the count of the circuit line (including, for example, a trace or a pad) in a unit area of the high-density circuit layer is greater than the count of the circuit line in an equal unit area of the low-density circuit layer, such as about 1.2 times or greater, about 1.5 times or greater, or about 2 times or greater. Alternatively, or in combination, a line width/line space (L/S) of the high-density circuit layer is less than a L/S of the low-density circuit layer, such as about 90% or less, about 50% or less, or about 20% or less. Further, the conductive structure that includes the high-density circuit layer may be designated as the “high-density conductive structure”, and the conductive structure that includes the low-density circuit layer may be designated as a “low-density conductive structure”. - The upper
conductive structure 2 a has atop surface 21 and abottom surface 22 opposite to thetop surface 21, and defines at least one throughhole 23, each of which is a single, continuous through hole. The upperconductive structure 2 a includes a plurality of dielectric layers (e.g., the two first dielectric layers 20 and the second dielectric layer 26), a plurality of circuit layers (e.g., the three first circuit layers 24 and the second circuit layer 28) and at least one inner via 25. The dielectric layers (e.g., the first dielectric layers 20 and the second dielectric layer 26) are stacked on one another. For example, thesecond dielectric layer 26 is disposed on the first dielectric layers 20, and, thus, thesecond dielectric layer 26 is the topmost dielectric layer. In some embodiments, a material of the dielectric layers (e.g., the first dielectric layers 20 and the second dielectric layer 26) is transparent, and can be seen through by human eyes or machine. That is, a mark disposed adjacent to thebottom surface 22 of the upperconductive structure 2 a can be recognized or detected from thetop surface 21 of the upperconductive structure 2 a by human eyes or machine. In some embodiments, a transparent material of the dielectric layers has a light transmission for a wavelength in the visible range (or other pertinent wavelength for detection of a mark) of at least about 60%, at least about 70%, or at least about 80%. - In addition, each of the first dielectric layers 20 has a
top surface 201 and abottom surface 202 opposite to thetop surface 201, and defines a throughhole 203 having aninner surface 2031. Thesecond dielectric layer 26 has atop surface 261 and abottom surface 262 opposite to thetop surface 261, and defines a throughhole 263 having aninner surface 2631. Thebottom surface 262 of thesecond dielectric layer 26 is disposed on and contacts thetop surface 201 of the adjacentfirst dielectric layer 20. Thus, thetop surface 21 of the upperconductive structure 2 a is thetop surface 261 of thesecond dielectric layer 26, and thebottom surface 22 of the upperconductive structure 2 a is thebottom surface 202 of the bottommostfirst dielectric layer 20. - As shown in
FIG. 4 , each of the throughholes 203 of the first dielectric layers 20 tapers downwardly along a direction from thetop surface 21 towards thebottom surface 22 of the upperconductive structure 2 a; that is, a size of a top portion of the throughhole 203 is greater than a size of a bottom portion of the throughhole 203. The throughhole 263 of thesecond dielectric layer 26 also tapers downwardly; that is, a size of a top portion of the throughhole 263 is greater than a size of a bottom portion of the throughhole 263. Further, the throughhole 263 of thesecond dielectric layer 26 is aligned with and in communication with the throughholes 203 of the first dielectric layers 20. The bottom portion of the throughhole 263 of thesecond dielectric layer 26 is disposed adjacent to or connected to the top portion of the throughhole 203 of thefirst dielectric layer 20 under thesecond dielectric layer 26. The size of the bottom portion of the throughhole 263 of thesecond dielectric layer 26 is substantially equal to the size of the top portion of the throughhole 203 of thefirst dielectric layer 20 under thesecond dielectric layer 26. Thus, theinner surface 2631 of the throughhole 263 of thesecond dielectric layer 26 is coplanar with or aligned with theinner surfaces 2031 of the throughholes 203 of the first dielectric layers 20. It is noted that the above-mentioned “coplanar” surfaces need not be flat. In some embodiments, theinner surface 2631 of the throughhole 263 of thesecond dielectric layer 26 and theinner surfaces 2031 of the throughholes 203 of the first dielectric layers 20 may be curved surfaces, and are portions of aninner surface 231 of the single, continuous throughhole 23 for accommodating the upper through via 14. The throughhole 263 of thesecond dielectric layer 26 and the throughholes 203 of the first dielectric layers 20 are collectively configured to form or define a portion of the single throughhole 23. As shown inFIG. 4 , cross-sectional views of one side of theinner surface 2631 of the throughhole 263 of thesecond dielectric layer 26 and theinner surfaces 2031 of the throughholes 203 of the first dielectric layers 20 are segments of a substantially straight line. That is, cross-sectional views of one side of theinner surface 2631 of the throughhole 263 of thesecond dielectric layer 26 and theinner surfaces 2031 of the throughholes 203 of the first dielectric layers 20 may extend along the same substantially straight line. The single throughhole 23 extends through the upperconductive structure 2; that is, the single throughhole 23 extends from thetop surface 21 of the upperconductive structure 2 a to thebottom surface 22 of the upperconductive structure 2 a. The single throughhole 23 tapers downwardly. - The first circuit layers 24 may be fan-out circuit layers or redistribution layers (RDLs), and an L/S of the first circuit layers 24 may be less than or equal to about 2 μm/about 2 μm, or less than or equal to about 1.8 μm/about 1.8 μm. Each of the first circuit layers 24 has a
top surface 241 and abottom surface 242 opposite to thetop surface 241. In some embodiments, thefirst circuit layer 24 is embedded in the correspondingfirst dielectric layer 20, and thetop surface 241 of thefirst circuit layer 24 may be substantially coplanar with thetop surface 201 of thefirst dielectric layer 20. In some embodiments, eachfirst circuit layer 24 may include aseed layer 243 and a conductivemetallic material 244 disposed on theseed layer 243. As shown inFIG. 4 , the bottommostfirst circuit layer 24 is disposed on and protrudes from thebottom surface 22 of the upperconductive structure 2 a (e.g., thebottom surface 202 of the bottommost first dielectric layer 20). In addition, thesecond circuit layer 28 is disposed on and protrudes from thetop surface 21 of the upperconductive structure 2 a (e.g., thetop surface 261 of the second dielectric layer 26). An L/S of thesecond circuit layer 28 may be greater than or equal to the L/S of thefirst circuit layer 24. As illustrated in the embodiment ofFIG. 4 , a horizontally connecting or extending circuit layer is omitted in thesecond dielectric layer 26. - The upper
conductive structure 2 a includes a plurality ofinner vias 25. Some of theinner vias 25 are disposed between two adjacent first circuit layers 24 for electrically connecting the two first circuit layers 24. Some of theinner vias 25 are disposed between thefirst circuit layer 24 and thesecond circuit layer 28 for electrically connecting thefirst circuit layer 24 and thesecond circuit layer 28. In some embodiments, each inner via 25 may include aseed layer 251 and a conductivemetallic material 252 disposed on theseed layer 251. In some embodiments, each inner via 25 and the correspondingfirst circuit layer 24 may be formed integrally as a monolithic or one-piece structure. Each inner via 25 tapers upwardly along a direction from thebottom surface 22 towards thetop surface 21 of the upperconductive structure 2. That is, a size (e.g., a width) of a top portion of the inner via 25 is less than a size (e.g., a width) of a bottom portion of the inner via 25 that is closer towards thebottom surface 22. In some embodiments, a maximum width of the inner via 25 (e.g., at the bottom portion) may be less than or equal to about 25 μm, such as about 25 μm, about 20 μm about 15 μm or about 10 μm. - As shown in
FIG. 1 toFIG. 3 , thelower substrate 3 includes at least one lowerconductive structure 3 a. For example, thelower substrate 3 may include a plurality of lowerconductive structures 3 a arranged in an array. Alternatively, thelower substrate 3 may be a panel type. It is noted that thelower substrate 3 is in a substrate type before a singulation process, and may be also referred to as a lower conductive structure. The lowerconductive structure 3 a may be a die unit after a singulation process. A position of the upperconductive structure 2 a corresponds to a position of the lowerconductive structure 3 a. In some embodiments, the upperconductive structure 2 a may be disposed right above the lowerconductive structure 3 a, and a central axis of the upperconductive structure 2 a may be aligned with a central axis of the lowerconductive structure 3 a. - As shown in
FIG. 4 , the lowerconductive structure 3 a includes at least one dielectric layer (including, for example, one firstupper dielectric layer 30, one secondupper dielectric layer 36, one firstlower dielectric layer 30 a and one secondlower dielectric layer 36 a) and at least one circuit layer (including, for example, one firstupper circuit layer 34, two second upper circuit layers 38, 38′, one firstlower circuit layer 34 a and two second lower circuit layers 38 a, 38 a′ formed of a metal, a metal alloy, or other conductive material) in contact with the dielectric layer (e.g., the firstupper dielectric layer 30, the secondupper dielectric layer 36, the firstlower dielectric layer 30 a and the secondlower dielectric layer 36 a). In some embodiments, the lowerconductive structure 3 a may be similar to a core substrate that further includes acore portion 37. The lowerconductive structure 3 a may be also referred to as “a stacked structure” or “a low-density conductive structure” or “a low-density stacked structure”. The circuit layer (including, for example, the firstupper circuit layer 34, the two second upper circuit layers 38, 38′, the firstlower circuit layer 34 a and the two second lower circuit layers 38 a, 38 a′) of the lowerconductive structure 3 a may be also referred to as “a low-density circuit layer”. As shown inFIG. 4 , the lowerconductive structure 3 a has atop surface 31 and abottom surface 32 opposite to thetop surface 31. The lowerconductive structure 3 a includes a plurality of dielectric layers (for example, the firstupper dielectric layer 30, the secondupper dielectric layer 36, the firstlower dielectric layer 30 a and the secondlower dielectric layer 36 a), a plurality of circuit layers (for example, the firstupper circuit layer 34, the two second upper circuit layers 38, 38′, the firstlower circuit layer 34 a and the two second lower circuit layers 38 a, 38 a′) and at least one inner via (including, for example, a plurality ofupper interconnection vias 35 and a plurality of lower interconnection vias 35 a). - The
core portion 37 has atop surface 371 and abottom surface 372 opposite to thetop surface 371, and defines a plurality of throughholes 373 extending through thecore portion 37. An interconnection via 39 is disposed or formed in each throughhole 373 for vertical connection. In some embodiments, each interconnection via 39 includes a basemetallic layer 391 and aninsulation material 392. The basemetallic layer 391 is disposed or formed on a side wall of the throughhole 373, and defines a central through hole. Theinsulation material 392 fills the central through hole defined by the basemetallic layer 391. In some embodiments, the interconnection via 39 may omit an insulation material, and may include a bulk metallic material that fills the throughhole 373. - The first
upper dielectric layer 30 is disposed on thetop surface 371 of thecore portion 37, and has atop surface 301 and abottom surface 302 opposite to thetop surface 301. Thus, thebottom surface 302 of the firstupper dielectric layer 30 contacts thetop surface 371 of thecore portion 37. The secondupper dielectric layer 36 is stacked or disposed on the firstupper dielectric layer 30, and has atop surface 361 and abottom surface 362 opposite to thetop surface 361. Thus, thebottom surface 362 of the secondupper dielectric layer 36 contacts thetop surface 301 of the firstupper dielectric layer 30, and the secondupper dielectric layer 36 is the topmost dielectric layer. In addition, the firstlower dielectric layer 30 a is disposed on thebottom surface 372 of thecore portion 37, and has atop surface 301 a and abottom surface 302 a opposite to thetop surface 301 a. Thus, thetop surface 301 a of the firstlower dielectric layer 30 a contacts thebottom surface 372 of thecore portion 37. The secondlower dielectric layer 36 a is stacked or disposed on the firstlower dielectric layer 30 a, and has atop surface 361 a and abottom surface 362 a opposite to thetop surface 361 a. Thus, thetop surface 361 a of the secondlower dielectric layer 36 a contacts thebottom surface 302 a of the firstlower dielectric layer 30 a, and the secondlower dielectric layer 36 a is the bottommost dielectric layer. As shown inFIG. 4 , thetop surface 31 of the lowerconductive structure 3 a is thetop surface 361 of the secondupper dielectric layer 36, and thebottom surface 32 of the lowerconductive structure 3 a is thebottom surface 362 a of the secondlower dielectric layer 36 a. - A thickness of each of the dielectric layers (e.g., the first dielectric layers 20 and the second dielectric layer 26) of the upper
conductive structure 2 a is less than or equal to about 40%, less than or equal to about 35%, less than or equal to about 30% of a thickness of each of the dielectric layers (e.g., the firstupper dielectric layer 30, the secondupper dielectric layer 36, the firstlower dielectric layer 30 a and the secondlower dielectric layer 36 a) of the lowerconductive structure 3 a. For example, a thickness of each of the dielectric layers (e.g., the first dielectric layers 20 and the second dielectric layer 26) of the upperconductive structure 2 a may be less than or equal to about 7 μm, and a thickness of each of the dielectric layers (e.g., the firstupper dielectric layer 30, the secondupper dielectric layer 36, the firstlower dielectric layer 30 a and the secondlower dielectric layer 36 a) of the lowerconductive structure 3 a may be about 40 μm. - An L/S of the first
upper circuit layer 34 may be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the firstupper circuit layer 34 may be greater than or equal to about five times the L/S of the first circuit layers 24 of the upperconductive structure 2 a. The firstupper circuit layer 34 has atop surface 341 and abottom surface 342 opposite to thetop surface 341. In some embodiments, the firstupper circuit layer 34 is formed or disposed on thetop surface 371 of thecore portion 37, and covered by the firstupper dielectric layer 30. Thebottom surface 342 of the firstupper circuit layer 34 contacts thetop surface 371 of thecore portion 37. In some embodiments, the firstupper circuit layer 34 may include a firstmetallic layer 343, a secondmetallic layer 344 and a thirdmetallic layer 345. The firstmetallic layer 343 is disposed on thetop surface 371 of thecore portion 37, and may be formed from a copper foil (e.g., may constitute a portion of the copper foil). The secondmetallic layer 344 is disposed on the firstmetallic layer 343, and may be a plated copper layer. The thirdmetallic layer 345 is disposed on the secondmetallic layer 344, and may be another plated copper layer. In some embodiments, the thirdmetallic layer 345 may be omitted. - An L/S of the second
upper circuit layer 38 may be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the secondupper circuit layer 38 may be substantially equal to the L/S of the firstupper circuit layer 34, and may be greater than or equal to about five times the L/S of the first circuit layers 24 of the upperconductive structure 2 a. The secondupper circuit layer 38 has atop surface 381 and abottom surface 382 opposite to thetop surface 381. In some embodiments, the secondupper circuit layer 38 is formed or disposed on thetop surface 301 of the firstupper dielectric layer 30, and covered by the secondupper dielectric layer 36. Thebottom surface 382 of the secondupper circuit layer 38 contacts thetop surface 301 of the firstupper dielectric layer 30. In some embodiments, the secondupper circuit layer 38 is electrically connected to the firstupper circuit layer 34 through theupper interconnection vias 35. That is, the upper interconnection vias 35 are disposed between the secondupper circuit layer 38 and the firstupper circuit layer 34 for electrically connecting the secondupper circuit layer 38 and the firstupper circuit layer 34. In some embodiments, the secondupper circuit layer 38 and the upper interconnection vias 35 are formed integrally as a monolithic or one-piece structure. Each upper interconnection via 35 tapers downwardly along a direction from thetop surface 31 towards thebottom surface 32 of the lowerconductive structure 3 a. - In addition, in some embodiments, the second
upper circuit layer 38′ is disposed on and protrudes from thetop surface 361 of the secondupper dielectric layer 36. In some embodiments, the secondupper circuit layer 38 is electrically connected to the secondupper circuit layer 38′ through theupper interconnection vias 35. That is, the upper interconnection vias 35 are disposed between the second upper circuit layers 38, 38′ for electrically connecting the second upper circuit layers 38, 38′. In some embodiments, the secondupper circuit layer 38′ and the upper interconnection vias 35 are formed integrally as a monolithic or one-piece structure. - An L/S of the first
lower circuit layer 34 a may be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the firstlower circuit layer 34 a may be greater than or equal to about five times the L/S of the first circuit layers 24 of the upperconductive structure 2 a. The firstlower circuit layer 34 a has atop surface 341 a and abottom surface 342 a opposite to thetop surface 341 a. In some embodiments, the firstlower circuit layer 34 a is formed or disposed on thebottom surface 372 of thecore portion 37, and covered by the firstlower dielectric layer 30 a. Thetop surface 341 a of the firstlower circuit layer 34 a contacts thebottom surface 372 of thecore portion 37. In some embodiments, the firstlower circuit layer 34 a may include a firstmetallic layer 343 a, a secondmetallic layer 344 a and a thirdmetallic layer 345 a. The firstmetallic layer 343 a is disposed on thebottom surface 372 of thecore portion 37, and may be formed from a copper foil. The secondmetallic layer 344 a is disposed on the firstmetallic layer 343 a, and may be a plated copper layer. The thirdmetallic layer 345 a is disposed on the secondmetallic layer 344 a, and may be another plated copper layer. In some embodiments, the thirdmetallic layer 345 a may be omitted. - An L/S of the second
lower circuit layer 38 a may be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the secondlower circuit layer 38 a may be substantially equal to the L/S of the firstupper circuit layer 34, and may be greater than or equal to about five times the L/S of the first circuit layers 24 of the upperconductive structure 2 a. The secondlower circuit layer 38 a has atop surface 381 a and abottom surface 382 a opposite to thetop surface 381 a. In some embodiments, the secondlower circuit layer 38 a is formed or disposed on thebottom surface 302 a of the firstlower dielectric layer 30 a, and covered by the secondlower dielectric layer 36 a. Thetop surface 381 a of the secondlower circuit layer 38 a contacts thebottom surface 302 a of the firstlower dielectric layer 30 a. In some embodiments, the secondlower circuit layer 38 a is electrically connected to the firstlower circuit layer 34 a through the lower interconnection vias 35 a. That is, the lower interconnection vias 35 a are disposed between the secondlower circuit layer 38 a and the firstlower circuit layer 34 a for electrically connecting the secondlower circuit layer 38 a and the firstlower circuit layer 34 a. In some embodiments, the secondlower circuit layer 38 a and the lower interconnection vias 35 a are formed integrally as a monolithic or one-piece structure. The lower interconnection vias 35 a tapers upwardly along a direction from thebottom surface 32 towards thetop surface 31 of the lowerconductive structure 3 a. - In addition, in some embodiments, the second
lower circuit layer 38 a′ is disposed on and protrudes from thebottom surface 362 a of the secondlower dielectric layer 36 a. In some embodiments, the secondlower circuit layer 38 a′ is electrically connected to the secondlower circuit layer 38 a through the lower interconnection vias 35 a. That is, the lower interconnection vias 35 a are disposed between the second lower circuit layers 38 a, 38 a′ for electrically connecting the second lower circuit layers 38 a, 38 a′. In some embodiments, the secondlower circuit layer 38 a′ and the lower interconnection vias 35 a are formed integrally as a monolithic or one-piece structure. - In some embodiments, each interconnection via 39 electrically connects the first
upper circuit layer 34 and the firstlower circuit layer 34 a. The basemetallic layer 391 of the interconnection via 39, the secondmetallic layer 344 of the firstupper circuit layer 34 and the secondmetallic layer 344 a the firstlower circuit layer 34 a may be formed integrally and concurrently as a monolithic or one-piece structure. - The
intermediate layer 12 is interposed or disposed between theupper strips 2 and thelower substrate 3 to bond theupper strips 2 and thelower substrate 3 together. That is, theintermediate layer 12 adheres to thebottom surface 22 of the upperconductive structure 2 a and thetop surface 31 of the lowerconductive structure 3 a. In some embodiments, theintermediate layer 12 may be an adhesion layer that is cured from an adhesive material (e.g., includes a cured adhesive material such as an adhesive polymeric material). Theintermediate layer 12 has atop surface 121 and abottom surface 122 opposite to thetop surface 121, and defines at least one throughhole 123 having aninner surface 1231. Thetop surface 121 of theintermediate layer 12 contacts thebottom surface 22 of the upperconductive structure 2 a (that is, thebottom surface 22 of the upperconductive structure 2 a is attached to thetop surface 121 of the intermediate layer 12), and thebottom surface 122 of theintermediate layer 12 contacts thetop surface 31 of the lowerconductive structure 3 a. Thus, the bottommostfirst circuit layer 24 of the upperconductive structure 2 a and thetopmost circuit layer 38′ (e.g., the secondupper circuit layer 38′) of the lowerconductive structure 3 a are embedded in theintermediate layer 12. In some embodiments, a bonding force between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upperconductive structure 2 a is greater than a bonding force between a dielectric layer (e.g., the bottommost first dielectric layers 20) of the upperconductive structure 2 a and theintermediate layer 12. A surface roughness of a boundary between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upperconductive structure 2 a is greater than a surface roughness of a boundary between a dielectric layer (e.g., the bottommost first dielectric layers 20) of the upperconductive structure 2 a and theintermediate layer 12, such as about 1.1 times or greater, about 1.3 times or greater, or about 1.5 times or greater in terms of root mean squared surface roughness. - In some embodiments, a material of the
intermediate layer 12 is transparent, and can be seen through by human eyes or machine. That is, a mark disposed adjacent to thetop surface 31 of the lowerconductive structure 3 a can be recognized or detected from thetop surface 21 of the upperconductive structure 2 a by human eyes or machine. In addition, a material of theintermediate layer 12 may include an insulating film, such as Ajinomoto build-up film (ABF). - The through
hole 123 extends through theintermediate layer 12. In some embodiments, the throughhole 123 of theintermediate layer 12 may extend through the bottommostfirst circuit layer 24 of the upperconductive structure 2 a and terminate at or on a topmost circuit layer (e.g., the secondupper circuit layer 38′) of the lowerconductive structure 3 a. That is, the throughhole 123 of theintermediate layer 12 does not extend through the topmost circuit layer (e.g., the secondupper circuit layer 38′) of the lowerconductive structure 3 a. The throughhole 123 of theintermediate layer 12 may expose a portion of the topmost circuit layer (e.g., the top surface of the secondupper circuit layer 38′) of the lowerconductive structure 3 a. - As shown in
FIG. 4 , the throughhole 123 of theintermediate layer 12 tapers downwardly along a direction from thetop surface 121 towards thebottom surface 122 of theintermediate layer 12; that is, a size of a top portion of the throughhole 123 is greater than a size of a bottom portion of the throughhole 123. Further, the throughhole 123 of theintermediate layer 12 is aligned with and in communication with the throughholes 203 of the first dielectric layers 20 and the throughhole 263 of thesecond dielectric layer 26. The bottom portion of the throughhole 203 of the bottommostfirst dielectric layer 20 is disposed adjacent to or connected to the top portion of the throughhole 123 of theintermediate layer 12. The size of the bottom portion of the throughhole 203 of the bottommostfirst dielectric layer 20 is substantially equal to the size of the top portion of the throughhole 123 of theintermediate layer 12. Thus, theinner surface 1231 of the throughhole 123 of theintermediate layer 12 is coplanar or aligned with theinner surfaces 2031 of the throughholes 203 of the first dielectric layers 20 and theinner surface 2631 of the throughhole 263 of thesecond dielectric layer 26. In some embodiments,inner surface 1231 of the throughhole 123 of theintermediate layer 12 may be a curved surface, and is a portion of aninner surface 231 of the single, continuous throughhole 23 for accommodating the upper through via 14. The throughhole 123 of theintermediate layer 12, the throughhole 203 of thefirst dielectric layer 20 and the throughhole 263 of thesecond dielectric layer 26 are collectively configured to form or define the single throughhole 23. Thus, the single throughhole 23 includes the throughhole 123 of theintermediate layer 12, the throughhole 203 of thefirst dielectric layer 20 and the throughhole 263 of thesecond dielectric layer 26. - As shown in
FIG. 4 , cross-sectional views of one side of the throughhole 123 of theintermediate layer 12, theinner surfaces 2031 of the throughholes 203 of the first dielectric layers 20 and theinner surface 2631 of the throughhole 263 of thesecond dielectric layer 26 are segments of a substantially straight line. That is, cross-sectional views of one side of theinner surface 1231 of the throughhole 123 of theintermediate layer 12, theinner surfaces 2031 of the throughholes 203 of the first dielectric layers 20 and theinner surface 2631 of the throughhole 263 of thesecond dielectric layer 26 may extend along the same substantially straight line. The single throughhole 23 extends through the upperconductive structure 2 a and theintermediate layer 12; that is, the single throughhole 23 extends from thetop surface 21 of the upperconductive structure 2 a to the bottom portion of theintermediate layer 12 to expose a portion of the topmost circuit layer (e.g., the top surface of the secondupper circuit layer 38′) of the lowerconductive structure 3 a. The single throughhole 23 tapers downwardly. A maximum width (e.g., at the top portion) of the single throughhole 23 may be about 25 μm to about 60 μm. - The upper through via 14 is formed or disposed in the corresponding single through
hole 23, and is formed of a metal, a metal alloy, or other conductive material. Thus, the upper through via 14 extends through at least a portion of the upperconductive structure 2 a and theintermediate layer 12, and is electrically connected to the topmost circuit layer (e.g., the top surface of the secondupper circuit layer 38′) of the lowerconductive structure 3 a. As shown inFIG. 4 , the upper through via 14 extends through and contacts the bottommostfirst circuit layer 24 of the upperconductive structure 2 a, and terminates at or on, and contacts a portion of the topmost circuit layer (e.g., the top surface of the secondupper circuit layer 38′) of the lowerconductive structure 3 a. The upper through via 14 extends from thetop surface 21 of the upperconductive structure 2 a to thebottom surface 122 of theintermediate layer 12. Thus, the upper through via 14 extends to contact a portion of the lowerconductive structure 3 a, and the upper through via 14 does not extend through the lowerconductive structure 3 a. In some embodiments, a low-density circuit layer (e.g., the secondupper circuit layer 38′) of the low-density conductive structure (e.g., the lowerconductive structure 3 a) is electrically connected to a high-density circuit layer (e.g., the bottommost first circuit layer 24) of the high-density conductive structure (e.g., the upperconductive structure 2 a) solely by the upper through via 14 extending through the high-density circuit layer (e.g., the bottommost first circuit layer 24) of the high-density conductive structure (e.g., the upperconductive structure 2 a). A length (along a longitudinal axis) of the upper through via 14 is greater than a thickness of the high-density conductive structure (e.g., the upperconductive structure 2 a). Further, the upper through via 14 tapers downwardly; that is, a size of a top portion of the upper through via 14 is greater than a size of a bottom portion of the upper through via 14. Thus, a tapering direction of the inner via 25 of the upperconductive structure 2 a is different from a tapering direction of the upper through via 14. In some embodiments, the upper through via 14 is a monolithic structure or a one-piece structure having a homogeneous material composition, and a peripheral surface of the upper through via 14 is a substantially continuous surface without boundaries. The upper through via 14 and thesecond circuit layer 28 may be formed integrally as a monolithic or one-piece structure. In some embodiments, a maximum width of the upper through via 14 may be less than about 40 such as about 30 μm or about 20 - As shown in the embodiment illustrated in
FIG. 1 toFIG. 4 , thewiring structure 1 is a combination of theupper strips 2 and the lower substrate 3 (e.g., the upperconductive structure 2 a and the lowerconductive structure 3 a), in which thefirst circuit layer 24 of the upper strip 2 (e.g., the upperconductive structure 2 a) has fine pitch, high yield and low thickness; and the circuit layers (e.g., the firstupper circuit layer 34, the second upper circuit layers 38, 38′, the firstlower circuit layer 34 a and the second lower circuit layers 38 a, 38 a′) of the lower substrate 3 (e.g., the lowerconductive structure 3 a) have low manufacturing cost. Thus, thewiring structure 1 has an advantageous compromise of yield and manufacturing cost, and thewiring structure 1 has a relatively low thickness. In some embodiments, if a package has 10000 I/O counts, thewiring structure 1 includes three layers of the first circuit layers 24 of the upper strip 2 (e.g., the upperconductive structure 2 a) and six layers of the circuit layers (e.g., the firstupper circuit layer 34, the second upper circuit layers 38, 38′, the firstlower circuit layer 34 a and the second lower circuit layers 38 a, 38 a′) of the lower substrate 3 (e.g., the lowerconductive structure 3 a). The manufacturing yield for one layer of the first circuit layers 24 of the upper strip 2 (e.g., the upperconductive structure 2 a) may be 99%, and the manufacturing yield for one layer of the circuit layers (e.g., the firstupper circuit layer 34, the second upper circuit layers 38, 38′, the firstlower circuit layer 34 a and the second lower circuit layers 38 a, 38 a′) of the lower substrate 3 (e.g., the lowerconductive structure 3 a) may be 90%. Thus, the yield of thewiring structure 1 may be improved. - In addition, the warpage of the upper strip 2 (e.g., the upper
conductive structure 2 a) and the warpage of the lower substrate 3 (e.g., the lowerconductive structure 3 a) are separated and will not influence each other. In some embodiments, a warpage shape of the upper strip 2 (e.g., the upperconductive structure 2 a) may be different from a warpage shape of the lower substrate 3 (e.g., the lowerconductive structure 3 a). For example, the warpage shape of the upper strip 2 (e.g., the upperconductive structure 2 a) may be a convex shape, and the warpage shape of the lower substrate 3 (e.g., the lowerconductive structure 3 a) may be a concave shape. In some embodiments, the warpage shape of the upper strip 2 (e.g., the upperconductive structure 2 a) may be the same as the warpage shape of the lower substrate 3 (e.g., the lowerconductive structure 3 a); however, the warpage of the lower substrate 3 (e.g., the lowerconductive structure 3 a) will not be accumulated onto the warpage of the upper strip 2 (e.g., the upperconductive structure 2 a). Thus, the yield of thewiring structure 1 may be further improved. - In addition, during a manufacturing process, the lower substrate 3 (e.g., the lower
conductive structure 3 a) and the upper strip 2 (e.g., the upperconductive structure 2 a) may be tested individually before being bonded together. Therefore, known good lower substrate 3 (e.g., the lowerconductive structure 3 a) and known good upper strip 2 (e.g., the upperconductive structure 2 a) may be selectively bonded together. Bad (or unqualified) lower substrate 3 (e.g., the lowerconductive structure 3 a) and bad (or unqualified) upper strip 2 (e.g., the upperconductive structure 2 a) may be discarded. As a result, the yield of thewiring structure 1 may be further improved. - In addition, during a manufacturing process, the relative positions of the
upper strips 2 are separated and will not influence each other. In some embodiments, if one or some of theupper strips 2 may be shifted with respect to a predetermined position of thelower substrate 3, the otherupper strips 2 still can be disposed on a predetermined position of thelower substrate 3. In addition, the design of theupper strips 2 can increase effective area of thelower substrate 3. That is, thelower substrate 3 can carry more upper strips 2 (or upperconductive structures 2 a) as compared with a panel type of upper conductive structure. -
FIG. 5 illustrates a cross-sectional view of a wiring structure 1 a according to some embodiments of the present disclosure. The wiring structure 1 a is similar to thewiring structure 1 shown inFIG. 4 , except for structures of an upperconductive structure 2 a and a lowerconductive structure 3 a. As shown inFIG. 5 , the upperconductive structure 2 a and the lowerconductive structure 3 a are both die units after a singulation process. In addition, a lateralperipheral surface 27 of the upperconductive structure 2 a, a lateralperipheral surface 125 of theintermediate layer 12 and a lateralperipheral surface 33 of the lowerconductive structure 3 a are substantially coplanar with each other. That is, a size of the upperconductive structure 2 a is equal to a size of the lowerconductive structure 3 a. -
FIG. 6 illustrates a cross-sectional view of a wiring structure 1 b according to some embodiments of the present disclosure. The wiring structure 1 b is similar to the wiring structure 1 a shown inFIG. 5 , except for a structure of at least one through via 16. The through via 16 is disposed in a single, continuous throughhole 17. The single throughhole 17 extends through the upperconductive structure 2 a, theintermediate layer 12 and the lowerconductive structure 3 a (including the secondlower circuit layer 38 a′); that is, the single throughhole 17 extends from thetop surface 21 of the upperconductive structure 2 a to thebottom surface 32 of the lowerconductive structure 3 a. A maximum width of the single throughhole 17 may be about 100 μm to about 1000 μm. In some embodiments, the single throughhole 17 may be formed by mechanical drilling. Thus, the throughhole 17 may not taper, and theinner surface 171 of the throughhole 17 may be substantially perpendicular to thetop surface 21 of the upperconductive structure 2 a and/or thebottom surface 32 of the lowerconductive structure 3 a. - Each through via 16 is formed or disposed in the corresponding through
hole 17, and is formed of a metal, a metal alloy, or other conductive material. Thus, the through via 16 extends through the upperconductive structure 2 a, theintermediate layer 12 and the lowerconductive structure 3 a. As shown inFIG. 6 , the lower through via 16 extends through and contacts thebottommost circuit layer 24 of the upperconductive structure 2 a, the topmost circuit layer (e.g., the secondupper circuit layer 38′) of the lowerconductive structure 3 a, and the bottommost circuit layer (e.g., the secondlower circuit layer 38 a′) of the lowerconductive structure 3 a. In some embodiments, a low-density circuit layer (e.g., the secondupper circuit layer 38′) of the low-density conductive structure (e.g., the lowerconductive structure 3 a) is electrically connected to a high-density circuit layer (e.g., the first circuit layer 24) of the high-density conductive structure (e.g., the upperconductive structure 2 a) solely by the through via 16. In some embodiments, the through via 16 is a monolithic structure or one-piece structure having a homogeneous material composition, and aperipheral surface 163 of the through via 16 is a substantially continuous surface without boundaries. The through via 16 and theouter circuit layer 28 may be formed integrally. -
FIG. 7 illustrates a cross-sectional view of a wiring structure 1 c according to some embodiments of the present disclosure. The wiring structure 1 c is similar to the wiring structure 1 a shown inFIG. 5 , except for structures of an upperconductive structure 2 c, a lowerconductive structure 3 c and alower encapsulant 80. A size of the upperconductive structure 2 c is substantially equal to a size of the lowerconductive structure 3 c. Thus, a width W2 of the upperconductive structure 2 c is substantially equal to a width W3 of the lowerconductive structure 3 c. The lateralperipheral surface 27 of the upperconductive structure 2 c is substantially coplanar with the lateralperipheral surface 33 of the lowerconductive structure 3 c. Thelower encapsulant 80 surrounds the lateralperipheral surface 33 of the lowerconductive structure 3 c. In some embodiments, thelower encapsulant 80 may be a molding compound, and may cover and contact the lateralperipheral surface 33 of the lowerconductive structure 3 c. Thus, the lateralperipheral surface 27 of the upperconductive structure 2 c is not coplanar with (e.g., is inwardly recessed from or otherwise displaced from) a lateralperipheral surface 803 of thelower encapsulant 80. In addition, a portion of theintermediate layer 12 covers atop surface 801 of thelower encapsulant 80. Thus, the lateralperipheral surface 27 of the upperconductive structure 2 c is not coplanar with (e.g., is inwardly recessed from or otherwise displaced from) the lateralperipheral surface 125 of theintermediate layer 12. In some embodiments, during a manufacturing process, a plurality of lowerconductive structures 3 c may be known good die units and are reconstituted and encapsulated in thelower encapsulant 80. Then, a plurality of known good upperconductive structures 2 c are attached to the lowerconductive structures 3 c respectively. Then, a singulation process is conducted along thelower encapsulant 80. Thus, a portion of thelower encapsulant 80 remains on the lateralperipheral surface 33 of the lowerconductive structure 3 c. -
FIG. 8 illustrates a cross-sectional view of awiring structure 1 d according to some embodiments of the present disclosure. Thewiring structure 1 d is similar to the wiring structure 1 c shown inFIG. 7 , except for a structure of an upperconductive structure 2 d. A size of the upperconductive structure 2 d is smaller than a size of the lowerconductive structure 3 c. Thus, a width W2′ of the upperconductive structure 2 d is less than the width W3 of the lowerconductive structure 3 c. The lateralperipheral surface 27 of the upperconductive structure 2 d is not coplanar with (e.g., is inwardly recessed from or otherwise displaced from) the lateralperipheral surface 33 of the lowerconductive structure 3 c. -
FIG. 9 illustrates a cross-sectional view of a wiring structure 1 e according to some embodiments of the present disclosure. The wiring structure 1 e is similar to the wiring structure 1 c shown inFIG. 7 , except that anupper encapsulant 82 is further included. Theupper encapsulant 82 surrounds the lateralperipheral surface 27 of the upperconductive structure 2 c. In some embodiments, theupper encapsulant 82 may be a molding compound, and may cover and contact the lateralperipheral surface 27 of the upperconductive structure 2 c. Thus, a lateralperipheral surface 823 of theupper encapsulant 82 is substantially coplanar with the lateralperipheral surface 803 of thelower encapsulant 80. In addition, theupper encapsulant 82 may cover and contact a portion a top surface of theintermediate layer 12. In some embodiments, during a manufacturing process, a plurality of lowerconductive structures 3 c may be known good die units and are reconstituted and encapsulated in thelower encapsulant 80, and a plurality of upperconductive structures 2 c may be known good die units and are reconstituted and encapsulated in theupper encapsulant 82. Then, theconductive structures 2 c with theupper encapsulant 82 are attached to the lowerconductive structures 3 c with thelower encapsulant 80. Then, a singulation process is conducted along theupper encapsulant 82 and thelower encapsulant 80. Thus, a portion of theupper encapsulant 82 remains on the lateralperipheral surface 27 of the upperconductive structure 2 c, and a portion of thelower encapsulant 80 remains on the lateralperipheral surface 33 of the lowerconductive structure 3 c. -
FIG. 10 illustrates a cross-sectional view of a wiring structure if according to some embodiments of the present disclosure. The wiring structure if is similar to the wiring structure 1 e shown inFIG. 9 , except for a structure of an upperconductive structure 2 f. A size of the upperconductive structure 2 f is smaller than a size of the lowerconductive structure 3 c. Thus, a width W2′ of the upperconductive structure 2 f is less than the width W3 of the lowerconductive structure 3 c. The lateralperipheral surface 27 of the upperconductive structure 2 f is not coplanar with (e.g., is inwardly recessed from or otherwise displaced from) the lateralperipheral surface 33 of the lowerconductive structure 3 c. -
FIG. 11 throughFIG. 51 illustrate a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing thewiring structure 1 shown inFIG. 4 and/or the wiring structure 1 a shown inFIG. 5 . - Referring to
FIG. 11 throughFIG. 31 , alower substrate 3 is provided. Thelower substrate 3 is manufactured as follows. Referring toFIG. 11 , acore portion 37 with atop copper foil 50 and abottom copper foil 52 is provided. Thecore portion 37 has atop surface 371 and abottom surface 372 opposite to thetop surface 371. Thetop copper foil 50 is disposed on thetop surface 371 of thecore portion 37, and thebottom copper foil 52 is disposed on thebottom surface 372 of thecore portion 37. - Referring to
FIG. 12 , a plurality of throughholes 373 are formed to extend through thecore portion 37, thetop copper foil 50 and thebottom copper foil 52 by a drilling technique (such as laser drilling or mechanical drilling) or other suitable techniques. - Referring to
FIG. 13 , a secondmetallic layer 54 is formed or disposed on thetop copper foil 50, thebottom copper foil 52 and side walls of the first throughholes 373 by a plating technique or other suitable techniques. A portion of the secondmetallic layer 54 on the side wall of each first throughhole 373 defines a central through hole. - Referring to
FIG. 14 , aninsulation material 392 is disposed to fill the central through hole defined by the secondmetallic layer 54. - Referring to
FIG. 15 , a top thirdmetallic layer 56 and a bottom thirdmetallic layer 56 a are formed or disposed on the secondmetallic layer 54 by a plating technique or other suitable techniques. The thirdmetallic layers insulation material 392. - Referring to
FIG. 16 , atop photoresist layer 57 is formed or disposed on the top thirdmetallic layer 56, and abottom photoresist layer 57 a is formed or disposed on the bottom thirdmetallic layer 56 a. Then, the photoresist layers 57, 57 a are patterned by exposure and development. - Referring to
FIG. 17 , portions of thetop copper foil 50, the secondmetallic layer 54 and the top thirdmetallic layer 56 that are not covered by thetop photoresist layer 57 are removed by an etching technique or other suitable techniques. Portions of thetop copper foil 50, the secondmetallic layer 54 and the top thirdmetallic layer 56 that are covered by thetop photoresist layer 57 remain to form a firstupper circuit layer 34. Meanwhile, portions of thebottom copper foil 52, the secondmetallic layer 54 and the bottom thirdmetallic layer 56 a that are not covered by thebottom photoresist layer 57 a are removed by an etching technique or other suitable techniques. Portions of thebottom copper foil 52, the secondmetallic layer 54 and the bottom thirdmetallic layer 56 a that are covered by thebottom photoresist layer 57 a remain to form a firstlower circuit layer 34 a. Meanwhile, portions of the secondmetallic layer 54 and theinsulation material 392 that are disposed in the throughhole 373 form an interconnection via 39. The interconnection via 39 electrically connects the firstupper circuit layer 34 and the firstlower circuit layer 34 a. - Referring to
FIG. 18 , thetop photoresist layer 57 and thebottom photoresist layer 57 a are removed by a stripping technique or other suitable techniques. - Referring to
FIG. 19 , a firstupper dielectric layer 30 is formed or disposed on thetop surface 371 of thecore portion 37 to cover thetop surface 371 of thecore portion 37 and the firstupper circuit layer 34 by a lamination technique or other suitable techniques. Meanwhile, a firstlower dielectric layer 30 a is formed or disposed on thebottom surface 372 of thecore portion 37 to cover thebottom surface 372 of thecore portion 37 and the firstlower circuit layer 34 a by a lamination technique or other suitable techniques. - Referring to
FIG. 20 , at least one throughhole 303 is formed to extend through the firstupper dielectric layer 30 to expose a portion of the firstupper circuit layer 34 by a drilling technique or other suitable techniques. Meanwhile, at least one throughhole 303 a is formed to extend through the firstlower dielectric layer 30 a to expose a portion of the firstlower circuit layer 34 a by a drilling technique or other suitable techniques. - Referring to
FIG. 21 , a topmetallic layer 58 is formed on the firstupper dielectric layer 30 and in the throughhole 303 to form an upper interconnection via 35 by a plating technique or other suitable techniques. Meanwhile, a bottommetallic layer 60 is formed on the firstlower dielectric layer 30 a and in the throughhole 303 a to form a lower interconnection via 35 a by a plating technique or other suitable techniques. - Referring to
FIG. 22 , atop photoresist layer 59 is formed or disposed on the topmetallic layer 58, and abottom photoresist layer 59 a is formed or disposed on the bottommetallic layer 60. Then, the photoresist layers 59, 59 a are patterned by exposure and development. - Referring to
FIG. 23 , portions of the topmetallic layer 58 that are not covered by thetop photoresist layer 59 are removed by an etching technique or other suitable techniques. Portions of the topmetallic layer 58 that are covered by thetop photoresist layer 59 remain to form a secondupper circuit layer 38. Meanwhile, portions of the bottommetallic layer 60 that are not covered by thebottom photoresist layer 59 a are removed by an etching technique or other suitable techniques. Portions of the bottommetallic layer 60 that are covered by thebottom photoresist layer 59 a remain to form a secondlower circuit layer 38 a. - Referring to
FIG. 24 , thetop photoresist layer 59 and thebottom photoresist layer 59 a are removed by a stripping technique or other suitable techniques. - Referring to
FIG. 25 , a secondupper dielectric layer 36 is formed or disposed on thetop surface 301 of the firstupper dielectric layer 30 to cover thetop surface 301 of the firstupper dielectric layer 30 and the secondupper circuit layer 38 by a lamination technique or other suitable techniques. Meanwhile, a secondlower dielectric layer 36 a is formed or disposed on thebottom surface 302 a of the firstlower dielectric layer 30 a to cover thebottom surface 302 a of the firstlower dielectric layer 30 a and the secondlower circuit layer 38 a by a lamination technique or other suitable techniques. - Referring to
FIG. 26 , at least one throughhole 363 is formed to extend through the secondupper dielectric layer 36 to expose a portion of the secondupper circuit layer 38 by a drilling technique or other suitable techniques. Meanwhile, at least one throughhole 363 a is formed to extend through the secondlower dielectric layer 36 a to expose a portion of the secondlower circuit layer 38 a by a drilling technique or other suitable techniques. - Referring to
FIG. 27 , a topmetallic layer 62 is formed on the secondupper dielectric layer 36 and in the throughhole 363 to form an upper interconnection via 35 by a plating technique or other suitable techniques. Meanwhile, a bottommetallic layer 64 is formed on the secondlower dielectric layer 36 a and in the throughhole 363 a to form a lower interconnection via 35 a by a plating technique or other suitable techniques. - Referring to
FIG. 28 , atop photoresist layer 63 is formed or disposed on the topmetallic layer 62, and abottom photoresist layer 63 a is formed or disposed on the bottommetallic layer 64. Then, the photoresist layers 63, 63 a are patterned by exposure and development. - Referring to
FIG. 29 , portions of the topmetallic layer 62 that are not covered by thetop photoresist layer 63 are removed by an etching technique or other suitable techniques. Portions of the topmetallic layer 62 that are covered by thetop photoresist layer 63 remain to form a secondupper circuit layer 38′. Meanwhile, portions of the bottommetallic layer 64 that are not covered by thebottom photoresist layer 63 a are removed by an etching technique or other suitable techniques. Portions of the bottommetallic layer 64 that are covered by thebottom photoresist layer 63 a remain to form a secondlower circuit layer 38 a′. - Referring to
FIG. 30 , thetop photoresist layer 63 and thebottom photoresist layer 63 a are removed by a stripping technique or other suitable techniques. Meanwhile, thelower substrate 3 with at least one lowerconductive structure 3 a is formed. - Referring to
FIG. 30 andFIG. 31 , whereinFIG. 31 illustrates a perspective view of thelower substrate 3 ofFIG. 30 . Thelower substrate 3 includes at least one lowerconductive structure 3 a. For example, thelower substrate 3 may include a plurality of lowerconductive structures 3 a arranged in an array. Thelower substrate 3 includes a plurality ofstrip areas 3′. Then, an electrical property (such as open circuit/short circuit) of the lower substrate 3 (e.g., the lowerconductive structures 3 a of thestrip areas 3′) is tested. - Referring to
FIG. 32 throughFIG. 44 , a plurality ofupper strips 2 are provided. Theupper strips 2 are manufactured as follows. Referring toFIG. 32 , acarrier 65 is provided. Thecarrier 65 may be a glass carrier, and may be in a wafer type or a panel type. - Referring to
FIG. 33 , arelease layer 66 is coated on a bottom surface of thecarrier 65. - Referring to
FIG. 34 , a conductive layer 67 (e.g., a seed layer) is formed or disposed on therelease layer 66 by a physical vapor deposition (PVD) technique or other suitable techniques. - Referring to
FIG. 35 , asecond dielectric layer 26 is formed on theconductive layer 67 by a coating technique or other suitable techniques. - Referring to
FIG. 36 , at least one throughhole 264 is formed to extend through thesecond dielectric layer 26 to expose a portion of theconductive layer 67 by an exposure and development technique or other suitable techniques. - Referring to
FIG. 37 , aseed layer 68 is formed on abottom surface 262 of thesecond dielectric layer 26 and in the throughhole 264 by a PVD technique or other suitable techniques. - Referring to
FIG. 38 , aphotoresist layer 69 is formed on theseed layer 68. Then, thephotoresist layer 69 is patterned to expose portions of theseed layer 68 by an exposure and development technique or other suitable techniques. Thephotoresist layer 69 defines a plurality ofopenings 691. At least oneopening 691 of thephotoresist layer 69 corresponds to, and is aligned with, the throughhole 264 of thesecond dielectric layer 26. - Referring to
FIG. 39 , a conductive material 70 (e.g., a metallic material) is disposed in theopenings 691 of thephotoresist layer 69 and on theseed layer 68 by a plating technique or other suitable techniques. - Referring to
FIG. 40 , thephotoresist layer 69 is removed by a stripping technique or other suitable techniques. - Referring to
FIG. 41 , portions of theseed layer 68 that are not covered by theconductive material 70 are removed by an etching technique or other suitable techniques. Meanwhile, acircuit layer 24 and at least one inner via 25 are formed. Thecircuit layer 24 may be a fan-out circuit layer or an RDL, and an L/S of thecircuit layer 24 may be less than or equal to about 2 μm/about 2 μm, or less than or equal to about 1.8 μm/about 1.8 μm. The inner via 25 is disposed in the throughhole 264 of thesecond dielectric layer 26. In some embodiments, the inner via 25 tapers upwardly. - Referring to
FIG. 42 , a plurality of firstdielectric layers 20 and a plurality of circuit layers 24 are formed by repeating the stages ofFIG. 35 toFIG. 41 . In some embodiments, eachcircuit layer 24 is embedded in the correspondingfirst dielectric layer 20, and atop surface 241 of thecircuit layer 24 may be substantially coplanar with atop surface 201 of thefirst dielectric layer 20. Meanwhile, aconductive structure 2′ is formed. Then, an electrical property (such as open circuit/short circuit) of theconductive structure 2′ is tested. It is noted that theconductive structure 2′ may be in a wafer type or a panel type. - Referring to
FIG. 43 andFIG. 44 , whereinFIG. 44 illustrates perspective views of theupper strips 2 ofFIG. 43 . Theconductive structure 2′ and thecarrier 65 are cut to form a plurality ofupper strips 2 with a plurality of carrier strips 65 a. Each of theupper strips 2 includes at least one upperconductive structure 2 a. For example, each of theupper strips 2 may include a plurality of upperconductive structures 2 a arranged in a row. It is noted that theupper strip 2 is in a strip type. - Referring to
FIG. 45 , anadhesive layer 12 is formed or applied on thetop surface 31 of thelower substrate 3. A material of theadhesive layer 12 may include an insulating film, such as ABF. In some embodiments, thelower substrate 3 may have a plurality of cutting lines 87. - Referring to
FIG. 46 , theupper strips 2 and the carrier strips 65 a are attached to thestrip areas 3′ of thelower substrate 3 side by side through theadhesive layer 12. Theupper strips 2 face thelower substrate 3. A position of the upperconductive structure 2 a of theupper strip 2 and thecarrier strip 65 a corresponds to a position of the lowerconductive structure 3 a of thelower substrate 3. That is, the upperconductive structure 2 a is disposed right above the lowerconductive structure 3 a. In some embodiments, known goodupper strip 2′ is selectively attached to knowngood strip area 3′ of thelower substrate 3. For example, a desired yield of the wiring structure 1 a (FIG. 5 ) may be set to be 80%. That is, (the yield of the upper strip 2)×(the yield of thestrip area 3′ of the lower substrate 3) is set to be greater than or equal to 80%. If a yield of theupper strip 2 is less than a predetermined yield such as 80% (which is specified as bad or unqualified component), then, the bad (or unqualified)upper strip 2 is discarded. If a yield of theupper strip 2 is greater than or equal to the predetermined yield such as 80% (which is specified as known good or qualified component), then the known goodupper strip 2 can be used. In addition, if a yield of thestrip area 3′ of thelower substrate 3 is less than a predetermined yield such as 80% (which is specified as bad or unqualified component), then the bad (or unqualified)strip area 3′ is marked and will not be bonded with anyupper strip 2. If a yield of thestrip area 3′ of thelower substrate 3 is greater than or equal to the predetermined yield such as 80% (which is specified as known good component or qualified component), then the known goodupper strip 2 can be bonded to the knowngood strip area 3′ of thelower substrate 3. It is noted that theupper strip 2 having a yield of 80% will not be bonded to thestrip area 3′ of thelower substrate 3 having a yield of 80%, since the resultant yield of the wiring structure 1 a (FIG. 5 ) is 64%, which is lower than the desired yield of 80%. Theupper strip 2 having a yield of 80% can be bonded to thestrip area 3′ of thelower substrate 3 having a yield of 100%; thus, the resultant yield of the wiring structure 1 a (FIG. 5 ) can be 80%. In addition, anupper strip 2 having a yield of 90% can be bonded to thestrip area 3′ of thelower substrate 3 having a yield of greater than 90%, since the resultant yield of the wiring structure 1 a (FIG. 5 ) can be greater than 80%. - In addition, the relative positions of the
upper strips 2 are separated and will not influence each other. In some embodiments, if one or some of theupper strips 2 may be shifted with respect to a predetermined position of thelower substrate 3, the otherupper strips 2 still can be disposed on a predetermined position of thelower substrate 3. - Then, the
adhesive layer 12 is cured to form anintermediate layer 12. - Referring to
FIG. 47 , the carrier strips 65 a, therelease layer 66 and theconductive layer 67 are removed so as to expose a portion of the inner via 25. - Referring to
FIG. 48 , at least one throughhole 23 is formed to extend through at least a portion of the upperconductive structure 2 and theintermediate layer 12 by drilling (such as laser drilling) to exposes a circuit layer (e.g., secondupper circuit layer 38′) of the lowerconductive structure 3. The throughhole 23 may include a throughhole 263 of thesecond dielectric layer 26, a plurality of throughholes 203 of the first dielectric layers 20 and a throughhole 123 of theintermediate layer 12. In some embodiments, the throughhole 23 extends through the bottommostfirst circuit layer 24 of the upperconductive structure 2 and terminates at or on a topmost circuit layer (e.g., the secondupper circuit layer 38′) of the lowerconductive structure 3. That is, the throughhole 23 does not extend through the topmost circuit layer (e.g., the secondupper circuit layer 38′) of the lowerconductive structure 3. The throughhole 23 may expose a portion of the topmost circuit layer (e.g., the top surface of the secondupper circuit layer 38′) of the lowerconductive structure 3. As shown inFIG. 48 , the throughhole 23 tapers downwardly; that is, a size of a top portion of the throughhole 23 is greater than a size of a bottom portion of the throughhole 23. In addition, aninner surface 1231 of the throughhole 123 of theintermediate layer 12 is coplanar with or aligned withinner surfaces 2031 of the throughholes 203 of the first dielectric layers 20 and aninner surface 2631 of the throughhole 263 of thesecond dielectric layer 26. - Referring to
FIG. 49 , ametallic layer 72 is formed on thesurface 21 of the upperconductive structure 2 and in the throughhole 23 to form at least one upper through via 14 in the throughhole 23 by a plating technique or other suitable techniques. Thus, the upperconductive structure 2 a of theupper strip 2 is electrically connected to the lowerconductive structure 3 a of thelower substrate 3 through the upper through via 14. - Referring to
FIG. 50 , atop photoresist layer 73 is formed or disposed on themetallic layer 72, and abottom photoresist layer 73 a is formed or disposed on thebottom surface 32 of the lowerconductive structure 3. Then, thetop photoresist layer 73 is patterned by an exposure and development technique or other suitable techniques. - Referring to
FIG. 51 , portions of themetallic layer 72 that are not covered by thetop photoresist layer 73 are removed by an etching technique or other suitable techniques. Portions of themetallic layer 72 that are covered by thetop photoresist layer 73 remain to form asecond circuit layer 28. Then, thetop photoresist layer 73 and thebottom photoresist layer 73 a are removed by a stripping technique or other suitable techniques, so as to obtain thewiring structure 1 ofFIG. 1 toFIG. 4 . - In some embodiments, a singulation process is conducted to the lower
conductive structure 3 and theintermediate layer 12 along thecutting lines 87 to obtain a plurality of wiring structure 1 a ofFIG. 5 . -
FIG. 52 throughFIG. 59 illustrate a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing the wiring structure 1 c shown inFIG. 7 . The initial stages of the illustrated process are the same as, or similar to, the stages illustrated inFIG. 11 toFIG. 31 .FIG. 52 depicts a stage subsequent to that depicted inFIG. 31 . - Referring to
FIG. 52 , a top view of thelower substrate 3 is illustrated. After a testing process, the lowerconductive structures 3 a that pass the testing are marked as known good die units or qualified die units. Meanwhile, the lowerconductive structures 3 a′ that fail to pass the testing are marked as known bad die units or unqualified die units. - Referring to
FIG. 53 , the known good lowerconductive structures 3 a are singulated and picked up from thelower substrate 3 to form a plurality ofopenings 84 in thelower substrate 3. In addition, the known bad lowerconductive structures 3 a′ remain in thelower substrate 3, and may be discarded. - Referring to
FIG. 54 , the known good lowerconductive structures 3 a are selectively constituted and rearranged is an array. Then, a lower encapsulant 80 (e.g., molding compound) is formed to encapsulate the known good lowerconductive structures 3 a to form alower module 86. - The following stages of the illustrated process are the same as, or similar to, the stages illustrated in
FIG. 32 toFIG. 42 .FIG. 55 depicts a stage subsequent to that depicted inFIG. 42 . Referring toFIG. 55 , theconductive structure 2′ and thecarrier 65 ofFIG. 42 are cut to form a plurality of upperconductive structures 2 a. It is noted that each of the upperconductive structures 2 a is a die unit. - Referring to
FIG. 56 ,FIG. 57 andFIG. 58 , whereinFIG. 57 illustrates a perspective view ofFIG. 56 , andFIG. 58 illustrates a cross-sectional view a portion ofFIG. 56 . The upperconductive structures 2 a and thecarrier 65 are attached to thelower module 86 through anadhesive layer 12. The upperconductive structures 2 a face thelower module 86. Then, theadhesive layer 12 is cured to form anintermediate layer 12. Then, the carrier strips 65, therelease layer 66 and theconductive layer 67 are removed so as to expose a portion of the inner via 25. As shown inFIG. 56 andFIG. 58 , thelower module 86 may include a plurality of cuttinglines 87 crossed with each other. - Referring to
FIG. 59 , at least one upper through via 14 is formed to extend through the upperconductive structure 2 a and theintermediate layer 12. Thus, the upperconductive structures 2 a are electrically connected to the lowerconductive structures 3 a of thelower module 86 through the upper through via 14. - Then, a singulation process is conducted to singulate the
lower module 86 along thecutting lines 87 to form a plurality of wiring structures 1 c ofFIG. 7 . -
FIG. 60 throughFIG. 65 illustrate a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing the wiring structure 1 e shown inFIG. 9 . The initial stages of the illustrated process are the same as, or similar to, the stages illustrated inFIG. 11 toFIG. 31 ,FIG. 52 toFIG. 54 , andFIG. 32 toFIG. 42 .FIG. 60 depicts a stage subsequent to that depicted inFIG. 42 . - Referring to
FIG. 60 , a top view of theconductive structure 2′ is illustrated. After a testing process, the upperconductive structures 2 a that pass the testing are marked as known good die units or qualified die units. Meanwhile, the upperconductive structures 2 a′ that fail to pass the testing are marked as known bad die units or unqualified die units. - Referring to
FIG. 61 , the known good upperconductive structures 2 a are singulated and picked up from theconductive structure 2′ to form a plurality ofopenings 88 in theconductive structure 2′. In addition, the known bad upperconductive structures 2 a′ remain in theconductive structure 2′, and may be discarded. - Referring to
FIG. 62 , the known good upperconductive structures 2 a are selectively constituted and rearranged is an array. Then, an upper encapsulant 82 (e.g., molding compound) is formed to encapsulate the known good upperconductive structures 2 a to form anupper module 90. - Referring to
FIG. 63 andFIG. 64 , whereinFIG. 64 illustrates a cross-sectional view of a portion ofFIG. 63 . Theupper module 90 is attached to thelower module 86 through anadhesive layer 12. Thus, the known good upperconductive structures 2 a are attached to the known good lowerconductive structures 3 a respectively. Then, theadhesive layer 12 is cured to form anintermediate layer 12. - Referring to
FIG. 65 , at least one upper through via 14 is formed to extend through the upperconductive structure 2 a and theintermediate layer 12. Thus, the upperconductive structures 2 a of theupper module 90 are electrically connected to the lowerconductive structures 3 a of thelower module 86 through the upper through via 14. - Then, a singulation process is conducted to singulate the
lower module 86, theintermediate layer 12 and theupper module 90 along the cutting lines to form a plurality of wiring structures 1 e ofFIG. 9 . - Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such an arrangement.
- As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, a first numerical value can be deemed to be “substantially” the same or equal to a second numerical value if the first numerical value is within a range of variation of less than or equal to ±10% of the second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.
- Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. A surface can be deemed to be substantially flat if a displacement between a highest point and a lowest point of the surface is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.
- As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise.
- As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 104 S/m, such as at least 105 S/m or at least 106 S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.
- Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
- While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.
Claims (30)
1. A wiring structure, comprising:
an upper conductive structure including at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer;
a lower conductive structure including at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer;
a lower encapsulant surrounding a lateral peripheral surface of the lower conductive structure; and
an intermediate layer disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure,
wherein a lateral peripheral surface of the intermediate layer is substantially coplanar with a lateral peripheral surface of the lower encapsulant.
2. The wiring structure of claim 1 , wherein a lateral peripheral surface of the upper conductive structure is inwardly recessed from the lateral peripheral surface of the lower encapsulant.
3. The wiring structure of claim 1 , wherein a lateral peripheral surface of the upper conductive structure is substantially coplanar with a lateral peripheral surface of the lower conductive structure.
4. The wiring structure of claim 1 , wherein a lateral peripheral surface of the upper conductive structure is inwardly recessed from a lateral peripheral surface of the lower conductive structure.
5. The wiring structure of claim 1 , wherein a portion of the intermediate layer covers a top surface of the lower encapsulant.
6. The wiring structure of claim 1 , further comprising an upper encapsulant surrounding a lateral peripheral surface of the upper conductive structure.
7. The wiring structure of claim 6 , wherein a lateral peripheral surface of the upper encapsulant is substantially coplanar with the lateral peripheral surface of the lower encapsulant.
8. The wiring structure of claim 6 , wherein the lateral peripheral surface of the upper conductive structure is substantially coplanar with a lateral peripheral surface of the lower conductive structure.
9. The wiring structure of claim 6 , wherein the lateral peripheral surface of the upper conductive structure is inwardly recessed from a lateral peripheral surface of the lower conductive structure.
10. The wiring structure of claim 1 , wherein a line space of the lower circuit layer of the lower conductive structure is greater than a line space of the upper circuit layer of the upper conductive structure.
11. A method for manufacturing a wiring structure, comprising:
(a) providing a lower substrate including at least one lower conductive structure, wherein the lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
(b) providing a plurality of upper strips, wherein each of the upper strips includes at least one upper conductive structure, and the upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
(c) attaching the upper strips to the lower substrate side by side, wherein a position of the upper conductive structure of the upper strip corresponds to a position of the lower conductive structure of the lower substrate;
(d) electrically connecting the upper conductive structure of the upper strip and the lower conductive structure of the lower substrate; and
(e) conducting a singulation process to form a plurality of wiring structures.
12. The method of claim 11 , wherein (b) comprises:
(b1) forming a conductive structure on a carrier; and
(b2) cutting the conductive structure and the carrier to form the upper strips with a plurality of carrier strips;
wherein in (c), the upper strips and the carrier strips are attached to the lower substrate, wherein the upper strips face the lower substrate;
wherein after (c), the method further comprises:
(c1) removing the carrier strips.
13. The method of claim 11 , wherein after (a), the method further comprises:
(a1) testing an electrical property of the lower conductive structure of the lower substrate; and
wherein after (b), the method further comprises:
(b1) testing an electrical property of the upper conductive structure of the upper strip.
14. The method of claim 11 , wherein in (c), the upper strips are attached to the lower substrate through an adhesive layer.
15. The method of claim 11 , wherein (d) includes:
(d1) forming at least one through hole to extend through the upper conductive structure of the upper strip by drilling; and
(d2) forming at least one upper through via in the through hole.
16. A method for manufacturing a wiring structure, comprising:
(a) providing a plurality of lower conductive structures, wherein each of the lower conductive structures includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
(b) forming a lower encapsulant to encapsulate a plurality of known good lower conductive structures to form a lower module;
(c) providing a plurality of upper conductive structures, wherein each of the upper conductive structures includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer of the upper conductive structure;
(d) attaching the upper conductive structures to the known good lower conductive structures of the lower module respectively;
(e) electrically connecting the upper conductive structures and the known good lower conductive structures of the lower module; and
(f) conducting a singulation process to form a plurality of wiring structures.
17. The method of claim 16 , wherein (c) comprises:
(c1) forming a conductive structure on a carrier; and
(c2) cutting the conductive structure and the carrier to form the plurality of upper conductive structures;
wherein in (d), the upper conductive structures and the carrier are attached to the lower module, wherein the upper conductive structures face the lower module;
wherein after (d), the method further comprises:
(d1) removing the carrier.
18. The method of claim 16 , wherein after (c), the method further comprises:
(c1) forming an upper encapsulant to encapsulate a plurality of known good upper conductive structures to form an upper module.
19. The method of claim 18 , wherein (d) comprises:
(d1) attaching the upper module to the lower module.
20. The method of claim 16 , wherein in (d), the upper conductive structures are attached to the known good lower conductive structures of the lower module through an adhesive layer.
21. A wiring structure, comprising:
a high-density conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
a low-density conductive structure bonded to and electrically connected to the high-density conductive structure, and including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
a lower encapsulant surrounding a lateral peripheral surface of the low-density conductive structure; and
an intermediate layer disposed between the high-density conductive structure and the low-density conductive structure and bonding the high-density conductive structure and the low-density conductive structure together, wherein a lateral peripheral surface of the intermediate layer is substantially coplanar with a lateral peripheral surface of the lower encapsulant.
22. The wiring structure of claim 21 , wherein the low-density conductive structure further includes a core portion, the at least one dielectric layer and the at least one circuit layer of the low-density conductive structure are disposed adjacent to a surface of the core portion.
23. The wiring structure of claim 21 , wherein a line space of the circuit layer of the low-density conductive structure is greater than a line space of the circuit layer of the high-density conductive structure.
24. The wiring structure of claim 21 , further comprising at least one upper through via extending through at least a portion of the high-density conductive structure, and electrically connected to the circuit layer of the low-density conductive structure.
25. A wiring structure, comprising:
an upper conductive structure including at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer;
a lower conductive structure electrically connected to the upper conductive structure, and including at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer;
an intermediate layer disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together; and
a lower encapsulant covering a lateral peripheral surface of the lower conductive structure and being in contact with a portion of the intermediate layer,
wherein a lateral peripheral surface of the intermediate layer is substantially coplanar with a lateral peripheral surface of the lower encapsulant.
26. The wiring structure of claim 25 , wherein a lateral peripheral surface of the upper conductive structure is inwardly recessed from the lateral peripheral surface of the lower encapsulant.
27. The wiring structure of claim 25 , further comprising an upper encapsulant surrounding a lateral peripheral surface of the upper conductive structure.
28. The wiring structure of claim 25 , wherein the lower conductive structure further includes a core portion, the at least one lower dielectric layer and the at least one lower circuit layer of the lower conductive structure are disposed adjacent to a surface of the core portion.
29. The wiring structure of claim 25 , wherein a line space of the lower circuit layer of the lower conductive structure is greater than a line space of the upper circuit layer of the upper conductive structure.
30. The wiring structure of claim 25 , further comprising at least one upper through via extending through at least a portion of the upper conductive structure and the intermediate layer, and electrically connected to the lower circuit layer of the lower conductive structure.
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US20220217841A1 (en) * | 2021-01-07 | 2022-07-07 | Unimicron Technology Corp. | Circuit board and manufacture method of the circuit board |
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US20130175699A1 (en) * | 2012-01-09 | 2013-07-11 | Invensas Corporation | Stackable microelectronic package structures |
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US7167373B1 (en) * | 2004-03-08 | 2007-01-23 | Virtium Technology, Inc. | Stacking multiple devices using flexible circuit |
JP4431747B2 (en) * | 2004-10-22 | 2010-03-17 | 富士通株式会社 | Manufacturing method of semiconductor device |
JP5296590B2 (en) | 2009-03-30 | 2013-09-25 | 新光電気工業株式会社 | Manufacturing method of semiconductor package |
KR101798571B1 (en) * | 2012-02-16 | 2017-11-16 | 삼성전자주식회사 | Semiconductor Packages |
JP6158676B2 (en) * | 2013-10-15 | 2017-07-05 | 新光電気工業株式会社 | WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD |
US9935026B2 (en) * | 2016-08-31 | 2018-04-03 | Qorvo Us, Inc. | Air-cavity package with dual signal-transition sides |
US10217728B2 (en) * | 2016-11-22 | 2019-02-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and semiconductor process |
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US20220217841A1 (en) * | 2021-01-07 | 2022-07-07 | Unimicron Technology Corp. | Circuit board and manufacture method of the circuit board |
US11483925B2 (en) * | 2021-01-07 | 2022-10-25 | Unimicron Technology Corp. | Circuit board and manufacture method of the circuit board |
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