US20200328973A1 - Packet coalescing - Google Patents
Packet coalescing Download PDFInfo
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- US20200328973A1 US20200328973A1 US16/870,991 US202016870991A US2020328973A1 US 20200328973 A1 US20200328973 A1 US 20200328973A1 US 202016870991 A US202016870991 A US 202016870991A US 2020328973 A1 US2020328973 A1 US 2020328973A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
- H04L69/161—Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
- H04L69/166—IP fragmentation; TCP segmentation
Definitions
- Networks enable computers and other devices to communicate.
- networks can carry data representing video, audio, e-mail, and so forth.
- data sent across a network is carried by smaller messages known as packets.
- packets By analogy, a packet is much like an envelope you drop in a mailbox.
- a packet typically includes “payload” and a “header”.
- the packet's “payload” is analogous to the letter inside the envelope.
- the packet's “header” is much like the information written on the envelope itself.
- the header can include information to help network devices handle the packet appropriately.
- TCP Transmission Control Protocol
- a number of network protocols cooperate to handle the complexity of network communication.
- a transport protocol known as Transmission Control Protocol (TCP) provides applications with simple mechanisms for establishing a flow and transferring data across a network. Behind the scenes, TCP transparently handles a variety of communication issues such as data retransmission, adapting to network traffic congestion, and so forth.
- TCP operates on packets known as segments.
- a TCP segment travels across a network within (“encapsulated” by) a larger packet such as an Internet Protocol (IP) datagram.
- IP Internet Protocol
- LAN Local Area Networks
- IP datagram is further encapsulated by an even larger packet such as an Ethernet frame.
- the payload of a TCP segment carries a portion of a stream of data sent across a network by an application.
- a receiver can restore the original stream of data by reassembling the received segments.
- ACK acknowledgment
- TCP associates a sequence number with each payload byte.
- FIGS. 1A-1C illustrate an example of packet coalescing.
- FIG. 2 is a diagram of a network interface controller.
- FIG. 3 is a diagram of a table used by a network interface controller to coalesce packets.
- FIGS. 4 and 5 are flow-charts illustrating packet coalescing.
- Desktop application examples include web-browsers, streaming media players, and network file sharing applications.
- Server applications include web servers, file servers, storage servers, e-mail servers, and database back-ends.
- the underlying protocol stack e.g., a TCP/IP stack
- processing overhead for example, due to parsing headers, identifying and updating flow state information, generating an ACK message, and so forth.
- FIGS. 1A-1C illustrate a sample implementation of a technique that coalesces multiple packets for a given flow into a single packet.
- the sample system shown in FIGS. 1A-1C includes a processor 104 and memory 102 .
- the system also includes a network interface controller (NIC) (a.k.a. network adapter) 100 that receives packets from a network. Instead of writing each received packet into memory 102 for subsequent processing, the controller 100 features logic 112 that coalesces packets.
- This logic 112 combines the TCP payloads of different packets belonging to the same flow and prepares a single TCP header and a single IP header for the combined TCP payloads.
- the combination of the IP header, TCP header, and combined TCP payloads forms a single coalesced packet.
- the protocol stack can, thus, perform receiving processing for fewer but larger packets, reducing the per packet processing penalty incurred.
- FIG. 1A depicts a packet 106 having a TCP and an IP header 106 a and a TCP payload 106 b received by the network interface controller 100 .
- the controller 100 may perform a variety of tasks including de-encapsulating the packet 106 from within a frame, verifying a frame checksum, and other link layer operations.
- a packet's flow can be identified by the controller 100 by data within the header(s).
- a TCP/IP flow can be identified by a tuple formed by a combination of the IP source and destination addresses and the source and destination port numbers in the TCP header.
- a tuple may not include all of these header fields and may include other information (e.g., a protocol identifier).
- the controller 100 stores the received packet's 106 header 106 a and payload 106 b for potential coalescing with subsequently received packets.
- the controller 100 may store the packet's 106 payload 106 b in memory 102 , for example, via one or more Direct Memory Access (DMA) operations and store the header 106 a in a controller 100 table.
- the table may also include other information used in the coalescing process.
- the location in memory 102 to write the payload data 106 b may be specified by a descriptor passed to the controller 100 by driver software operating on processor 104 .
- the descriptor may also include other fields such as a memory address of a location to store packet headers, for example, to support header splitting.
- the controller 100 receives a second packet 108 that belongs to the same flow (“1”) as the packet received in FIG. 1A .
- the controller 100 combines the two payloads 106 b, 108 b of the packets 106 , 108 together into a monolithic payload 110 b.
- Combining may involve physically storing the payload bits 106 b, 108 b contiguously.
- combining may involve associating the payloads 106 b, 108 b, for example, as nodes in a linked list. This combining of payloads may continue for additional packets received for the flow.
- the controller 100 In addition to collecting the different payloads, the controller 100 also prepares a single IP header and a single TCP header 110 a for the coalesced packet 110 that reflects the combined TCP payloads 110 b. For example, the controller 100 may lookup TCP/IP headers 106 a associated with the flow and modify the IP header's length field to reflect the length of the combined payloads. The controller 100 may also revise the TCP header's checksum. Additionally, the controller 100 may alter the TCP header's ACK sequence number to coalesce incoming ACK messages. This updating may be performed as each payload is combined. Alternately, the updating may be postponed, for example, for a period of time.
- the controller 100 may write the headers 110 a of the coalesced packet and the flow's descriptor to memory 102 .
- the controller 100 may then signal an interrupt to initiate receive processing (e.g., network and/or transport layer processing) of the coalesced packet 110 .
- receive processing e.g., network and/or transport layer processing
- TCP receive processing can include reassembly, reordering, generation of ACKs, navigating the TCP state machine for a flow, and so forth.
- the number of packets coalesced and/or the period of time to coalesce packets may be configurable.
- network interface controllers use a technique known as interrupt moderation to batch signaling of packets received in some window of time.
- the controller 100 can use the interrupt moderation window to coalesce as many packets of a flow as possible.
- the controller 100 may use a window of time (coalescing window) smaller than the interrupt moderation window to coalesce packets.
- the controller 100 obtains a descriptor for flows that receive data during the coalescing window (e.g., by dequeuing a descriptor provided by a controller 100 device driver) and, generally, retains the descriptor until either the coalescing window expires or the controller 100 receives a flow packet that does not meet coalescing criteria (described below), or the size of the payload exceeds the available space in the packet buffer identified by the descriptor.
- the controller 100 prepares headers, writes the descriptors to memory, signals an interrupt at the end of the interrupt moderation time, and clears data used to coalesce packets during the preceding window. The coalescing process then begins anew.
- the system shown in FIGS. 1A-1C does not include many conventional components of a typical platform (e.g., a chipset and/or I/O controller hub interconnecting the processor 104 , memory 102 , and NIC 100 ).
- the configuration shown in FIGS. 1A-1C may vary considerably in different systems.
- a given system may feature multiple processors (e.g., discrete processors and/or processor cores integrated within the same die), multiple NICs, and/or a variety of memory devices (e.g., single, dual, or quad port memory).
- the controller 100 may be integrated within a processor 104 , chipset (not shown), or other circuitry.
- the system may include a TCP/IP offload engine (TOE) that can perform tasks described above as being handled by the NIC 100 or processor 104 .
- TOE TCP/IP offload engine
- FIG. 2 illustrates a sample architecture of a network interface controller 200 in greater detail. Though shown as processing ingress packets from a network the controller 200 may also process egress packets to the network.
- the controller 100 can include a physical layer device (PHY) 202 that interfaces to a communications medium (e.g., a cable or wireless radio).
- PHY physical layer device
- the PHY 202 can convert between the analog signals of the communications medium and the digital bits used to process a packet.
- a media access controller (MAC) 204 collects bits output by the PHY 202 (e.g., via a FIFO queue).
- the MAC 204 can perform a variety of link-layer operations (e.g., verifying an Ethernet checksum and so forth).
- Coalesce circuitry 206 operates on packets output by the MAC 204 , for example, as illustrated in FIGS. 1A-1C .
- the coalesce circuitry 206 may be “hard-wired” circuitry such as an Application Specific Integrated Circuitry (ASIC). Alternately, the circuitry 206 may feature a programmable engine that executes instructions to process the packets. As shown, the circuitry 206 interfaces to a host system via DMA controller 210 .
- ASIC Application Specific Integrated Circuitry
- the coalesce circuitry 206 may implement coalescing in a variety of ways. For example, as shown in FIG. 3 , the circuitry 206 may build a table 212 that tracks on-going coalescing. As illustrated, such a table 212 may associate a flow ID (e.g., a TCP/IP tuple or hash of a TCP/IP tuple) with the starting byte sequence number of a packet, a number of payload bytes, an address of a packet descriptor, an address of a payload buffer, and an address of a header buffer. The table 212 may store other data (not shown) such as header fields for the flow.
- a flow ID e.g., a TCP/IP tuple or hash of a TCP/IP tuple
- the table 212 may store other data (not shown) such as header fields for the flow.
- the table 212 may store the IP source, IP destination, IP identification and version, IPv6 flow ID and priority, TCP source port, TCP destination port, TCP sequence number, TCP ACK number, TCP checksum, and/or TCP timestamp(s).
- the table 212 may also tally the number of packets being coalesced for the flow to later pass that information to the TCP/IP stack (e.g., via a field in the descriptor), the number of ACK segments coalesced, and may store an aging counter to support “descriptor aging” (described below) used to close idle descriptors before the end of a coalesce window.
- the table 212 data for a given flow is modified as coalescing progresses. For example, the number of bytes may be adjusted to reflect additional bytes of a newly combined payload. Similarly, the number of payloads coalesced may be incremented with each additional TCP payload combined.
- the table 212 data can be used to prepare a header for coalesced packets and prepare the corresponding descriptor. Again, the table 212 data may be cleared, for example, after the end of a coalescing window.
- the controller may include other components (not shown).
- the controller may include registers that enable, for example, a driver to enable or disable coalescing.
- FIG. 4 depicts a flow-chart of a process to coalesce packets. As shown, the process combines 256 the payloads of packets in the same flow and prepares 258 a single TCP segment header and a single IP header for the combined payloads. An interrupt may then be generated to initiate processing of the coalesced packet by a TCP/IP stack.
- some packets may be excluded 254 from coalescing.
- a packet may need to satisfy one or more criteria. For example, coalescing may only be performed for TCP segments having a valid checksum. Additionally, even a valid TCP segment may be excluded from coalescing with a previously received packet based on header information such as information identifying the segment as a control segment (e.g., a RST, FIN, SYN, SYN-ACK, URG flag set). In these cases, previously on-going coalescing for this flow may terminate (e.g., an IP and TCP header may be prepared and written to memory for any previously combined flow payloads and the corresponding descriptor data written).
- a TCP/IP packet may be received out-of-order (i.e., the sequence number of a received packet does not match the next sequential sequence number of the flow).
- a new coalesce packet may be started (e.g., a descriptor obtained and table entry written). That is, a given flow may have coalescing in-progress at multiple points in the flow's byte sequence. Thereafter, the payload of a flow packet may be added onto one of a variety of packets being coalesced for a given flow based on the received packets sequence number. Alternately, for simplicity, previously on-going packet coalescing for a flow may be terminated after a packet is received out of order.
- FIG. 5 illustrates a sample implementation of packet coalescing.
- a packet 300 is an IP datagram 302 (e.g., an IPv4 or IPv6 datagram) or a frame encapsulating an IP datagram
- the IP header is examined 304 for header options and/or fragmentation. If either of these conditions exist, coalescing may not occur 308 and the packet may be handled conventionally (e.g., a descriptor obtained, written back, and the packet DMA-ed into memory). Otherwise, the process attempts to validate 306 the TCP segment within the IP packet (e.g., by determining if the TCP segment header checksum is valid). If the TCP segment is not valid, again, no coalescing 308 occurs for the packet.
- IP datagram 302 e.g., an IPv4 or IPv6 datagram
- the IP header is examined 304 for header options and/or fragmentation. If either of these conditions exist, coalescing may not occur 308 and the packet may be handled conventionally (e.g.
- the process determines 310 a flow ID, for example, based on the packet's TCP/IP tuple. If the TCP segment is a data segment (e.g., IPheader.total_len-Ipheader.header_len-TCPheader.Data_Offset>0) 312 , the TCP segment header is examined 314 , 316 for options other than the timestamp option and for flags other than ACK and/or PSH. If any 312 , 314 , 316 of these conditions exist, no coalescing occurs 308 . Additionally, if coalescing had already begun for the flow, the existing coalescing is halted 332 by generating the TCP and IP headers, closing the descriptor being used to coalesce packets for the flow, and invalidating the flow's table entry.
- a flow ID for example, based on the packet's TCP/IP tuple. If the TCP segment is a data segment (e.g., IPheader.to
- the process determines 320 whether coalescing is already being performed for the flow. If not, and the TCP PSH flag is not set, the process can (table space permitting 326 ) initialize a table entry for the flow, read a descriptor, and start coalescing 330 for the flow with the current packet. If sufficient space does not exist in the table 326 for an additional entry, a previously written entry may be victimized (not shown), for example, using a Least Recently Used algorithm to select an entry to delete and closing the associated descriptor.
- coalescing 320 had already been established for this flow, the process can determine whether the TCP segment was received in-order 324 based on its sequence number. If the segment was received out-of-order 324 , on-going coalescing for the flow may be terminated 332 .
- the process can combine the payload of the received TCP segment with the payload of previously received TCP segments in the flow by copying 336 the payload data to a determined offset 328 into the payload buffer specified by the flow's descriptor and updating the entry data for the flow (e.g., updating the number of packets coalesced, next expected sequence number, number of payload bytes, and so forth). If the PSH flag for the current segment was set 338 , coalescing may be terminated 342 after these operations.
- the TCP and IP headers may be prepared and the flow descriptor closed 340 .
- the PSH flag is set 346 , the packet is handled conventionally. Otherwise, a new read descriptor is obtained for the flow and coalescing begins anew 348 with the packet.
- a wide variety of different variations of the sample process illustrated in FIG. 5 may be implemented.
- the process could close aging descriptors after some fixed amount of time without receipt of additional sequential packets even though the coalesce window may not have expired.
- earlier descriptors may be closed when a later one completes.
- FIGS. 1-5 and corresponding text described sample implementations
- a wide variety of other implementations may use one or more of the techniques described above.
- the controller instead of coalescing the packet in memory, the controller may coalesce packets in its own internal buffers before transferring to memory.
- the techniques may be used to implement other transport layer protocol, protocols in other layers within a network protocol stack, protocols other than TCP and IP, and to handle other protocol data units.
- the packets may be carried by HDLC or PPP frames.
- IP encompasses both IPv4 and IPv6 IP implementations.
- circuitry as used herein includes hardwired circuitry, digital circuitry, analog circuitry, programmable circuitry, and so forth.
- the programmable circuitry may operate on executable instructions disposed on an article of manufacture (e.g., a non-volatile memory such as a Read Only Memory).
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Abstract
Description
- The present application is a Continuation of (and claims the benefit of priority under 35 U.S.C. § 120) U.S. patent application Ser. No. 15/859,301 filed on Dec. 29, 2017, entitled PACKET COALESCING, which application is a continuation of Ser. No. 15/339,354, filed Oct. 31, 2016, which is a continuation of U.S. patent application Ser. No. 14/229,545, filed Mar. 28, 2014, now patented as U.S. Pat. No. 9,485,178, issued on Nov. 1, 2016, which is a continuation of U.S. patent application Ser. No. 12/980,682, filed Dec. 29, 2010, now U.S. Pat. No. 8,718,096, issued on May 6, 2014, which is a continuation of U.S. patent application Ser. No. 12/586,964, filed Sep. 30, 2009, now patented as U.S. Pat. No. 8,036,246, issued on Oct. 11, 2011, which is a continuation of U.S. patent application Ser. No. 10/991,239, filed Nov. 16, 2004, now patented as U.S. Pat. No. 7,620,071, issued on Nov. 17, 2009, all of which are hereby incorporated by reference in their entirety as if originally and explicitly set forth herein.
- Networks enable computers and other devices to communicate. For example, networks can carry data representing video, audio, e-mail, and so forth. Typically, data sent across a network is carried by smaller messages known as packets. By analogy, a packet is much like an envelope you drop in a mailbox. A packet typically includes “payload” and a “header”. The packet's “payload” is analogous to the letter inside the envelope. The packet's “header” is much like the information written on the envelope itself. The header can include information to help network devices handle the packet appropriately.
- A number of network protocols (e.g., “a protocol stack”) cooperate to handle the complexity of network communication. For example, a transport protocol known as Transmission Control Protocol (TCP) provides applications with simple mechanisms for establishing a flow and transferring data across a network. Behind the scenes, TCP transparently handles a variety of communication issues such as data retransmission, adapting to network traffic congestion, and so forth.
- To provide these services, TCP operates on packets known as segments. Generally, a TCP segment travels across a network within (“encapsulated” by) a larger packet such as an Internet Protocol (IP) datagram. Frequently, for example, in Local Area Networks (LAN), an IP datagram is further encapsulated by an even larger packet such as an Ethernet frame. The payload of a TCP segment carries a portion of a stream of data sent across a network by an application. A receiver can restore the original stream of data by reassembling the received segments. To permit reassembly and acknowledgment (ACK) of received data back to the sender, TCP associates a sequence number with each payload byte.
-
FIGS. 1A-1C illustrate an example of packet coalescing. -
FIG. 2 is a diagram of a network interface controller. -
FIG. 3 is a diagram of a table used by a network interface controller to coalesce packets. -
FIGS. 4 and 5 are flow-charts illustrating packet coalescing. - Many applications receive and process significant amounts of network data. Desktop application examples include web-browsers, streaming media players, and network file sharing applications. Server applications include web servers, file servers, storage servers, e-mail servers, and database back-ends. Typically, the underlying protocol stack (e.g., a TCP/IP stack) receives many packets and individually processes them, even though some or all of these packets are part of the same flow. Associated with the processing of each packet is some processing overhead, for example, due to parsing headers, identifying and updating flow state information, generating an ACK message, and so forth.
-
FIGS. 1A-1C illustrate a sample implementation of a technique that coalesces multiple packets for a given flow into a single packet. The sample system shown inFIGS. 1A-1C includes aprocessor 104 andmemory 102. The system also includes a network interface controller (NIC) (a.k.a. network adapter) 100 that receives packets from a network. Instead of writing each received packet intomemory 102 for subsequent processing, thecontroller 100 featureslogic 112 that coalesces packets. Thislogic 112 combines the TCP payloads of different packets belonging to the same flow and prepares a single TCP header and a single IP header for the combined TCP payloads. The combination of the IP header, TCP header, and combined TCP payloads forms a single coalesced packet. The protocol stack can, thus, perform receiving processing for fewer but larger packets, reducing the per packet processing penalty incurred. - To illustrate coalescing,
FIG. 1A depicts apacket 106 having a TCP and anIP header 106 a and aTCP payload 106 b received by thenetwork interface controller 100. Thecontroller 100 may perform a variety of tasks including de-encapsulating thepacket 106 from within a frame, verifying a frame checksum, and other link layer operations. - As shown, the packet belongs to a flow (arbitrarily labeled “1” in
FIG. 1A ). A packet's flow can be identified by thecontroller 100 by data within the header(s). For example, a TCP/IP flow can be identified by a tuple formed by a combination of the IP source and destination addresses and the source and destination port numbers in the TCP header. A tuple may not include all of these header fields and may include other information (e.g., a protocol identifier). - In
FIG. 1A , thecontroller 100 stores the received packet's 106header 106 a andpayload 106 b for potential coalescing with subsequently received packets. For example, as shown, thecontroller 100 may store the packet's 106payload 106 b inmemory 102, for example, via one or more Direct Memory Access (DMA) operations and store theheader 106 a in acontroller 100 table. The table may also include other information used in the coalescing process. The location inmemory 102 to write thepayload data 106 b may be specified by a descriptor passed to thecontroller 100 by driver software operating onprocessor 104. The descriptor may also include other fields such as a memory address of a location to store packet headers, for example, to support header splitting. - In
FIG. 1B , thecontroller 100 receives asecond packet 108 that belongs to the same flow (“1”) as the packet received inFIG. 1A . Instead of simply writing thepacket memory 102, thecontroller 100 combines the twopayloads packets monolithic payload 110 b. Combining may involve physically storing thepayload bits payloads - In addition to collecting the different payloads, the
controller 100 also prepares a single IP header and asingle TCP header 110 a for the coalescedpacket 110 that reflects the combinedTCP payloads 110 b. For example, thecontroller 100 may lookup TCP/IP headers 106 a associated with the flow and modify the IP header's length field to reflect the length of the combined payloads. Thecontroller 100 may also revise the TCP header's checksum. Additionally, thecontroller 100 may alter the TCP header's ACK sequence number to coalesce incoming ACK messages. This updating may be performed as each payload is combined. Alternately, the updating may be postponed, for example, for a period of time. - Eventually (e.g., after a coalescing window ends), as shown in
FIG. 1C , thecontroller 100 may write theheaders 110 a of the coalesced packet and the flow's descriptor tomemory 102. Thecontroller 100 may then signal an interrupt to initiate receive processing (e.g., network and/or transport layer processing) of the coalescedpacket 110. For example, TCP receive processing can include reassembly, reordering, generation of ACKs, navigating the TCP state machine for a flow, and so forth. - The number of packets coalesced and/or the period of time to coalesce packets may be configurable. For example, typically, network interface controllers use a technique known as interrupt moderation to batch signaling of packets received in some window of time. The
controller 100 can use the interrupt moderation window to coalesce as many packets of a flow as possible. To allow for coalescing overhead (e.g., header preparation), thecontroller 100 may use a window of time (coalescing window) smaller than the interrupt moderation window to coalesce packets. During the coalescing window, thecontroller 100 obtains a descriptor for flows that receive data during the coalescing window (e.g., by dequeuing a descriptor provided by acontroller 100 device driver) and, generally, retains the descriptor until either the coalescing window expires or thecontroller 100 receives a flow packet that does not meet coalescing criteria (described below), or the size of the payload exceeds the available space in the packet buffer identified by the descriptor. After the coalesce window expires, thecontroller 100 prepares headers, writes the descriptors to memory, signals an interrupt at the end of the interrupt moderation time, and clears data used to coalesce packets during the preceding window. The coalescing process then begins anew. - For simplicity of illustration, the system shown in
FIGS. 1A-1C does not include many conventional components of a typical platform (e.g., a chipset and/or I/O controller hub interconnecting theprocessor 104,memory 102, and NIC 100). Additionally, the configuration shown inFIGS. 1A-1C may vary considerably in different systems. For example, a given system may feature multiple processors (e.g., discrete processors and/or processor cores integrated within the same die), multiple NICs, and/or a variety of memory devices (e.g., single, dual, or quad port memory). Similarly, thecontroller 100 may be integrated within aprocessor 104, chipset (not shown), or other circuitry. Additionally, the system may include a TCP/IP offload engine (TOE) that can perform tasks described above as being handled by theNIC 100 orprocessor 104. -
FIG. 2 illustrates a sample architecture of anetwork interface controller 200 in greater detail. Though shown as processing ingress packets from a network thecontroller 200 may also process egress packets to the network. - As shown, the
controller 100 can include a physical layer device (PHY) 202 that interfaces to a communications medium (e.g., a cable or wireless radio). ThePHY 202 can convert between the analog signals of the communications medium and the digital bits used to process a packet. As shown, a media access controller (MAC) 204 collects bits output by the PHY 202 (e.g., via a FIFO queue). TheMAC 204 can perform a variety of link-layer operations (e.g., verifying an Ethernet checksum and so forth). Coalescecircuitry 206 operates on packets output by theMAC 204, for example, as illustrated inFIGS. 1A-1C . The coalescecircuitry 206 may be “hard-wired” circuitry such as an Application Specific Integrated Circuitry (ASIC). Alternately, thecircuitry 206 may feature a programmable engine that executes instructions to process the packets. As shown, thecircuitry 206 interfaces to a host system viaDMA controller 210. - The coalesce
circuitry 206 may implement coalescing in a variety of ways. For example, as shown inFIG. 3 , thecircuitry 206 may build a table 212 that tracks on-going coalescing. As illustrated, such a table 212 may associate a flow ID (e.g., a TCP/IP tuple or hash of a TCP/IP tuple) with the starting byte sequence number of a packet, a number of payload bytes, an address of a packet descriptor, an address of a payload buffer, and an address of a header buffer. The table 212 may store other data (not shown) such as header fields for the flow. For example the table 212 may store the IP source, IP destination, IP identification and version, IPv6 flow ID and priority, TCP source port, TCP destination port, TCP sequence number, TCP ACK number, TCP checksum, and/or TCP timestamp(s). The table 212 may also tally the number of packets being coalesced for the flow to later pass that information to the TCP/IP stack (e.g., via a field in the descriptor), the number of ACK segments coalesced, and may store an aging counter to support “descriptor aging” (described below) used to close idle descriptors before the end of a coalesce window. - The table 212 data for a given flow is modified as coalescing progresses. For example, the number of bytes may be adjusted to reflect additional bytes of a newly combined payload. Similarly, the number of payloads coalesced may be incremented with each additional TCP payload combined. The table 212 data can be used to prepare a header for coalesced packets and prepare the corresponding descriptor. Again, the table 212 data may be cleared, for example, after the end of a coalescing window.
- The controller may include other components (not shown). For example, the controller may include registers that enable, for example, a driver to enable or disable coalescing.
-
FIG. 4 depicts a flow-chart of a process to coalesce packets. As shown, the process combines 256 the payloads of packets in the same flow and prepares 258 a single TCP segment header and a single IP header for the combined payloads. An interrupt may then be generated to initiate processing of the coalesced packet by a TCP/IP stack. - As shown, some packets may be excluded 254 from coalescing. For example, a packet may need to satisfy one or more criteria. For example, coalescing may only be performed for TCP segments having a valid checksum. Additionally, even a valid TCP segment may be excluded from coalescing with a previously received packet based on header information such as information identifying the segment as a control segment (e.g., a RST, FIN, SYN, SYN-ACK, URG flag set). In these cases, previously on-going coalescing for this flow may terminate (e.g., an IP and TCP header may be prepared and written to memory for any previously combined flow payloads and the corresponding descriptor data written).
- Potentially, a TCP/IP packet may be received out-of-order (i.e., the sequence number of a received packet does not match the next sequential sequence number of the flow). In this case, a new coalesce packet may be started (e.g., a descriptor obtained and table entry written). That is, a given flow may have coalescing in-progress at multiple points in the flow's byte sequence. Thereafter, the payload of a flow packet may be added onto one of a variety of packets being coalesced for a given flow based on the received packets sequence number. Alternately, for simplicity, previously on-going packet coalescing for a flow may be terminated after a packet is received out of order.
- Other scenarios can affect packet coalescing. For example, if a packet's TCP header indicates the “PUSH” flag is set, coalescing for this flow may complete after coalescing of the received packet and subsequent packets for this flow will be coalesced using a new descriptor. Similarly, if coalescing of an incoming packet's payload exceeds available space in the allocated buffer, the controller can terminate (e.g., generate a single TCP and a single IP header and write the corresponding descriptor) currently on-going coalescing and restart coalescing for the flow anew (e.g., write a new table entry and obtain a new descriptor).
-
FIG. 5 illustrates a sample implementation of packet coalescing. In the implementation shown, if apacket 300 is an IP datagram 302 (e.g., an IPv4 or IPv6 datagram) or a frame encapsulating an IP datagram, the IP header is examined 304 for header options and/or fragmentation. If either of these conditions exist, coalescing may not occur 308 and the packet may be handled conventionally (e.g., a descriptor obtained, written back, and the packet DMA-ed into memory). Otherwise, the process attempts to validate 306 the TCP segment within the IP packet (e.g., by determining if the TCP segment header checksum is valid). If the TCP segment is not valid, again, no coalescing 308 occurs for the packet. - For valid TCP segments, the process determines 310 a flow ID, for example, based on the packet's TCP/IP tuple. If the TCP segment is a data segment (e.g., IPheader.total_len-Ipheader.header_len-TCPheader.Data_Offset>0) 312, the TCP segment header is examined 314, 316 for options other than the timestamp option and for flags other than ACK and/or PSH. If any 312, 314, 316 of these conditions exist, no coalescing occurs 308. Additionally, if coalescing had already begun for the flow, the existing coalescing is halted 332 by generating the TCP and IP headers, closing the descriptor being used to coalesce packets for the flow, and invalidating the flow's table entry.
- Assuming
conditions - If coalescing 320 had already been established for this flow, the process can determine whether the TCP segment was received in-
order 324 based on its sequence number. If the segment was received out-of-order 324, on-going coalescing for the flow may be terminated 332. If the segment was retrieved in-order 324 and the payload buffer hassufficient room 334 for the additional TCP payload, the process can combine the payload of the received TCP segment with the payload of previously received TCP segments in the flow by copying 336 the payload data to a determined offset 328 into the payload buffer specified by the flow's descriptor and updating the entry data for the flow (e.g., updating the number of packets coalesced, next expected sequence number, number of payload bytes, and so forth). If the PSH flag for the current segment was set 338, coalescing may be terminated 342 after these operations. - If the buffer to store payloads did not have
sufficient room 334 to add the TCP payload of the current packet, the TCP and IP headers may be prepared and the flow descriptor closed 340. In this case, if the PSH flag is set 346, the packet is handled conventionally. Otherwise, a new read descriptor is obtained for the flow and coalescing begins anew 348 with the packet. - After handling the packet, if a coalesce window has expired, packet descriptors and headers are prepared and written to memory and the table contents flushed. Otherwise, the process illustrated in
FIG. 5 repeats for another packet. - A wide variety of different variations of the sample process illustrated in
FIG. 5 may be implemented. For example, in order to prevent an unfinished descriptor from holding up later descriptors (e.g., if a NIC driver reads descriptors sequentially), the process could close aging descriptors after some fixed amount of time without receipt of additional sequential packets even though the coalesce window may not have expired. Alternately, earlier descriptors may be closed when a later one completes. - While
FIGS. 1-5 and corresponding text described sample implementations, a wide variety of other implementations may use one or more of the techniques described above. For example, instead of coalescing the packet in memory, the controller may coalesce packets in its own internal buffers before transferring to memory. Additionally, the techniques may be used to implement other transport layer protocol, protocols in other layers within a network protocol stack, protocols other than TCP and IP, and to handle other protocol data units. For example, instead of Ethernet frames, the packets may be carried by HDLC or PPP frames. Additionally, the term IP encompasses both IPv4 and IPv6 IP implementations. - The term circuitry as used herein includes hardwired circuitry, digital circuitry, analog circuitry, programmable circuitry, and so forth. The programmable circuitry may operate on executable instructions disposed on an article of manufacture (e.g., a non-volatile memory such as a Read Only Memory).
- Other embodiments are within the scope of the following claims.
Claims (24)
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11979479B1 (en) | 2022-10-21 | 2024-05-07 | Chung Yuan Christian University | Packet sorting and reassembly circuit module |
Families Citing this family (110)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6957281B2 (en) | 2002-01-15 | 2005-10-18 | Intel Corporation | Ingress processing optimization via traffic classification and grouping |
US7620071B2 (en) | 2004-11-16 | 2009-11-17 | Intel Corporation | Packet coalescing |
US7404040B2 (en) * | 2004-12-30 | 2008-07-22 | Intel Corporation | Packet data placement in a processor cache |
US8457131B2 (en) * | 2005-02-18 | 2013-06-04 | Broadcom Corporation | Dynamic table sharing of memory space within a network device |
US20070022212A1 (en) * | 2005-07-22 | 2007-01-25 | Fan Kan F | Method and system for TCP large receive offload |
US8311059B2 (en) * | 2005-09-07 | 2012-11-13 | Emulex Design & Manufacturing Corporation | Receive coalescing and automatic acknowledge in network interface controller |
US20070219663A1 (en) * | 2006-01-03 | 2007-09-20 | Eddy Verstraeten | Tracking an Item on a Packaging Line |
US7570175B2 (en) * | 2006-02-16 | 2009-08-04 | Intelliserv International Holding, Ltd. | Node discovery in physically segmented logical token network |
US8102842B2 (en) | 2006-08-04 | 2012-01-24 | Broadcom Corporation | Integrated switch |
US7987307B2 (en) * | 2006-09-22 | 2011-07-26 | Intel Corporation | Interrupt coalescing control scheme |
US8165133B2 (en) * | 2006-12-22 | 2012-04-24 | Broadcom Corporation | Physical layer device with integrated switch |
US7840703B2 (en) * | 2007-08-27 | 2010-11-23 | International Business Machines Corporation | System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture |
US8140731B2 (en) | 2007-08-27 | 2012-03-20 | International Business Machines Corporation | System for data processing using a multi-tiered full-graph interconnect architecture |
US8185896B2 (en) * | 2007-08-27 | 2012-05-22 | International Business Machines Corporation | Method for data processing using a multi-tiered full-graph interconnect architecture |
US8014387B2 (en) * | 2007-08-27 | 2011-09-06 | International Business Machines Corporation | Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture |
US7769892B2 (en) | 2007-08-27 | 2010-08-03 | International Business Machines Corporation | System and method for handling indirect routing of information between supernodes of a multi-tiered full-graph interconnect architecture |
US7769891B2 (en) * | 2007-08-27 | 2010-08-03 | International Business Machines Corporation | System and method for providing multiple redundant direct routes between supernodes of a multi-tiered full-graph interconnect architecture |
US7958182B2 (en) | 2007-08-27 | 2011-06-07 | International Business Machines Corporation | Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture |
US7904590B2 (en) | 2007-08-27 | 2011-03-08 | International Business Machines Corporation | Routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture |
US7822889B2 (en) * | 2007-08-27 | 2010-10-26 | International Business Machines Corporation | Direct/indirect transmission of information using a multi-tiered full-graph interconnect architecture |
US8108545B2 (en) | 2007-08-27 | 2012-01-31 | International Business Machines Corporation | Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture |
US7958183B2 (en) | 2007-08-27 | 2011-06-07 | International Business Machines Corporation | Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture |
US7793158B2 (en) * | 2007-08-27 | 2010-09-07 | International Business Machines Corporation | Providing reliability of communication between supernodes of a multi-tiered full-graph interconnect architecture |
US7809970B2 (en) | 2007-08-27 | 2010-10-05 | International Business Machines Corporation | System and method for providing a high-speed message passing interface for barrier operations in a multi-tiered full-graph interconnect architecture |
US8427951B2 (en) * | 2007-08-30 | 2013-04-23 | International Business Machines Corporation | Method, system, and apparatus for reliable data packet recovery in a link layer of a data center ethernet network |
US7827428B2 (en) | 2007-08-31 | 2010-11-02 | International Business Machines Corporation | System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture |
US7921316B2 (en) | 2007-09-11 | 2011-04-05 | International Business Machines Corporation | Cluster-wide system clock in a multi-tiered full-graph interconnect architecture |
US7738471B2 (en) | 2007-09-14 | 2010-06-15 | Harris Corporation | High speed packet processing in a wireless network |
US8661167B2 (en) * | 2007-09-17 | 2014-02-25 | Intel Corporation | DMA (direct memory access) coalescing |
US20090086736A1 (en) * | 2007-09-28 | 2009-04-02 | Annie Foong | Notification of out of order packets |
US8001278B2 (en) * | 2007-09-28 | 2011-08-16 | Intel Corporation | Network packet payload compression |
US7916728B1 (en) | 2007-09-28 | 2011-03-29 | F5 Networks, Inc. | Lockless atomic table update |
US7779148B2 (en) | 2008-02-01 | 2010-08-17 | International Business Machines Corporation | Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips |
US20090198956A1 (en) * | 2008-02-01 | 2009-08-06 | Arimilli Lakshminarayana B | System and Method for Data Processing Using a Low-Cost Two-Tier Full-Graph Interconnect Architecture |
US8077602B2 (en) * | 2008-02-01 | 2011-12-13 | International Business Machines Corporation | Performing dynamic request routing based on broadcast queue depths |
CN101500341B (en) * | 2008-02-02 | 2011-02-02 | 上海贝尔阿尔卡特股份有限公司 | Gateway and base station for content synchronization based on window and method thereof |
US8306036B1 (en) | 2008-06-20 | 2012-11-06 | F5 Networks, Inc. | Methods and systems for hierarchical resource allocation through bookmark allocation |
US8341286B1 (en) * | 2008-07-31 | 2012-12-25 | Alacritech, Inc. | TCP offload send optimization |
US8769681B1 (en) | 2008-08-11 | 2014-07-01 | F5 Networks, Inc. | Methods and system for DMA based distributed denial of service protection |
US8160060B2 (en) * | 2008-11-10 | 2012-04-17 | Infosys Technologies Limited | System and method for transferring data using variance based messaging |
US8447884B1 (en) | 2008-12-01 | 2013-05-21 | F5 Networks, Inc. | Methods for mapping virtual addresses to physical addresses in a network device and systems thereof |
US8495403B2 (en) * | 2008-12-31 | 2013-07-23 | Intel Corporation | Platform and processor power management |
US9152483B2 (en) | 2009-01-16 | 2015-10-06 | F5 Networks, Inc. | Network devices with multiple fully isolated and independently resettable direct memory access channels and methods thereof |
US8112491B1 (en) | 2009-01-16 | 2012-02-07 | F5 Networks, Inc. | Methods and systems for providing direct DMA |
US8103809B1 (en) | 2009-01-16 | 2012-01-24 | F5 Networks, Inc. | Network devices with multiple direct memory access channels and methods thereof |
US8880696B1 (en) | 2009-01-16 | 2014-11-04 | F5 Networks, Inc. | Methods for sharing bandwidth across a packetized bus and systems thereof |
US8880632B1 (en) | 2009-01-16 | 2014-11-04 | F5 Networks, Inc. | Method and apparatus for performing multiple DMA channel based network quality of service |
US8693688B2 (en) * | 2009-03-03 | 2014-04-08 | Intel Corporation | Adaptive packet ciphering |
US9313047B2 (en) | 2009-11-06 | 2016-04-12 | F5 Networks, Inc. | Handling high throughput and low latency network data packets in a traffic management device |
US8417778B2 (en) | 2009-12-17 | 2013-04-09 | International Business Machines Corporation | Collective acceleration unit tree flow control and retransmit |
US8949210B2 (en) | 2010-05-13 | 2015-02-03 | Microsoft Corporation | Analysis stack for complex event flows |
US8537815B2 (en) * | 2010-06-17 | 2013-09-17 | Apple Inc. | Accelerating data routing |
US10135831B2 (en) | 2011-01-28 | 2018-11-20 | F5 Networks, Inc. | System and method for combining an access control system with a traffic management system |
US8996718B2 (en) * | 2012-02-02 | 2015-03-31 | Apple Inc. | TCP-aware receive side coalescing |
US9036822B1 (en) | 2012-02-15 | 2015-05-19 | F5 Networks, Inc. | Methods for managing user information and devices thereof |
US8863307B2 (en) | 2012-06-05 | 2014-10-14 | Broadcom Corporation | Authenticating users based upon an identity footprint |
US8848741B2 (en) | 2012-06-21 | 2014-09-30 | Breakingpoint Systems, Inc. | High-speed CLD-based TCP segmentation offload |
US8824508B2 (en) * | 2012-06-21 | 2014-09-02 | Breakingpoint Systems, Inc. | High-speed CLD-based TCP assembly offload |
US9130879B2 (en) * | 2012-08-24 | 2015-09-08 | Vmware, Inc. | Methods and systems for offload processing of encapsulated packets |
US9351196B2 (en) * | 2012-08-31 | 2016-05-24 | International Business Machines Corporation | Byte caching in wireless communication networks |
JP6024318B2 (en) * | 2012-09-10 | 2016-11-16 | 富士通株式会社 | Wireless LAN base station, wireless LAN terminal, and packet transfer method |
US10033837B1 (en) | 2012-09-29 | 2018-07-24 | F5 Networks, Inc. | System and method for utilizing a data reducing module for dictionary compression of encoded data |
US9723045B2 (en) | 2012-10-18 | 2017-08-01 | Hewlett Packard Enterprise Development Lp | Communicating tuples in a message |
JP2014090241A (en) * | 2012-10-29 | 2014-05-15 | Fujitsu Ltd | Tunnel communication system |
US9047417B2 (en) | 2012-10-29 | 2015-06-02 | Intel Corporation | NUMA aware network interface |
US9270602B1 (en) | 2012-12-31 | 2016-02-23 | F5 Networks, Inc. | Transmit rate pacing of large network traffic bursts to reduce jitter, buffer overrun, wasted bandwidth, and retransmissions |
US10375155B1 (en) | 2013-02-19 | 2019-08-06 | F5 Networks, Inc. | System and method for achieving hardware acceleration for asymmetric flow connections |
US9300578B2 (en) * | 2013-02-21 | 2016-03-29 | Applied Micro Circuits Corporation | Large receive offload functionality for a system on chip |
CN103297430B (en) * | 2013-05-24 | 2017-04-26 | 华为技术有限公司 | Data transmission equipment and data transmission method |
US10684973B2 (en) | 2013-08-30 | 2020-06-16 | Intel Corporation | NUMA node peripheral switch |
US9864606B2 (en) | 2013-09-05 | 2018-01-09 | F5 Networks, Inc. | Methods for configurable hardware logic device reloading and devices thereof |
WO2015095000A1 (en) | 2013-12-16 | 2015-06-25 | F5 Networks, Inc. | Methods for facilitating improved user authentication using persistent data and devices thereof |
US10015143B1 (en) | 2014-06-05 | 2018-07-03 | F5 Networks, Inc. | Methods for securing one or more license entitlement grants and devices thereof |
US11838851B1 (en) | 2014-07-15 | 2023-12-05 | F5, Inc. | Methods for managing L7 traffic classification and devices thereof |
US10182013B1 (en) | 2014-12-01 | 2019-01-15 | F5 Networks, Inc. | Methods for managing progressive image delivery and devices thereof |
US11895138B1 (en) | 2015-02-02 | 2024-02-06 | F5, Inc. | Methods for improving web scanner accuracy and devices thereof |
JP2017046325A (en) * | 2015-08-28 | 2017-03-02 | 株式会社東芝 | Communication device, communication method, and program |
US9876613B2 (en) | 2015-08-28 | 2018-01-23 | Qualcomm Incorporated | Transport protocol communications reduction |
US9749266B2 (en) | 2015-08-28 | 2017-08-29 | International Business Machines Corporation | Coalescing messages using a network interface controller |
TWI580199B (en) | 2015-12-18 | 2017-04-21 | 瑞昱半導體股份有限公司 | Receiving apparatus and packet processing method thereof |
US10521283B2 (en) * | 2016-03-07 | 2019-12-31 | Mellanox Technologies, Ltd. | In-node aggregation and disaggregation of MPI alltoall and alltoallv collectives |
US10212623B2 (en) * | 2016-12-28 | 2019-02-19 | Intel IP Corporation | Apparatus, system and method of packet coalescing |
US10972453B1 (en) | 2017-05-03 | 2021-04-06 | F5 Networks, Inc. | Methods for token refreshment based on single sign-on (SSO) for federated identity environments and devices thereof |
US10645200B2 (en) * | 2017-08-16 | 2020-05-05 | Qualcomm Incorporated | Alternate acknowledgment (ACK) signals in a coalescing transmission control protocol/internet protocol (TCP/IP) system |
US20190124180A1 (en) * | 2017-10-20 | 2019-04-25 | Hewlett Packard Enterprise Development Lp | Packet compression and decompression |
US11855898B1 (en) | 2018-03-14 | 2023-12-26 | F5, Inc. | Methods for traffic dependent direct memory access optimization and devices thereof |
JP7102936B2 (en) * | 2018-05-23 | 2022-07-20 | 日本電信電話株式会社 | Packet processing device and packet processing method |
US11277455B2 (en) | 2018-06-07 | 2022-03-15 | Mellanox Technologies, Ltd. | Streaming system |
KR102619952B1 (en) * | 2018-08-08 | 2024-01-02 | 삼성전자주식회사 | Apparatus and method for processing data packets |
CN110958213B (en) | 2018-09-27 | 2021-10-22 | 华为技术有限公司 | Method for processing TCP message, TOE component and network equipment |
KR102608382B1 (en) * | 2018-10-18 | 2023-12-01 | 삼성전자주식회사 | A method and an electronic device processing data |
US11537716B1 (en) | 2018-11-13 | 2022-12-27 | F5, Inc. | Methods for detecting changes to a firmware and devices thereof |
US10757166B2 (en) * | 2018-11-20 | 2020-08-25 | International Business Machines Corporation | Passive re-assembly of HTTP2 fragmented segments |
US11625393B2 (en) | 2019-02-19 | 2023-04-11 | Mellanox Technologies, Ltd. | High performance computing system |
EP3699770A1 (en) | 2019-02-25 | 2020-08-26 | Mellanox Technologies TLV Ltd. | Collective communication system and methods |
US11805081B2 (en) | 2019-03-04 | 2023-10-31 | Intel Corporation | Apparatus and method for buffer management for receive segment coalescing |
JP7143808B2 (en) * | 2019-04-23 | 2022-09-29 | 日本電信電話株式会社 | Packet processing device and packet processing method |
CN113874848A (en) | 2019-05-23 | 2021-12-31 | 慧与发展有限责任合伙企业 | System and method for facilitating management of operations on accelerators in a Network Interface Controller (NIC) |
US11528641B2 (en) * | 2019-07-26 | 2022-12-13 | Qualcomm Incorporated | Transmission control protocol (TCP) and/or user datagram protocol (UDP) receive offloading |
US11750699B2 (en) | 2020-01-15 | 2023-09-05 | Mellanox Technologies, Ltd. | Small message aggregation |
US11252027B2 (en) | 2020-01-23 | 2022-02-15 | Mellanox Technologies, Ltd. | Network element supporting flexible data reduction operations |
EP4131880A4 (en) * | 2020-04-17 | 2023-03-15 | Huawei Technologies Co., Ltd. | Stateful service processing method and apparatus |
KR20210137702A (en) * | 2020-05-11 | 2021-11-18 | 삼성전자주식회사 | Electronic device and method for processing a data packet received in the electronic device |
US11876885B2 (en) | 2020-07-02 | 2024-01-16 | Mellanox Technologies, Ltd. | Clock queue with arming and/or self-arming features |
US11922207B2 (en) * | 2020-08-13 | 2024-03-05 | Advanced Micro Devices, Inc | Network command coalescing on GPUs |
CN116472741A (en) * | 2020-10-06 | 2023-07-21 | 联发科技(新加坡)私人有限公司 | Reducing protocol data unit rate in mobile communications |
US11556378B2 (en) | 2020-12-14 | 2023-01-17 | Mellanox Technologies, Ltd. | Offloading execution of a multi-task parameter-dependent operation to a network device |
US20230102614A1 (en) * | 2021-09-27 | 2023-03-30 | Qualcomm Incorporated | Grouping data packets at a modem |
US11909851B2 (en) * | 2021-10-04 | 2024-02-20 | Nxp B.V. | Coalescing interrupts based on fragment information in packets and a network controller for coalescing |
US11922237B1 (en) | 2022-09-12 | 2024-03-05 | Mellanox Technologies, Ltd. | Single-step collective operations |
Family Cites Families (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3749845A (en) | 1971-08-27 | 1973-07-31 | Bell Telephone Labor Inc | Digital data communication system |
EP0763915B1 (en) | 1995-09-18 | 2006-03-08 | Kabushiki Kaisha Toshiba | Packet transfer device and method adaptive to a large number of input ports |
US6021263A (en) | 1996-02-16 | 2000-02-01 | Lucent Technologies, Inc. | Management of ATM virtual circuits with resources reservation protocol |
US6185209B1 (en) * | 1997-07-11 | 2001-02-06 | Telefonaktiebolaget Lm Ericsson | VC merging for ATM switch |
US6434620B1 (en) | 1998-08-27 | 2002-08-13 | Alacritech, Inc. | TCP/IP offload network interface device |
US5937169A (en) * | 1997-10-29 | 1999-08-10 | 3Com Corporation | Offload of TCP segmentation to a smart adapter |
US6351474B1 (en) | 1998-01-14 | 2002-02-26 | Skystream Networks Inc. | Network distributed remultiplexer for video program bearing transport streams |
US6246683B1 (en) | 1998-05-01 | 2001-06-12 | 3Com Corporation | Receive processing with network protocol bypass |
US6389468B1 (en) * | 1999-03-01 | 2002-05-14 | Sun Microsystems, Inc. | Method and apparatus for distributing network traffic processing on a multiprocessor computer |
US6453360B1 (en) | 1999-03-01 | 2002-09-17 | Sun Microsystems, Inc. | High performance network interface |
US6804237B1 (en) * | 1999-06-23 | 2004-10-12 | Nortel Networks Limited | Method, devices and signals for multiplexing payload data for transport in a data network |
US6427169B1 (en) * | 1999-07-30 | 2002-07-30 | Intel Corporation | Parsing a packet header |
US6633576B1 (en) | 1999-11-04 | 2003-10-14 | William Melaragni | Apparatus and method for interleaved packet storage |
US6564267B1 (en) * | 1999-11-22 | 2003-05-13 | Intel Corporation | Network adapter with large frame transfer emulation |
US7050437B2 (en) * | 2000-03-24 | 2006-05-23 | International Business Machines Corporation | Wire speed reassembly of data frames |
US7136377B1 (en) * | 2000-03-31 | 2006-11-14 | Cisco Technology, Inc. | Tunneled datagram switching |
US6574195B2 (en) | 2000-04-19 | 2003-06-03 | Caspian Networks, Inc. | Micro-flow management |
US6715005B1 (en) * | 2000-06-29 | 2004-03-30 | International Business Machines Corporation | Method and system for reducing latency in message passing systems |
US6718326B2 (en) | 2000-08-17 | 2004-04-06 | Nippon Telegraph And Telephone Corporation | Packet classification search device and method |
US6708292B1 (en) | 2000-08-18 | 2004-03-16 | Network Associates, Inc. | System, method and software for protocol analyzer remote buffer management |
AU2001296248A1 (en) * | 2000-09-12 | 2002-03-26 | Innovative Communications Technologies, Inc. | Bit synchronizer and internetworking system and method |
US6665495B1 (en) | 2000-10-27 | 2003-12-16 | Yotta Networks, Inc. | Non-blocking, scalable optical router architecture and method for routing optical traffic |
US6618793B2 (en) | 2000-12-18 | 2003-09-09 | Redback Networks, Inc. | Free memory manager scheme and cache |
US6665755B2 (en) | 2000-12-22 | 2003-12-16 | Nortel Networks Limited | External memory engine selectable pipeline architecture |
US7079501B2 (en) * | 2001-01-31 | 2006-07-18 | International Business Machines Corporation | Method and system for efficiently delivering content to multiple requesters |
KR100902513B1 (en) | 2001-04-13 | 2009-06-15 | 프리스케일 세미컨덕터, 인크. | Manipulating data streams in data stream processors |
US6816455B2 (en) | 2001-05-09 | 2004-11-09 | Telecom Italia S.P.A. | Dynamic packet filter utilizing session tracking |
US7164680B2 (en) | 2001-06-04 | 2007-01-16 | Koninklijke Philips Electronics N.V. | Scheme for supporting real-time packetization and retransmission in rate-based streaming applications |
US7076560B1 (en) * | 2001-06-12 | 2006-07-11 | Network Appliance, Inc. | Methods and apparatus for storing and serving streaming media data |
US7170893B2 (en) * | 2001-06-15 | 2007-01-30 | Lucent Technologies Inc. | Technique for selecting the number of packets to be concatenated |
US7590143B2 (en) * | 2001-07-05 | 2009-09-15 | Qualcomm Incorporated | System and method for voice over IP |
US7194550B1 (en) * | 2001-08-30 | 2007-03-20 | Sanera Systems, Inc. | Providing a single hop communication path between a storage device and a network switch |
US20030108044A1 (en) * | 2001-12-11 | 2003-06-12 | Roland Hendel | Stateless TCP/IP protocol |
US6801940B1 (en) | 2002-01-10 | 2004-10-05 | Networks Associates Technology, Inc. | Application performance monitoring expert |
US6957281B2 (en) | 2002-01-15 | 2005-10-18 | Intel Corporation | Ingress processing optimization via traffic classification and grouping |
JP2003258911A (en) * | 2002-03-06 | 2003-09-12 | Hitachi Ltd | Access node device and analyzing method for internet utilization state |
US7080308B2 (en) * | 2002-03-22 | 2006-07-18 | Intel Corporation | Method and apparatus to perform error control |
US7496689B2 (en) | 2002-04-22 | 2009-02-24 | Alacritech, Inc. | TCP/IP offload device |
US7512128B2 (en) * | 2002-06-12 | 2009-03-31 | Sun Microsystems, Inc. | System and method for a multi-packet data link layer data transmission |
US20030231657A1 (en) * | 2002-06-12 | 2003-12-18 | Kacheong Poon | System and method for a multi-data network layer transmit interface |
US7277963B2 (en) * | 2002-06-26 | 2007-10-02 | Sandvine Incorporated | TCP proxy providing application layer modifications |
US7142540B2 (en) * | 2002-07-18 | 2006-11-28 | Sun Microsystems, Inc. | Method and apparatus for zero-copy receive buffer management |
US6968358B2 (en) * | 2002-07-25 | 2005-11-22 | International Business Machines Corporation | Method and apparatus for network communication card memory management |
US20040047367A1 (en) * | 2002-09-05 | 2004-03-11 | Litchfield Communications, Inc. | Method and system for optimizing the size of a variable buffer |
CN100393012C (en) * | 2002-09-09 | 2008-06-04 | 西南交通大学 | Method for parallelly-redundantly transmitting and parallelly-merging and receiving block data in mixed automatic retransmission request system |
US20040088262A1 (en) * | 2002-11-06 | 2004-05-06 | Alacritech, Inc. | Enabling an enhanced function of an electronic device |
US7308000B2 (en) * | 2002-11-07 | 2007-12-11 | Sun Microsystems, Inc. | Methods and systems for efficient multi-packet data processing in a layered network protocol |
US7680944B1 (en) * | 2003-02-28 | 2010-03-16 | Comtrol Corporation | Rapid transport service in a network to peripheral device servers |
US7483532B2 (en) * | 2003-07-03 | 2009-01-27 | Microsoft Corporation | RTP payload format |
US7586925B2 (en) | 2003-09-09 | 2009-09-08 | Sonus Networks, Inc. | Data adaptation protocol |
US7562158B2 (en) * | 2004-03-24 | 2009-07-14 | Intel Corporation | Message context based TCP transmission |
US8155117B2 (en) * | 2004-06-29 | 2012-04-10 | Qualcomm Incorporated | Filtering and routing of fragmented datagrams in a data network |
US20060004933A1 (en) * | 2004-06-30 | 2006-01-05 | Sujoy Sen | Network interface controller signaling of connection event |
US20060031474A1 (en) * | 2004-07-19 | 2006-02-09 | Linden Cornett | Maintaining reachability measures |
US7620071B2 (en) | 2004-11-16 | 2009-11-17 | Intel Corporation | Packet coalescing |
US8311059B2 (en) * | 2005-09-07 | 2012-11-13 | Emulex Design & Manufacturing Corporation | Receive coalescing and automatic acknowledge in network interface controller |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11979479B1 (en) | 2022-10-21 | 2024-05-07 | Chung Yuan Christian University | Packet sorting and reassembly circuit module |
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CN102427446B (en) | 2015-01-14 |
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CN102427446A (en) | 2012-04-25 |
EP1813084A1 (en) | 2007-08-01 |
US9485178B2 (en) | 2016-11-01 |
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