US20200328757A1 - Delta sigma modulator for and method of generating a digital output voltage - Google Patents
Delta sigma modulator for and method of generating a digital output voltage Download PDFInfo
- Publication number
- US20200328757A1 US20200328757A1 US16/305,142 US201716305142A US2020328757A1 US 20200328757 A1 US20200328757 A1 US 20200328757A1 US 201716305142 A US201716305142 A US 201716305142A US 2020328757 A1 US2020328757 A1 US 2020328757A1
- Authority
- US
- United States
- Prior art keywords
- input
- voltage
- capacitance
- amplifier
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2605—Measuring capacitance
Definitions
- Various aspects of this disclosure relate to delta sigma modulators for generating digital output voltages.
- Various aspects of this disclosure relate to methods of generating digital output voltages.
- Capacitive sensors are based on the modulation of electrical capacitance by a physical or chemical parameter of interest. This principle is widely used, for instance in pressure sensors, liquid level gauges, accelerometers, and humidity sensors. Since capacitive sensors do not consume static power, they are very suitable for use in low-power and energy-constrained applications, such as battery-powered systems and wireless sensor networks. However, in such applications, the energy consumption of the capacitive sensor would be dominated by the interface circuit that converts capacitance values to the digital domain. Hence, for such applications, an energy-efficient capacitive-sensor interface is crucial. Recently, there has been lot of focus on ultra-low power energy efficient capacitive sensing based on novel techniques. However, the resolution of most of the designs is limited by the architecture. Period modulation is one technique used to achieve higher resolution. However, the need for a high-resolution time reference decreases the overall power efficiency of the system.
- Delta sigma ( ⁇ ) modulation is a popular technique when high resolution is desired.
- CDC capacitance-to-digital convertors
- Some CDCs may use discrete-time ⁇ modulators (DT- ⁇ M).
- DT- ⁇ M discrete-time ⁇ modulators
- KTC noise thermal noise
- SNR signal-to-noise ratio
- these modulators employ sensing capacitors as the sampling capacitors. Hence, there are charging and discharging of large off-chip and parasitic capacitors at the same rate as the sampling frequency, which consumes additional energy.
- the delta sigma modulator may be for generating a digital output voltage.
- the delta sigma modulator may include a capacitance-to-voltage converter for converting a sensed continuous-in-time applied capacitance signal to a delta analog output voltage signal.
- the converter may include an amplifier having a first input, a second input, and an output.
- the converter may further include a feedback capacitor with a first end coupled to the first input of the amplifier, and a second end coupled to the output.
- the converter may also include a sensor element with a first end coupled to the first input of the amplifier, and a second end for coupling to a first reference voltage, the sensor element for sensing an external input to generate the continuous-in-time applied capacitance signal.
- the converter may further include a reference capacitor with a first end coupled to the first input of the amplifier, and a second end for coupling to a second reference voltage.
- the reference capacitor may have a reference capacitance.
- the converter may additionally include a switch capacitor arrangement with a first end coupled to the first input of the amplifier, and a second end. The switch capacitor arrangement may be configured to have a charge capacitance based on an analog charging voltage.
- the converter may also include a switching mechanism configured to switch the second end of the switch capacitor arrangement, between the second end of the sensor element so that the switch capacitor arrangement is in parallel connection with the sensor element, and the second end of the reference capacitor so that the switch capacitor arrangement is in parallel connection with the reference capacitor.
- the switching may be based on the charge capacitance relative to the applied capacitance signal and the reference capacitance.
- the switching may adjust a first voltage signal at the first input of the amplifier relative to a second voltage signal at the second input of the amplifier, thereby adjusting the delta analog output voltage signal generated at the output.
- the modulator may further include an integrator circuit arrangement configured to generate an analog output voltage signal based on the delta analog output voltage signal.
- the modulator may also include a quantizer circuit arrangement configured to generate the digital output signal based on the analog output voltage signal.
- the modulator may further include a voltage digital-to-analog converter configured to generate the analog charging voltage based on the digital output signal, thereby generating the delta analog output voltage signal based on the digital output signal.
- Various embodiments may provide a method of generating a digital output voltage or a method of operating a delta sigma modulator.
- the method may include converting a sensed continuous-in-time applied capacitance signal to a delta analog output voltage signal using a capacitance-to-voltage converter.
- the converter may include an amplifier having a first input, a second input, and an output.
- the converter may also include a feedback capacitor with a first end coupled to the first input of the amplifier, and a second end coupled to the output.
- the converter may further include a sensor element with a first end coupled to the first input of the amplifier, and a second end for coupling to a first reference voltage, the sensor element for sensing an external input to generate the continuous-in-time applied capacitance signal.
- the converter may additionally include a reference capacitor with a first end coupled to the first input of the amplifier, and a second end for coupling to a second reference voltage, the reference capacitor having a reference capacitance.
- the converter may also include a switch capacitor arrangement with a first end coupled to the first input of the amplifier, and a second end, the switch capacitor arrangement configured to have a charge capacitance based on an analog charging voltage.
- the converter may further include a switching mechanism configured to switch the second end of the switch capacitor arrangement, between the second end of the sensor element so that the switch capacitor arrangement is in parallel connection with the sensor element, and the second end of the reference capacitor so that the switch capacitor arrangement is in parallel connection with the reference capacitor.
- the switching may be based on the charge capacitance relative to the applied capacitance and the reference capacitance.
- the switching may adjust a first voltage signal at the first input of the amplifier relative to a second voltage signal at the second input of the amplifier, thereby adjusting the delta analog output voltage signal generated at the output.
- the method may also include generating an analog output voltage signal based on the delta analog output voltage signal using an integrator circuit arrangement.
- the method may additionally include generating the digital output signal based on the analog output voltage signal using a quantizer circuit arrangement.
- the analog charging voltage may be generated based on the digital output signal using a voltage digital-to-analog converter, thereby generating the delta analog output voltage signal based on the digital output signal.
- FIG. 1 is a schematic of a capacitance to voltage converter (CVC).
- CVC capacitance to voltage converter
- FIG. 2 is a general schematic of a delta sigma modulator according to various embodiments.
- FIG. 3 is a schematic of a continuous-time delta sigma modulator (CT- ⁇ ) according to various embodiments.
- FIG. 4A is a schematic showing a capacitance-to-voltage converter according to various embodiments.
- FIG. 4B illustrates the differential sensor according to various embodiments.
- FIG. 4C illustrates the single ended or half bridge sensor according to various embodiments.
- FIG. 5A is a schematic showing a second order capacitance-to-digital converter (CDC) according to various embodiments.
- FIG. 5B is a schematic showing an exemplary implementation of the second order capacitance-to-digital (CDC) according to various embodiments.
- FIG. 5C illustrates the capacitance-to-digital converter (CDC) according to various embodiments in calibration phase.
- FIG. 5D illustrates the capacitance-to-digital converter (CDC) according to various embodiments in zoom-in phase.
- FIG. 6 is a plot of amplitude as a function of frequency (in kilohertz or kHz) showing the fast fourier transform (FFT) spectrum of the capacitance-to-digital converter (CDC) output according to various embodiments.
- FFT fast fourier transform
- FIG. 7 is a schematic showing a method of generating a digital output voltage or a method of operating a delta sigma modulator according to various embodiments.
- FIG. 8A is a table comparing the performance parameters of the modulator according to various embodiments with the performance parameters of conventional devices.
- FIG. 8B is another table comparing the performance parameters of the modulator according to various embodiments with the performance parameters of conventional devices.
- Embodiments described in the context of one of the methods or one of the modulators/converters/devices is analogously valid for the other methods or modulators/converters/devices.
- embodiments described in the context of a method are analogously valid for a modulator/converter/device, and vice versa.
- a first layer “over” a second layer may refer to the first layer directly on the second layer, or that the first layer and the second layer are separated by one or more intervening layers.
- the articles “a”, “an” and “the” as used with regard to a feature or element include a reference to one or more of the features or elements.
- the term “about” or “approximately” as applied to a numeric value encompasses the exact value and a reasonable variance.
- Continuous-time ⁇ modulators on the other hand do not have this problem as the sampling is performed just before the quantization.
- existing continuous-time ⁇ modulators require an additional capacitance-to-voltage converter (CVC), which increases power consumption.
- FIG. 1 is a schematic of a capacitance to voltage converter (CVC) 100 .
- C X may be the sensor capacitor and C REF may be a reference capacitance connected in series between a predetermined non-zero voltage (VDD) and ground (GND).
- VDD non-zero voltage
- GND ground
- C REF may be selected to cancel out the minimum rest capacitance of sensor.
- C F may be the feedback capacitor and C P1 and C P1 may be parasitic capacitances associated with sensor capacitor plates.
- the virtual ground may be set to V CM .
- the readout process may then extract charge proportional to difference between C X and C REF and may store the charge difference on C F . If V OUT is the voltage at the output of amplifier, by virtue of charge balancing it can be shown that
- V OUT (( C REF ⁇ C X )/ C F )* VDD/ 2 (1)
- the voltage at the output of the amplifier may be indicative of the sensor capacitance value.
- Various embodiments may provide an improved delta-sigma modulator, which may have advantages over conventional delta-sigma modulators, and/or which may address one or more issues faced by conventional delta-sigma modulators.
- Various embodiments may have lower power consumption, lower thermal noise, and/or higher signal-to-noise ratio compared to conventional devices.
- the delta-sigma modulator may be a continuous-time delta-sigma modulator (CT- ⁇ M) that embeds a capacitance-to-voltage converter (CVC) inside the sigma-delta loop, thereby improving energy efficiency.
- CVC capacitance-to-voltage converter
- Various embodiments may include a voltage controlled oscillator-based (VCO-based) integrator as the second stage, which performs multi-bit quantization that alleviates the biasing current requirements for the operational transconductance amplifiers (OTAs) used.
- VCO-based voltage controlled oscillator-based
- FIG. 2 is a general schematic of a delta sigma modulator 200 according to various embodiments.
- the delta sigma modulator 200 may be for generating a digital output voltage.
- the delta sigma modulator 200 may include a capacitance-to-voltage converter 202 for converting a sensed continuous-in-time applied capacitance signal to a delta analog output voltage signal.
- the converter 202 may include an amplifier 204 having a first input, a second input, and an output.
- the converter 204 may further include a feedback capacitor 206 with a first end coupled to the first input of the amplifier 204 , and a second end coupled to the output.
- the converter 202 may also include a sensor element 208 with a first end coupled to the first input of the amplifier 204 , and a second end for coupling to a first reference voltage, the sensor element 208 for sensing an external input to generate the continuous-in-time applied capacitance signal.
- the converter 202 may further include a reference capacitor 210 with a first end coupled to the first input of the amplifier 204 , and a second end for coupling to a second reference voltage.
- the reference capacitor 210 may have a reference capacitance.
- the converter 202 may additionally include a switch capacitor arrangement 212 with a first end coupled to the first input of the amplifier 204 , and a second end.
- the switch capacitor arrangement 212 may be configured to have a charge capacitance based on an analog charging voltage.
- the converter 202 may also include a switching mechanism 214 configured to switch the second end of the switch capacitor arrangement 212 , between the second end of the sensor element 208 so that the switch capacitor arrangement 212 is in parallel connection with the sensor element 208 , and the second end of the reference capacitor 210 so that the switch capacitor arrangement 212 is in parallel connection with the reference capacitor 210 .
- the switching may be based on the charge capacitance relative to the applied capacitance signal and the reference capacitance.
- the switching may adjust a first voltage signal at the first input of the amplifier 204 relative to a second voltage signal at the second input of the amplifier 204 , thereby adjusting the delta analog output voltage signal generated at the output.
- the modulator 200 may further include an integrator circuit arrangement 216 configured to generate an analog output voltage signal based on the delta analog output voltage signal.
- the modulator 200 may also include a quantizer circuit arrangement 218 configured to generate the digital output signal based on the analog output voltage signal.
- the modulator 200 may further include a voltage digital-to-analog converter 220 configured to generate the analog charging voltage based on the digital output signal, thereby generating the delta analog output voltage signal based on the digital output signal.
- the delta sigma modulator 200 may include a capacitance-to-voltage converter 202 configured to generate a continuous-in-time applied capacitance signal based on an external input, and may further configured to convert the continuous-in-time applied capacitance signal into a delta analog output voltage signal.
- the delta sigma modulator may further include an integrator circuit arrangement 216 coupled to the capacitance-to-voltage converter 202 and a quantizer circuit arrangement 218 coupled to the integrator circuit arrangement 216 to generate a digital output.
- the delta sigma modulator 200 may also include a voltage digital-to-analog converter 220 arranged along a feedback loop to couple the quantizer circuit arrangement 218 and the capacitance-to-voltage converter 202 .
- the delta sigma modulator 200 may be or may be included in a capacitance-to-digital (CDC) converter.
- CDC capacitance-to-digital
- FIG. 3 is a schematic of a continuous-time delta sigma modulator 300 (CT- ⁇ ) according to various embodiments.
- the delta sigma modulator 300 may include an embedded capacitance-to-voltage converter 302 (CVC).
- a modulator that follows the CVC 100 shown in FIG. 1 may be used for digitizing the sensor capacitance.
- such an implementation may not be energy efficient as both CVC and first integrator of the CT- ⁇ modulator need to meet noise requirements.
- the CVC may be modified to be embedded inside the CT- ⁇ M 300 as shown in FIG. 3 .
- a one bit quantizer 318 and digital-to-analog converter (DAC) 320 is shown in FIG. 3 .
- a switch capacitor 312 C DAC , may be used to feedback the output.
- One end of capacitor 312 may be tied to the floating node and other end may be switched between VDD and GND depending on the previous output using a switching arrangement 314 , e.g. including one or two switches.
- the switching arrangement 314 when set to 0, may connect capacitor 312 to sensor element 308 , i.e. capacitor C X , and when set to 1, may connect capacitor 312 to reference capacitor 310 , i.e. C REF .
- Equation (1) the output of the amplifier 304 may be modified from Equation (1) as follows:
- V OUT [( C REF ⁇ C X ⁇ 2* C DAC )/ C F ]* VDD/ 2 (2)
- the circuit 302 in FIG. 3 may perform the delta operation in a ⁇ modulator 300 .
- the circuit 302 embedded in a ⁇ loop may form a CT- ⁇ modulator.
- the value of capacitance of feedback capacitor (C F ) 306 may set the gain of the CVC 302 .
- the delta sigma modulator 300 shown in FIG. 3 may include a capacitance-to-voltage converter 302 for converting a sensed continuous-in-time applied capacitance signal to a delta analog output voltage signal.
- the converter 302 may include an amplifier 304 having a first input, a second input, and an output.
- the converter 304 may further include a feedback capacitor 306 with a first end coupled to the first input of the amplifier 304 , and a second end coupled to the output (of the amplifier 304 ).
- the converter 302 may further include a sensor element 308 , e.g. a sensing capacitor, with a first end coupled to the first input of the amplifier 304 , and a second end for coupling to a first reference voltage (e.g.
- the converter 308 may additionally include a reference capacitor 310 with a first end coupled to the first input of the amplifier 304 , and a second end for coupling to a second reference voltage (e.g. GND), the reference capacitor 310 having a reference capacitance.
- the converter 302 may also include a switch capacitor arrangement 312 (the switch capacitor arrangement 312 including a capacitor) with a first end coupled to the first input of the amplifier 304 , and a second end.
- the switch capacitor arrangement 312 may be configured to have a charge capacitance based on an analog charging voltage.
- the converter 302 may further include a switching mechanism 314 (including one, two or more switches) configured to switch the second end of the switch capacitor arrangement 314 , between the second end of the sensor element 308 so that the switch capacitor arrangement 314 is in parallel connection with the sensor element 308 , and the second end of the reference capacitor 310 so that the switch capacitor arrangement 312 is in parallel connection with the reference capacitor 310 .
- the switching (in the current time interval) may be based on the charge capacitance relative to the applied capacitance signal and the reference capacitance (of a previous or preceding time interval).
- the switching may adjust a first voltage signal at the first input of the amplifier relative to a second voltage signal at the second input of the amplifier, thereby adjusting the delta analog output voltage signal generated at the output.
- the delta analog output voltage signal generated at the output of the capacitance-to-voltage converter 302 may alternatively be referred to as CVC output signal.
- the modulator 300 may further include an integrator circuit arrangement or integrator 316 configured to generate an analog output voltage signal based on the delta analog output voltage signal.
- the modulator 300 may also include a quantizer circuit arrangement or quantizer 318 configured to generate the digital output signal based on the analog output voltage signal.
- the modulator 300 may further include a voltage digital-to-analog converter 320 configured to generate the analog charging voltage based on the digital output signal, thereby generating the delta analog output voltage signal based on the digital output signal.
- the second input of the amplifier 304 may be configured to receive a common mode voltage.
- a larger gain of the CVC 302 may alleviate the noise requirements of the integrator 316 that follows the CVC 302 .
- choosing the right value of C F 306 may make the proposed architecture energy efficient.
- a large resistor in the order of few gigaohms (G ⁇ ) may be used to set the direct current (DC) bias at the input of the amplifier, and feedback capacitor may form a high-pass filter at the input of the amplifier with a cut-off frequency in the range of few tens of Hz.
- DC direct current
- feedback capacitor may form a high-pass filter at the input of the amplifier with a cut-off frequency in the range of few tens of Hz.
- the capacitive input signal and in-band quantization noise may have to be chopped to a higher frequency.
- chopping may be done to demodulate the signal back to base band.
- FIG. 4A is a schematic showing a capacitance-to-voltage converter 402 according to various embodiments.
- the converter 402 may include step-up input choppers 424 a , 424 b , and output step-down chopper 426 .
- Adding reference chopping may also be beneficial in dealing with offset and flicker noise of the operational amplifier 404 (op-amp). This may reduce or eliminate the need for additional chopping for handling op-amp noise.
- the chopping frequency may be chosen to be larger than the flicker corner of the operational amplifier 404 .
- the delay offered by the operational amplifier 404 may result in a glitch at the output of CVC 402 . This may reduce the SNR of the overall CDC. Hence, careful analysis may be required in choosing the chopping frequency.
- a chopping frequency of 16 KHz may be used.
- the converter 402 may include a first switching circuit 422 a including the reference capacitor 410 , the switch capacitor arrangement 412 , and the switching mechanism 414 .
- the switch capacitor arrangement 412 may include one or more switching capacitors.
- the switching mechanism may include one, two or more switches.
- the converter 402 may include a second switching circuit 422 b including the further reference capacitor, the further switch capacitor arrangement, and the further switching mechanism.
- the further reference capacitor, the further switch capacitor arrangement, and the further switching mechanism are hidden from view in FIG. 4A .
- the first switching circuit 422 a and the second switching circuit 422 b may be substantially identical or similar.
- the further switch capacitor arrangement 422 b may include one or more further switching capacitors.
- the further switching mechanism may include one, two or more further switches.
- the capacitance-to-voltage converter 402 may include an amplifier 404 having a first input, a second input, and an output.
- the converter 402 may further include a feedback capacitor 406 a with a first end coupled to the first input of the amplifier 404 , and a second end coupled to the output.
- the converter 402 may further include a sensor element 408 a , e.g. a sensing capacitor, with a first end coupled to the first input of the amplifier 404 , and a second end for coupling to a first reference voltage, the sensor element 408 a for sensing an external input to generate the continuous-in-time applied capacitance signal.
- the converter 404 may additionally include a reference capacitor 410 with a first end coupled to the first input of the amplifier 404 , and a second end for coupling to a second reference voltage, the reference capacitor 410 having a reference capacitance.
- the converter 402 may also include a switch capacitor arrangement 412 with a first end coupled to the first input of the amplifier 404 , and a second end.
- the switch capacitor arrangement 412 may be configured to have a charge capacitance based on an analog charging voltage.
- the converter 404 may further include a switching mechanism 414 configured to switch the second end of the switch capacitor arrangement 412 , between the second end of the sensor element 408 a so that the switch capacitor arrangement 412 is in parallel connection with the sensor element 408 a , and the second end of the reference capacitor 410 so that the switch capacitor arrangement 414 is in parallel connection with the reference capacitor 410 .
- the switching may be based on the charge capacitance relative to the applied capacitance signal and the reference capacitance.
- the switching may adjust a first voltage signal at the first input of the amplifier relative to a second voltage signal at the second input of the amplifier 404 , thereby adjusting the delta analog output voltage signal generated at the output.
- the capacitance-to-voltage converter 402 may include a further feedback capacitor 406 b with a first end coupled to the second input and a second end coupled to the output.
- the converter 402 may also include a further sensor element (hidden from view in FIG. 4 ) with a first end coupled to the second input of the amplifier 404 , and a second end for coupling to the first reference voltage, the further sensor element for sensing the external input to generate a further applied capacitance signal.
- the converter 402 may further include the further reference capacitor with a first end coupled to the second input of the amplifier 404 , and a second end for coupling to the second reference voltage, the further reference capacitor having the reference capacitance.
- the converter 402 may additionally include the further switch capacitor arrangement with a first end coupled to the second input of the amplifier 404 , and a second end.
- the further switch capacitor arrangement may be configured to have a further charge capacitance based on a further analog charging voltage.
- the converter 402 may further include a further switching mechanism configured to switch the second end of the further switch capacitor arrangement, between the second end of the further sensor element so that the further switch capacitor arrangement is in parallel connection with the further sensor element, and the second end of the further reference capacitor so that the further switch capacitor arrangement is in parallel connection with the further reference capacitor.
- the switching may be based on the further charge capacitance relative to the applied capacitance signal and the reference capacitance.
- the switching may adjust the second voltage signal at the second input of the amplifier 404 .
- the delta sigma modulator 400 may further include a resistor 428 a connected in parallel to the feedback capacitor 406 a .
- the resistance of the resistor 428 a may be at least 1 giga-ohm.
- the delta sigma modulator 400 may further include a further resistor 428 b connected in parallel to the further feedback capacitor 406 b .
- the resistance of the further resistor 428 b may be at least 1 giga-ohm.
- the differential amplifier 404 may be a fully differential amplifier.
- the output of the differential amplifier 404 may include the first output end and a second output end.
- the second end of the feedback capacitor 406 a may be coupled to the first output end.
- the first end of the feedback capacitor 406 a may be coupled to the first input of the amplifier 404 .
- the second end of the further feedback capacitor 406 b may be coupled to the second output end.
- the first end of the further feedback capacitor 406 b may be coupled to the second input of the amplifier 404 .
- the modulator 400 or converter 402 may include an output step-down chopper 426 connected to the first output end and the second output end of the fully differential amplifier 404 .
- the output step-down chopper 426 may be configured to decrease a frequency of the delta analog output voltage signal.
- the first switching circuit 422 a may include the first step-up input chopper 424 a , and the second step-up input chopper 424 b .
- the modulator 400 or converter 402 may include the first step-up input chopper 424 a connected to the second end of the sensor element 408 a .
- the modulator 400 or converter 402 may also include a second step-up input chopper 424 b connected to the second end of the reference capacitor 410 .
- the first step-up input chopper 424 a and the second step-up input chopper 424 b may be configured to increase a frequency of the first voltage signal and a frequency of the second voltage signal.
- the first step-up input chopper 424 a may be configured to increase a frequency of the first voltage signal.
- the second step-up input chopper 424 b may be configured to increase a frequency of the second voltage signal.
- the first reference voltage may be provided by the first step-up input chopper 424 a .
- the second reference voltage may be provided by the second step-up input chopper 424 b .
- Each of the step-up input chopper 424 a , 424 b may be coupled to VDD and GND.
- the further switching circuit 422 a may include a first further step-up input chopper 424 a , and a second further step-up input chopper 424 b .
- the modulator 400 or converter 402 may include a first further step-up input chopper connected to the second end of the further sensor element.
- the modulator 400 or converter 402 may also include a second further step-up input chopper 424 b connected to the second end of the reference capacitor 410 .
- the first step-up input chopper 424 a and the second step-up input chopper 424 b may be configured to increase a frequency of the first voltage signal and a frequency of the second voltage signal.
- the modulator 400 or converter 402 may include an output step-down chopper 426 connected to the first output end and the second output end of the fully differential amplifier 404 .
- the output step-down chopper 426 may be configured to decrease a frequency of the delta analog output voltage signal.
- the sensor element 408 a may be in electrical connection with the further sensor element.
- the sensor element 408 a and the further sensor element may be or may form a differential sensor.
- FIG. 4B illustrates the differential sensor according to various embodiments.
- the differential sensor may include the sensor element 408 a and the further sensor element (denoted as 408 b ).
- the applied capacitance signal may have a static component and a dynamic component.
- the further applied capacitance signal may have a static component and a dynamic component.
- the static component (C x ) of the applied capacitance signal may substantially be equal to the static component (C x ) of the further applied capacitance signal.
- the dynamic component of the applied capacitance signal ( ⁇ Cx) may have an opposite polarity to the dynamic component of the further applied capacitance signal ( ⁇ Cx).
- the static capacitance in two branches may be substantially the same.
- the dynamic capacitance may change in a differential way. This implies that the sensor element 408 a may have or generate a capacitance value of Cx+ ⁇ Cx and the further sensor element 408 b may have or generate a capacitance value of Cx ⁇ Cx.
- the sensor element 408 a and the further sensor element may be or may form a single ended or half bridge sensor.
- FIG. 4C illustrates the single ended or half bridge sensor according to various embodiments.
- the single ended or half bridge sensor may include the sensor element 408 a and the further sensor element (denoted as 408 b ).
- the applied capacitance signal may have a static component and a dynamic component.
- the further applied capacitance signal may have a static component.
- the further applied capacitance signal may not have a dynamic component.
- the static component (Cx) of the applied capacitance signal may substantially be equal to the static component (Cx) of the further applied capacitance signal.
- the dynamic component of the applied capacitance signal ( ⁇ Cx) may vary between ⁇ Cx and + ⁇ Cx.
- the sensor element 408 a may have or generate a capacitance value of Cx ⁇ Cx
- the further sensor element 408 b may have or generate a capacitance value of Cx.
- FIG. 5A is a schematic showing a second order capacitance-to-digital converter (CDC) 500 according to various embodiments.
- FIG. 5A shows the architecture of the second order ⁇ loop with the CVC 502 with the sensor embedded or included in the loop.
- FIG. 5B is a schematic showing an exemplary implementation of the second order capacitance-to-digital (CDC) 500 according to various embodiments.
- a fully differential topology may be used.
- Two capacitive sensors i.e. first sensing capacitor 508 a and second sensing capacitor (hidden from view in FIG. 5B ), may be arranged in full bridge configuration, which may suppress or reduce supply noise or other common mode noise present in the system.
- the output of the CVC 502 may be equivalent to delta operation in ⁇ loop as discussed before.
- the output of CVC 502 may be integrated using an operational amplifier resistor-capacitor (op-amp RC) integrator 516 a .
- Voltage-controlled oscillator integrators (VCO-integrator) 538 a , 538 b may be used as the second integrator 516 b .
- FIG. 5B shows two voltage-controlled oscillator integrators 516 b .
- the phase of a VCO 538 a , 538 b may be proportional to the integral of its input.
- each of the VCOs 538 a , 538 b may act as a linear integrator if the input to the VCO 538 a , 538 b is within a predetermined linear range of the VCO 538 a , 538 b . Comparing the phase outputs of both VCOs 538 a , 538 b may give integral of the input. Sampling this multi-phase output using a D-flip-flop (DFF) 518 may quantize the phase in time domain.
- DFF D-flip-flop
- a multi-bit non-zero return (NRZ) current digital-to-analog converter (DAC) 548 may be used in the feedback path.
- Multi-bit feedback may keep the input to each VCO 538 a , 538 b within the linear range of the VCO 538 a , 538 b .
- the 31-stage VCOs 538 a , 538 b may performs 5-bit quantization.
- the 5-bit quantized value may be used in capacitive feedback as well. While FIG. 5B shows 31 stages, 31 lines, i.e. ⁇ 0:30>, and 31 capacitors in each capacitor bank C DAC 512 , the number of stages, lines and capacitors in each capacitor bank C DAc may vary in various other embodiments. The number may be provided by 2 n ⁇ 1, where n is the quantization resolution.
- the output of the VCO-based integrator 516 b may be inherently clocked level averaged (CLA), which is one form of Dynamic Element Matching (DEM) technique.
- CLA Dynamic Element Matching
- the CLA output of the VCO-based integrator 516 b may modulate any nonlinearity arising from DAC mismatches around twice the center frequency of the VCO-based integrator 516 b .
- the op-amp RC integrator 516 a may use chopping to minimize its flicker noise contribution.
- the high loop gain may provide first order shaping for the noise contribution from the VCO-based integrator 516 b , obviating the need for any additional noise reduction techniques.
- the second order capacitance-to-digital converter (CDC) or delta sigma modulator 500 may include a capacitance-to-voltage converter 502 similar to the capacitance-to-voltage converter 502 shown in FIG. 4A .
- the converter 502 may include an amplifier 504 , a first switching circuit 522 a coupled to a first input of the amplifier 504 , and a second switching circuit 522 b coupled to a second input of the amplifier 504 .
- the components of the second switching circuit 522 b are hidden from view in FIG. 5B .
- Each switching circuit 522 a , 522 b may include a sensor element e.g.
- the second order capacitance-to-digital converter 500 may also include an output step-down chopper 526 coupled to the first output end of the amplifier 504 and the second output end of the amplifier 504 .
- the second order capacitance-to-digital converter (CDC) or delta sigma modulator 500 may include may include an integrator circuit arrangement or integrator.
- the integrator circuit arrangement or integrator may include the first integrator stage 516 a and the second integrator stage 516 b .
- the first integrator stage 516 a may include an operational amplifier 530 .
- the operational amplifier 530 may include a first input coupled to the output step-down chopper 526 via resistor (R INT ) 532 a , and a second input coupled to the output step-down chopper 526 via resistor (R INT ) 532 b .
- the operational amplifier 530 may also include a chopper 534 a .
- the first integrator stage 516 a may also include an input chopper 534 b , which may couple the resistors 532 a , 532 b to the operational amplifier 530 .
- the operational amplifier 530 may further include a first output end, which may be coupled to the first input via capacitor (C INT ) 536 a , and a second output end, which may be coupled to the second input via capacitor (C INT ) 536 b.
- the second integrator stage 516 b may be coupled to the first integrator stage 516 a .
- the second integrator stage 516 b or CDC 500 may include a first voltage-controlled oscillator (VCO) 538 a and a second voltage-controlled oscillator (VCO) 538 b .
- the first VCO 538 a and the second VCO 538 b may each be a 31-stage VCO.
- the first VCO 538 a may be coupled to the first output end of the operational amplifier 530 via resistor (R N ) 540 a .
- the second VCO 538 b may be coupled to the second output end of the operational amplifier 530 via resistor (R N ) 540 b .
- the first VCO 538 a may be coupled to current source 540 a
- the second VCO 538 b may be coupled to current source 540 b.
- the second integrator stage 516 b or CDC 500 may include an exclusive OR gate (XOR) gate 542 .
- the XOR gate 542 may be coupled to the first VCO 538 a and the second VCO 538 b .
- the output of the first VCO 538 a and output of the second VCO 538 b may be provided to inputs of the XOR gate 542 .
- the second order capacitance-to-digital converter (CDC) or delta sigma modulator 500 may include a quantizer circuit arrangement or quantizer 518 .
- the quantizer circuit arrangement or quantizer 518 may be integrated with the second integrator stage 516 b to form an integrated stage, or may be coupled to the second integrator stage 516 b .
- the CDC 500 or quantizer circuit arrangement 518 may include a delay flip flop (DFF) 544 .
- the XOR gate 542 may be coupled to the first VCO 538 a and the second VCO 538 b . The output of the first VCO 538 a and the output of the second VCO 538 b may be provided to inputs of the XOR gate 542 .
- the XOR gate 542 may be coupled to delay flip flop (DFF) 544 . The output of the XOR gate may be provided to DFF 544 .
- the second order capacitance-to-digital converter (CDC) or delta sigma modulator 500 may include a digital-to-analog (DAC) converter 520 .
- the digital-to-analog (DAC) converter 520 may include a digital-to-analog driver 546 , which may include a first NAND gate and a second NAND gate.
- a non-zero return (NRZ) current digital-to-analog converter (DAC) 548 may be coupled to the digital-to-analog driver 546 .
- the non-zero return (NRZ) current digital-to-analog converter (DAC) 548 may be coupled to the first VCO 538 a and the second VCO 538 b , and may include a first transistor and a second transistor. As shown in FIG. 5B , the SWB line may couple the converter 548 to the first VCO 538 a and the current source 540 a , while the SW line may couple the converter 548 to the second VCO 538 b and the current source 540 b .
- the converter 520 may also be coupled to the capacitance-to-voltage converter 502 .
- the architecture proposed may also be implemented in various other ways.
- the implementation shown in FIG. 5B uses VCOs 538 a , 538 b as quantizer to yield a 5-bit output.
- VCOs 538 a , 538 b any number of bits may be used.
- any type of quantizers such as flash, successive approximation register (SAR) or simple comparator for single bit quantizer may be used.
- the choice of quantizer may be decided based on the requirement.
- FIG. 5B shows a second order delta-sigma modulator 500 with an oversampling ratio of about 125. Based on the resolution required, the order and/or oversampling ratio may be varied.
- FIG. 5C illustrates the capacitance-to-digital converter (CDC) 500 according to various embodiments in calibration phase.
- FIG. 5D illustrates the capacitance-to-digital converter (CDC) 500 according to various embodiments in zoom-in phase.
- a full bridge configuration may be used for the sensor elements or sensing capacitors.
- the sensor elements or sensing capacitors may be arranged in half-bridge configuration in FIG. 4C to form a single ended or half-bridge sensor.
- the sensor may alternatively be a differential sensor as shown in FIG. 4B .
- the sensing capacitors and feedback DAC may be connected to either VDD or GND, and may be excited by direct current (DC) sources.
- DC direct current
- other waveforms such as sinusoid, triangular or any other arbitrary waveform may be used for excitation.
- Various embodiments may be implemented in commercial 180 nm technology. Simulation has been carried out. Differential sinusoids have been used for testing and the CDC has been shown to achieve 14 bits effective number of bits (ENOB) for a power consumption of 48 uW by using a 1.2 V power supply.
- the CDC may use a sampling clock of 1 MHz and may sense from 0-10 pF capacitance with a resolution of 100 aF.
- FIG. 6 is a plot 600 of amplitude as a function of frequency (in kilohertz or kHz) showing the fast fourier transform (FFT) spectrum of the capacitance-to-digital converter (CDC) output according to various embodiments.
- the varying input capacitance used to simulate FIG. 6 is in the form of a sinusoid.
- the sampling frequency is about 500 kHz and the bandwidth is 4 kHz.
- the CVC stage operational amplifier open loop (OL) gain is about 60 dB and the integrator operational amplifier open loop (OL) gain is about 60 dB.
- the VCO tuning coefficient is sampling frequency (Fs).
- the Signal-to-Noise Distortion Ratio (SNDR) is about 113 dB.
- OSR oversampling
- KTC thermal
- OSR may have no effect in the total input referred (KTC) noise of the system.
- KTC total input referred
- the multibit capacitive DAC may help to reduce the swing at the output of C-to-V stage, which may improve power efficiency.
- the amount of power overhead added may be minimal because power consumption of the first stage is decided by the noise requirements of the system.
- FIG. 7 is a schematic 700 showing a method of generating a digital output voltage or a method of operating a delta sigma modulator according to various embodiments.
- the method may include, in 702 , converting a sensed continuous-in-time applied capacitance signal to a delta analog output voltage signal using a capacitance-to-voltage converter.
- the converter may include an amplifier having a first input, a second input, and an output.
- the converter may also include a feedback capacitor with a first end coupled to the first input of the amplifier, and a second end coupled to the output.
- the converter may further include a sensor element with a first end coupled to the first input of the amplifier, and a second end for coupling to a first reference voltage, the sensor element for sensing an external input to generate the continuous-in-time applied capacitance signal.
- the converter may additionally include a reference capacitor with a first end coupled to the first input of the amplifier, and a second end for coupling to a second reference voltage, the reference capacitor having a reference capacitance.
- the converter may also include a switch capacitor arrangement with a first end coupled to the first input of the amplifier, and a second end, the switch capacitor arrangement configured to have a charge capacitance based on an analog charging voltage.
- the converter may further include a switching mechanism configured to switch the second end of the switch capacitor arrangement, between the second end of the sensor element so that the switch capacitor arrangement is in parallel connection with the sensor element, and the second end of the reference capacitor so that the switch capacitor arrangement is in parallel connection with the reference capacitor.
- the switching may be based on the charge capacitance relative to the applied capacitance and the reference capacitance.
- the switching may adjust a first voltage signal at the first input of the amplifier relative to a second voltage signal at the second input of the amplifier, thereby adjusting the delta analog output voltage signal generated at the output.
- the method may also include, in 704 , generating an analog output voltage signal based on the delta analog output voltage signal using an integrator circuit arrangement.
- the method may additionally include, in 706 , generating the digital output signal based on the analog output voltage signal using a quantizer circuit arrangement.
- the analog charging voltage may be generated based on the digital output signal using a voltage digital-to-analog converter, thereby generating the delta analog output voltage signal based on the digital output signal.
- the capacitance-to-voltage converter may generate a delta analog output voltage signal.
- the integrator circuit arrangement may generate an analog output voltage signal based on the delta analog output voltage signal.
- the quantizer circuit arrangement may generate the digital output signal based on the analog output voltage signal using a quantizer circuit arrangement.
- There may also be a feedback loop including a voltage digital-to-analog converter connecting the output of the quantizer circuit arrangement to the integrator circuit arrangement.
- the sensor element and/or the further sensor element may be configured to generate the continuous-in-time applied capacitance signal based on a parameter of interest, such as a force or pressure applied to the sensor element and/or a force or pressure applied to the further sensor element.
- a parameter of interest such as a force or pressure applied to the sensor element and/or a force or pressure applied to the further sensor element.
- Other parameters may include a level of liquid detected by the sensor element(s), a humidity detected by the sensor element(s), or an acceleration detected by the sensor element(s) etc.
- the method may further include calibrating the modulator.
- the method may further include determining a baseline voltage based on a coarse voltage digital-to-analog converter during calibration.
- the analog charging voltage may be further based on the base-line voltage generated by the coarse voltage digital-to-analog converter.
- FIG. 8A is a table 800 a comparing the performance parameters of the modulator according to various embodiments with the performance parameters of conventional devices.
- FIG. 8B is another table 800 b comparing the performance parameters of the modulator according to various embodiments with the performance parameters of conventional devices.
- Various embodiments may provide a modulator including a continuous time CVC in a closed loop sigma delta.
- Various embodiments may provide a CVC, which may alleviate the need for charging and discharging of the sensing capacitor(s).
- Various embodiments may provide a charge balancing scheme to the capacitance-to-voltage (C-to-V) input using feedback digital-to-analog (DAC).
- C-to-V capacitance-to-voltage
- DAC digital-to-analog
- the CVC may be embedded in a sigma delta loop to improve energy efficiency.
- the sigma delta loop may be continuous time (CT) or hybrid.
- An open loop C-to-V stage followed by digital conversion may be energy inefficient.
- the switched capacitor delta sigma CDCs are popular. However, the energy efficiency may be limited by thermal noise folding and bandwidth requirements of loop filter, and the need to charge and discharge the sensor capacitor at the rate of sampling.
- Various embodiments may be analogous to continuous time sigma delta architecture for ADCs.
- the capacitive information may be converted to charge/voltage in the C-to-V stage.
Abstract
Description
- This application claims the benefit of priority of Singapore application No. 10201604413S filed on Jun. 1, 2016, the contents of it being hereby incorporated by reference in its entirety for all purposes.
- Various aspects of this disclosure relate to delta sigma modulators for generating digital output voltages. Various aspects of this disclosure relate to methods of generating digital output voltages.
- Capacitive sensors are based on the modulation of electrical capacitance by a physical or chemical parameter of interest. This principle is widely used, for instance in pressure sensors, liquid level gauges, accelerometers, and humidity sensors. Since capacitive sensors do not consume static power, they are very suitable for use in low-power and energy-constrained applications, such as battery-powered systems and wireless sensor networks. However, in such applications, the energy consumption of the capacitive sensor would be dominated by the interface circuit that converts capacitance values to the digital domain. Hence, for such applications, an energy-efficient capacitive-sensor interface is crucial. Recently, there has been lot of focus on ultra-low power energy efficient capacitive sensing based on novel techniques. However, the resolution of most of the designs is limited by the architecture. Period modulation is one technique used to achieve higher resolution. However, the need for a high-resolution time reference decreases the overall power efficiency of the system.
- Delta sigma (ΔΣ) modulation is a popular technique when high resolution is desired. There are several publications describing capacitance-to-digital convertors (CDC) using ΔΣ modulators. Some CDCs may use discrete-time ΔΣ modulators (DT-ΔΣM). However, there are two main disadvantages of this technique. The sampling operation at the input of the DT-ΔΣM may cause noise folding, resulting in increased thermal noise (KTC noise) and reducing signal-to-noise ratio (SNR). In addition, these modulators employ sensing capacitors as the sampling capacitors. Hence, there are charging and discharging of large off-chip and parasitic capacitors at the same rate as the sampling frequency, which consumes additional energy.
- Various embodiments may provide a delta sigma modulator. The delta sigma modulator may be for generating a digital output voltage. The delta sigma modulator may include a capacitance-to-voltage converter for converting a sensed continuous-in-time applied capacitance signal to a delta analog output voltage signal. The converter may include an amplifier having a first input, a second input, and an output. The converter may further include a feedback capacitor with a first end coupled to the first input of the amplifier, and a second end coupled to the output. The converter may also include a sensor element with a first end coupled to the first input of the amplifier, and a second end for coupling to a first reference voltage, the sensor element for sensing an external input to generate the continuous-in-time applied capacitance signal. The converter may further include a reference capacitor with a first end coupled to the first input of the amplifier, and a second end for coupling to a second reference voltage. The reference capacitor may have a reference capacitance. The converter may additionally include a switch capacitor arrangement with a first end coupled to the first input of the amplifier, and a second end. The switch capacitor arrangement may be configured to have a charge capacitance based on an analog charging voltage. The converter may also include a switching mechanism configured to switch the second end of the switch capacitor arrangement, between the second end of the sensor element so that the switch capacitor arrangement is in parallel connection with the sensor element, and the second end of the reference capacitor so that the switch capacitor arrangement is in parallel connection with the reference capacitor. The switching may be based on the charge capacitance relative to the applied capacitance signal and the reference capacitance. The switching may adjust a first voltage signal at the first input of the amplifier relative to a second voltage signal at the second input of the amplifier, thereby adjusting the delta analog output voltage signal generated at the output. The modulator may further include an integrator circuit arrangement configured to generate an analog output voltage signal based on the delta analog output voltage signal. The modulator may also include a quantizer circuit arrangement configured to generate the digital output signal based on the analog output voltage signal. The modulator may further include a voltage digital-to-analog converter configured to generate the analog charging voltage based on the digital output signal, thereby generating the delta analog output voltage signal based on the digital output signal.
- Various embodiments may provide a method of generating a digital output voltage or a method of operating a delta sigma modulator. The method may include converting a sensed continuous-in-time applied capacitance signal to a delta analog output voltage signal using a capacitance-to-voltage converter. The converter may include an amplifier having a first input, a second input, and an output. The converter may also include a feedback capacitor with a first end coupled to the first input of the amplifier, and a second end coupled to the output. The converter may further include a sensor element with a first end coupled to the first input of the amplifier, and a second end for coupling to a first reference voltage, the sensor element for sensing an external input to generate the continuous-in-time applied capacitance signal. The converter may additionally include a reference capacitor with a first end coupled to the first input of the amplifier, and a second end for coupling to a second reference voltage, the reference capacitor having a reference capacitance. The converter may also include a switch capacitor arrangement with a first end coupled to the first input of the amplifier, and a second end, the switch capacitor arrangement configured to have a charge capacitance based on an analog charging voltage. The converter may further include a switching mechanism configured to switch the second end of the switch capacitor arrangement, between the second end of the sensor element so that the switch capacitor arrangement is in parallel connection with the sensor element, and the second end of the reference capacitor so that the switch capacitor arrangement is in parallel connection with the reference capacitor. The switching may be based on the charge capacitance relative to the applied capacitance and the reference capacitance. The switching may adjust a first voltage signal at the first input of the amplifier relative to a second voltage signal at the second input of the amplifier, thereby adjusting the delta analog output voltage signal generated at the output. The method may also include generating an analog output voltage signal based on the delta analog output voltage signal using an integrator circuit arrangement. The method may additionally include generating the digital output signal based on the analog output voltage signal using a quantizer circuit arrangement. The analog charging voltage may be generated based on the digital output signal using a voltage digital-to-analog converter, thereby generating the delta analog output voltage signal based on the digital output signal.
- The invention will be better understood with reference to the detailed description when considered in conjunction with the non-limiting examples and the accompanying drawings, in which:
-
FIG. 1 is a schematic of a capacitance to voltage converter (CVC). -
FIG. 2 is a general schematic of a delta sigma modulator according to various embodiments. -
FIG. 3 is a schematic of a continuous-time delta sigma modulator (CT-ΔΣ) according to various embodiments. -
FIG. 4A is a schematic showing a capacitance-to-voltage converter according to various embodiments. -
FIG. 4B illustrates the differential sensor according to various embodiments. -
FIG. 4C illustrates the single ended or half bridge sensor according to various embodiments. -
FIG. 5A is a schematic showing a second order capacitance-to-digital converter (CDC) according to various embodiments. -
FIG. 5B is a schematic showing an exemplary implementation of the second order capacitance-to-digital (CDC) according to various embodiments. -
FIG. 5C illustrates the capacitance-to-digital converter (CDC) according to various embodiments in calibration phase. -
FIG. 5D illustrates the capacitance-to-digital converter (CDC) according to various embodiments in zoom-in phase. -
FIG. 6 is a plot of amplitude as a function of frequency (in kilohertz or kHz) showing the fast fourier transform (FFT) spectrum of the capacitance-to-digital converter (CDC) output according to various embodiments. -
FIG. 7 is a schematic showing a method of generating a digital output voltage or a method of operating a delta sigma modulator according to various embodiments. -
FIG. 8A is a table comparing the performance parameters of the modulator according to various embodiments with the performance parameters of conventional devices. -
FIG. 8B is another table comparing the performance parameters of the modulator according to various embodiments with the performance parameters of conventional devices. - The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, and logical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.
- Embodiments described in the context of one of the methods or one of the modulators/converters/devices is analogously valid for the other methods or modulators/converters/devices. Similarly, embodiments described in the context of a method are analogously valid for a modulator/converter/device, and vice versa.
- Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.
- The word “over” used with regards to a deposited material formed “over” a side or surface, may be used herein to mean that the deposited material may be formed “directly on”, e.g. in direct contact with, the implied side or surface. The word “over” used with regards to a deposited material formed “over” a side or surface, may also be used herein to mean that the deposited material may be formed “indirectly on” the implied side or surface with one or more additional layers being arranged between the implied side or surface and the deposited material. In other words, a first layer “over” a second layer may refer to the first layer directly on the second layer, or that the first layer and the second layer are separated by one or more intervening layers.
- In the context of various embodiments, the articles “a”, “an” and “the” as used with regard to a feature or element include a reference to one or more of the features or elements.
- In the context of various embodiments, the term “about” or “approximately” as applied to a numeric value encompasses the exact value and a reasonable variance.
- As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- Continuous-time ΔΣ modulators (CT-ΔΣM) on the other hand do not have this problem as the sampling is performed just before the quantization. However, existing continuous-time ΔΣ modulators require an additional capacitance-to-voltage converter (CVC), which increases power consumption.
-
FIG. 1 is a schematic of a capacitance to voltage converter (CVC) 100. CX may be the sensor capacitor and CREF may be a reference capacitance connected in series between a predetermined non-zero voltage (VDD) and ground (GND). CREF may be selected to cancel out the minimum rest capacitance of sensor. CF may be the feedback capacitor and CP1 and CP1 may be parasitic capacitances associated with sensor capacitor plates. The virtual ground may be set to VCM. The readout process may then extract charge proportional to difference between CX and CREF and may store the charge difference on CF. If VOUT is the voltage at the output of amplifier, by virtue of charge balancing it can be shown that -
V OUT=((C REF −C X)/C F)*VDD/2 (1) - As such, the voltage at the output of the amplifier may be indicative of the sensor capacitance value.
- Various embodiments may provide an improved delta-sigma modulator, which may have advantages over conventional delta-sigma modulators, and/or which may address one or more issues faced by conventional delta-sigma modulators. Various embodiments may have lower power consumption, lower thermal noise, and/or higher signal-to-noise ratio compared to conventional devices.
- In various embodiments, the delta-sigma modulator may be a continuous-time delta-sigma modulator (CT-ΔΣM) that embeds a capacitance-to-voltage converter (CVC) inside the sigma-delta loop, thereby improving energy efficiency. Various embodiments may include a voltage controlled oscillator-based (VCO-based) integrator as the second stage, which performs multi-bit quantization that alleviates the biasing current requirements for the operational transconductance amplifiers (OTAs) used.
-
FIG. 2 is a general schematic of a delta sigma modulator 200 according to various embodiments. The delta sigma modulator 200 may be for generating a digital output voltage. The delta sigma modulator 200 may include a capacitance-to-voltage converter 202 for converting a sensed continuous-in-time applied capacitance signal to a delta analog output voltage signal. Theconverter 202 may include anamplifier 204 having a first input, a second input, and an output. Theconverter 204 may further include afeedback capacitor 206 with a first end coupled to the first input of theamplifier 204, and a second end coupled to the output. Theconverter 202 may also include asensor element 208 with a first end coupled to the first input of theamplifier 204, and a second end for coupling to a first reference voltage, thesensor element 208 for sensing an external input to generate the continuous-in-time applied capacitance signal. Theconverter 202 may further include areference capacitor 210 with a first end coupled to the first input of theamplifier 204, and a second end for coupling to a second reference voltage. Thereference capacitor 210 may have a reference capacitance. Theconverter 202 may additionally include aswitch capacitor arrangement 212 with a first end coupled to the first input of theamplifier 204, and a second end. Theswitch capacitor arrangement 212 may be configured to have a charge capacitance based on an analog charging voltage. Theconverter 202 may also include aswitching mechanism 214 configured to switch the second end of theswitch capacitor arrangement 212, between the second end of thesensor element 208 so that theswitch capacitor arrangement 212 is in parallel connection with thesensor element 208, and the second end of thereference capacitor 210 so that theswitch capacitor arrangement 212 is in parallel connection with thereference capacitor 210. The switching may be based on the charge capacitance relative to the applied capacitance signal and the reference capacitance. The switching may adjust a first voltage signal at the first input of theamplifier 204 relative to a second voltage signal at the second input of theamplifier 204, thereby adjusting the delta analog output voltage signal generated at the output. - The
modulator 200 may further include anintegrator circuit arrangement 216 configured to generate an analog output voltage signal based on the delta analog output voltage signal. Themodulator 200 may also include aquantizer circuit arrangement 218 configured to generate the digital output signal based on the analog output voltage signal. Themodulator 200 may further include a voltage digital-to-analog converter 220 configured to generate the analog charging voltage based on the digital output signal, thereby generating the delta analog output voltage signal based on the digital output signal. - In other words, the delta sigma modulator 200 may include a capacitance-to-
voltage converter 202 configured to generate a continuous-in-time applied capacitance signal based on an external input, and may further configured to convert the continuous-in-time applied capacitance signal into a delta analog output voltage signal. The delta sigma modulator may further include anintegrator circuit arrangement 216 coupled to the capacitance-to-voltage converter 202 and aquantizer circuit arrangement 218 coupled to theintegrator circuit arrangement 216 to generate a digital output. The delta sigma modulator 200 may also include a voltage digital-to-analog converter 220 arranged along a feedback loop to couple thequantizer circuit arrangement 218 and the capacitance-to-voltage converter 202. - The delta sigma modulator 200 may be or may be included in a capacitance-to-digital (CDC) converter.
-
FIG. 3 is a schematic of a continuous-time delta sigma modulator 300 (CT-ΔΣ) according to various embodiments. The delta sigma modulator 300 may include an embedded capacitance-to-voltage converter 302 (CVC). - A modulator that follows the
CVC 100 shown inFIG. 1 , may be used for digitizing the sensor capacitance. However, such an implementation may not be energy efficient as both CVC and first integrator of the CT-ΔΣ modulator need to meet noise requirements. - Alternatively, the CVC may be modified to be embedded inside the CT-
ΔΣM 300 as shown inFIG. 3 . For simplicity, a onebit quantizer 318 and digital-to-analog converter (DAC) 320 is shown inFIG. 3 . Aswitch capacitor 312, CDAC, may be used to feedback the output. One end ofcapacitor 312 may be tied to the floating node and other end may be switched between VDD and GND depending on the previous output using aswitching arrangement 314, e.g. including one or two switches. The switchingarrangement 314 when set to 0, may connectcapacitor 312 tosensor element 308, i.e. capacitor CX, and when set to 1, may connectcapacitor 312 toreference capacitor 310, i.e. CREF. This may in turn balance the charge for all the capacitances connected to virtual ground. With every switching,capacitor 312 may be charged or discharged depending on the previous amount of charge held by thecapacitor 312. Hence, the amount of charge pumped in or out by CDAC for every switching is ±CDAC*VDD. By virtue of this charge balancing, the output of theamplifier 304 may be modified from Equation (1) as follows: -
V OUT=[(C REF −C X±2*C DAC)/C F]*VDD/2 (2) - If 2*CDAC corresponds to the quantized value of CX from the previous sampling interval, then the
circuit 302 inFIG. 3 may perform the delta operation in aΔΣ modulator 300. Thus, thecircuit 302 embedded in a ΔΣ loop may form a CT-ΔΣ modulator. The value of capacitance of feedback capacitor (CF) 306 may set the gain of theCVC 302. - In other words, the delta sigma modulator 300 shown in
FIG. 3 may include a capacitance-to-voltage converter 302 for converting a sensed continuous-in-time applied capacitance signal to a delta analog output voltage signal. Theconverter 302 may include anamplifier 304 having a first input, a second input, and an output. Theconverter 304 may further include afeedback capacitor 306 with a first end coupled to the first input of theamplifier 304, and a second end coupled to the output (of the amplifier 304). Theconverter 302 may further include asensor element 308, e.g. a sensing capacitor, with a first end coupled to the first input of theamplifier 304, and a second end for coupling to a first reference voltage (e.g. VDD), thesensor element 308 for sensing an external input to generate the continuous-in-time applied capacitance signal. Theconverter 308 may additionally include areference capacitor 310 with a first end coupled to the first input of theamplifier 304, and a second end for coupling to a second reference voltage (e.g. GND), thereference capacitor 310 having a reference capacitance. Theconverter 302 may also include a switch capacitor arrangement 312 (theswitch capacitor arrangement 312 including a capacitor) with a first end coupled to the first input of theamplifier 304, and a second end. Theswitch capacitor arrangement 312 may be configured to have a charge capacitance based on an analog charging voltage. Theconverter 302 may further include a switching mechanism 314 (including one, two or more switches) configured to switch the second end of theswitch capacitor arrangement 314, between the second end of thesensor element 308 so that theswitch capacitor arrangement 314 is in parallel connection with thesensor element 308, and the second end of thereference capacitor 310 so that theswitch capacitor arrangement 312 is in parallel connection with thereference capacitor 310. The switching (in the current time interval) may be based on the charge capacitance relative to the applied capacitance signal and the reference capacitance (of a previous or preceding time interval). The switching may adjust a first voltage signal at the first input of the amplifier relative to a second voltage signal at the second input of the amplifier, thereby adjusting the delta analog output voltage signal generated at the output. - The delta analog output voltage signal generated at the output of the capacitance-to-
voltage converter 302 may alternatively be referred to as CVC output signal. - The
modulator 300 may further include an integrator circuit arrangement orintegrator 316 configured to generate an analog output voltage signal based on the delta analog output voltage signal. Themodulator 300 may also include a quantizer circuit arrangement orquantizer 318 configured to generate the digital output signal based on the analog output voltage signal. Themodulator 300 may further include a voltage digital-to-analog converter 320 configured to generate the analog charging voltage based on the digital output signal, thereby generating the delta analog output voltage signal based on the digital output signal. The second input of theamplifier 304 may be configured to receive a common mode voltage. - A larger gain of the
CVC 302 may alleviate the noise requirements of theintegrator 316 that follows theCVC 302. Thus choosing the right value ofC F 306 may make the proposed architecture energy efficient. - In various embodiments, a large resistor, in the order of few gigaohms (GΩ), may be used to set the direct current (DC) bias at the input of the amplifier, and feedback capacitor may form a high-pass filter at the input of the amplifier with a cut-off frequency in the range of few tens of Hz. This may increase the in-band quantization noise in a ΔΣ loop. To mitigate this problem, the capacitive input signal and in-band quantization noise may have to be chopped to a higher frequency. At the output of CVC, chopping may be done to demodulate the signal back to base band.
-
FIG. 4A is a schematic showing a capacitance-to-voltage converter 402 according to various embodiments. Theconverter 402 may include step-upinput choppers chopper 426. Adding reference chopping may also be beneficial in dealing with offset and flicker noise of the operational amplifier 404 (op-amp). This may reduce or eliminate the need for additional chopping for handling op-amp noise. The chopping frequency may be chosen to be larger than the flicker corner of theoperational amplifier 404. At every chopping instance, the delay offered by theoperational amplifier 404 may result in a glitch at the output ofCVC 402. This may reduce the SNR of the overall CDC. Hence, careful analysis may be required in choosing the chopping frequency. In one implementation, a chopping frequency of 16 KHz may be used. - The
converter 402 may include afirst switching circuit 422 a including thereference capacitor 410, theswitch capacitor arrangement 412, and theswitching mechanism 414. Theswitch capacitor arrangement 412 may include one or more switching capacitors. The switching mechanism may include one, two or more switches. Theconverter 402 may include asecond switching circuit 422 b including the further reference capacitor, the further switch capacitor arrangement, and the further switching mechanism. The further reference capacitor, the further switch capacitor arrangement, and the further switching mechanism are hidden from view inFIG. 4A . Thefirst switching circuit 422 a and thesecond switching circuit 422 b may be substantially identical or similar. The furtherswitch capacitor arrangement 422 b may include one or more further switching capacitors. The further switching mechanism may include one, two or more further switches. - The capacitance-to-
voltage converter 402 may include anamplifier 404 having a first input, a second input, and an output. Theconverter 402 may further include afeedback capacitor 406 a with a first end coupled to the first input of theamplifier 404, and a second end coupled to the output. Theconverter 402 may further include asensor element 408 a, e.g. a sensing capacitor, with a first end coupled to the first input of theamplifier 404, and a second end for coupling to a first reference voltage, thesensor element 408 a for sensing an external input to generate the continuous-in-time applied capacitance signal. Theconverter 404 may additionally include areference capacitor 410 with a first end coupled to the first input of theamplifier 404, and a second end for coupling to a second reference voltage, thereference capacitor 410 having a reference capacitance. Theconverter 402 may also include aswitch capacitor arrangement 412 with a first end coupled to the first input of theamplifier 404, and a second end. Theswitch capacitor arrangement 412 may be configured to have a charge capacitance based on an analog charging voltage. Theconverter 404 may further include aswitching mechanism 414 configured to switch the second end of theswitch capacitor arrangement 412, between the second end of thesensor element 408 a so that theswitch capacitor arrangement 412 is in parallel connection with thesensor element 408 a, and the second end of thereference capacitor 410 so that theswitch capacitor arrangement 414 is in parallel connection with thereference capacitor 410. The switching may be based on the charge capacitance relative to the applied capacitance signal and the reference capacitance. The switching may adjust a first voltage signal at the first input of the amplifier relative to a second voltage signal at the second input of theamplifier 404, thereby adjusting the delta analog output voltage signal generated at the output. - The capacitance-to-
voltage converter 402 may include afurther feedback capacitor 406 b with a first end coupled to the second input and a second end coupled to the output. Theconverter 402 may also include a further sensor element (hidden from view inFIG. 4 ) with a first end coupled to the second input of theamplifier 404, and a second end for coupling to the first reference voltage, the further sensor element for sensing the external input to generate a further applied capacitance signal. Theconverter 402 may further include the further reference capacitor with a first end coupled to the second input of theamplifier 404, and a second end for coupling to the second reference voltage, the further reference capacitor having the reference capacitance. Theconverter 402 may additionally include the further switch capacitor arrangement with a first end coupled to the second input of theamplifier 404, and a second end. The further switch capacitor arrangement may be configured to have a further charge capacitance based on a further analog charging voltage. Theconverter 402 may further include a further switching mechanism configured to switch the second end of the further switch capacitor arrangement, between the second end of the further sensor element so that the further switch capacitor arrangement is in parallel connection with the further sensor element, and the second end of the further reference capacitor so that the further switch capacitor arrangement is in parallel connection with the further reference capacitor. The switching may be based on the further charge capacitance relative to the applied capacitance signal and the reference capacitance. The switching may adjust the second voltage signal at the second input of theamplifier 404. - As highlighted above, the delta sigma modulator 400 may further include a
resistor 428 a connected in parallel to thefeedback capacitor 406 a. The resistance of theresistor 428 a may be at least 1 giga-ohm. The delta sigma modulator 400 may further include afurther resistor 428 b connected in parallel to thefurther feedback capacitor 406 b. The resistance of thefurther resistor 428 b may be at least 1 giga-ohm. - In various embodiments, the
differential amplifier 404 may be a fully differential amplifier. The output of thedifferential amplifier 404 may include the first output end and a second output end. - The second end of the
feedback capacitor 406 a may be coupled to the first output end. The first end of thefeedback capacitor 406 a may be coupled to the first input of theamplifier 404. - The second end of the
further feedback capacitor 406 b may be coupled to the second output end. The first end of thefurther feedback capacitor 406 b may be coupled to the second input of theamplifier 404. - As highlighted above, the modulator 400 or
converter 402 may include an output step-downchopper 426 connected to the first output end and the second output end of the fullydifferential amplifier 404. The output step-downchopper 426 may be configured to decrease a frequency of the delta analog output voltage signal. - The
first switching circuit 422 a may include the first step-upinput chopper 424 a, and the second step-upinput chopper 424 b. The modulator 400 orconverter 402 may include the first step-upinput chopper 424 a connected to the second end of thesensor element 408 a. The modulator 400 orconverter 402 may also include a second step-upinput chopper 424 b connected to the second end of thereference capacitor 410. The first step-upinput chopper 424 a and the second step-upinput chopper 424 b may be configured to increase a frequency of the first voltage signal and a frequency of the second voltage signal. The first step-upinput chopper 424 a may be configured to increase a frequency of the first voltage signal. The second step-upinput chopper 424 b may be configured to increase a frequency of the second voltage signal. The first reference voltage may be provided by the first step-upinput chopper 424 a. The second reference voltage may be provided by the second step-upinput chopper 424 b. Each of the step-upinput chopper - Similarly, the
further switching circuit 422 a may include a first further step-upinput chopper 424 a, and a second further step-upinput chopper 424 b. The modulator 400 orconverter 402 may include a first further step-up input chopper connected to the second end of the further sensor element. The modulator 400 orconverter 402 may also include a second further step-upinput chopper 424 b connected to the second end of thereference capacitor 410. The first step-upinput chopper 424 a and the second step-upinput chopper 424 b may be configured to increase a frequency of the first voltage signal and a frequency of the second voltage signal. - The modulator 400 or
converter 402 may include an output step-downchopper 426 connected to the first output end and the second output end of the fullydifferential amplifier 404. The output step-downchopper 426 may be configured to decrease a frequency of the delta analog output voltage signal. - In various embodiments, the
sensor element 408 a may be in electrical connection with the further sensor element. - In various embodiments, the
sensor element 408 a and the further sensor element may be or may form a differential sensor.FIG. 4B illustrates the differential sensor according to various embodiments. The differential sensor may include thesensor element 408 a and the further sensor element (denoted as 408 b). The applied capacitance signal may have a static component and a dynamic component. The further applied capacitance signal may have a static component and a dynamic component. The static component (Cx) of the applied capacitance signal may substantially be equal to the static component (Cx) of the further applied capacitance signal. The dynamic component of the applied capacitance signal (ΔCx) may have an opposite polarity to the dynamic component of the further applied capacitance signal (−ΔCx). - For a differential sensor, the static capacitance in two branches (i.e. the sensor element and the further sensor element) may be substantially the same. However, the dynamic capacitance may change in a differential way. This implies that the
sensor element 408 a may have or generate a capacitance value of Cx+ΔCx and thefurther sensor element 408 b may have or generate a capacitance value of Cx−ΔCx. - In various embodiments, the
sensor element 408 a and the further sensor element may be or may form a single ended or half bridge sensor.FIG. 4C illustrates the single ended or half bridge sensor according to various embodiments. The single ended or half bridge sensor may include thesensor element 408 a and the further sensor element (denoted as 408 b). The applied capacitance signal may have a static component and a dynamic component. The further applied capacitance signal may have a static component. The further applied capacitance signal may not have a dynamic component. The static component (Cx) of the applied capacitance signal may substantially be equal to the static component (Cx) of the further applied capacitance signal. The dynamic component of the applied capacitance signal (ΔCx) may vary between −ΔCx and +ΔCx. For a single ended or half bridge sensor, thesensor element 408 a may have or generate a capacitance value of Cx±ΔCx, while thefurther sensor element 408 b may have or generate a capacitance value of Cx. -
FIG. 5A is a schematic showing a second order capacitance-to-digital converter (CDC) 500 according to various embodiments.FIG. 5A shows the architecture of the second order ΔΣ loop with theCVC 502 with the sensor embedded or included in the loop.FIG. 5B is a schematic showing an exemplary implementation of the second order capacitance-to-digital (CDC) 500 according to various embodiments. - A fully differential topology may be used. Two capacitive sensors i.e.
first sensing capacitor 508 a and second sensing capacitor (hidden from view inFIG. 5B ), may be arranged in full bridge configuration, which may suppress or reduce supply noise or other common mode noise present in the system. The output of theCVC 502 may be equivalent to delta operation in ΔΣ loop as discussed before. The output ofCVC 502 may be integrated using an operational amplifier resistor-capacitor (op-amp RC)integrator 516 a. Voltage-controlled oscillator integrators (VCO-integrator) 538 a, 538 b may be used as thesecond integrator 516 b.FIG. 5B shows two voltage-controlledoscillator integrators 516 b. The phase of aVCO - Thus, each of the
VCOs VCO VCO VCOs VCO VCO stage VCOs FIG. 5B shows 31 stages, 31 lines, i.e. <0:30>, and 31 capacitors in eachcapacitor bank C DAC 512, the number of stages, lines and capacitors in each capacitor bank CDAc may vary in various other embodiments. The number may be provided by 2n−1, where n is the quantization resolution. This may reduce the swing at the output of CVC and may help reduce power consumption of the op-amp 504. The output of the VCO-basedintegrator 516 b may be inherently clocked level averaged (CLA), which is one form of Dynamic Element Matching (DEM) technique. The CLA output of the VCO-basedintegrator 516 b may modulate any nonlinearity arising from DAC mismatches around twice the center frequency of the VCO-basedintegrator 516 b. The op-amp RC integrator 516 a may use chopping to minimize its flicker noise contribution. The high loop gain may provide first order shaping for the noise contribution from the VCO-basedintegrator 516 b, obviating the need for any additional noise reduction techniques. - In various embodiments, the second order capacitance-to-digital converter (CDC) or delta sigma modulator 500 may include a capacitance-to-
voltage converter 502 similar to the capacitance-to-voltage converter 502 shown inFIG. 4A . Theconverter 502 may include anamplifier 504, afirst switching circuit 522 a coupled to a first input of theamplifier 504, and asecond switching circuit 522 b coupled to a second input of theamplifier 504. The components of thesecond switching circuit 522 b are hidden from view inFIG. 5B . Each switchingcircuit reference capacitor 510, aswitch capacitor arrangement 512,e.g. capacitor bank 512 including a plurality of capacitors, a switching mechanism e.g. 514 including one, two or more switches, a first step-up input chopper e.g. 528 a, and a second step-up input chopper e.g. 528 b.Feedback capacitor 506 a andresistor 528 a may be coupled in parallel from the first input to the first output end of theamplifier 504. Further feedback capacitor 506 b andfurther resistor 528 b may be coupled in parallel from the second input to the second output end of theamplifier 504. The second order capacitance-to-digital converter 500 may also include an output step-downchopper 526 coupled to the first output end of theamplifier 504 and the second output end of theamplifier 504. - In various embodiments, the second order capacitance-to-digital converter (CDC) or delta sigma modulator 500 may include may include an integrator circuit arrangement or integrator. The integrator circuit arrangement or integrator may include the
first integrator stage 516 a and thesecond integrator stage 516 b. Thefirst integrator stage 516 a may include anoperational amplifier 530. Theoperational amplifier 530 may include a first input coupled to the output step-downchopper 526 via resistor (RINT) 532 a, and a second input coupled to the output step-downchopper 526 via resistor (RINT) 532 b. Theoperational amplifier 530 may also include achopper 534 a. Thefirst integrator stage 516 a may also include an input chopper 534 b, which may couple theresistors operational amplifier 530. Theoperational amplifier 530 may further include a first output end, which may be coupled to the first input via capacitor (CINT) 536 a, and a second output end, which may be coupled to the second input via capacitor (CINT) 536 b. - The
second integrator stage 516 b may be coupled to thefirst integrator stage 516 a. Thesecond integrator stage 516 b orCDC 500 may include a first voltage-controlled oscillator (VCO) 538 a and a second voltage-controlled oscillator (VCO) 538 b. Thefirst VCO 538 a and thesecond VCO 538 b may each be a 31-stage VCO. Thefirst VCO 538 a may be coupled to the first output end of theoperational amplifier 530 via resistor (RN) 540 a. Thesecond VCO 538 b may be coupled to the second output end of theoperational amplifier 530 via resistor (RN) 540 b. Thefirst VCO 538 a may be coupled tocurrent source 540 a, and thesecond VCO 538 b may be coupled tocurrent source 540 b. - The
second integrator stage 516 b orCDC 500 may include an exclusive OR gate (XOR)gate 542. TheXOR gate 542 may be coupled to thefirst VCO 538 a and thesecond VCO 538 b. The output of thefirst VCO 538 a and output of thesecond VCO 538 b may be provided to inputs of theXOR gate 542. - In various embodiments, the second order capacitance-to-digital converter (CDC) or delta sigma modulator 500 may include a quantizer circuit arrangement or
quantizer 518. In various embodiments, the quantizer circuit arrangement orquantizer 518 may be integrated with thesecond integrator stage 516 b to form an integrated stage, or may be coupled to thesecond integrator stage 516 b. TheCDC 500 orquantizer circuit arrangement 518 may include a delay flip flop (DFF) 544. TheXOR gate 542 may be coupled to thefirst VCO 538 a and thesecond VCO 538 b. The output of thefirst VCO 538 a and the output of thesecond VCO 538 b may be provided to inputs of theXOR gate 542. TheXOR gate 542 may be coupled to delay flip flop (DFF) 544. The output of the XOR gate may be provided toDFF 544. - In various embodiments, the second order capacitance-to-digital converter (CDC) or delta sigma modulator 500 may include a digital-to-analog (DAC)
converter 520. The digital-to-analog (DAC)converter 520 may include a digital-to-analog driver 546, which may include a first NAND gate and a second NAND gate. A non-zero return (NRZ) current digital-to-analog converter (DAC) 548 may be coupled to the digital-to-analog driver 546. The non-zero return (NRZ) current digital-to-analog converter (DAC) 548 may be coupled to thefirst VCO 538 a and thesecond VCO 538 b, and may include a first transistor and a second transistor. As shown inFIG. 5B , the SWB line may couple theconverter 548 to thefirst VCO 538 a and thecurrent source 540 a, while the SW line may couple theconverter 548 to thesecond VCO 538 b and thecurrent source 540 b. Theconverter 520 may also be coupled to the capacitance-to-voltage converter 502. - The architecture proposed may also be implemented in various other ways. For instance, the implementation shown in
FIG. 5B usesVCOs - Also,
FIG. 5B shows a second order delta-sigma modulator 500 with an oversampling ratio of about 125. Based on the resolution required, the order and/or oversampling ratio may be varied. - Calculating baseline value of capacitance may be important in sensory applications where manufacturing process variations and other parasitic capacitances may drift or vary the value from a desired value. For a multi-bit quantizer, a coarse feedback may be used during the calibration phase that sets the coarse value of the baseline capacitance.
FIG. 5C illustrates the capacitance-to-digital converter (CDC) 500 according to various embodiments in calibration phase. - Once the coarse value is set, the
CDC 500 may continue regular operation with fine value of capacitors for feedback DAC. A similar approach may be used for implementing zoom-in CDC.FIG. 5D illustrates the capacitance-to-digital converter (CDC) 500 according to various embodiments in zoom-in phase. - In various embodiments, a full bridge configuration may be used for the sensor elements or sensing capacitors. In various other embodiments, the sensor elements or sensing capacitors may be arranged in half-bridge configuration in
FIG. 4C to form a single ended or half-bridge sensor. The sensor may alternatively be a differential sensor as shown inFIG. 4B . - In the architecture, the sensing capacitors and feedback DAC may be connected to either VDD or GND, and may be excited by direct current (DC) sources. However, other waveforms such as sinusoid, triangular or any other arbitrary waveform may be used for excitation.
- Various embodiments may be implemented in commercial 180 nm technology. Simulation has been carried out. Differential sinusoids have been used for testing and the CDC has been shown to achieve 14 bits effective number of bits (ENOB) for a power consumption of 48 uW by using a 1.2 V power supply. The CDC may use a sampling clock of 1 MHz and may sense from 0-10 pF capacitance with a resolution of 100 aF.
-
FIG. 6 is aplot 600 of amplitude as a function of frequency (in kilohertz or kHz) showing the fast fourier transform (FFT) spectrum of the capacitance-to-digital converter (CDC) output according to various embodiments. The varying input capacitance used to simulateFIG. 6 is in the form of a sinusoid. The sampling frequency is about 500 kHz and the bandwidth is 4 kHz. The CVC stage operational amplifier open loop (OL) gain is about 60 dB and the integrator operational amplifier open loop (OL) gain is about 60 dB. The VCO tuning coefficient is sampling frequency (Fs). The Signal-to-Noise Distortion Ratio (SNDR) is about 113 dB. - The advantages of various embodiments may include one or more of the following:
- No noise folding: Since the input capacitance is not sampled there may be no noise folding at the input of the CDC. In the presence of chopping, noise present at the input may be dominated only by the thermal noise of the CVC op-amp. Noise from other circuit components may not be aliased. This may improve the resolution that could be achieved for a given amount of power when compared to switched capacitor implementation.
- Power need not scale with performance: For a switched capacitor implementation increased oversampling (OSR) improves thermal (KTC) noise. However, increased OSR comes with a penalty in higher power consumption as op-amp settling time, and other delays have to be optimized for a given sampling frequency. In various embodiments, OSR may have no effect in the total input referred (KTC) noise of the system. Thus, OSR may be freely chosen based on the quantization noise requirements.
- Large sensing capacitors and associated parasitics may not be charged and discharged at the rate of sampling frequency, which may improve energy efficiency.
- The multibit capacitive DAC may help to reduce the swing at the output of C-to-V stage, which may improve power efficiency.
- Even though various embodiments may need one additional op-amp for CVC, the amount of power overhead added may be minimal because power consumption of the first stage is decided by the noise requirements of the system.
-
FIG. 7 is a schematic 700 showing a method of generating a digital output voltage or a method of operating a delta sigma modulator according to various embodiments. The method may include, in 702, converting a sensed continuous-in-time applied capacitance signal to a delta analog output voltage signal using a capacitance-to-voltage converter. - The converter may include an amplifier having a first input, a second input, and an output. The converter may also include a feedback capacitor with a first end coupled to the first input of the amplifier, and a second end coupled to the output. The converter may further include a sensor element with a first end coupled to the first input of the amplifier, and a second end for coupling to a first reference voltage, the sensor element for sensing an external input to generate the continuous-in-time applied capacitance signal. The converter may additionally include a reference capacitor with a first end coupled to the first input of the amplifier, and a second end for coupling to a second reference voltage, the reference capacitor having a reference capacitance. The converter may also include a switch capacitor arrangement with a first end coupled to the first input of the amplifier, and a second end, the switch capacitor arrangement configured to have a charge capacitance based on an analog charging voltage. The converter may further include a switching mechanism configured to switch the second end of the switch capacitor arrangement, between the second end of the sensor element so that the switch capacitor arrangement is in parallel connection with the sensor element, and the second end of the reference capacitor so that the switch capacitor arrangement is in parallel connection with the reference capacitor. The switching may be based on the charge capacitance relative to the applied capacitance and the reference capacitance. The switching may adjust a first voltage signal at the first input of the amplifier relative to a second voltage signal at the second input of the amplifier, thereby adjusting the delta analog output voltage signal generated at the output. The method may also include, in 704, generating an analog output voltage signal based on the delta analog output voltage signal using an integrator circuit arrangement. The method may additionally include, in 706, generating the digital output signal based on the analog output voltage signal using a quantizer circuit arrangement. The analog charging voltage may be generated based on the digital output signal using a voltage digital-to-analog converter, thereby generating the delta analog output voltage signal based on the digital output signal.
- In other words, the capacitance-to-voltage converter may generate a delta analog output voltage signal. The integrator circuit arrangement may generate an analog output voltage signal based on the delta analog output voltage signal. The quantizer circuit arrangement may generate the digital output signal based on the analog output voltage signal using a quantizer circuit arrangement. There may also be a feedback loop including a voltage digital-to-analog converter connecting the output of the quantizer circuit arrangement to the integrator circuit arrangement.
- The sensor element and/or the further sensor element may be configured to generate the continuous-in-time applied capacitance signal based on a parameter of interest, such as a force or pressure applied to the sensor element and/or a force or pressure applied to the further sensor element. Other parameters may include a level of liquid detected by the sensor element(s), a humidity detected by the sensor element(s), or an acceleration detected by the sensor element(s) etc.
- The method may further include calibrating the modulator. The method may further include determining a baseline voltage based on a coarse voltage digital-to-analog converter during calibration. The analog charging voltage may be further based on the base-line voltage generated by the coarse voltage digital-to-analog converter.
-
FIG. 8A is a table 800 a comparing the performance parameters of the modulator according to various embodiments with the performance parameters of conventional devices. - The conventional devices are described in the following publications:
- 1. J. Wanyeong, J. Seokhyeon, O. Sechang, D. Sylvester, and D. Blaauw, “27.6 A 0.7 pF-to-10 nF fully digital capacitance-to-digital converter using iterative delay-chain discharge,” in Solid-State Circuits Conference—(ISSCC), 2015 IEEE International, 2015, pp. 1-3.
- 2. O. Sechang, J. Wanyeong, Y. Kaiyuan, D. Blaauw, and D. Sylvester, “15.4b incremental sigma-delta capacitance-to-digital converter with zoom-in 9b asynchronous SAR,” in VLSI Circuits Digest of Technical Papers, 2014 Symposium on, 2014, pp. 1-2.
- 3. H. Yuming, C. Zu-yao, L. Pakula, S. H. Shalmany, and M. Pertijs, “27.7 A 0.05 mm2 1V capacitance-to-digital converter based on period modulation,” in Solid-State Circuits Conference—(ISSCC), 2015 IEEE International, 2015, pp. 1-3.
- 4. T. Zhichao, R. Daamen, A. Humbert, Y. V. Ponomarev, C. Youngcheol, and M. A. P. Pertijs, “A 1.2-V 8.3-nJ CMOS Humidity Sensor for RFID Applications,” Solid-State Circuits, IEEE Journal of, vol. 48, pp. 2469-2477, 2013.
- 5. X. Sha, K. Makinwa, and S. Nihtianov, “A capacitance-to-digital converter for displacement sensing with 17 b resolution and 20 μs conversion time,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, 2012, pp. 198-200.
-
FIG. 8B is another table 800 b comparing the performance parameters of the modulator according to various embodiments with the performance parameters of conventional devices. - Various embodiments may provide a modulator including a continuous time CVC in a closed loop sigma delta. Various embodiments may provide a CVC, which may alleviate the need for charging and discharging of the sensing capacitor(s). Various embodiments may provide a charge balancing scheme to the capacitance-to-voltage (C-to-V) input using feedback digital-to-analog (DAC).
- In various embodiments, the CVC may be embedded in a sigma delta loop to improve energy efficiency. The sigma delta loop may be continuous time (CT) or hybrid.
- An open loop C-to-V stage followed by digital conversion may be energy inefficient. The switched capacitor delta sigma CDCs are popular. However, the energy efficiency may be limited by thermal noise folding and bandwidth requirements of loop filter, and the need to charge and discharge the sensor capacitor at the rate of sampling.
- The abovementioned issues may be mitigated by using a continuous time solution. Various embodiments may be analogous to continuous time sigma delta architecture for ADCs. The capacitive information may be converted to charge/voltage in the C-to-V stage.
- While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.
Claims (20)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG10201604413S | 2016-06-01 | ||
SG10201604413S | 2016-06-01 | ||
PCT/SG2017/050269 WO2017209690A1 (en) | 2016-06-01 | 2017-05-24 | Delta sigma modulator for and method of generating a digital output voltage |
Publications (2)
Publication Number | Publication Date |
---|---|
US20200328757A1 true US20200328757A1 (en) | 2020-10-15 |
US10819366B1 US10819366B1 (en) | 2020-10-27 |
Family
ID=60477717
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/305,142 Active 2037-11-17 US10819366B1 (en) | 2016-06-01 | 2017-05-24 | Delta sigma modulator for and method of generating a digital output voltage |
Country Status (3)
Country | Link |
---|---|
US (1) | US10819366B1 (en) |
SG (1) | SG11201810578UA (en) |
WO (1) | WO2017209690A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113206671A (en) * | 2021-01-05 | 2021-08-03 | 珠海市杰理科技股份有限公司 | Sigma-Delta modulator realized based on VCO (Voltage controlled Oscillator) and audio equipment |
US11175179B2 (en) * | 2019-04-24 | 2021-11-16 | Egis Technology Inc. | Calibration circuit for use in sensor and related sensor thereof |
US20220057207A1 (en) * | 2020-08-19 | 2022-02-24 | Invensense, Inc. | Minimizing a delay of a capacitance-to-voltage converter of a gyroscope by including such converter within a bandpass sigma-delta analog-to-digital converter of the gyroscope |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3933367B1 (en) * | 2020-06-03 | 2023-12-20 | NXP USA, Inc. | Sensor interface circuit, sensor system, and method of signal measurement |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5995036A (en) | 1998-03-17 | 1999-11-30 | Sonic Innovations, Inc. | Passive switched capacitor delta analog-to-digital converter with programmable gain control |
JP2002030970A (en) | 2000-07-17 | 2002-01-31 | Honda Motor Co Ltd | Combustion state control device for cylinder fuel injection type internal combustion engine |
US6954159B1 (en) | 2003-07-01 | 2005-10-11 | Impinj, Inc. | Low distortion band-pass analog to digital converter with feed forward |
DE102004009611B4 (en) | 2004-02-27 | 2010-01-14 | Infineon Technologies Ag | Time-continuous sigma-delta analog-to-digital converter |
JP2008507221A (en) * | 2004-07-17 | 2008-03-06 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Sigma delta modulator |
DE102005038875A1 (en) * | 2005-05-25 | 2006-11-30 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Capacitance measuring circuit |
US7324029B2 (en) * | 2006-01-26 | 2008-01-29 | Emerson Process Management | Capacitance-to-digital interface circuit for differential pressure sensor |
US8547114B2 (en) | 2006-11-14 | 2013-10-01 | Cypress Semiconductor Corporation | Capacitance to code converter with sigma-delta modulator |
US7817075B2 (en) * | 2009-02-03 | 2010-10-19 | Windtop Technology Corp. | Apparatus for converting MEMS inductive capacitance |
US8629795B2 (en) * | 2009-09-09 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Micro-electro-mechanical systems (MEMS), systems, and operating methods thereof |
US8344928B2 (en) * | 2010-11-10 | 2013-01-01 | Stmicroelectronics Asia Pacific Pte Ltd. | Method and apparatus for capacitance sensing |
EP2930851B1 (en) * | 2014-04-09 | 2018-09-12 | Ams Ag | Capacitance-to-digital converter and method for providing a digital output signal |
US9628104B2 (en) * | 2015-03-13 | 2017-04-18 | Rosemount Inc. | High resolution sigma delta modulator for capacitance sensor terminal displacement measurement |
US9976924B2 (en) * | 2015-04-20 | 2018-05-22 | Infineon Technologies Ag | System and method for a MEMS sensor |
US10224884B2 (en) * | 2017-02-07 | 2019-03-05 | Xilinx, Inc. | Circuit for and method of implementing a multifunction output generator |
DE102017110976B8 (en) * | 2017-05-19 | 2018-12-06 | Infineon Technologies Austria Ag | Self-oscillating multi-ramp converter and method for converting a capacitance into a digital signal |
-
2017
- 2017-05-24 US US16/305,142 patent/US10819366B1/en active Active
- 2017-05-24 WO PCT/SG2017/050269 patent/WO2017209690A1/en active Application Filing
- 2017-05-24 SG SG11201810578UA patent/SG11201810578UA/en unknown
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11175179B2 (en) * | 2019-04-24 | 2021-11-16 | Egis Technology Inc. | Calibration circuit for use in sensor and related sensor thereof |
US20220057207A1 (en) * | 2020-08-19 | 2022-02-24 | Invensense, Inc. | Minimizing a delay of a capacitance-to-voltage converter of a gyroscope by including such converter within a bandpass sigma-delta analog-to-digital converter of the gyroscope |
US11821731B2 (en) * | 2020-08-19 | 2023-11-21 | Invensense, Inc. | Minimizing a delay of a capacitance-to-voltage converter of a gyroscope by including such converter within a bandpass sigma-delta analog-to-digital converter of the gyroscope |
CN113206671A (en) * | 2021-01-05 | 2021-08-03 | 珠海市杰理科技股份有限公司 | Sigma-Delta modulator realized based on VCO (Voltage controlled Oscillator) and audio equipment |
Also Published As
Publication number | Publication date |
---|---|
SG11201810578UA (en) | 2018-12-28 |
US10819366B1 (en) | 2020-10-27 |
WO2017209690A1 (en) | 2017-12-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10819366B1 (en) | Delta sigma modulator for and method of generating a digital output voltage | |
US7136006B2 (en) | Systems and methods for mismatch cancellation in switched capacitor circuits | |
JP5836020B2 (en) | A / D converter | |
US20140167995A1 (en) | Analog-to-digital converter | |
US11265008B2 (en) | Successive approximation register (SAR) analog to digital converter (ADC) | |
US20210258014A1 (en) | Time-domain incremental two-step capacitance-to-digital converter | |
Singh et al. | A 20bit continuous-time ΣΔ modulator with a Gm-C integrator, 120dB CMRR and 15 ppm INL | |
US9419643B2 (en) | Delta sigma modulator | |
Sanjurjo et al. | An energy-efficient 17-bit noise-shaping Dual-Slope Capacitance-to-Digital Converter for MEMS sensors | |
Narasimman et al. | A 1.2 V, 0.84 pJ/conv.-Step ultra-low power capacitance to digital converter for microphone based auscultation | |
Nilchi et al. | Charge-pump based switched-capacitor integrator for ΔΣ modulators | |
Radjen et al. | A continuous time delta-sigma modulator with reduced clock jitter sensitivity through DSCR feedback | |
Rogi et al. | A novel architecture for a Capacitive-to-Digital Converter using time-encoding and noise shaping | |
US11095262B2 (en) | Circuit arrangement and a method for operating a circuit arrangement | |
Fu et al. | A 14.5-Bit ENOB, 10MS/s SAR-ADC With 2 nd Order Hybrid Passive-Active Resonator Noise Shaping | |
Kareppagoudr et al. | Switched-Capacitor Integrator with Slew-Rate Enhancement and Low Distortion | |
Tan et al. | The design of ΔΣ-ADC in MEMS gyro interface ASIC | |
Vasishta et al. | A sawtooth relaxation ico based 1-1 mash adc | |
Laifi et al. | A 96 dB SNDR current-mode continuous-time ΔΣ modulator for electrochemical sensor arrays | |
Salomaa et al. | A ΔΣ ADC for low power sensor applications | |
Li et al. | An Energy-Efficient 13-bit Zero-Crossing ΔΣ Capacitance-to-Digital Converter with 1 pF-to-10 nF Sensing Range | |
Basha et al. | Accurate Data Acquisition Circuit for MEMS Accelerometer | |
Liu et al. | A 100dB-SNR mixed CT/DT audio-band sigma delta ADC | |
Hsieh et al. | A sar-assisted continuous-time incremental σδ adc with first-order noise coupling | |
Chatterjee et al. | Design, integration and performance analysis of ΣΔ ADC for capacitive sensor interfacing |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: NANYANG TECHNOLOGICAL UNIVERSITY, SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NARASIMMAN, NEELAKANTAN;NAG, DIPANKAR;CHAI, KEVIN TSHUN CHUAN;AND OTHERS;SIGNING DATES FROM 20190121 TO 20190122;REEL/FRAME:048362/0494 Owner name: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH, SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NARASIMMAN, NEELAKANTAN;NAG, DIPANKAR;CHAI, KEVIN TSHUN CHUAN;AND OTHERS;SIGNING DATES FROM 20190121 TO 20190122;REEL/FRAME:048362/0494 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |