US20200321291A1 - Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die - Google Patents
Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die Download PDFInfo
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- US20200321291A1 US20200321291A1 US16/907,520 US202016907520A US2020321291A1 US 20200321291 A1 US20200321291 A1 US 20200321291A1 US 202016907520 A US202016907520 A US 202016907520A US 2020321291 A1 US2020321291 A1 US 2020321291A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
Definitions
- the present disclosure relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming backside openings for an ultra-thin semiconductor die.
- a semiconductor wafer or substrate can be made with a variety of base substrate materials, such as silicon (Si), germanium, aluminum phosphide, aluminum arsenide, gallium arsenide (GaAs), gallium nitride (GaN), aluminum gallium nitride over gallium nitride (AlGaN/GaN), indium phosphide, silicon carbide (SiC), or other bulk material for structural support.
- a plurality of semiconductor die is formed on the wafer separated by a non-active, inter-die substrate area or saw street. The saw street provides cutting areas to singulate the semiconductor wafer into individual semiconductor die.
- the primary current path is vertical from the top surface of the die to a back surface of the die.
- the vertical resistance e.g., drain-source resistance (RDSON) of a vertical transistor, decreases with the thickness of the semiconductor die.
- RDSON drain-source resistance
- the semiconductor die should be as thin as possible while still maintaining structural integrity.
- An opening can be formed in the back surface to reduce thickness of the semiconductor die and vertical resistance.
- FIGS. 1 a -1 b illustrate a semiconductor substrate with a plurality of semiconductor die separated by a saw street
- FIGS. 2 a -2 l illustrate a process of forming a backside opening to enable lift-off of a backside metal
- FIG. 3 illustrates the semiconductor die of FIGS. 2 a -2 l post singulation
- FIGS. 4 a -4 n illustrate a process of forming honeycomb pattern of base substrate material for support of ultra-thin semiconductor die
- FIG. 5 illustrates the semiconductor die of FIGS. 4 a -4 n post singulation.
- semiconductor die refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
- FIG. 1 a shows a semiconductor wafer or substrate 100 with a base substrate material 102 , such as Si, germanium, aluminum phosphide, aluminum arsenide, GaAs, GaN, AlGaN/GaN, indium phosphide, SiC, or other bulk material for structural support.
- Semiconductor substrate 100 has a width or diameter of 100-450 millimeters (mm) and thickness of about 700-800 micrometers ( ⁇ m).
- a plurality of semiconductor die 104 is formed on substrate 100 separated by a non-active, inter-die substrate area or saw street 106 .
- Saw street 106 provides cutting areas to singulate semiconductor substrate 100 into individual semiconductor die 104 .
- FIG. 1 b shows a cross-sectional view of a portion of semiconductor substrate 100 .
- Each semiconductor die 104 includes a back surface 108 and active surface or region 110 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die.
- the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface or region 110 to implement analog circuits or digital circuits.
- semiconductor die 104 implements a diode, transistor, or other discrete semiconductor device.
- the gate region and source region are typically accessible on active surface 110
- the drain region of the vertical transistor is back surface 108 .
- Semiconductor die 104 may also contain a digital signal processor (DSP), microcontroller, ASIC, standard logic, amplifiers, clock management, memory, interface circuit, optoelectronics, and other signal processing circuits.
- DSP digital signal processor
- ASIC application-specific integrated circuit
- IPDs integrated passive devices
- An electrically conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process.
- Conductive layer 112 includes one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium tungsten (TiW), TiNiCu, TiNiAg, or other suitable electrically conductive material.
- Conductive layer 112 operates as contact pads electrically connected to the circuits, e.g., gate region and source region of the vertical transistor, on active surface 110 .
- FIGS. 2 a -2 l show a process of forming a backside opening to achieve an ultra-thin semiconductor die and enable lift-off of a backside metal without singulation through the backside metal.
- semiconductor substrate 100 is positioned with active surface 110 oriented toward carrier or backgrinding tape 120 .
- an interior region of back surface 108 a of semiconductor substrate 100 is thinned with grinding wheel 122 , leaving a thick support ring 124 around a perimeter of the semiconductor substrate.
- FIG. 2 c illustrates back surface 108 b, after thinning, of semiconductor substrate 100 with optional support ring 124 for structural support.
- semiconductor wafer 100 has a thickness of 90-150 ⁇ m between active surface 110 and back surface 108 b.
- photoresist layer 126 is formed over back surface 108 b of semiconductor substrate 100 .
- Photoresist layer 126 is patterned with openings 128 over back surface 108 b. There is one opening 128 aligned with each semiconductor die 104 .
- a plurality of openings 130 is formed partially into back surface 108 b but not completely through base substrate material 102 through openings 128 by isotropic etching, non-isotropic etching, or laser direct ablation (LDA).
- Photoresist layer 126 covers any laser mark area of semiconductor substrate 100 to avoid forming opening 130 within the laser mark area.
- FIG. 2 f shows a cross-sectional view, taken along line 2 f - 2 f of FIG. 2 e , of a portion of semiconductor substrate 100 with support ring 124 and openings 130 partially through base substrate material 102 .
- each opening 130 is formed over one semiconductor die 104 , i.e., the boundaries of the opening align with the boundaries of the semiconductor die.
- openings 130 have a width of 2000 ⁇ m and depth of 65-75 ⁇ m.
- the isotropic etch leaves pillars 132 of base substrate material 102 between openings 130 in an area defining saw streets 106 .
- pillars 132 have a width of 20 ⁇ m.
- a portion of photoresist layer 126 remains over pillars 132 .
- Surface 136 defines the bottom of opening 130 and the new back surface of semiconductor die 104 .
- an electrically conductive layer 134 is formed over the pedestal defined by photoresist layer 126 on pillars 132 and into openings 130 over surface 136 using evaporation, sputtering, PVD, CVD, or other suitable metal deposition process.
- Conductive layer 134 includes one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, TiW, TiNiCu, or other suitable electrically conductive material.
- conductive layer 134 has a thickness of 20-50 ⁇ m or more to provide support for the ultra-thin semiconductor die 104 .
- conductive layer portion 134 a is formed over the pedestal defined by photoresist layer 126 on pillars 132
- conductive layer portion 134 b is formed into openings 130 over surface 136 .
- Photoresist layer 126 on pillars 132 of base substrate material 102 elevates and separates conductive layer portion 134 a with respect to conductive layer portion 134 b in openings 130 .
- conductive layer portion 134 a is removed or lifted-off by dissolving photoresist layer 126 using a solvent spray or bath with ultrasonic action.
- the solvent does not remove conductive layer portion 134 b, which remains over surface 136 of semiconductor die 104 .
- the lift-off of conductive layer portion 134 a can be done with a hard-mask for wet etched openings 130 .
- a portion of pillars 132 of base substrate material 102 may remain between semiconductor die 104 after lift-off of conductive layer portion 134 a.
- the surface level of conductive layer 134 a may be less than or greater than the surface level of pillars 132 .
- the lift-off of conductive layer portion 134 a eliminates the singulation issues of the saw blade cutting through thick metal, as described in the background.
- an edge pattern 138 is an opening formed in photoresist layer 126 around a perimeter of semiconductor substrate 100 .
- a thicker metal is more difficult to lift-off.
- Edge pattern opening 138 provides a break to assist with lift-off of thicker conductive layer 134 a for semiconductor die 104 having side surfaces proximate to the perimeter of semiconductor substrate 100 .
- the continuous break of conductive layer 134 a extends around the perimeter of semiconductor substrate 100 by nature of edge pattern opening 138 .
- semiconductor substrate 100 with backgrinding tape 120 is inverted with back surface 136 and conductive layer portion 134 b oriented toward carrier 140 .
- Semiconductor substrate 100 is mounted to carrier 140 and backgrinding tape 120 is removed.
- Optional support ring 124 can provide additional support of the thinned semiconductor substrate 100 during wafer handling.
- semiconductor substrate 100 is again inverted with active surface 110 and conductive layer 112 oriented toward dicing tape 144 .
- Semiconductor substrate 100 is mounted to dicing tape 144 .
- semiconductor substrate 100 is singulated through saw street 106 and pillars 132 by plasma etching.
- Plasma etching has advantages of forming precision side surfaces along saw streets 106 , while retaining the structure and integrity of the base substrate material.
- semiconductor substrate 100 is singulated through saw street 106 and pillars 132 using a saw blade or laser cutting tool 146 into individual semiconductor die 104 . The singulation occurs without cutting through a thick conductive layer.
- Support ring 124 is also removed during singulation. Support ring 124 could have been removed in FIG. 2 h.
- FIG. 3 shows ultra-thin semiconductor die 104 post singulation.
- semiconductor die 104 has a thickness of 50 ⁇ m, i.e., 25 ⁇ m for base substrate material 102 and conductive layer 112 , and 25 ⁇ m for conductive layer 134 b.
- conductive layer 134 may decrease in thickness and substrate 110 may increase in thickness.
- Conductive layer 112 provides electrical connection for the source region and gate region of the vertical transistor.
- Conductive layer 134 b is formed within openings 130 , while conductive layer 134 a is formed over photoresist layer 126 on pillars 132 . Photoresist layer 126 is removed to lift-off conductive layer portion 134 a.
- Conductive layer 134 b remains on back surface 136 of semiconductor die 104 after the lift-off to provide electrical connection for the drain region of the vertical transistor.
- the lift-off of conductive layer 134 a allows semiconductor substrate 100 to be singulated through saw street 106 and pillars 132 , without the need to cut through a thick metal layer.
- FIGS. 4 a -4 n show a process of forming a plurality of backside openings for an ultra-thin semiconductor die.
- a photoresist layer 150 is formed over back surface 108 b of semiconductor substrate 100 , as shown in FIG. 4 a .
- Photoresist layer 150 is patterned with offset hexagon-shaped openings 152 over back surface 108 b, or alternate opening shapes such as circles, rectangles, lines, or combinations of each. There are many openings 152 for each semiconductor die.
- a plurality of hexagon-shaped openings 160 is formed partially into back surface 108 b but not completely through base substrate material 102 through openings 152 by isotropic etching or non-isotropic etching that is independent of substrate 100 crystal orientation.
- the hexagon-shaped openings 160 are arranged in an offset pattern of multiple rows formed partially into base substrate material 102 within the boundaries of one semiconductor die 104 .
- openings 160 each have a width of 200 ⁇ m or less and depth of 65-75 ⁇ m for a 2 mm by 2 mm semiconductor die 104 .
- Photoresist layer 150 covers any laser mark area of semiconductor substrate 100 to avoid forming opening 160 within the laser mark area.
- FIG. 4 c shows a cross-sectional view, taken along line 4 c - 4 c of FIG. 4 b , of a portion of semiconductor substrate 100 with support ring 124 and openings 160 disposed on carrier or backgrinding tape 162 .
- Support ring 124 can be formed separately or simultaneously as pillars 164 by using photoresist layer 150 .
- a portion of photoresist layer 150 remains over base substrate material 102 between openings 152 to form openings 160 .
- Photoresist layer 150 between openings 152 leaves base substrate material 102 between each opening 160 , i.e., under photoresist layer 150 between adjacent openings 152 .
- Base substrate material 102 has a honeycomb pattern 164 around the offset pattern of openings 160 over back surface 108 b of semiconductor die 104 , see FIG. 4 d .
- the thickness of honeycomb pattern 164 of base substrate material 102 over back surface 108 b of semiconductor die 104 is the thickness of semiconductor substrate 100 , i.e., 90-150 ⁇ m, for structural support of semiconductor die 104 .
- Openings 160 make up the vast majority of the area of semiconductor die 104 ultra-thin for low on-resistance. In other words, the thickness of semiconductor die 104 between active surface 110 and the bottom of each opening 160 is about 20-50 ⁇ m.
- the large number of openings 160 across a surface area of semiconductor die 104 allows the majority of drain current to flow through the ultra-thin base substrate material 102 to achieve the low on-resistance.
- the honeycomb pattern 164 of base substrate material 102 over back surface 108 b of semiconductor die 104 take little area but provides support for the remaining ultra-thin regions of semiconductor die 104 .
- FIG. 4 e shows another embodiment with region 166 of photoresist layer 150 between rows of honeycomb pattern 164 .
- Region 166 of photoresist layer 150 leaves base substrate material 102 between the rows of honeycomb pattern 164 for additional support.
- Other patterns of openings 160 can be formed in base substrate material 102 .
- FIG. 4 f shows regions 168 of photoresist layer 150 disposed interstitially within honeycomb pattern 164 .
- Regions 168 of photoresist layer 150 leave larger regions of base substrate material 102 disposed interstitially within honeycomb pattern 164 for additional support.
- Openings 160 in honeycomb pattern 164 still occupy the majority of the area of semiconductor die 104 ultra-thin for low on-resistance.
- the large number of openings 160 across a surface area of semiconductor die 104 allows the majority of drain current to flow through the ultra-thin base substrate material 102 to achieve the low on-resistance.
- the honeycomb pattern 164 of base substrate material 102 over back surface 108 b of semiconductor die 104 take a small portion of the area but provides support for the remaining ultra-thin regions of semiconductor die 104 .
- FIG. 4 g shows another embodiment with a high aspect ratio semiconductor die 104 offset on semiconductor substrate 100 .
- the length of semiconductor die 104 is greater than its width.
- the boundaries of the offset pattern of hexagon-shaped openings 160 align with the boundaries of semiconductor die 104 .
- the offset pattern of openings 160 leaves base substrate material 102 between each opening 160 , i.e., under photoresist layer 150 between adjacent openings 152 .
- Base substrate material 102 has a honeycomb pattern 170 around the offset pattern of openings 160 over back surface 108 b of semiconductor die 104 . Openings 160 make the vast majority of the area of semiconductor die 104 ultra-thin for low on-resistance.
- Honeycomb pattern 170 of base substrate material 102 over back surface 108 b of semiconductor die 104 take little area but provides support for remaining ultra-thin regions of semiconductor die 104 .
- the remaining photoresist layer 150 between semiconductor die 104 leaves additional base substrate material 102 to provide additional support.
- FIG. 4 h shows yet another embodiment with a high aspect ratio semiconductor die 104 offset on semiconductor substrate 100 .
- the boundaries of the offset pattern of hexagon-shaped openings 160 align with the boundaries of semiconductor die 104 .
- the offset pattern of openings 160 leaves base substrate material 102 between each opening 160 , i.e., under photoresist layer 150 between adjacent openings 152 .
- Base substrate material 102 has a honeycomb pattern 176 around the offset pattern of openings 160 over back surface 108 b of semiconductor die 104 . Openings 160 make the vast majority of the area of semiconductor die 104 ultra-thin for low on-resistance.
- Honeycomb pattern 176 of base substrate material 102 over back surface 108 b of semiconductor die 104 take little area but provides support for remaining ultra-thin regions of semiconductor die 104 .
- the remaining photoresist layer 150 between semiconductor die 104 leaves additional base substrate material 102 to provide additional support and can act as a solder dam to control solder movement.
- Additional base substrate material separate from the honeycomb structures, can be retained interior to the die for additional structural support.
- photoresist layer 150 is removed and an electrically conductive layer 180 is formed over honeycomb pattern 164 of base substrate material 102 and into openings 160 using evaporation, sputtering, PVD, CVD, or other suitable metal deposition process, as shown in FIG. 4 i .
- FIG. 4 j shows a plan view of conductive layer 180 formed over honeycomb pattern 164 of base substrate material 102 and into openings 160 .
- FIG. 4 k shows adjacent openings 160 in honeycomb pattern 164 of base substrate material 102 covered by conductive layer 180 , including the top surface, side surfaces, and bottom surface of the structure.
- Conductive layer 180 includes one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, TiW, TiNiCu, TiNiAg, or other suitable electrically conductive material. Conductive layer 180 provides electrical connection for the drain region of the vertical transistor. Conductive layer 180 is made relatively thin, e.g., 0.5-1.5 ⁇ m or less, because the primary support for the ultra-thin semiconductor die 104 is realized with honeycomb pattern 164 of base substrate material 102 .
- support ring 124 may be removed by a saw blade or laser cutting tool 184 .
- semiconductor substrate 100 with backgrinding tape 120 is inverted with back surface 108 b and conductive layer 180 oriented toward dicing tape 186 .
- Semiconductor substrate 100 is mounted to dicing tape 186 .
- Backgrinding tape 162 is removed.
- semiconductor substrate 100 is singulated through saw street 106 by plasma etching.
- Plasma etching has advantages of forming precision side surfaces along saw streets 106 , while retaining the structure and integrity of the base substrate material.
- semiconductor substrate 100 is singulated through saw street 106 using a saw blade or laser cutting tool 188 into individual semiconductor die 104 .
- Plasma etch or saw blade 188 easily cuts or breaks through the relatively thin conductive layer 180 .
- Honeycomb patterns 170 and 176 of base substrate material 102 for offset semiconductor die 104 in FIGS. 4 g -4 h would follow the same process of FIGS. 4 i - 4 n.
- FIG. 5 shows semiconductor die 104 post singulation.
- Conductive layer 112 provides electrical connection for the source region and gate region of the vertical transistor.
- Honeycomb pattern 164 of base substrate material 102 provides structural support for semiconductor die 104 .
- Conductive layer 180 provides electrical connection for the drain region of the vertical transistor.
- Semiconductor die 104 with honeycomb pattern 164 is robust during die handling, while retaining a low on-resistance through the ultra-thin portions of the die.
- the relatively thin conductive layer 180 can be easily cut or broken by plasma etch or saw blade without the singulation issues encountered by the thick metal layer.
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Abstract
Description
- The present application is a continuation application of the earlier U.S. Patent Application to Gordon Grivna, entitled “Semiconductor Device and Method of Forming Backside Openings for an Ultra-thin Semiconductor Die,” application Ser. No. 16/035,838, filed Jul. 16, 2018, now pending; which application is a division of the U.S. Patent Application to Gordon Grivna, entitled “Semiconductor Device and Method of Forming Backside Openings for an Ultra-thin Semiconductor Die,” application Ser. No. 15/452,888, filed Mar. 8, 2017, now U.S. Pat. No. 10,074,611, issued Sep. 11, 2018, the disclosures of each of which are hereby incorporated entirely herein by reference.
- The present disclosure relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming backside openings for an ultra-thin semiconductor die.
- A semiconductor wafer or substrate can be made with a variety of base substrate materials, such as silicon (Si), germanium, aluminum phosphide, aluminum arsenide, gallium arsenide (GaAs), gallium nitride (GaN), aluminum gallium nitride over gallium nitride (AlGaN/GaN), indium phosphide, silicon carbide (SiC), or other bulk material for structural support. A plurality of semiconductor die is formed on the wafer separated by a non-active, inter-die substrate area or saw street. The saw street provides cutting areas to singulate the semiconductor wafer into individual semiconductor die.
- In a vertical semiconductor device, the primary current path is vertical from the top surface of the die to a back surface of the die. The vertical resistance, e.g., drain-source resistance (RDSON) of a vertical transistor, decreases with the thickness of the semiconductor die. To minimize vertical resistance, the semiconductor die should be as thin as possible while still maintaining structural integrity. An opening can be formed in the back surface to reduce thickness of the semiconductor die and vertical resistance. A thick metal layer, such as 25 micrometers (μm) copper, is formed across the back surface and into the opening for structural support and electrical interconnect. Unfortunately, cutting through the thick metal layer within the saw street to separate the semiconductor die can be difficult and impose premature wear and excessive cutting debris on the saw blade.
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FIGS. 1a-1b illustrate a semiconductor substrate with a plurality of semiconductor die separated by a saw street; -
FIGS. 2a-2l illustrate a process of forming a backside opening to enable lift-off of a backside metal; -
FIG. 3 illustrates the semiconductor die ofFIGS. 2a-2l post singulation; -
FIGS. 4a-4n illustrate a process of forming honeycomb pattern of base substrate material for support of ultra-thin semiconductor die; and -
FIG. 5 illustrates the semiconductor die ofFIGS. 4a-4n post singulation. - The following describes one or more embodiments with reference to the figures, in which like numerals represent the same or similar elements. While the figures are described in terms of the best mode for achieving certain objectives, the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
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FIG. 1a shows a semiconductor wafer orsubstrate 100 with abase substrate material 102, such as Si, germanium, aluminum phosphide, aluminum arsenide, GaAs, GaN, AlGaN/GaN, indium phosphide, SiC, or other bulk material for structural support.Semiconductor substrate 100 has a width or diameter of 100-450 millimeters (mm) and thickness of about 700-800 micrometers (μm). A plurality of semiconductor die 104 is formed onsubstrate 100 separated by a non-active, inter-die substrate area or sawstreet 106.Saw street 106 provides cutting areas tosingulate semiconductor substrate 100 into individual semiconductor die 104. -
FIG. 1b shows a cross-sectional view of a portion ofsemiconductor substrate 100. Each semiconductor die 104 includes aback surface 108 and active surface orregion 110 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface orregion 110 to implement analog circuits or digital circuits. In one embodiment, semiconductor die 104 implements a diode, transistor, or other discrete semiconductor device. In a vertical transistor, the gate region and source region are typically accessible onactive surface 110, and the drain region of the vertical transistor is backsurface 108. Semiconductor die 104 may also contain a digital signal processor (DSP), microcontroller, ASIC, standard logic, amplifiers, clock management, memory, interface circuit, optoelectronics, and other signal processing circuits. Semiconductor die 104 may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. - An electrically
conductive layer 112 is formed overactive surface 110 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process.Conductive layer 112 includes one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium tungsten (TiW), TiNiCu, TiNiAg, or other suitable electrically conductive material.Conductive layer 112 operates as contact pads electrically connected to the circuits, e.g., gate region and source region of the vertical transistor, onactive surface 110. -
FIGS. 2a-2l show a process of forming a backside opening to achieve an ultra-thin semiconductor die and enable lift-off of a backside metal without singulation through the backside metal. InFIG. 2a ,semiconductor substrate 100 is positioned withactive surface 110 oriented toward carrier orbackgrinding tape 120. InFIG. 2b , an interior region ofback surface 108 a ofsemiconductor substrate 100 is thinned withgrinding wheel 122, leaving athick support ring 124 around a perimeter of the semiconductor substrate.FIG. 2c illustrates backsurface 108 b, after thinning, ofsemiconductor substrate 100 withoptional support ring 124 for structural support. In one embodiment,semiconductor wafer 100 has a thickness of 90-150 μm betweenactive surface 110 andback surface 108 b. - In
FIG. 2d ,photoresist layer 126 is formed overback surface 108 b ofsemiconductor substrate 100.Photoresist layer 126 is patterned withopenings 128 overback surface 108 b. There is oneopening 128 aligned with each semiconductor die 104. - In
FIG. 2e , a plurality ofopenings 130 is formed partially intoback surface 108 b but not completely throughbase substrate material 102 throughopenings 128 by isotropic etching, non-isotropic etching, or laser direct ablation (LDA).Photoresist layer 126 covers any laser mark area ofsemiconductor substrate 100 to avoid formingopening 130 within the laser mark area. -
FIG. 2f shows a cross-sectional view, taken alongline 2 f-2 f ofFIG. 2e , of a portion ofsemiconductor substrate 100 withsupport ring 124 andopenings 130 partially throughbase substrate material 102. In particular, eachopening 130 is formed over one semiconductor die 104, i.e., the boundaries of the opening align with the boundaries of the semiconductor die. In one embodiment,openings 130 have a width of 2000 μm and depth of 65-75 μm. The isotropic etch leavespillars 132 ofbase substrate material 102 betweenopenings 130 in an area defining sawstreets 106. In one embodiment,pillars 132 have a width of 20 μm. A portion ofphotoresist layer 126 remains overpillars 132.Surface 136 defines the bottom ofopening 130 and the new back surface of semiconductor die 104. - In
FIG. 2g , an electrically conductive layer 134 is formed over the pedestal defined byphotoresist layer 126 onpillars 132 and intoopenings 130 oversurface 136 using evaporation, sputtering, PVD, CVD, or other suitable metal deposition process. Conductive layer 134 includes one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, TiW, TiNiCu, or other suitable electrically conductive material. In one embodiment, conductive layer 134 has a thickness of 20-50 μm or more to provide support for the ultra-thin semiconductor die 104. In particular,conductive layer portion 134 a is formed over the pedestal defined byphotoresist layer 126 onpillars 132, andconductive layer portion 134 b is formed intoopenings 130 oversurface 136.Photoresist layer 126 onpillars 132 ofbase substrate material 102 elevates and separatesconductive layer portion 134 a with respect toconductive layer portion 134 b inopenings 130. - In
FIG. 2h ,conductive layer portion 134 a is removed or lifted-off by dissolvingphotoresist layer 126 using a solvent spray or bath with ultrasonic action. The solvent does not removeconductive layer portion 134 b, which remains oversurface 136 of semiconductor die 104. Alternatively, the lift-off ofconductive layer portion 134 a can be done with a hard-mask for wetetched openings 130. A portion ofpillars 132 ofbase substrate material 102 may remain between semiconductor die 104 after lift-off ofconductive layer portion 134 a. The surface level ofconductive layer 134 a may be less than or greater than the surface level ofpillars 132. The lift-off ofconductive layer portion 134 a eliminates the singulation issues of the saw blade cutting through thick metal, as described in the background. - In
FIG. 2i , anedge pattern 138 is an opening formed inphotoresist layer 126 around a perimeter ofsemiconductor substrate 100. A thicker metal is more difficult to lift-off. Edge pattern opening 138 provides a break to assist with lift-off of thickerconductive layer 134 a for semiconductor die 104 having side surfaces proximate to the perimeter ofsemiconductor substrate 100. The continuous break ofconductive layer 134 a extends around the perimeter ofsemiconductor substrate 100 by nature of edge pattern opening 138. - In
FIG. 2j ,semiconductor substrate 100 withbackgrinding tape 120 is inverted withback surface 136 andconductive layer portion 134 b oriented towardcarrier 140.Semiconductor substrate 100 is mounted tocarrier 140 andbackgrinding tape 120 is removed.Optional support ring 124 can provide additional support of the thinnedsemiconductor substrate 100 during wafer handling. - In
FIG. 2k ,semiconductor substrate 100 is again inverted withactive surface 110 andconductive layer 112 oriented toward dicingtape 144.Semiconductor substrate 100 is mounted to dicingtape 144. - In
FIG. 2 l,semiconductor substrate 100 is singulated throughsaw street 106 andpillars 132 by plasma etching. Plasma etching has advantages of forming precision side surfaces along sawstreets 106, while retaining the structure and integrity of the base substrate material. Alternatively,semiconductor substrate 100 is singulated throughsaw street 106 andpillars 132 using a saw blade orlaser cutting tool 146 into individual semiconductor die 104. The singulation occurs without cutting through a thick conductive layer.Support ring 124 is also removed during singulation.Support ring 124 could have been removed inFIG. 2 h. -
FIG. 3 shows ultra-thin semiconductor die 104 post singulation. In one embodiment, semiconductor die 104 has a thickness of 50 μm, i.e., 25 μm forbase substrate material 102 andconductive layer 112, and 25 μm forconductive layer 134 b. In some embodiments toward the edge of thedie 104, conductive layer 134 may decrease in thickness andsubstrate 110 may increase in thickness.Conductive layer 112 provides electrical connection for the source region and gate region of the vertical transistor.Conductive layer 134 b is formed withinopenings 130, whileconductive layer 134 a is formed overphotoresist layer 126 onpillars 132.Photoresist layer 126 is removed to lift-offconductive layer portion 134 a.Conductive layer 134 b remains onback surface 136 of semiconductor die 104 after the lift-off to provide electrical connection for the drain region of the vertical transistor. The lift-off ofconductive layer 134 a allowssemiconductor substrate 100 to be singulated throughsaw street 106 andpillars 132, without the need to cut through a thick metal layer. -
FIGS. 4a-4n show a process of forming a plurality of backside openings for an ultra-thin semiconductor die. Continuing fromFIG. 2c , aphotoresist layer 150 is formed overback surface 108 b ofsemiconductor substrate 100, as shown inFIG. 4a .Photoresist layer 150 is patterned with offset hexagon-shapedopenings 152 overback surface 108 b, or alternate opening shapes such as circles, rectangles, lines, or combinations of each. There aremany openings 152 for each semiconductor die. - In
FIG. 4b , a plurality of hexagon-shapedopenings 160 is formed partially intoback surface 108 b but not completely throughbase substrate material 102 throughopenings 152 by isotropic etching or non-isotropic etching that is independent ofsubstrate 100 crystal orientation. The hexagon-shapedopenings 160 are arranged in an offset pattern of multiple rows formed partially intobase substrate material 102 within the boundaries of one semiconductor die 104. In one embodiment,openings 160 each have a width of 200 μm or less and depth of 65-75 μm for a 2 mm by 2 mm semiconductor die 104.Photoresist layer 150 covers any laser mark area ofsemiconductor substrate 100 to avoid formingopening 160 within the laser mark area. -
FIG. 4c shows a cross-sectional view, taken alongline 4 c-4 c ofFIG. 4b , of a portion ofsemiconductor substrate 100 withsupport ring 124 andopenings 160 disposed on carrier orbackgrinding tape 162.Support ring 124 can be formed separately or simultaneously aspillars 164 by usingphotoresist layer 150. A portion ofphotoresist layer 150 remains overbase substrate material 102 betweenopenings 152 to formopenings 160.Photoresist layer 150 betweenopenings 152 leavesbase substrate material 102 between each opening 160, i.e., underphotoresist layer 150 betweenadjacent openings 152.Base substrate material 102 has ahoneycomb pattern 164 around the offset pattern ofopenings 160 overback surface 108 b of semiconductor die 104, seeFIG. 4d . The thickness ofhoneycomb pattern 164 ofbase substrate material 102 overback surface 108 b of semiconductor die 104 is the thickness ofsemiconductor substrate 100, i.e., 90-150 μm, for structural support of semiconductor die 104.Openings 160 make up the vast majority of the area of semiconductor die 104 ultra-thin for low on-resistance. In other words, the thickness of semiconductor die 104 betweenactive surface 110 and the bottom of eachopening 160 is about 20-50 μm. The large number ofopenings 160 across a surface area of semiconductor die 104 allows the majority of drain current to flow through the ultra-thinbase substrate material 102 to achieve the low on-resistance. Thehoneycomb pattern 164 ofbase substrate material 102 overback surface 108 b of semiconductor die 104 take little area but provides support for the remaining ultra-thin regions of semiconductor die 104. -
FIG. 4e shows another embodiment with region 166 ofphotoresist layer 150 between rows ofhoneycomb pattern 164. Region 166 ofphotoresist layer 150 leavesbase substrate material 102 between the rows ofhoneycomb pattern 164 for additional support. Other patterns ofopenings 160 can be formed inbase substrate material 102. For example, there can bebase substrate material 102 between columns ofhoneycomb pattern 164 for additional support.FIG. 4f showsregions 168 ofphotoresist layer 150 disposed interstitially withinhoneycomb pattern 164.Regions 168 ofphotoresist layer 150 leave larger regions ofbase substrate material 102 disposed interstitially withinhoneycomb pattern 164 for additional support.Openings 160 inhoneycomb pattern 164 still occupy the majority of the area of semiconductor die 104 ultra-thin for low on-resistance. The large number ofopenings 160 across a surface area of semiconductor die 104 allows the majority of drain current to flow through the ultra-thinbase substrate material 102 to achieve the low on-resistance. Thehoneycomb pattern 164 ofbase substrate material 102 overback surface 108 b of semiconductor die 104 take a small portion of the area but provides support for the remaining ultra-thin regions of semiconductor die 104. -
FIG. 4g shows another embodiment with a high aspect ratio semiconductor die 104 offset onsemiconductor substrate 100. In this case, the length of semiconductor die 104 is greater than its width. The boundaries of the offset pattern of hexagon-shapedopenings 160 align with the boundaries of semiconductor die 104. The offset pattern ofopenings 160 leavesbase substrate material 102 between each opening 160, i.e., underphotoresist layer 150 betweenadjacent openings 152.Base substrate material 102 has ahoneycomb pattern 170 around the offset pattern ofopenings 160 overback surface 108 b of semiconductor die 104.Openings 160 make the vast majority of the area of semiconductor die 104 ultra-thin for low on-resistance.Honeycomb pattern 170 ofbase substrate material 102 overback surface 108 b of semiconductor die 104 take little area but provides support for remaining ultra-thin regions of semiconductor die 104. The remainingphotoresist layer 150 between semiconductor die 104 leaves additionalbase substrate material 102 to provide additional support. -
FIG. 4h shows yet another embodiment with a high aspect ratio semiconductor die 104 offset onsemiconductor substrate 100. The boundaries of the offset pattern of hexagon-shapedopenings 160 align with the boundaries of semiconductor die 104. The offset pattern ofopenings 160 leavesbase substrate material 102 between each opening 160, i.e., underphotoresist layer 150 betweenadjacent openings 152.Base substrate material 102 has ahoneycomb pattern 176 around the offset pattern ofopenings 160 overback surface 108 b of semiconductor die 104.Openings 160 make the vast majority of the area of semiconductor die 104 ultra-thin for low on-resistance.Honeycomb pattern 176 ofbase substrate material 102 overback surface 108 b of semiconductor die 104 take little area but provides support for remaining ultra-thin regions of semiconductor die 104. The remainingphotoresist layer 150 between semiconductor die 104 leaves additionalbase substrate material 102 to provide additional support and can act as a solder dam to control solder movement. Additional base substrate material separate from the honeycomb structures, can be retained interior to the die for additional structural support. - Returning to
FIG. 4d ,photoresist layer 150 is removed and an electricallyconductive layer 180 is formed overhoneycomb pattern 164 ofbase substrate material 102 and intoopenings 160 using evaporation, sputtering, PVD, CVD, or other suitable metal deposition process, as shown inFIG. 4i .FIG. 4j shows a plan view ofconductive layer 180 formed overhoneycomb pattern 164 ofbase substrate material 102 and intoopenings 160.FIG. 4k showsadjacent openings 160 inhoneycomb pattern 164 ofbase substrate material 102 covered byconductive layer 180, including the top surface, side surfaces, and bottom surface of the structure.Conductive layer 180 includes one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, TiW, TiNiCu, TiNiAg, or other suitable electrically conductive material.Conductive layer 180 provides electrical connection for the drain region of the vertical transistor.Conductive layer 180 is made relatively thin, e.g., 0.5-1.5 μm or less, because the primary support for the ultra-thin semiconductor die 104 is realized withhoneycomb pattern 164 ofbase substrate material 102. - In
FIG. 4 l,support ring 124 may be removed by a saw blade orlaser cutting tool 184. - In
FIG. 4m ,semiconductor substrate 100 withbackgrinding tape 120 is inverted withback surface 108 b andconductive layer 180 oriented toward dicingtape 186.Semiconductor substrate 100 is mounted to dicingtape 186.Backgrinding tape 162 is removed. - In
FIG. 4n ,semiconductor substrate 100 is singulated throughsaw street 106 by plasma etching. Plasma etching has advantages of forming precision side surfaces along sawstreets 106, while retaining the structure and integrity of the base substrate material. Alternatively,semiconductor substrate 100 is singulated throughsaw street 106 using a saw blade orlaser cutting tool 188 into individual semiconductor die 104. Plasma etch or sawblade 188 easily cuts or breaks through the relatively thinconductive layer 180.Honeycomb patterns base substrate material 102 for offset semiconductor die 104 inFIGS. 4g-4h would follow the same process ofFIGS. 4i -4 n. -
FIG. 5 shows semiconductor die 104 post singulation.Conductive layer 112 provides electrical connection for the source region and gate region of the vertical transistor.Honeycomb pattern 164 ofbase substrate material 102 provides structural support for semiconductor die 104.Conductive layer 180 provides electrical connection for the drain region of the vertical transistor. Semiconductor die 104 withhoneycomb pattern 164 is robust during die handling, while retaining a low on-resistance through the ultra-thin portions of the die. The relatively thinconductive layer 180 can be easily cut or broken by plasma etch or saw blade without the singulation issues encountered by the thick metal layer. - While one or more embodiments have been illustrated and described in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present disclosure.
Claims (20)
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US15/452,888 US10074611B1 (en) | 2017-03-08 | 2017-03-08 | Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die |
US16/035,838 US10727188B2 (en) | 2017-03-08 | 2018-07-16 | Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die |
US16/907,520 US20200321291A1 (en) | 2017-03-08 | 2020-06-22 | Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die |
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US16/035,838 Active US10727188B2 (en) | 2017-03-08 | 2018-07-16 | Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die |
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US10811298B2 (en) * | 2018-12-31 | 2020-10-20 | Micron Technology, Inc. | Patterned carrier wafers and methods of making and using the same |
US20200321236A1 (en) * | 2019-04-02 | 2020-10-08 | Semiconductor Components Industries, Llc | Edge ring removal methods |
US20210013176A1 (en) * | 2019-07-09 | 2021-01-14 | Semiconductor Components Industries, Llc | Pre-stacking mechanical strength enhancement of power device structures |
US20210296176A1 (en) * | 2020-03-23 | 2021-09-23 | Semiconductor Components Industries, Llc | Structure and method for electronic die singulation using alignment structures and multi-step singulation |
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US4191788A (en) * | 1978-11-13 | 1980-03-04 | Trw Inc. | Method to reduce breakage of V-grooved <100> silicon substrate |
US6087199A (en) * | 1998-02-04 | 2000-07-11 | International Business Machines Corporation | Method for fabricating a very dense chip package |
US6033489A (en) | 1998-05-29 | 2000-03-07 | Fairchild Semiconductor Corp. | Semiconductor substrate and method of making same |
US20070042549A1 (en) | 2000-04-17 | 2007-02-22 | Fairchild Semiconductor Corporation | Semiconductor device having reduced effective substrate resistivity and associated methods |
US7198988B1 (en) | 2005-11-16 | 2007-04-03 | Emcore Corporation | Method for eliminating backside metal peeling during die separation |
US7951688B2 (en) | 2007-10-01 | 2011-05-31 | Fairchild Semiconductor Corporation | Method and structure for dividing a substrate into individual devices |
US8158506B2 (en) | 2008-05-05 | 2012-04-17 | Fairchild Semiconductor Corporation | Methods and designs for localized wafer thinning |
US8685774B2 (en) * | 2011-12-27 | 2014-04-01 | Sharp Laboratories Of America, Inc. | Method for fabricating three-dimensional gallium nitride structures with planar surfaces |
US9818837B2 (en) | 2014-12-10 | 2017-11-14 | Semiconductor Components Industries, Llc | Process of forming an electronic device having an electronic component |
US10163859B2 (en) * | 2015-10-21 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method for chip package |
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