US20200266718A1 - Flyback converter with edge-based isolated communication - Google Patents
Flyback converter with edge-based isolated communication Download PDFInfo
- Publication number
- US20200266718A1 US20200266718A1 US16/276,475 US201916276475A US2020266718A1 US 20200266718 A1 US20200266718 A1 US 20200266718A1 US 201916276475 A US201916276475 A US 201916276475A US 2020266718 A1 US2020266718 A1 US 2020266718A1
- Authority
- US
- United States
- Prior art keywords
- signal
- receiver
- responsive
- switch transistor
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004891 communication Methods 0.000 title abstract description 9
- 239000003990 capacitor Substances 0.000 claims abstract description 29
- 230000000295 complement effect Effects 0.000 claims abstract description 13
- 230000008859 change Effects 0.000 claims description 22
- 238000001514 detection method Methods 0.000 claims description 21
- 230000001360 synchronised effect Effects 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 9
- 238000004804 winding Methods 0.000 claims description 9
- 230000001351 cycling effect Effects 0.000 claims description 5
- 238000001914 filtration Methods 0.000 claims description 3
- 230000003139 buffering effect Effects 0.000 claims 1
- 230000004044 response Effects 0.000 description 12
- 230000000630 rising effect Effects 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 230000036039 immunity Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 230000001960 triggered effect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
- H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- This application relates to flyback converters, and more particularly to a flyback converter with edge-based communication through a ground-isolating channel.
- a flyback switching power converter is typically provided with a mobile device for battery charging as its transformer provides safe isolation from AC household current.
- This isolation introduces a problem in that the power switching may be controlled by a primary-side controller that in turn needs to coordinate a cycling of a synchronous rectifier transistor on the secondary side.
- the primary-side controller cannot directly control the synchronous rectifier transistor through a wire or lead because the ground isolation is then broken.
- An analogous problem occurs for a secondary-side controller that must control the power switch transistor.
- a digital isolator uses a high-frequency carrier signal to modulate a gate driver signal at the transmitting side.
- the carrier signal may be one GHz or higher in frequency, having a pulse width distortion of less than 10 ns and a common-mode transient immunity of 50V/ns.
- a digital isolator typically requires a low-pass filter and a relatively-fast comparator.
- Such digital isolators are expensive and over-qualified for typical flyback converter application in which common-mode transient immunity is normally less then 1v/ns and the pulse-width distortion is larger than 50 ns.
- a flyback converter includes a ground-isolating communication channel over which a pulsed signal may be exchanged between the primary and secondary sides of the flyback converter's transformer.
- the transmitter of the pulsed signal may be located on either the primary or secondary side of the transformer.
- the receiver would be opposite side of the transformer from the receiver.
- the ground-isolating communication channel includes a positive capacitor and a negative capacitor.
- the transmitter drives a pulsed transmitter signal into a transmitter terminal of the positive capacitor.
- the transmitter inverts the pulsed transmitter signal to form a complement transmitter signal that is driven into a transmitter terminal of the negative capacitor.
- the receiver couples to a receiving terminal for the both capacitors to receive the transmitter signal and the complement transmitter signal.
- the receiver high-pass filters the received transmitter signal to form a positive filtered signal.
- the receiver high-pass filters the received complement transmitter signal to form a negative filtered signal.
- a difference between the positive filtered signal and the negative filtered signal forms an edge-triggering signal that is pulsed temporarily to a positive voltage in response to a rising edge for the transmitter signal and that is pulsed temporality to a negative voltage in response to a falling edge for the transmitter signal.
- the receiver To generate a received signal that is pulsed in common with the transmitter signal, the receiver includes a comparator that compares the positive filtered signal to the negative filtered signal so as to respond to the edge-triggering signal.
- the comparator may include hysteresis such that the comparator does not assert the receive signal to a power supply voltage until the edge-triggering signal voltage exceeds a positive threshold value.
- the comparator grounds the receiver signal when the edge-triggering signal voltage is below a negative threshold value.
- FIG. 1 illustrates a flyback converter including a ground-isolating channel for the transmission of an edge-triggering signal in accordance with an aspect of the disclosure.
- FIG. 2 illustrates an example transmitter for the transmission of the edge-triggering signal and an example receiver for receiving the edge-triggering signal in accordance with an aspect of the disclosure.
- FIG. 3 illustrates some waveforms for the transmitter and receiver of FIG. 2 .
- FIG. 4 illustrates a transmitter and receiver for an edge-triggering signal in which the receiver includes a detection circuit for forcing the receiver signal low in response to a rate of change for a common-mode noise exceeding a threshold value in accordance with an aspect of the disclosure.
- FIG. 5 illustrates some waveforms for the transmitter and receiver of FIG. 4 .
- FIG. 6 illustrates a transmitter and receiver for an edge-triggering signal in which the receiver includes a detection circuit for forcing the receiver signal high in response to a rate of change for a common-mode noise exceeding a threshold value in accordance with an aspect of the disclosure.
- FIG. 7 illustrate some waveforms for the transmitter and receiver of FIG. 6 .
- a flyback converter is provided with an isolated communication channel that propagates an edge-triggered gate control signal.
- a transmitter pulses a transmitter signal (TX) to control a transistor switch on the receiving side of the channel.
- TX transmitter signal
- the transmitter signal is either ground or a power supply voltage.
- the transmitter also generates a complement transmitter signal that is the complement of the transmitter signal.
- the complement transmitter signal will thus equal the power supply voltage while the transmitter signal is grounded and will be grounded while the transmitter signal is charged to the power supply voltage.
- the channel includes a positive blocking capacitor over which the transmitter drives the positive signal.
- the channel includes a negative blocking capacitor over which the transmitter drives the negative signal.
- the positive and negative blocking capacitors block any DC signal transmission from the transmitter to a receiver at a receiving-end of the channel.
- a receiving-end terminal for the positive blocking capacitor is coupled to a first resistor to form a first high-pass filter that filters the positive signal to form a filtered positive signal (Vp).
- a receiving-end terminal for the negative blocking capacitor is coupled to a second resistor to form a second high-pass filter that filters the negative signal to form a filtered negative signal (Vn). Due to the high-pass filtering, a difference of the filtered voltages (Vp ⁇ Vn) will have a relatively-narrow positive voltage pulse in response to a rising edge for the positive signal and then return to zero volts.
- the difference of the filtered voltages will have a relatively-narrow negative voltage pulse in response to the falling edge for the positive signal and then return to zero volts.
- the difference signal (Vp ⁇ Vn) may thus be denoted as an edge-triggering signal.
- a comparator with hysteresis may compare the filtered positive signal Vp to the filtered negative signal Vn to respond to edge-triggering signal.
- a receiver output (RX) signal from the comparator may then be used to control the gate voltage of a switch transistor. Should the transmission be from the secondary side of the transformer to the primary side, the controlled switch transistor may be the power switch transistor. Conversely, if the transmission is from the primary side of the transformer to the secondary side, the controlled switch transistor may be a synchronous rectifier switch transistor.
- FIG. 1 An example flyback converter 100 that includes an edge-triggered isolating communication channel is shown in FIG. 1 .
- Flyback converter 100 includes a transformer T 1 having a primary winding 105 and a secondary winding 110 .
- a power switch transistor S 1 controls whether a magnetizing current flows through primary winding 105 .
- an input voltage Vin causes the magnetizing current to increase until power switch transistor S 1 shuts off.
- a synchronous rectifier (SR) switch transistor S 2 prevents a secondary current from flowing in secondary winding 110 .
- SR switch transistor S 2 switches on to allow the secondary current to charge an output voltage Vout and deliver power to a load (not illustrated).
- the control of power switch transistor S 1 or of SR switch transistor S 2 may be advantageously accomplished through an edge-triggering signaling conducted through a ground-isolating channel 125 formed by a positive capacitor Cp and a negative capacitor Cn.
- a primary side controller (not illustrated) controls the cycling of power switch transistor S 1 .
- the controller may trigger SR switch transistor S 2 to turn on by transmitting an edge-triggering signal from a transmitter 115 through channel 125 to a receiver 120 .
- receiver 120 controls a gate voltage of SR switch transistor S 2 accordingly.
- a secondary-side controller (not illustrated) controls the cycling of power switch transistor S 1 as well as the cycling of SR switch transistor S 2 .
- receiver 120 instead as a transmitter of the edge-triggering signal through channel 125 such that transmitter 115 acts as a receiver to control a gate voltage of power switch S 1 responsive to the edge-triggering signal.
- Transmitter 115 and receiver 120 may be implemented as shown in FIG. 2 .
- Transmitter 115 includes a buffer 205 for driving the transmitter signal TX into a terminal of positive capacitor Cp.
- transmitter 115 includes an inverter for inverting the transmitter signal to form the complement transmitter signal and for driving the complement transmitter signal into a terminal of negative capacitor Cn.
- a receiving-end terminal for positive capacitor Cp is coupled to a resistor Rp to form the first high-pass filter that filters the transmitter signal TX to form the filtered positive signal (Vp).
- a receiving-end terminal for negative capacitor Cn is coupled to a resistor Rn to form the second high-pass filter that filters the complement transmitter signal to form the filtered negative signal (Vn).
- Resistors Rn and Rp are coupled in series across the receiving end terminals of capacitors Cp and Cn.
- a comparator 215 with hysteresis may compare the filtered positive signal Vp to the filtered negative signal Vn to respond to the edge-triggering signal (Vp ⁇ Vn) to produce the receiver signal RX.
- a zener diode Z 1 clamps the filtered negative signal whereas a zener diode Z 2 clamps the filtered positive signal.
- receiver 120 is symmetric with regard to a node 220 between resistors Rn and Rp. Such symmetry ensures that comparator 215 will be immune to static levels of common-mode noise that affects the filtered signals Vp and Vn.
- Some waveforms for the transmitter signal TX, the receiver signal RX, and the edge-triggering signal (Vp ⁇ Vn) are shown in FIG. 3 .
- the transmitter signal TX pulses high to cause the edge-triggering signal to have a transient positive pulse.
- the receiver signal RX is driven high to the power supply voltage at time t 0 .
- the pulse for the transmitter signal TX ends at a time t 1 , which cause the edge-triggering signal to have a transient negative pulse.
- the pulse for the receiver signal RX ends at time t 1 .
- the pulsing of the transmitter signal TX is thus duplicated by the pulsing of the receiver signal RX.
- the transmitter signal TX again pulses high.
- a common-mode noise for both the positive filtered signal Vp and the negative filtered signal Vn increases at time t 2 , which forces the edge-triggered signal to remain at ground at time t 2 .
- the receiver signal RX thus does not pulse high at time t 2 despite the pulsing of the transmitter signal TX.
- the second pulse for the transmitter signal TX ends at time t 3 during which the common-mode noise remains high.
- the common-mode noise is high, it is static at time t 3 such that the edge-triggering signal responds to the falling edge for the transmitter signal TX and is thus pulsed low at time t 3 .
- the impedance symmetry in receiver 120 to node 220 ensures this immunity to static common-mode noise.
- a reference circuit may maintain node 220 at a reference voltage such as one-half the power supply voltage.
- a third pulse for the transmitter signal TX begins at a time t 4 . Since the common-mode noise is static although still high, the receiver signal RX is also pulsed high at time t 4 . The third pulse for the transmitter signal TX ends at a time t 5 but the common-mode node changes to a low state at time t 4 as well. The change in the common-mode noise causes the receiver signal RX to not respond to the falling edger for the transmitter signal at time t 5 .
- a fourth pulse for the transmitter signal TX begins at a time t 6 but the receiver signal RX was already pulsed high at time t 4 . The fourth pulse for the transmitter signal ends at a time t 7 , which also ends the pulse for the receiver signal RX.
- the common-mode noise changes cause the receiver signal ILX to miss a rising edge at times t 2 and t 6 and miss a falling edge at times t 3 and t 5 . Should the receiver signal RX control the SR switch transistor, the missing falling edges may result in converter failure. Moreover, a very large rate of change for the common-mode noise may result in a false spike for the edge-triggering signal and improperly pulse the receiver signal RX. Such improper pulsing of the receiver signal RX may also result in converter failure.
- the common-mode noise may be monitored by a clamping and detection circuit 400 as shown in FIG. 4 for a receiver 405 .
- Transmitter 115 , capacitors Cn and Cp, resistors Rn and Rp, as well as comparator 215 are arranged as discussed with regard to FIG. 2 .
- Clamping and detection circuit 400 couples to the nodes for the positive and negative filtered signals Vp and Vn and functions to clamp these signals to protect comparator 215 .
- clamping and detection circuit 400 functions to detect whether the common-mode noise for signals Vp and Vn has a sufficiently large rate of change (dV/dt), which can be either positive or negative.
- SR latch 410 asserts an output signal AS that is inverted by an inverter 420 to drive an input of an AND gate 425 .
- AND gate 425 also processes the output of comparator 215 to form the receiver signal RX.
- SR latch 410 is reset such that the output signal AS is grounded, which causes the output of inverter 420 to go high to the power supply voltage.
- the state of receiver signal RX will thus depend upon an output signal VC from comparator 215 during normal operation. Should the output signal VC be driven high, the receiver signal RX will follow. Similarly, if the output signal VC is low, so will be the receiver signal RX during normal operation.
- AND gate 425 drives the receiver signal RX low and will no longer respond to the output signal VC.
- a timer such as an analog timer circuit 415 times a reset period in response to the assertion of the AS signal.
- analog timer circuit 415 asserts a reset signal to reset SR latch 410 so that the output of inverter 420 goes high.
- AND gate 425 can then respond normally to the output signal VC to pulse the receiver signal RX accordingly.
- the transmitter signal TX is pulsed four times so as to have a rising edge at a time t 0 , a time t 2 , a time t 5 , and a time t 8 .
- the first pulse for transmitter signal TX ends at a time t 1 . Since there was no large common-mode noise rate of change at time t 0 , the receiver signal RX pulses normally and also ends at time t 1 .
- the second pulse for the transmitter signal TX begins at time t 2 . During this pulse, a large rate of change occurs for the common-mode noise at a time t 3 .
- the detection signal DET is thus pulsed, which causes the AS signal to pulse high.
- the receiver signal RX is thus reset at time t 3 back to ground.
- the analog timer times out so that the reset signal RST is pulsed to cause the AS signal to drop low.
- the receiver signal RX may thus have a rising edge at time t 5 in response to the rising edge for the transmitter signal TX.
- the common-mode noise again has a large rate of change to cause the detection signal DET to pulse and begin a timer period for the AS signal.
- the receiver signal RX thus drops low at time t 6 .
- the AS signal times out at time t 7 .
- the receiver signal RX is pulsed normally.
- the signals Vp and Vn are clamped at times t 4 and t 6 .
- an SR controller controls the synchronous rectification but that may be switched off by a primary-side controller.
- the synchronous rectification may be switched off should the flyback converter enter into a continuous conduction mode of operation.
- a pulsing high of the receiver signal RX command the SR controller to switch off the synchronous rectification while the receiver signal RX remains high.
- the SR control may then resume when the receiver signal RX drops low. Should the rate of change for the common-mode noise be higher than a threshold level, the safest response would be to assert the receiver signal RX so that the synchronous rectification is switched off.
- An example transmitter 115 and receiver 600 are shown in FIG. 6 for an embodiment in which a sufficiently-high rate of change for the common-mode noise triggers an assertion of the receiver RX signal.
- Transmitter 115 , capacitors Cp and Cn, resistors Rn and Rp, comparator 215 , clamping and detection circuit 400 , SR latch 410 , and analog timer circuit 415 are all arranged as discussed with regard to FIG. 4 .
- the AS signal from SR latch 410 is not inverted but instead drives an input to an OR gate 605 that also processes the VC output signal from comparator 215 .
- SR latch 410 is in a reset state such that the AS signal is low during normal operation.
- the state of the VC output signal as controlled by the transmitter signal TX will then control the state of the receiver signal RX such that the pulsing of the receiver signal RX matches the pulsing of the transmitter signal TX.
- clamping and detection asserts the detection signal DET to set SR latch 410 and assert the AS signal.
- the receiver signal RX will then be asserted even if the transmitter signal TX is still low to assure that the synchronous rectification is turned off. After analog timer circuit 415 times out, it asserts the reset signal RST to again pull the AS signal low so that normal operation may resume.
- the receiver signal RX Since the receiver signal RX was already high at time t 3 , it remains high until the timeout period expires at a time t 4 . At a time t 5 , the rate of change also exceeds its threshold value. The receiver signal RX was low so it has a rising edge at time t 5 and is not de-asserted until the timeout period expires at a time t 6 .
Abstract
Description
- This application relates to flyback converters, and more particularly to a flyback converter with edge-based communication through a ground-isolating channel.
- A flyback switching power converter is typically provided with a mobile device for battery charging as its transformer provides safe isolation from AC household current. This isolation introduces a problem in that the power switching may be controlled by a primary-side controller that in turn needs to coordinate a cycling of a synchronous rectifier transistor on the secondary side. The primary-side controller cannot directly control the synchronous rectifier transistor through a wire or lead because the ground isolation is then broken. An analogous problem occurs for a secondary-side controller that must control the power switch transistor.
- To accommodate the flow of control signals either from the primary side to the secondary side or from the secondary side to the primary side, it is conventional to use optoisolators. But the use of optoisolators is complicated by their wide variation in current transfer ratio and other operating parameters. An alternative is the use of digital isolators to transfer the control signals with high voltage isolation and accurate timing. A digital isolator uses a high-frequency carrier signal to modulate a gate driver signal at the transmitting side. For example, the carrier signal may be one GHz or higher in frequency, having a pulse width distortion of less than 10 ns and a common-mode transient immunity of 50V/ns.
- To demodulate the transmitted signal on the receiving side, a digital isolator typically requires a low-pass filter and a relatively-fast comparator. Such digital isolators are expensive and over-qualified for typical flyback converter application in which common-mode transient immunity is normally less then 1v/ns and the pulse-width distortion is larger than 50 ns.
- Accordingly, there is a need in the art for flyback converters with improved communication of control signals between the primary and second sides of the transformer.
- A flyback converter includes a ground-isolating communication channel over which a pulsed signal may be exchanged between the primary and secondary sides of the flyback converter's transformer. The transmitter of the pulsed signal may be located on either the primary or secondary side of the transformer. The receiver would be opposite side of the transformer from the receiver. The ground-isolating communication channel includes a positive capacitor and a negative capacitor. The transmitter drives a pulsed transmitter signal into a transmitter terminal of the positive capacitor. In addition, the transmitter inverts the pulsed transmitter signal to form a complement transmitter signal that is driven into a transmitter terminal of the negative capacitor.
- The receiver couples to a receiving terminal for the both capacitors to receive the transmitter signal and the complement transmitter signal. In addition, the receiver high-pass filters the received transmitter signal to form a positive filtered signal. Similarly, the receiver high-pass filters the received complement transmitter signal to form a negative filtered signal. A difference between the positive filtered signal and the negative filtered signal forms an edge-triggering signal that is pulsed temporarily to a positive voltage in response to a rising edge for the transmitter signal and that is pulsed temporality to a negative voltage in response to a falling edge for the transmitter signal.
- To generate a received signal that is pulsed in common with the transmitter signal, the receiver includes a comparator that compares the positive filtered signal to the negative filtered signal so as to respond to the edge-triggering signal. To combat noise, the comparator may include hysteresis such that the comparator does not assert the receive signal to a power supply voltage until the edge-triggering signal voltage exceeds a positive threshold value. Similarly, the comparator grounds the receiver signal when the edge-triggering signal voltage is below a negative threshold value.
- These advantageous features may be better appreciated through a consideration of the following detailed description.
-
FIG. 1 illustrates a flyback converter including a ground-isolating channel for the transmission of an edge-triggering signal in accordance with an aspect of the disclosure. -
FIG. 2 illustrates an example transmitter for the transmission of the edge-triggering signal and an example receiver for receiving the edge-triggering signal in accordance with an aspect of the disclosure. -
FIG. 3 illustrates some waveforms for the transmitter and receiver ofFIG. 2 . -
FIG. 4 illustrates a transmitter and receiver for an edge-triggering signal in which the receiver includes a detection circuit for forcing the receiver signal low in response to a rate of change for a common-mode noise exceeding a threshold value in accordance with an aspect of the disclosure. -
FIG. 5 illustrates some waveforms for the transmitter and receiver ofFIG. 4 . -
FIG. 6 illustrates a transmitter and receiver for an edge-triggering signal in which the receiver includes a detection circuit for forcing the receiver signal high in response to a rate of change for a common-mode noise exceeding a threshold value in accordance with an aspect of the disclosure. -
FIG. 7 illustrate some waveforms for the transmitter and receiver ofFIG. 6 . - Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.
- To address the need in the art for low-cost and accurate control signal communication, a flyback converter is provided with an isolated communication channel that propagates an edge-triggered gate control signal. On the transmitting side of the channel, a transmitter pulses a transmitter signal (TX) to control a transistor switch on the receiving side of the channel. Depending upon the pulsing, the transmitter signal is either ground or a power supply voltage. The transmitter also generates a complement transmitter signal that is the complement of the transmitter signal. The complement transmitter signal will thus equal the power supply voltage while the transmitter signal is grounded and will be grounded while the transmitter signal is charged to the power supply voltage. The channel includes a positive blocking capacitor over which the transmitter drives the positive signal. In addition, the channel includes a negative blocking capacitor over which the transmitter drives the negative signal.
- The positive and negative blocking capacitors block any DC signal transmission from the transmitter to a receiver at a receiving-end of the channel. A receiving-end terminal for the positive blocking capacitor is coupled to a first resistor to form a first high-pass filter that filters the positive signal to form a filtered positive signal (Vp). Similarly, a receiving-end terminal for the negative blocking capacitor is coupled to a second resistor to form a second high-pass filter that filters the negative signal to form a filtered negative signal (Vn). Due to the high-pass filtering, a difference of the filtered voltages (Vp−Vn) will have a relatively-narrow positive voltage pulse in response to a rising edge for the positive signal and then return to zero volts. Conversely, the difference of the filtered voltages will have a relatively-narrow negative voltage pulse in response to the falling edge for the positive signal and then return to zero volts. The difference signal (Vp−Vn) may thus be denoted as an edge-triggering signal. A comparator with hysteresis may compare the filtered positive signal Vp to the filtered negative signal Vn to respond to edge-triggering signal. A receiver output (RX) signal from the comparator may then be used to control the gate voltage of a switch transistor. Should the transmission be from the secondary side of the transformer to the primary side, the controlled switch transistor may be the power switch transistor. Conversely, if the transmission is from the primary side of the transformer to the secondary side, the controlled switch transistor may be a synchronous rectifier switch transistor.
- The resulting control signal transmission is quite advantageous since it avoids both the expense of digital isolators and the stability and control issues for optoisolators. An
example flyback converter 100 that includes an edge-triggered isolating communication channel is shown inFIG. 1 .Flyback converter 100 includes a transformer T1 having aprimary winding 105 and asecondary winding 110. A power switch transistor S1 controls whether a magnetizing current flows throughprimary winding 105. When power switch transistor S1 conducts, an input voltage Vin causes the magnetizing current to increase until power switch transistor S1 shuts off. While power switch transistor S1 conducts, a synchronous rectifier (SR) switch transistor S2 prevents a secondary current from flowing insecondary winding 110. After power switch transistor S1 shuts off, SR switch transistor S2 switches on to allow the secondary current to charge an output voltage Vout and deliver power to a load (not illustrated). - The control of power switch transistor S1 or of SR switch transistor S2 may be advantageously accomplished through an edge-triggering signaling conducted through a ground-isolating
channel 125 formed by a positive capacitor Cp and a negative capacitor Cn. For example, suppose that a primary side controller (not illustrated) controls the cycling of power switch transistor S1. After power switch transistor S1 is turned off, the controller may trigger SR switch transistor S2 to turn on by transmitting an edge-triggering signal from atransmitter 115 throughchannel 125 to areceiver 120. Based upon the edge-triggering signal,receiver 120 controls a gate voltage of SR switch transistor S2 accordingly. - Conversely, suppose that a secondary-side controller (not illustrated) controls the cycling of power switch transistor S1 as well as the cycling of SR switch transistor S2. In that case,
receiver 120 instead as a transmitter of the edge-triggering signal throughchannel 125 such thattransmitter 115 acts as a receiver to control a gate voltage of power switch S1 responsive to the edge-triggering signal. -
Transmitter 115 andreceiver 120 may be implemented as shown inFIG. 2 .Transmitter 115 includes abuffer 205 for driving the transmitter signal TX into a terminal of positive capacitor Cp. In addition,transmitter 115 includes an inverter for inverting the transmitter signal to form the complement transmitter signal and for driving the complement transmitter signal into a terminal of negative capacitor Cn. A receiving-end terminal for positive capacitor Cp is coupled to a resistor Rp to form the first high-pass filter that filters the transmitter signal TX to form the filtered positive signal (Vp). Similarly, a receiving-end terminal for negative capacitor Cn is coupled to a resistor Rn to form the second high-pass filter that filters the complement transmitter signal to form the filtered negative signal (Vn). Resistors Rn and Rp are coupled in series across the receiving end terminals of capacitors Cp and Cn. Acomparator 215 with hysteresis may compare the filtered positive signal Vp to the filtered negative signal Vn to respond to the edge-triggering signal (Vp−Vn) to produce the receiver signal RX. A zener diode Z1 clamps the filtered negative signal whereas a zener diode Z2 clamps the filtered positive signal. - Note that
receiver 120 is symmetric with regard to anode 220 between resistors Rn and Rp. Such symmetry ensures thatcomparator 215 will be immune to static levels of common-mode noise that affects the filtered signals Vp and Vn. Some waveforms for the transmitter signal TX, the receiver signal RX, and the edge-triggering signal (Vp−Vn) are shown inFIG. 3 . At a time t0, the transmitter signal TX pulses high to cause the edge-triggering signal to have a transient positive pulse. In response to the pulsing of the edge-triggering signal, the receiver signal RX is driven high to the power supply voltage at time t0. The pulse for the transmitter signal TX ends at a time t1, which cause the edge-triggering signal to have a transient negative pulse. In response to the pulsing of the edge-triggering signal, the pulse for the receiver signal RX ends at time t1. The pulsing of the transmitter signal TX is thus duplicated by the pulsing of the receiver signal RX. At a time t2, the transmitter signal TX again pulses high. But a common-mode noise for both the positive filtered signal Vp and the negative filtered signal Vn increases at time t2, which forces the edge-triggered signal to remain at ground at time t2. The receiver signal RX thus does not pulse high at time t2 despite the pulsing of the transmitter signal TX. The second pulse for the transmitter signal TX ends at time t3 during which the common-mode noise remains high. Although the common-mode noise is high, it is static at time t3 such that the edge-triggering signal responds to the falling edge for the transmitter signal TX and is thus pulsed low at time t3. The impedance symmetry inreceiver 120 tonode 220 ensures this immunity to static common-mode noise. To further enforce this common-mode noise immunity, a reference circuit (not illustrated) may maintainnode 220 at a reference voltage such as one-half the power supply voltage. - A third pulse for the transmitter signal TX begins at a time t4. Since the common-mode noise is static although still high, the receiver signal RX is also pulsed high at time t4. The third pulse for the transmitter signal TX ends at a time t5 but the common-mode node changes to a low state at time t4 as well. The change in the common-mode noise causes the receiver signal RX to not respond to the falling edger for the transmitter signal at time t5. A fourth pulse for the transmitter signal TX begins at a time t6 but the receiver signal RX was already pulsed high at time t4. The fourth pulse for the transmitter signal ends at a time t7, which also ends the pulse for the receiver signal RX.
- The common-mode noise changes cause the receiver signal ILX to miss a rising edge at times t2 and t6 and miss a falling edge at times t3 and t5. Should the receiver signal RX control the SR switch transistor, the missing falling edges may result in converter failure. Moreover, a very large rate of change for the common-mode noise may result in a false spike for the edge-triggering signal and improperly pulse the receiver signal RX. Such improper pulsing of the receiver signal RX may also result in converter failure.
- To eliminate the risk of missing falling edges for the receiver signal RX, the common-mode noise may be monitored by a clamping and
detection circuit 400 as shown inFIG. 4 for areceiver 405.Transmitter 115, capacitors Cn and Cp, resistors Rn and Rp, as well ascomparator 215 are arranged as discussed with regard toFIG. 2 . Clamping anddetection circuit 400 couples to the nodes for the positive and negative filtered signals Vp and Vn and functions to clamp these signals to protectcomparator 215. In addition, clamping anddetection circuit 400 functions to detect whether the common-mode noise for signals Vp and Vn has a sufficiently large rate of change (dV/dt), which can be either positive or negative. Should clamping anddetection circuit 400 detect such a large rate of change in the common-mode noise, it asserts a detection signal (DET) that sets a set-reset (SR)latch 410. In response,SR latch 410 asserts an output signal AS that is inverted by an inverter 420 to drive an input of an ANDgate 425. ANDgate 425 also processes the output ofcomparator 215 to form the receiver signal RX. During normal operation (no large rate of change in the common-mode noise),SR latch 410 is reset such that the output signal AS is grounded, which causes the output of inverter 420 to go high to the power supply voltage. The state of receiver signal RX will thus depend upon an output signal VC fromcomparator 215 during normal operation. Should the output signal VC be driven high, the receiver signal RX will follow. Similarly, if the output signal VC is low, so will be the receiver signal RX during normal operation. - When the common-mode noise rate of change is sufficient for clamping and
detection circuit 400 to asset the detection signal DET, ANDgate 425 drives the receiver signal RX low and will no longer respond to the output signal VC. To enable future pulses of the receiver signal RX, a timer such as ananalog timer circuit 415 times a reset period in response to the assertion of the AS signal. At the termination of the reset period,analog timer circuit 415 asserts a reset signal to resetSR latch 410 so that the output of inverter 420 goes high. ANDgate 425 can then respond normally to the output signal VC to pulse the receiver signal RX accordingly. - Some waveforms for
receiver 405 andtransmitter 115 are shown inFIG. 5 . The transmitter signal TX is pulsed four times so as to have a rising edge at a time t0, a time t2, a time t5, and a time t8. The first pulse for transmitter signal TX ends at a time t1. Since there was no large common-mode noise rate of change at time t0, the receiver signal RX pulses normally and also ends at time t1. The second pulse for the transmitter signal TX begins at time t2. During this pulse, a large rate of change occurs for the common-mode noise at a time t3. The detection signal DET is thus pulsed, which causes the AS signal to pulse high. The receiver signal RX is thus reset at time t3 back to ground. At a time t4, the analog timer times out so that the reset signal RST is pulsed to cause the AS signal to drop low. The receiver signal RX may thus have a rising edge at time t5 in response to the rising edge for the transmitter signal TX. At a time t6 during this pulse of the transmitter signal TX, the common-mode noise again has a large rate of change to cause the detection signal DET to pulse and begin a timer period for the AS signal. The receiver signal RX thus drops low at time t6. The AS signal times out at time t7. During the pulse of the transmitter signal from time 8 to a time t9, the receiver signal RX is pulsed normally. The signals Vp and Vn are clamped at times t4 and t6. - There may be embodiments in which an SR controller controls the synchronous rectification but that may be switched off by a primary-side controller. For example, the synchronous rectification may be switched off should the flyback converter enter into a continuous conduction mode of operation. In such an embodiment, a pulsing high of the receiver signal RX command the SR controller to switch off the synchronous rectification while the receiver signal RX remains high. The SR control may then resume when the receiver signal RX drops low. Should the rate of change for the common-mode noise be higher than a threshold level, the safest response would be to assert the receiver signal RX so that the synchronous rectification is switched off.
- An
example transmitter 115 andreceiver 600 are shown inFIG. 6 for an embodiment in which a sufficiently-high rate of change for the common-mode noise triggers an assertion of the receiver RX signal.Transmitter 115, capacitors Cp and Cn, resistors Rn and Rp,comparator 215, clamping anddetection circuit 400,SR latch 410, andanalog timer circuit 415 are all arranged as discussed with regard toFIG. 4 . However, the AS signal fromSR latch 410 is not inverted but instead drives an input to anOR gate 605 that also processes the VC output signal fromcomparator 215. Should the rate of change for the common-mode noise be below the threshold applied in clamping anddetection circuit 400,SR latch 410 is in a reset state such that the AS signal is low during normal operation. The state of the VC output signal as controlled by the transmitter signal TX will then control the state of the receiver signal RX such that the pulsing of the receiver signal RX matches the pulsing of the transmitter signal TX. If the rate of change is greater than the threshold level, clamping and detection asserts the detection signal DET to setSR latch 410 and assert the AS signal. The receiver signal RX will then be asserted even if the transmitter signal TX is still low to assure that the synchronous rectification is turned off. Afteranalog timer circuit 415 times out, it asserts the reset signal RST to again pull the AS signal low so that normal operation may resume. - Same waveforms for
receiver 600 andtransmitter 115 are shown inFIG. 7 . At a time t1, the transmitter signal TX had pulsed during normal operation such that the receiver signal RX is already high but the rate of change for the common-mode noise exceeds its threshold value. The detection signal DET thus pulses high at time t1 but there is no rising edge for the receiver signal RX since it was already asserted. The AS signal is asserted and the timeout period initiated. The timeout period expires at a time t2, so that the reset signal RST is pulsed to force the AS signal low and de-assert the receiver signal RX. The rate of change again exceeds the threshold at a time t3. Since the receiver signal RX was already high at time t3, it remains high until the timeout period expires at a time t4. At a time t5, the rate of change also exceeds its threshold value. The receiver signal RX was low so it has a rising edge at time t5 and is not de-asserted until the timeout period expires at a time t6. - As those of some skill in this art will by now appreciate and depending on the particular application at hand, many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the spirit and scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.
Claims (15)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/276,475 US10797608B2 (en) | 2019-02-14 | 2019-02-14 | Flyback converter with edge-based isolated communication |
CN201910477591.4A CN111564975B (en) | 2019-02-14 | 2019-06-03 | Receiver for flyback converter and control method thereof |
US17/064,533 US11588409B2 (en) | 2019-02-14 | 2020-10-06 | Flyback converter with edge-based isolated communication |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/276,475 US10797608B2 (en) | 2019-02-14 | 2019-02-14 | Flyback converter with edge-based isolated communication |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/064,533 Continuation US11588409B2 (en) | 2019-02-14 | 2020-10-06 | Flyback converter with edge-based isolated communication |
Publications (2)
Publication Number | Publication Date |
---|---|
US20200266718A1 true US20200266718A1 (en) | 2020-08-20 |
US10797608B2 US10797608B2 (en) | 2020-10-06 |
Family
ID=72042314
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/276,475 Active US10797608B2 (en) | 2019-02-14 | 2019-02-14 | Flyback converter with edge-based isolated communication |
US17/064,533 Active 2039-06-24 US11588409B2 (en) | 2019-02-14 | 2020-10-06 | Flyback converter with edge-based isolated communication |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/064,533 Active 2039-06-24 US11588409B2 (en) | 2019-02-14 | 2020-10-06 | Flyback converter with edge-based isolated communication |
Country Status (2)
Country | Link |
---|---|
US (2) | US10797608B2 (en) |
CN (1) | CN111564975B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220115941A1 (en) * | 2020-10-08 | 2022-04-14 | Silicon Laboratories Inc. | Interface for passing control information over an isolation channel |
US11539559B2 (en) | 2020-10-08 | 2022-12-27 | Skyworks Solutions, Inc. | Demodulator for an isolation communication channel for dual communication |
US11888658B2 (en) | 2020-10-08 | 2024-01-30 | Skyworks Solutions, Inc. | Transmitter for dual communication over an isolation channel |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113419595B (en) * | 2021-07-22 | 2022-03-18 | 苏州纳芯微电子股份有限公司 | Digital isolator and common mode interference suppression circuit thereof |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4656661A (en) * | 1984-12-13 | 1987-04-07 | American Telephone And Telegraph Company | Switched capacitor coupled line receiver circuit |
EP0741447A3 (en) * | 1995-05-04 | 1997-04-16 | At & T Corp | Circuit and method for controlling a synchronous recifier converter |
US6188209B1 (en) * | 2000-02-07 | 2001-02-13 | University Of Hong Kong | Stepping inductor for fast transient response of switching converter |
US6590436B2 (en) * | 2001-10-12 | 2003-07-08 | Texas Instruments Incorporated | System and method of translating wide common mode voltage ranges into narrow common mode voltage ranges |
JP2005534275A (en) * | 2002-07-26 | 2005-11-10 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for controlling transient response of power converter supplying power to load, transient response controller, and power converter |
US6982582B1 (en) * | 2003-06-23 | 2006-01-03 | Marvell International Ltd. | Simplified comparator with digitally controllable hysteresis and bandwidth |
US7864546B2 (en) * | 2007-02-13 | 2011-01-04 | Akros Silicon Inc. | DC-DC converter with communication across an isolation pathway |
CN101026338A (en) * | 2007-03-13 | 2007-08-29 | 艾默生网络能源有限公司 | Low-voltage large-current DC/DC module topology |
US7885084B2 (en) * | 2007-10-03 | 2011-02-08 | System General Corp. | Control circuit for synchronous rectifying and soft switching of power converters |
CN101572485B (en) * | 2008-04-30 | 2012-06-06 | 杭州茂力半导体技术有限公司 | Intelligent driving control method and device for secondary synchronous rectifier |
WO2009150794A1 (en) * | 2008-06-13 | 2009-12-17 | ローム株式会社 | Motor drive circuit |
US8792256B2 (en) * | 2012-01-27 | 2014-07-29 | Power Systems Technologies Ltd. | Controller for a switch and method of operating the same |
US9698728B2 (en) * | 2012-12-13 | 2017-07-04 | Texas Instruments Incorporated | Digital isolator |
US9461546B2 (en) * | 2013-02-08 | 2016-10-04 | Advanced Charging Technologies, LLC | Power device and method for delivering power to electronic devices |
US9184668B2 (en) * | 2013-03-15 | 2015-11-10 | Flextronics Ap, Llc | Power management integrated circuit partitioning with dedicated primary side control winding |
KR101514553B1 (en) * | 2013-10-17 | 2015-04-22 | 삼성전기주식회사 | Power supply device |
CN104079190B (en) * | 2014-05-21 | 2016-10-26 | 杰华特微电子(杭州)有限公司 | A kind of synchronous rectification control method |
US9998301B2 (en) * | 2014-11-03 | 2018-06-12 | Analog Devices, Inc. | Signal isolator system with protection for common mode transients |
US9882500B2 (en) * | 2014-12-07 | 2018-01-30 | Alpha & Omega Semiconductor (Cayman), Ltd. | Power supply device |
CN106411136A (en) * | 2016-08-25 | 2017-02-15 | 浙江大学 | High-voltage capacitance coupling based control chip of isolated type power converter |
US10211744B2 (en) * | 2017-05-15 | 2019-02-19 | Stmicroelectronics S.R.L. | Secondary side current mode control for a converter |
-
2019
- 2019-02-14 US US16/276,475 patent/US10797608B2/en active Active
- 2019-06-03 CN CN201910477591.4A patent/CN111564975B/en active Active
-
2020
- 2020-10-06 US US17/064,533 patent/US11588409B2/en active Active
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220115941A1 (en) * | 2020-10-08 | 2022-04-14 | Silicon Laboratories Inc. | Interface for passing control information over an isolation channel |
US11539559B2 (en) | 2020-10-08 | 2022-12-27 | Skyworks Solutions, Inc. | Demodulator for an isolation communication channel for dual communication |
US11575305B2 (en) * | 2020-10-08 | 2023-02-07 | Skyworks Solutions, Inc. | Interface for passing control information over an isolation channel |
US20230387782A1 (en) * | 2020-10-08 | 2023-11-30 | Skyworks Solutions, Inc. | Interface for passing control information over an isolation channel |
US11888658B2 (en) | 2020-10-08 | 2024-01-30 | Skyworks Solutions, Inc. | Transmitter for dual communication over an isolation channel |
US11962233B2 (en) * | 2020-10-08 | 2024-04-16 | Skyworks Solutions, Inc. | Interface for passing control information over an isolation channel |
Also Published As
Publication number | Publication date |
---|---|
US11588409B2 (en) | 2023-02-21 |
CN111564975B (en) | 2021-11-09 |
CN111564975A (en) | 2020-08-21 |
US20210021201A1 (en) | 2021-01-21 |
US10797608B2 (en) | 2020-10-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11588409B2 (en) | Flyback converter with edge-based isolated communication | |
US10651752B1 (en) | Flyback converter with reliable pulse-based isolated communication | |
US10418911B2 (en) | Adaptive synchronous rectifier sensing deglitch | |
CA1248583A (en) | Power switching circuit | |
US20180262096A1 (en) | Advanced frequency reduction of quasi-resonant converters | |
CN103312200B (en) | Power converter, current limiting unit, control circuit and related control method | |
EP4283852A1 (en) | Protecting semiconductor switches in switched mode power converters | |
US20230353145A1 (en) | Low-latency switch drive circuit with power transfer | |
US20200162129A1 (en) | Communications using an inductive couplings | |
US9397573B2 (en) | Integrated circuit for controlling a switch of a current path with leading edge blanking device of the current signal | |
JP6659566B2 (en) | Switch controller with verification circuit to improve noise immunity | |
CN103368400A (en) | System and method for constant voltage control and constant current control | |
CN105896975A (en) | System and method for output current adjustment in power transformation system | |
NZ568937A (en) | Detecting voltage ringing in an inductive load for a dimmer | |
GB2511846A (en) | A gate drive circuit for a semiconductor switch | |
CN109088396A (en) | A kind of current foldback circuit and the Switching Power Supply comprising the circuit | |
US11936288B2 (en) | Discharge of an AC capacitor using totem-pole power factor correction (PFC) circuitry | |
Kaeriyama et al. | A 2.5 kV isolation 35kV/us CMR 250Mbps 0.13 mA/Mbps digital isolator in standard CMOS with an on-chip small transformer | |
US11942925B2 (en) | Management of multiple switching-synchronized measurements using combined prioritized measurement and round-robin sequence measurement | |
Kagaya et al. | A 500-Mbps digital isolator circuits using counter-pulse immune receiver scheme for power electronics | |
RU2290737C1 (en) | Method for controlling semiconductor switch | |
US20220308618A1 (en) | Clock data recovery circuit | |
US5285481A (en) | Receiver circuit with smart squelch | |
US20230137936A1 (en) | Isolated gate driver | |
TWI445303B (en) | Driver for driving power switch element |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: DIALOG SEMICONDUCTOR INC., CALIFORNIA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBER 16276472 AND THIRD ASSIGNOR'S NAME LAIGING PING AND EXECUTION DATE PREVIOUSLY RECORDED ON REEL 048383 FRAME 0189. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNORS:LIU, WENDUO;YANG, KUN;PING, LAIQING;SIGNING DATES FROM 20190219 TO 20190221;REEL/FRAME:048896/0528 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |