US20200251561A1 - SiC EPITAXIAL WAFER, AND METHOD OF MANUFACTURING THE SAME - Google Patents

SiC EPITAXIAL WAFER, AND METHOD OF MANUFACTURING THE SAME Download PDF

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US20200251561A1
US20200251561A1 US16/781,294 US202016781294A US2020251561A1 US 20200251561 A1 US20200251561 A1 US 20200251561A1 US 202016781294 A US202016781294 A US 202016781294A US 2020251561 A1 US2020251561 A1 US 2020251561A1
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sic
sic epitaxial
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Yoshitaka Nishihara
Keisuke Fukada
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Resonac Holdings Corp
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Showa Denko KK
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/20—Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B28/00—Production of homogeneous polycrystalline material with defined structure
    • C30B28/12—Production of homogeneous polycrystalline material with defined structure directly from the gas state
    • C30B28/14—Production of homogeneous polycrystalline material with defined structure directly from the gas state by chemical reaction of reactive gases
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Definitions

  • the present invention relates to a SiC epitaxial wafer and a method of manufacturing the same.
  • Silicon carbide has characteristics such as a dielectric breakdown electric field one order of magnitude larger, a band gap three times larger, and a thermal conductivity approximately three times higher than that of silicon (Si). Since silicon carbide has these characteristics, it is expected that the silicon carbide will be applied to power devices, high-frequency devices, high-temperature operating devices, and the like. For this reason, in recent years, SiC epitaxial wafers have been used for the above-described semiconductor devices.
  • SiC devices are generally manufactured using a SiC epitaxial wafer obtained by growing a SiC epitaxial layer (film) serving as an activated region of a device on a SiC single crystal substrate (may also be simply referred to as a SiC substrate), obtained by being processed from SiC bulk single crystal grown by sublimation recrystallization method or the like, through chemical vapor deposition (CVD) or the like.
  • a SiC epitaxial wafer obtained by growing a SiC epitaxial layer (film) serving as an activated region of a device on a SiC single crystal substrate (may also be simply referred to as a SiC substrate), obtained by being processed from SiC bulk single crystal grown by sublimation recrystallization method or the like, through chemical vapor deposition (CVD) or the like.
  • CVD chemical vapor deposition
  • SiC epitaxial wafers are generally obtained by performing step flow growth (lateral growth from atomic steps) on a SiC single crystal substrate having a surface with an off-angle in a ⁇ 11-20> direction from a (0001) plane as a growth surface to grow a 4H—SiC epitaxial layer.
  • defects in the epitaxial layer of the SiC epitaxial wafer defects that inherit defects in the SiC single crystal substrate and defects newly formed in the epitaxial layer are known. Threading dislocations, basal plane dislocations, carrot defects, and the like are known as the former, and triangular defects and the like are known as the latter.
  • a carrot defect is a rod-like defect which is long in the step-flow growth direction when viewed from the epitaxial surface side, it is said to be formed by using dislocations of the substrate (threading screw dislocations (TSD) or basal plane dislocations (BPD)) or scratches on the substrate as starting points (see Non-Patent Document 1).
  • TSD thread screw dislocations
  • BPD basal plane dislocations
  • a triangular defect is formed toward a direction in such a manner that the apex of the triangle and the opposite side (base) thereof are aligned in order from the upstream to downstream side along the step-flow growth direction ( ⁇ 11-20> direction).
  • the triangular defect is said to be a defect which is originated from the foreign matter (downfall) present on the SiC single crystal substrate before epitaxial growth at the time of manufacturing the SiC epitaxial wafer or within the epitaxial layer during epitaxial growth as a starting point, and which is exposed on the epitaxial surface by extending a 3C polymorphous layer along the off angle of the substrate (see Non-Patent Document 2).
  • substrate carbon inclusions large-pit defects caused by carbon inclusions in a SiC single crystal substrate (hereinafter sometimes referred to as “substrate carbon inclusions”) have been found (see Patent Document 1).
  • substrate carbon inclusions are converted as new defects in the epitaxial layer from the substrate carbon inclusions in the SiC single crystal substrate as a starting point.
  • V F degradation occurs when current is applied in a forward direction to an element configured to perform a bipolar operation, such as a pn diode or a parasitic diode (body diode) of a MOSFET which is manufactured using a SiC epitaxial wafer.
  • the V F deterioration is a phenomenon in which, when current flows in the forward direction, the basal plane dislocation expands to a stacking fault (SF), which is a plane defect, and the stacking fault acts as a resistance, thereby causing an increase in the forward voltage (V F ).
  • SF stacking fault
  • Both large-pit defects caused by substrate carbon inclusions and large-pit defects caused by micropipes in the substrate can be expanded and converted into stacking faults from the large-pit defects as a starting point after the forward conduction is applied.
  • SiC epitaxial wafer for the SiC device it is required to use a SiC epitaxial wafer having a reduced density of large-pit defects, and it is desirable to use a SiC epitaxial wafer having no large-pit defects.
  • the present invention has been made in view of the above-described problem, and an object thereof to provide a SiC epitaxial wafer in which V F deterioration is suppressed and a method of manufacturing the same.
  • the present invention provides the following means in order to solve the above-described problem.
  • a SiC epitaxial wafer comprising a SiC epitaxial layer formed on a SiC single crystal substrate, wherein a total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, is 1 defect/cm 2 or less.
  • the present invention can provide a SiC epitaxial wafer in which V F deterioration is suppressed.
  • FIG. 1 is a schematic cross-sectional view of a SiC substrate wafer according to an embodiment of the present invention.
  • FIG. 2A is a SICA image of a SiC substrate wafer of the present invention.
  • FIG. 2B is a PL image corresponding to FIG. 2A .
  • FIG. 3 is a STEM image of a cross section in the vicinity of a large-pit defect caused by micropipes in the substrate.
  • FIG. 4 is a graph showing electrical characteristics of a pn diode manufactured using the SiC epitaxial wafer shown in FIG. 2 before and after a forward conduction test.
  • FIG. 1 illustrates a schematic cross-sectional view of a SiC epitaxial wafer according to an embodiment of the present invention.
  • a SiC epitaxial wafer 10 shown in FIG. 1 is a SiC epitaxial wafer comprising a SiC epitaxial layer 2 formed on a SiC single crystal substrate 1 , wherein a total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer 2 , is 1 defects/cm 2 or less.
  • the SiC single crystal substrate used in the SiC epitaxial wafer of the present invention is preferably a 4H—SiC single crystal substrate.
  • the SiC single crystal substrate used in the SiC epitaxial wafer of the present invention preferably has an off angle.
  • a SiC single crystal substrate having an off angle of 4° can be used.
  • the thickness of the SiC single crystal substrate is not particularly limited, for example, a SiC single crystal substrate having a thickness of 150 ⁇ m or more and 550 ⁇ m or less can be used. Preferably, a SiC single crystal substrate having a thickness of 300 ⁇ m or more and 400 ⁇ m or less can be used.
  • the size of the SiC single crystal substrate is not particularly limited, for example, a SiC single crystal substrate with a size of 3 inches to 6 inches can be used.
  • the term “large-pit defect” refers to a defect having the following characteristics when an inspection apparatus (manufactured by Lasertec Corporation, SICA88) having both a confocal differential interference microscope and a photoluminescence (PL) observation function is used.
  • SICA image an obtained microscope image
  • the defect appears a dent or hole having a size (maximum distance when connecting two points on the outer circumference of the image with a straight line) of 5 ⁇ m or more.
  • the defect appears bright with a size equal to or larger than the size in the microscope image.
  • defects that are pits or holes with a size of 10 ⁇ m or more and less than 15 ⁇ m in the SICA image and appear bright in the PL image at the same size or larger than the size in the microscope image, empirically, about 90% of the defects are caused by substrate carbon inclusions or micropipes in the substrate.
  • defects that are pits or holes with a size of 15 ⁇ m or more in the SICA image and appear bright in the PL image at the same size or larger than the size in the microscope image, empirically, about 100% of the defects are caused by substrate carbon inclusions or micropipes in the substrate.
  • the probability that the dent or hole is one of the large-pit defect caused by the substrate carbon inclusion and the large-pit defect caused by the micropipe in the substrate can be identified by the above probability.
  • the cause of the large-pit defect in the SiC epitaxial layer of the SiC epitaxial wafer can be identified with high accuracy by comparing the SICA image and the PL image of the substrate carbon inclusions and micropipes in the SiC single crystal substrate with the SICA image and the PL image of the SiC epitaxial wafer.
  • a dark spot exists in the PL image of the SiC single crystal substrate
  • the dark spot can be identified as a micropipe in the substrate.
  • a large-pit defect formed at a position corresponding to the dark spot on the SiC epitaxial wafer after forming an epitaxial layer can be identified as a large-pit defect caused by a micropipe in the substrate.
  • the large-pit defect at this time is observed as a pit in the SICA image, and is often observed as a bright circle (including oval shape, oblate shape, and so on) or a spider web (a core at the center and a string around it, a collection of strings, and so on) in the PL image.
  • a bright circle including oval shape, oblate shape, and so on
  • a spider web a core at the center and a string around it, a collection of strings, and so on
  • a pit exists in the SICA image of the SiC single crystal substrate and a dark spot exists in the PL image of the SiC single crystal substrate when a dark spot does not exist at almost the same position in a PL image of an adjacent SiC single crystal substrate in the same ingot as the SiC single crystal substrate, the dark spot can be identified as a substrate carbon inclusion.
  • a large-pit defect formed at a position corresponding to the dark spot on the SiC epitaxial wafer after forming an epitaxial layer can be identified as a large-pit defect caused by a substrate carbon inclusion.
  • the large-pit defect at this time is observed as a pit in the SICA image, and is often observed as a bright circle (including oval shape, oblate shape, and so on) in the PL image.
  • the SiC epitaxial wafer satisfies the specifications of a normal SiC device.
  • the “large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions” in “the total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions” in SiC epitaxial wafers corresponds to defects having the following characteristics for each size. Regarding defects that are pits or holes with a size of 5 ⁇ m or more and less than 10 ⁇ m in the SICA image and appear bright in the PL image at the same size or larger than the size in the SICA image, it is assumed that 50% of the counted number of defects corresponds to the above-described defects.
  • defects that are pits or holes with a size of 10 ⁇ m or more and less than 15 ⁇ m in the SICA image and appear bright in the PL image at the same size or larger than the size in the SICA image it is assumed that 90% of the counted number of defects corresponds to the above-described defects.
  • defects that are pits or holes with a size of 15 ⁇ m or more in the SICA image and appear bright in the PL image at the same size or larger than the size in the SICA image it is assumed that all of the counted number of defects corresponds to the above-described defects. The sum of these defects is defined as the total number of the above-described defects. “The total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions” means an area density obtained by dividing the total number of the above defects by the unit area.
  • the total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions is preferably 0.1 defect/cm 2 or less, it is more preferably 0.01 defect/cm 2 or less, and it is even more preferably 0 defect/cm 2 or less.
  • FIGS. 2A and 2B are a SICA image and a PL image of a SiC substrate wafer of the present invention.
  • FIG. 2A is a SICA image and
  • FIG. 2B is a PL image.
  • the SiC epitaxial wafer was manufactured as follows.
  • a 4-inch 4H—SiC single crystal substrate having an off angle of 4° in the ⁇ 11-20> direction with respect to the (0001) Si plane was used as a SiC single crystal substrate.
  • a known polishing step was performed on the 4H—SiC single crystal substrate. Thereafter, the single crystal substrate was set in a CVD apparatus, and a step of cleaning (etching) the single crystal substrate surface with hydrogen gas was performed. Next, a SiC epitaxial growth step was performed under the conditions of a growth temperature of 1500° C. or more and a C/Si ratio of 1.25 or less while using silane and propane as source gases and supplying hydrogen as a carrier gas. Thus, a 10 ⁇ m-thick SiC epitaxial layer was formed on the SiC single crystal substrate to obtain a SiC epitaxial wafer.
  • the large-pit defect in the SiC epitaxial wafer shown in FIG. 2 has a circular shape with a diameter of about 15 ⁇ m in the SICA image and a circular shape with a diameter of about 20 to 30 ⁇ m in the PL image.
  • An SICA image was obtained on the surface of the 4H—SiC single crystal substrate before the formation of the SiC epitaxial layer. It was confirmed by a cross-sectional analysis that this large-pit defect was a large-pit defect caused by a micropipe in the substrate.
  • FIG. 3 is an image obtained by observing the cross section of the large-pit defect using a scanning transmission electron microscope (STEM). The scale indicates 0.6 ⁇ m on each scale.
  • the STEM image shown in FIG. 3 is an example.
  • a micropipe is visible in the substrate located below.
  • dislocations extending from the micropipe in the substrate are present, and large-pit defects ( FIG. 2 ) are visible on the surface located at the tip of the dislocation.
  • the STEM image shown in FIG. 3 clearly shows that the large-pit defect on the surface of the epitaxial layer is a large-pit defect caused by the micropipe in the substrate.
  • Dislocations are present between the micropipe in the substrate and the large-pit defects on the surface, as shown in FIG. 3 . Some of these dislocations extend along the basal plane in addition to those extending toward the surface. The dislocations extending along the basal plane expand into stacking faults when forward current is applied, causing V F degradation.
  • FIG. 4 shows the results of measuring the electrical characteristics in the forward direction before and after the current was passed through the pn diode at 960 A/cm 2 for 1 hour. It was confirmed that this current test resulted in a 3.4% forward voltage (V F ) deterioration.
  • V F forward voltage
  • a SiC epitaxial wafer having no BPD in the SiC epitaxial layer and a BPD density of the SiC single crystal substrate of 400/cm 2 or less was used. Thus, the contribution of deterioration due to a defect expansion factor other than the large-pit defect was reduced.
  • a density of the large-pit defects caused by micropipes in the substrate in SiC epitaxial wafer of the present invention is preferably 0.5 defect/cm 2 or less.
  • a density of the large-pit defects caused by micropipes in the substrate in SiC epitaxial wafer means an area density obtained by dividing the counted number of large-pit defects identified as large pit defects caused by micropipes in the substrate by the unit area. Identification of the large-pit defects caused by micropipes in the substrate was described above. That is, the large-pit defect caused by micropipe in the substrate is observed as a pit in the SICA image of SiC epitaxial wafer using an adjacent SiC single crystal substrate in the same ingot, and is often observed as a bright circle (including oval shape, oblate shape, and so on) or a spider web (a core at the center and a string around it, a collection of strings, and so on) in the PL image.
  • a bright circle including oval shape, oblate shape, and so on
  • a spider web a core at the center and a string around it, a collection of strings, and so on
  • the inventor has found that the micropipe of the substrate, especially located at the peripheral edge portion of the substrate, is liable to crack during the growth of the SiC epitaxial layer.
  • a method of manufacturing a SiC epitaxial wafer according to an embodiment of the present invention is a method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a single crystal substrate, which includes a step of selecting a SiC single crystal substrate in which a total density of micropipes and substrate carbon inclusions in the SiC single crystal substrate is 1 defect/cm 2 or less.
  • a total density of micropipes and substrate carbon inclusions in the SiC single crystal substrate in the method of manufacturing a SiC epitaxial wafer means an area density obtained by dividing the total counted number of micropipes and substrate carbon inclusions in the SiC single crystal substrate by the unit area.
  • the micropipe and the substrate carbon inclusion in the SiC single crystal substrate are observed as a pit in the SICA image of the SiC single crystal substrate and as a dark spot in the PL image of the SiC single crystal substrate.
  • steps such as a step of polishing the substrate and a step of forming a SiC epitaxial layer can be performed under known conditions.
  • a SiC epitaxial wafer in which a total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, is 1 defect/cm 2 or less, can be manufactured.

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Abstract

A SiC epitaxial wafer includes a SiC epitaxial layer formed on a SiC single crystal substrate, in which a total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, is 1 defect/cm2 or less.

Description

    BACKGROUND OF THE INVENTION Field of the Invention
  • The present invention relates to a SiC epitaxial wafer and a method of manufacturing the same.
  • Priority is claimed on Japanese Patent Application No. 2019-020075 filed on Feb. 6, 2019, the content of which is incorporated herein by reference.
    • Background Art
  • Silicon carbide (SiC) has characteristics such as a dielectric breakdown electric field one order of magnitude larger, a band gap three times larger, and a thermal conductivity approximately three times higher than that of silicon (Si). Since silicon carbide has these characteristics, it is expected that the silicon carbide will be applied to power devices, high-frequency devices, high-temperature operating devices, and the like. For this reason, in recent years, SiC epitaxial wafers have been used for the above-described semiconductor devices.
  • In order to promote the practical application of SiC devices, it is essential to establish a high-quality crystal growth technique and a high-quality epitaxial growth technique.
  • SiC devices are generally manufactured using a SiC epitaxial wafer obtained by growing a SiC epitaxial layer (film) serving as an activated region of a device on a SiC single crystal substrate (may also be simply referred to as a SiC substrate), obtained by being processed from SiC bulk single crystal grown by sublimation recrystallization method or the like, through chemical vapor deposition (CVD) or the like.
  • More specifically, SiC epitaxial wafers are generally obtained by performing step flow growth (lateral growth from atomic steps) on a SiC single crystal substrate having a surface with an off-angle in a <11-20> direction from a (0001) plane as a growth surface to grow a 4H—SiC epitaxial layer.
  • As defects in the epitaxial layer of the SiC epitaxial wafer, defects that inherit defects in the SiC single crystal substrate and defects newly formed in the epitaxial layer are known. Threading dislocations, basal plane dislocations, carrot defects, and the like are known as the former, and triangular defects and the like are known as the latter.
  • For example, although a carrot defect is a rod-like defect which is long in the step-flow growth direction when viewed from the epitaxial surface side, it is said to be formed by using dislocations of the substrate (threading screw dislocations (TSD) or basal plane dislocations (BPD)) or scratches on the substrate as starting points (see Non-Patent Document 1).
  • Further, a triangular defect is formed toward a direction in such a manner that the apex of the triangle and the opposite side (base) thereof are aligned in order from the upstream to downstream side along the step-flow growth direction (<11-20> direction). The triangular defect is said to be a defect which is originated from the foreign matter (downfall) present on the SiC single crystal substrate before epitaxial growth at the time of manufacturing the SiC epitaxial wafer or within the epitaxial layer during epitaxial growth as a starting point, and which is exposed on the epitaxial surface by extending a 3C polymorphous layer along the off angle of the substrate (see Non-Patent Document 2).
  • Recently, large-pit defects caused by carbon inclusions in a SiC single crystal substrate (hereinafter sometimes referred to as “substrate carbon inclusions”) have been found (see Patent Document 1). The large-pit defects caused by substrate carbon inclusions are converted as new defects in the epitaxial layer from the substrate carbon inclusions in the SiC single crystal substrate as a starting point.
    • CITATION LIST Patent Documents
    • [Patent Document 1] Japanese Unexamined Patent Application, First Publication No. 2018-039714
    Non-Patent Documents
    • [Non-Patent Document 1] J. Hassan et al., Journal of Crystal Growth 312 (2010) 1828-1837
    • [Non-Patent Document 2] C. Hallin et al., Diamond and Related Materials 6 (1997) 1297-1300
    SUMMARY OF THE INVENTION
  • It is known that VF degradation (bipolar degradation) occurs when current is applied in a forward direction to an element configured to perform a bipolar operation, such as a pn diode or a parasitic diode (body diode) of a MOSFET which is manufactured using a SiC epitaxial wafer. The VF deterioration is a phenomenon in which, when current flows in the forward direction, the basal plane dislocation expands to a stacking fault (SF), which is a plane defect, and the stacking fault acts as a resistance, thereby causing an increase in the forward voltage (VF).
  • As a result of intensive studies, the present inventor has found for the first time that large-pit defects expand to stacking faults due to forward conduction and cause VF deterioration. It has been known that after a forward current is applied, a stacking fault is formed by expanding from a basal plane dislocation as a starting point. However, it has not been previously known that after a forward current is applied, a stacking fault is formed by expanding from a large-pit defect as a starting point. It is considered that the mechanism of formation of stacking faults originating from the large-pit defects involves dislocations extending in the direction of the basal plane accompanying the large-pit defects.
  • Both large-pit defects caused by substrate carbon inclusions and large-pit defects caused by micropipes in the substrate can be expanded and converted into stacking faults from the large-pit defects as a starting point after the forward conduction is applied.
  • Therefore, as a SiC epitaxial wafer for the SiC device, it is required to use a SiC epitaxial wafer having a reduced density of large-pit defects, and it is desirable to use a SiC epitaxial wafer having no large-pit defects.
  • The present invention has been made in view of the above-described problem, and an object thereof to provide a SiC epitaxial wafer in which VF deterioration is suppressed and a method of manufacturing the same.
  • The present invention provides the following means in order to solve the above-described problem.
  • (1) A SiC epitaxial wafer comprising a SiC epitaxial layer formed on a SiC single crystal substrate, wherein a total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, is 1 defect/cm2 or less.
  • (2) A SiC epitaxial wafer according to (1), wherein a density of the large-pit defects caused by micropipes in the substrate is 0.5 defect/cm2 or less.
  • (3) A method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a single crystal substrate, the method comprising
  • a step of selecting a SiC single crystal substrate in which a total density of micropipes and substrate carbon inclusions in the SiC single crystal substrate is 1 defect/cm2 or less.
  • The present invention can provide a SiC epitaxial wafer in which VF deterioration is suppressed.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic cross-sectional view of a SiC substrate wafer according to an embodiment of the present invention.
  • FIG. 2A is a SICA image of a SiC substrate wafer of the present invention.
  • FIG. 2B is a PL image corresponding to FIG. 2A.
  • FIG. 3 is a STEM image of a cross section in the vicinity of a large-pit defect caused by micropipes in the substrate.
  • FIG. 4 is a graph showing electrical characteristics of a pn diode manufactured using the SiC epitaxial wafer shown in FIG. 2 before and after a forward conduction test.
    •  PREFERRED EMBODIMENTS
  • Hereinafter, a SiC epitaxial wafer and a method of manufacturing the same according to an embodiment to which the present invention is applied will be described in detail with reference to the accompanying drawings. Meanwhile, in the drawings used in the following description, characteristic portions may be illustrated at an enlarged scale for convenience of easy understanding of characteristics, and the dimensional ratios and the like of the respective components are not necessarily the same as the actual ones. Further, in the following description, materials, dimensions, and the like are merely exemplary, do not limit the present invention, and can be appropriately modified within a range in which the effects of the present invention are exerted.
    • (SiC Epitaxial Wafer)
  • FIG. 1 illustrates a schematic cross-sectional view of a SiC epitaxial wafer according to an embodiment of the present invention.
  • A SiC epitaxial wafer 10 shown in FIG. 1 is a SiC epitaxial wafer comprising a SiC epitaxial layer 2 formed on a SiC single crystal substrate 1, wherein a total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer 2, is 1 defects/cm2 or less.
  • The SiC single crystal substrate used in the SiC epitaxial wafer of the present invention is preferably a 4H—SiC single crystal substrate.
  • The SiC single crystal substrate used in the SiC epitaxial wafer of the present invention preferably has an off angle. For example, it is preferable to use a SiC single crystal substrate having an off angle of 0.4° or more and 8° or less. Typically, a SiC single crystal substrate having an off angle of 4° can be used.
  • Although the thickness of the SiC single crystal substrate is not particularly limited, for example, a SiC single crystal substrate having a thickness of 150 μm or more and 550 μm or less can be used. Preferably, a SiC single crystal substrate having a thickness of 300 μm or more and 400 μm or less can be used.
  • Although the size of the SiC single crystal substrate is not particularly limited, for example, a SiC single crystal substrate with a size of 3 inches to 6 inches can be used.
  • In the present specification, the term “large-pit defect” refers to a defect having the following characteristics when an inspection apparatus (manufactured by Lasertec Corporation, SICA88) having both a confocal differential interference microscope and a photoluminescence (PL) observation function is used. In an obtained microscope image (hereinafter sometimes referred to as “SICA image”), the defect appears a dent or hole having a size (maximum distance when connecting two points on the outer circumference of the image with a straight line) of 5 μm or more. In addition, in a PL image obtained using a long-pass filter (≥660 nm), the defect appears bright with a size equal to or larger than the size in the microscope image.
  • Regarding smaller ones of defects that are pits or holes with a size of 5 μm or more and less than 10 μm in the SICA image and appear bright in the PL image at the same size or larger than the size in the microscope image, empirically, about 50% of the smaller ones is not due to substrate carbon inclusions or to micropipes in the substrate. In other words, about 50% of such defects are caused by substrate carbon inclusions or micropipes in the substrate.
  • Regarding defects that are pits or holes with a size of 10 μm or more and less than 15 μm in the SICA image and appear bright in the PL image at the same size or larger than the size in the microscope image, empirically, about 90% of the defects are caused by substrate carbon inclusions or micropipes in the substrate.
  • Regarding defects that are pits or holes with a size of 15 μm or more in the SICA image and appear bright in the PL image at the same size or larger than the size in the microscope image, empirically, about 100% of the defects are caused by substrate carbon inclusions or micropipes in the substrate.
  • As described above, based on the size of the dent or hole of the SICA image of the SiC epitaxial wafer and the size and appearance of the PL image of the dent or hole, the probability that the dent or hole is one of the large-pit defect caused by the substrate carbon inclusion and the large-pit defect caused by the micropipe in the substrate can be identified by the above probability.
  • By combining the SICA image and the PL image of the SiC epitaxial wafer with the SICA image and the PL image of the SiC single crystal substrate, large-pit defects caused by substrate carbon inclusions and large-pit defects caused by micropipes in the substrate can be distinguished with high probability. In the following, a method for performing the above will be described.
    • <A Method for Distinguishing Large-Pit Defects Caused by Micropipes in the Substrate and Large-Pit Defects Caused by Substrate Carbon Inclusions>
  • The cause of the large-pit defect in the SiC epitaxial layer of the SiC epitaxial wafer can be identified with high accuracy by comparing the SICA image and the PL image of the substrate carbon inclusions and micropipes in the SiC single crystal substrate with the SICA image and the PL image of the SiC epitaxial wafer.
  • In a case that a dark spot exists in the PL image of the SiC single crystal substrate, when a dark spot exists at almost the same position in a PL image of an adjacent SiC single crystal substrate in the same ingot as the SiC single crystal substrate, the dark spot can be identified as a micropipe in the substrate. As a result, a large-pit defect formed at a position corresponding to the dark spot on the SiC epitaxial wafer after forming an epitaxial layer can be identified as a large-pit defect caused by a micropipe in the substrate. The large-pit defect at this time is observed as a pit in the SICA image, and is often observed as a bright circle (including oval shape, oblate shape, and so on) or a spider web (a core at the center and a string around it, a collection of strings, and so on) in the PL image.
  • In a case that a pit exists in the SICA image of the SiC single crystal substrate and a dark spot exists in the PL image of the SiC single crystal substrate, when a dark spot does not exist at almost the same position in a PL image of an adjacent SiC single crystal substrate in the same ingot as the SiC single crystal substrate, the dark spot can be identified as a substrate carbon inclusion. As a result, a large-pit defect formed at a position corresponding to the dark spot on the SiC epitaxial wafer after forming an epitaxial layer can be identified as a large-pit defect caused by a substrate carbon inclusion. The large-pit defect at this time is observed as a pit in the SICA image, and is often observed as a bright circle (including oval shape, oblate shape, and so on) in the PL image.
  • Note that the observation of the cross section of the SiC epitaxial wafer with an electron microscope or the like also makes it possible to accurately distinguish large-pit defects caused by micropipes in the substrate from large-pit defects caused by substrate carbon inclusions.
  • In a SiC epitaxial wafer, if the total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions is 1 defect/cm2 or less, the SiC epitaxial wafer satisfies the specifications of a normal SiC device.
  • Here, the “large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions” in “the total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions” in SiC epitaxial wafers corresponds to defects having the following characteristics for each size. Regarding defects that are pits or holes with a size of 5 μm or more and less than 10 μm in the SICA image and appear bright in the PL image at the same size or larger than the size in the SICA image, it is assumed that 50% of the counted number of defects corresponds to the above-described defects. Regarding defects that are pits or holes with a size of 10 μm or more and less than 15 μm in the SICA image and appear bright in the PL image at the same size or larger than the size in the SICA image, it is assumed that 90% of the counted number of defects corresponds to the above-described defects. Regarding defects that are pits or holes with a size of 15 μm or more in the SICA image and appear bright in the PL image at the same size or larger than the size in the SICA image, it is assumed that all of the counted number of defects corresponds to the above-described defects. The sum of these defects is defined as the total number of the above-described defects. “The total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions” means an area density obtained by dividing the total number of the above defects by the unit area.
  • In a SiC epitaxial wafer, the total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions is preferably 0.1 defect/cm2 or less, it is more preferably 0.01 defect/cm2 or less, and it is even more preferably 0 defect/cm2 or less.
  • FIGS. 2A and 2B are a SICA image and a PL image of a SiC substrate wafer of the present invention. FIG. 2A is a SICA image and FIG. 2B is a PL image.
  • The SiC epitaxial wafer was manufactured as follows.
  • A 4-inch 4H—SiC single crystal substrate having an off angle of 4° in the <11-20> direction with respect to the (0001) Si plane was used as a SiC single crystal substrate.
  • A known polishing step was performed on the 4H—SiC single crystal substrate. Thereafter, the single crystal substrate was set in a CVD apparatus, and a step of cleaning (etching) the single crystal substrate surface with hydrogen gas was performed. Next, a SiC epitaxial growth step was performed under the conditions of a growth temperature of 1500° C. or more and a C/Si ratio of 1.25 or less while using silane and propane as source gases and supplying hydrogen as a carrier gas. Thus, a 10 μm-thick SiC epitaxial layer was formed on the SiC single crystal substrate to obtain a SiC epitaxial wafer.
  • The large-pit defect in the SiC epitaxial wafer shown in FIG. 2 has a circular shape with a diameter of about 15 μm in the SICA image and a circular shape with a diameter of about 20 to 30 μm in the PL image. An SICA image was obtained on the surface of the 4H—SiC single crystal substrate before the formation of the SiC epitaxial layer. It was confirmed by a cross-sectional analysis that this large-pit defect was a large-pit defect caused by a micropipe in the substrate.
  • FIG. 3 is an image obtained by observing the cross section of the large-pit defect using a scanning transmission electron microscope (STEM). The scale indicates 0.6 μm on each scale.
  • The STEM image shown in FIG. 3 is an example. In the STEM image, a micropipe is visible in the substrate located below. Further, dislocations extending from the micropipe in the substrate are present, and large-pit defects (FIG. 2) are visible on the surface located at the tip of the dislocation. Thus, the STEM image shown in FIG. 3 clearly shows that the large-pit defect on the surface of the epitaxial layer is a large-pit defect caused by the micropipe in the substrate. Dislocations are present between the micropipe in the substrate and the large-pit defects on the surface, as shown in FIG. 3. Some of these dislocations extend along the basal plane in addition to those extending toward the surface. The dislocations extending along the basal plane expand into stacking faults when forward current is applied, causing VF degradation.
  • A pn diode was produced by a known method using the SiC epitaxial wafer shown in FIG. 2. FIG. 4 shows the results of measuring the electrical characteristics in the forward direction before and after the current was passed through the pn diode at 960 A/cm2 for 1 hour. It was confirmed that this current test resulted in a 3.4% forward voltage (VF) deterioration. At this time, a SiC epitaxial wafer having no BPD in the SiC epitaxial layer and a BPD density of the SiC single crystal substrate of 400/cm2 or less was used. Thus, the contribution of deterioration due to a defect expansion factor other than the large-pit defect was reduced.
  • A density of the large-pit defects caused by micropipes in the substrate in SiC epitaxial wafer of the present invention is preferably 0.5 defect/cm2 or less.
  • Here, “a density of the large-pit defects caused by micropipes in the substrate” in SiC epitaxial wafer means an area density obtained by dividing the counted number of large-pit defects identified as large pit defects caused by micropipes in the substrate by the unit area. Identification of the large-pit defects caused by micropipes in the substrate was described above. That is, the large-pit defect caused by micropipe in the substrate is observed as a pit in the SICA image of SiC epitaxial wafer using an adjacent SiC single crystal substrate in the same ingot, and is often observed as a bright circle (including oval shape, oblate shape, and so on) or a spider web (a core at the center and a string around it, a collection of strings, and so on) in the PL image.
  • The inventor has found that the micropipe of the substrate, especially located at the peripheral edge portion of the substrate, is liable to crack during the growth of the SiC epitaxial layer.
  • It is feared that even those which did not crack during the growth of the SiC epitaxial layer were liable to crack in subsequent device fabrication. However, if the density of large-pit defects caused by micropipes in the substrate is 10 defects/cm2 or less, the fear is eliminated.
    • (Method of Manufacturing a SiC Epitaxial Wafer)
  • A method of manufacturing a SiC epitaxial wafer according to an embodiment of the present invention is a method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a single crystal substrate, which includes a step of selecting a SiC single crystal substrate in which a total density of micropipes and substrate carbon inclusions in the SiC single crystal substrate is 1 defect/cm2 or less.
  • Here, “a total density of micropipes and substrate carbon inclusions in the SiC single crystal substrate” in the method of manufacturing a SiC epitaxial wafer means an area density obtained by dividing the total counted number of micropipes and substrate carbon inclusions in the SiC single crystal substrate by the unit area. The micropipe and the substrate carbon inclusion in the SiC single crystal substrate are observed as a pit in the SICA image of the SiC single crystal substrate and as a dark spot in the PL image of the SiC single crystal substrate.
  • Other steps such as a step of polishing the substrate and a step of forming a SiC epitaxial layer can be performed under known conditions.
  • According to the method of manufacturing a SiC epitaxial wafer having a selecting step, a SiC epitaxial wafer, in which a total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, is 1 defect/cm2 or less, can be manufactured.

Claims (3)

What is claimed is:
1. A SiC epitaxial wafer comprising a SiC epitaxial layer formed on a SiC single crystal substrate,
wherein a total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, is 1 defect/cm2 or less.
2. A SiC epitaxial wafer according to claim 1,
wherein a density of the large-pit defects caused by micropipes in the substrate is 0.5 defect/cm2 or less.
3. A method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a single crystal substrate, the method comprising:
a step of selecting a SiC single crystal substrate in which a total density of micropipes and substrate carbon inclusions in the SiC single crystal substrate is 1 defect/cm2 or less.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200321437A1 (en) * 2019-04-05 2020-10-08 Mitsubishi Electric Corporation Silicon carbide epitaxial wafer, method for manufacturing silicon carbide epitaxial wafer, and power converter

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007269627A (en) 2002-03-19 2007-10-18 Central Res Inst Of Electric Power Ind METHOD FOR MANUFACTURING SIC CRYSTAL TO REDUCE MICROPIPE PROPAGATING FROM SUBSTRATE AND SiC CRYSTAL, SiC SINGLE CRYSTAL FILM, SiC SEMICONDUCTOR ELEMENT, SiC SINGLE CRYSTAL SUBSTRATE AND ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SiC BULK CRYSTAL
US7201799B1 (en) * 2004-11-24 2007-04-10 Kla-Tencor Technologies Corporation System and method for classifying, detecting, and counting micropipes
CN101536168A (en) * 2006-09-14 2009-09-16 科锐有限公司 Micropipe-free silicon carbide and related method of manufacture
KR101731239B1 (en) * 2012-04-20 2017-04-28 투-식스 인코포레이티드 LARGE DIAMETER, HIGH QUALITY SiC SINGLE CRYSTALS, METHOD AND APPARATUS
JP2015040146A (en) 2013-08-22 2015-03-02 三菱電機株式会社 Single crystal production device and single crystal production method using the same
JP5854013B2 (en) * 2013-09-13 2016-02-09 トヨタ自動車株式会社 Method for producing SiC single crystal
JP6493690B2 (en) 2016-08-31 2019-04-03 昭和電工株式会社 SiC epitaxial wafer, manufacturing method thereof, large pit defect detection method, defect identification method
JP6459132B2 (en) 2016-08-31 2019-01-30 昭和電工株式会社 SiC epitaxial wafer, manufacturing method thereof, and defect identification method
JP2019020075A (en) 2017-07-20 2019-02-07 日立アプライアンス株式会社 refrigerator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Kubota, T., Talekar, P., Ma, X. et al. "A nondestructive automated defect detection system for silicon carbide wafers" Machine Vision and Applications 16, 170–176 (2005) (Year: 2005) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200321437A1 (en) * 2019-04-05 2020-10-08 Mitsubishi Electric Corporation Silicon carbide epitaxial wafer, method for manufacturing silicon carbide epitaxial wafer, and power converter

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