US20200235098A1 - Vertically-integrated two-dimensional (2d) semiconductor slabs in complementary field effect transistor (cfet) cell circuits, and method of fabricating - Google Patents
Vertically-integrated two-dimensional (2d) semiconductor slabs in complementary field effect transistor (cfet) cell circuits, and method of fabricating Download PDFInfo
- Publication number
- US20200235098A1 US20200235098A1 US16/255,008 US201916255008A US2020235098A1 US 20200235098 A1 US20200235098 A1 US 20200235098A1 US 201916255008 A US201916255008 A US 201916255008A US 2020235098 A1 US2020235098 A1 US 2020235098A1
- Authority
- US
- United States
- Prior art keywords
- slabs
- drain
- source
- end portions
- slab
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 113
- 230000000295 complement effect Effects 0.000 title claims abstract description 17
- 230000005669 field effect Effects 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 61
- 239000000463 material Substances 0.000 claims abstract description 177
- 239000010410 layer Substances 0.000 claims description 267
- 238000000034 method Methods 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 17
- 230000006854 communication Effects 0.000 claims description 12
- 238000004891 communication Methods 0.000 claims description 12
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052982 molybdenum disulfide Inorganic materials 0.000 claims description 10
- 150000003624 transition metals Chemical class 0.000 claims description 9
- 229910052723 transition metal Inorganic materials 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- ITRNXVSDJBHYNJ-UHFFFAOYSA-N tungsten disulfide Chemical compound S=[W]=S ITRNXVSDJBHYNJ-UHFFFAOYSA-N 0.000 claims description 3
- 230000001413 cellular effect Effects 0.000 claims description 2
- 230000000977 initiatory effect Effects 0.000 claims description 2
- 108091006146 Channels Proteins 0.000 abstract description 179
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract description 12
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract description 11
- 229910052751 metal Inorganic materials 0.000 description 37
- 239000002184 metal Substances 0.000 description 37
- 239000011295 pitch Substances 0.000 description 20
- 125000006850 spacer group Chemical group 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 238000002955 isolation Methods 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 14
- 230000008569 process Effects 0.000 description 13
- 238000000151 deposition Methods 0.000 description 12
- 230000009467 reduction Effects 0.000 description 10
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 239000008186 active pharmaceutical agent Substances 0.000 description 7
- 230000010354 integration Effects 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 150000001787 chalcogens Chemical group 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052711 selenium Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052717 sulfur Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- -1 MX2 compound Chemical class 0.000 description 1
- 230000007175 bidirectional communication Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8256—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252 and H01L21/8254
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Definitions
- CMOS complementary metal-oxide semiconductor
- MOS complementary metal-oxide semiconductor
- Transistors are essential and employed in large numbers in integrated circuit (IC) components.
- components such as central processing units (CPUs) and memory systems each employ a large quantity of transistors for logic circuits and memory devices.
- Transistors are formed of semiconductor materials and may be identified as one of an N-type or a P-type depending on whether the semiconductor material in a channel region of the transistor is an n-type or a p-type channel, which determines whether the majority carriers for current flow are electrons or holes.
- a Field-Effect Transistor (FET) is a transistor technology widely used in logic circuits and memory devices.
- a metal-oxide semiconductor (MOS) FET may be one of a P-type or an N-type, and is referred to as a PMOS FET (PFET) and an NMOS FET (NFET).
- PFET PMOS FET
- NFET NMOS FET
- Forming logic circuits and memory devices of PFETs and NFETs coupled together in a complementary configuration provides improved performance, power reduction, and resistance to noise in comparison to designs of either NFET or PFET circuits alone.
- Such complementary configurations are known as complementary MOS (CMOS) circuits.
- CMOS complementary MOS
- Design automation tools are able to generate physical layouts of circuits in which the standardized CMOS circuits are optimally positioned to minimize a total circuit area.
- Such standardized CMOS circuits are known as standard cells and may also be referred to herein as cell circuits.
- a physical layout of a CMOS cell circuit which may also be referred to as a “standard cell,” includes at least one PMOS transistor and at least one NMOS transistor for forming logic gates as well as internal interconnects of the PMOS and NMOS transistors, and contacts for external interconnection to power, ground, and other circuits.
- the physical layout of the elements of the CMOS cell circuit determines a total area or footprint occupied by a CMOS cell circuit.
- a gate length in the direction of current flow in the channel structure may be reduced.
- problems such as leakage currents and on/off control.
- gate length scaling is reaching a physical limitation due to a quantum tunneling effect.
- FinFET devices and Gate-All-Around (GAA) devices have been developed with gates that at least partially surround a semiconductor channel forming a channel region to apply an electric field to a larger surface area of the channel region than in planar FETs.
- FIG. 1 illustrates a top view of a layout 100 as an example of a conventional CMOS standard cell 102 (also referred to as “standard cell 102 ”) employing FinFETs.
- FinFETs are a transistor technology in which a semiconductor channel is provided in a fin structure extending vertically above the substrate, making it possible to increase a cross-sectional area of current flow without increasing a horizontal area.
- the standard cell 102 includes gates 104 ( 1 )- 104 ( 4 ) disposed along respective, parallel longitudinal axes A 1 Y ( 1 )-A 1 Y ( 4 ) in a first direction 106 of the Y-axis with a defined gate pitch G.
- the standard cell 102 includes a first voltage rail 108 configured to be coupled to a supply voltage.
- the first voltage rail 108 is disposed along a longitudinal axis A 1 X ( 1 ) in a second direction 110 of the X-axis substantially orthogonal to the first direction 106 in a first metal layer 112 (e.g., a metal zero (M0) metal layer).
- the standard cell 102 includes a second voltage rail 114 having a longitudinal axis A 1 X ( 2 ) in the second direction 110 in the first metal layer 112 .
- the standard cell 102 also includes diffusion regions 116 P, 116 N of P-type doped and N-type doped semiconductor materials, respectively, for forming active devices that include semiconducting materials, such as transistors.
- the standard cell 102 also includes fins 118 ( 1 )- 118 ( 4 ) for forming semiconductor channels of FinFETs disposed in the second direction 110 between the first and second voltage rails 108 , 114 .
- a first FinFET 120 N formed in the P-type diffusion region 116 P will include two fins 118 ( 1 ), 118 ( 2 ) to form its semiconductor channel
- a second FinFET 120 P formed in the N-type diffusion region 116 N will include two fins 118 ( 3 ), 118 ( 4 ) to form its semiconductor channel.
- the gate 104 ( 3 ) is disposed on a top surface and both side surfaces of each of the fins 118 ( 1 )- 118 ( 4 ) for improved current flow control.
- Trench contacts 122 ( 1 )- 122 ( 3 ) are also formed in the first direction 106 to provide contacts to source/drain regions S( 1 )-S( 4 ), D( 1 )-D( 4 ) of the fins 118 ( 1 )- 118 ( 4 ) formed in the standard cell 102 .
- Trench contact 122 ( 1 ) has been cut.
- a metal line 124 ( 1 ) can be formed in the first metal layer 112 to provide an interconnection to the trench contact 122 ( 1 ) to provide interconnections to the source or drain region S( 1 ), D( 1 ).
- Vias (V 1 ) 126 ( 1 ), 126 ( 2 ) can be formed over portions of the gates 104 ( 1 )- 104 ( 4 ) to form metal contacts to the gates 104 ( 1 )- 104 ( 4 ).
- a dimension of the standard cell 102 in the Y-axis direction includes dimensions of the P-type diffusion region 116 P, the N-type diffusion region 116 N, and a non-diffusion region between the N-type and P-type diffusion regions 116 P and 116 N.
- the FinFETs 120 N, 120 P in the standard cell 102 in FIG. 1 each have two (2) respective fins 118 ( 1 )- 118 ( 2 ) and 118 ( 3 )- 118 ( 4 ) to serve as channel structures.
- a Y-axis dimension of a conventional CMOS standard cell may be minimized by employing a FinFET with only one fin in each of the P-type diffusion region 116 P and the N-type diffusion region 116 N, and further advancements in technology have made it possible to fabricate standard cells that support FinFETs employing a single fin for a channel structure.
- a CMOS standard cell layout for single-fin FinFETs can occupy less area than the standard cell 102 in FIG. 1 for example, which can reduce total chip size and the number of internal interconnections required.
- a dimension of a standard cell layout in the Y-axis direction remains constant but dimensions of cells vary in the X-axis direction. Reducing the Y-axis dimension of standard cells can significantly reduce layout size.
- the Y-axis dimension is dominated by a metal line pitch in the first and second metal layers (M0, M1), which are used for transistor contacts for routing power and signals, M0/M1 pitch scaling is an important factor in determining a minimum layout size but benefits of scaling M0/M1 pitch are limited by fin pitch, contact location/pitch and minimum routing requirements.
- M0, M1 pitch scaling is an important factor in determining a minimum layout size but benefits of scaling M0/M1 pitch are limited by fin pitch, contact location/pitch and minimum routing requirements.
- a dimension of the standard cell 102 includes a length of a gate region along the longitudinal axes A 1 Y ( 1 )-A 1 Y ( 4 ) of the fins 118 ( 1 )- 118 ( 4 ).
- a length of a gate region may be reduced.
- leakage currents become difficult to control, despite the increased current flow control made possible by multi-faceted gates employed in FinFETs and GAA FETs. Further gate length scaling will be limited as physical limitations are reached.
- An exemplary CFET cell circuit includes an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of vertically-stacked elongated slabs of 2D semiconductor material to provide a footprint reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit.
- the CFET cell circuit may include a complementary metal-oxide semiconductor (CMOS) circuit in an integrated circuit structure with an N-type semiconductor channel structure of an N-type FET (NFET) in a first layer and a P-type semiconductor channel structure of a P-type FET (PFET) in a second layer stacked vertically above the first layer to reduce a Y-axis dimension of the horizontal footprint of the CFET cell circuit.
- CMOS complementary metal-oxide semiconductor
- NFET N-type FET
- PFET P-type FET
- the horizontal footprint of the (TEE cell circuit may also be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type semiconductor channel structures.
- the N-type and P-type semiconductor channel structures may be formed of vertically-stacked layers of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current.
- the 2D semiconductor materials may be MX 2 -type compounds (e.g., transition metal dichalcogenides) formed in elongated 2D atomic monolayers, each capable of conducting an amount of current.
- a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.
- a CFET cell circuit in an aspect, includes a substrate, a lower circuit layer, and an upper circuit layer.
- the lower circuit layer includes an NFET that is disposed above the substrate and includes a lower channel structure and a lower gate.
- the lower channel structure includes a first two-dimensional (2D) semiconductor slab of a first type vertically integrated with a second 2D semiconductor slab of the first type. Each of the first and second 2D slabs has a longitudinal axis in a first direction.
- the lower channel structure also includes a lower source/drain region integrated with first end portions of the first and second 2D slabs, and a lower drain/source region integrated with second end portions of the first and second 2D slabs.
- the lower gate is disposed on faces of the first and second 2D slabs between the lower source/drain region and the lower drain/source region.
- the upper circuit layer includes a PFET that is disposed above the lower circuit layer and includes an upper channel structure and an upper gate.
- the upper channel structure includes a third 2D semiconductor slab of a second type vertically integrated with a fourth 2D semiconductor slab of the second type. Each of the third and fourth 2D slabs has a longitudinal axis in a second direction.
- the upper channel structure also includes an upper source/drain region integrated with first end portions of the third and fourth 2D slabs, and an upper drain/source region integrated with second end portions of the third and fourth 2D slabs.
- the upper gate is disposed on faces of the third and fourth 2D slabs between the lower source/drain region and the lower drain/source region.
- a method of fabricating a CFET cell circuit includes forming a lower circuit layer including an NFET above a substrate, and forming an upper circuit layer including a PE ET above the lower circuit layer.
- Forming the lower circuit layer includes vertically stacking a first 2D slab and a second 2D slab to form a lower semiconductor channel structure for the NFET, with the first and second 2D slabs each having a longitudinal axis and including a semiconductor material of a first type.
- Forming the lower circuit layer further includes disposing a lower gate of the NFET on faces of the first and second 2D slabs.
- Forming the lower circuit layer further includes integrating a lower source/drain material with first end portions of the first and second 2D slabs to form a lower source/drain region of the NFET on a first side of the lower gate, and integrating a lower drain/source material with second end portions of the first and second 2D slabs to form a lower drain/source region of the NFET on a second side of the lower gate.
- Forming the upper circuit layer includes vertically stacking a third 2D slab and a fourth 2D slab to form an upper semiconductor channel structure of the PFET, with the third and fourth 2D slabs each having a longitudinal axis and including a semiconductor material of a second type.
- Forming the upper circuit layer further includes disposing an upper gate of the PET on faces of the third and fourth 2D slabs. Forming the upper circuit layer further includes integrating an upper source/drain material with first end portions of the third and fourth 2D slabs to form an upper source/drain region of the PFET on a first side of the upper gate, and integrating an upper drain/source material with second end portions of the third and fourth 2D slabs to form an upper drain/source region of the PFET on a second side of the upper gate.
- FIG. 1 is a top view of a conventional complementary metal-oxide semiconductor (CMOS) cell circuit layout including a P-type metal oxide semiconductor (MOS) (PMOS) Fin Field-Effect Transistor (FET) (FinFET) and an N-type MOS (NMOS) FinFET laterally disposed on a semiconductor layer;
- CMOS complementary metal-oxide semiconductor
- FIG. 2A is a cross-sectional side view in a first direction of an exemplary Complementary FET (CFET) cell circuit with a lower circuit layer including an N-type FET (NFET) disposed above a substrate, the NFET including a lower channel structure formed of vertically-integrated 2D semiconductor slabs of a first type, and an upper circuit layer including a P-type FET (PFET) disposed above the lower circuit layer, the PFET including an upper channel structure formed of vertically-integrated 2D semiconductor slabs of a second type to reduce the footprint size of the CFET cell circuit;
- CFET Complementary FET
- FIG. 2B is a cross-sectional side view of the CFET cell circuit shown in FIG. 2A in a second direction orthogonal to the first direction in FIG. 2A ;
- FIGS. 2C-1 and 2C-2 are top views of the lower circuit layer of the CFET cell circuit shown in FIGS. 2A and 2B , which includes an NFET disposed on a substrate, and the upper circuit layer including a PFET disposed on the lower circuit layer during fabrication;
- FIG. 2D is a top view of the lower and upper circuit layers of the CFET cell circuit in FIGS. 2C-1 and 2C-2 , respectively, forming the CFET cell circuit in FIGS. 2A and 2B ;
- FIG. 3 is a flowchart illustrating an exemplary process for fabricating the lower and upper circuit layers that include the respective NFET and PFET in the CFET cell circuit in FIGS. 2A-2D ;
- FIG. 4A is a cross-sectional side view of a first exemplary fabrication stage for fabricating the CFET cell circuit in FIGS. 2A-2D , in which a first plurality of vertically-stacked 2D slabs, each having a first semiconductor type, is disposed above a substrate, according to the exemplary fabrication process in FIG. 3 ;
- FIG. 4B is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D of an exemplary dummy gate disposed on a lower gate region of a first plurality of vertically-integrated 2D slabs;
- FIG. 4C is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which oxide layers between first end portions and second end portions of the first plurality of vertically-integrated 2D slabs are removed, and side spacers are formed on sides of the dummy gate and sides of the lower gate region;
- FIG. 4D is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit shown in FIGS. 2A-2D in which an inter-layer dielectric (ILD) is formed between the first end portions and the second end portions of the first plurality of vertically-integrated 2D slabs, and the first plurality of vertically-integrated 2D slabs is covered with a mask layer;
- ILD inter-layer dielectric
- FIG. 4E is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which an opening is formed in the mask layer to allow deposition of high-k dielectric material and gate metal on faces of the first plurality of vertically-integrated 2D slabs to form a lower gate in the lower gate region, according to the fabrication process in FIG. 3 ;
- FIG. 4F is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which the ILD between the first end portions and second end portions of the first plurality of vertically-integrated 2D slabs is removed and replaced by NMOS source/drain material to form a lower source/drain region and a lower drain/source region, according to the fabrication process in FIG. 3 ;
- FIG. 4G is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which ILD is deposited above the first plurality of vertically-integrated 2D slabs, and contacts to the lower source/drain region and lower drain/source region are formed in the ILD, according to the fabrication process in FIG. 3 ;
- FIG. 4H is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which ILD is disposed on the first plurality of vertically-integrated 2D slabs to form a lower circuit layer, and a second plurality of vertically-stacked 2D slabs, each having a second semiconductor type, is disposed above the lower circuit layer, according to the fabrication process in FIG. 3 ;
- FIG. 4I is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which an exemplary dummy gate is disposed on an upper gate region of the second plurality of vertically-integrated 2D slabs;
- FIG. 4K is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which oxide layers between first end portions and second end portions of the second plurality of vertically-integrated 2D slabs are removed, and side spacers are formed on sides of the dummy gate and sides of the upper gate region;
- FIG. 4K is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which ILD is formed between the first end portions and the second end portions of the second plurality of vertically-integrated 2D slabs, and the second plurality of vertically-integrated 2D slabs is covered with a mask layer;
- FIG. 4L is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which an opening is formed in the mask layer in FIG. 4K to allow deposition of high-k dielectric material and gate metal on faces of the second plurality of vertically-integrated 2D slabs to form an upper gate in the upper gate region, according to the fabrication process in FIG. 3 ;
- FIG. 4M is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which the ILD between the first end portions and second end portions of the second plurality of vertically-integrated 2D slabs is removed and replaced by PMOS source/drain material to form an upper source/drain region and an upper drain/source region, according to the fabrication process in FIG. 3 ;
- FIG. 4N is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which ILD is deposited above the second plurality of vertically-integrated 2D slabs, and contacts to the upper source/drain region and upper drain/source region are formed in the ILD;
- FIG. 4O is a cross-sectional side view in an another exemplary fabrication stage of the CFET cell circuit in FIGS. 2A-2D in which additional ILD is deposited above the contacts to the upper source/drain region and the upper drain/source region, and metal interconnects coupled to the contacts are formed in the additional ILD;
- FIG. 5A is a cross-sectional side view in a first direction of another exemplary CFET cell circuit with a lower circuit layer including a PFET disposed above a substrate, the NTT including a lower channel structure formed of vertically-integrated 2D semiconductor slabs of a first type, and an upper circuit layer including an NFET disposed above the lower circuit layer, the NFET including an upper channel structure formed of vertically-integrated 2D semiconductor slabs of a second type to reduce the footprint size of the CFET cell circuit;
- FIG. 5B is a cross-sectional side view of the CFET cell circuit shown in FIG. 5A in a second direction orthogonal to the first direction in FIG. 5A ;
- FIGS. 5C-1 and 5C-2 are top views of the lower circuit layer of the CFET′ cell circuit shown in FIGS. 5A and 5B , which includes a PFET disposed on a substrate, and the upper circuit layer including an NFET disposed on the lower circuit layer during fabrication;
- FIG. 5D is a top view of the lower and upper circuit layers of the CFET cell circuit in FIGS. 5C-1 and 5C-2 , respectively, forming the CFET cell circuit in FIGS. 5A and 5B ;
- FIG. 6 is a block diagram of an exemplary processor-based system that can include a CFET cell circuit in which a PFET and an NFET are vertically integrated by stacking a second semiconductor layer that includes a second FET above a first semiconductor layer that includes a first FET, such that the channel structure of the second FET is formed above the channel structure of the first FET to reduce a footprint of a CFET cell circuit including, but not limited to, the CFET cell circuits in FIGS. 2A-2D and 5A-5D ; and
- FIG. 7 is a block diagram of an exemplary wireless communications device that includes radio frequency (RF) components formed from an integrated circuit (IC), wherein any of the components therein can include a CFET cell circuit including, but not limited to, the CFET cell circuits in FIGS. 2A-2D and 5A-5D .
- RF radio frequency
- An exemplary CFET cell circuit includes an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of vertically-stacked elongated slabs of 2D semiconductor material to provide a footprint reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit.
- the CFET cell circuit may include a complementary metal-oxide semiconductor (CMOS) circuit in an integrated circuit structure with an N-type semiconductor channel structure of an N-type FET (NFET) in a first layer and a P-type semiconductor channel structure of a P-type FET (PFET) in a second layer stacked vertically above the first layer to reduce a Y-axis dimension of the horizontal footprint of the CFET cell circuit.
- CMOS complementary metal-oxide semiconductor
- NFET N-type FET
- PFET P-type FET
- the horizontal footprint of the CFET cell circuit may also be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type semiconductor channel structures.
- the N-type and P-type semiconductor channel structures may be formed of vertically-stacked layers of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current.
- the 2D semiconductor materials may be MX 2 -type compounds (e.g., transition metal dichalcogenides) formed in elongated 2D atomic monolayers, each capable of conducting an amount of current.
- a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.
- a CFET cell circuit may include an NFET vertically-integrated with a PFET in a complementary configuration (e.g., as a CMOS circuit).
- the disclosed CFET cell circuit is provided in an integrated circuit structure including an N-type channel structure and a P-type channel structure stacked vertically to reduce a horizontal footprint.
- FIG. 2A illustrates a cross-sectional side view of a of a CFET cell circuit 200 in the Z-axis and Z-axis shown therein. The cross-sectional view shown in FIG. 2A is taken along the line X-X′ shown in a top view of the CFET cell circuit 200 illustrated in FIG.
- the CFET cell circuit 200 includes an upper circuit layer 202 U with a PFET 204 P disposed vertically above (i.e., stacked above) a lower circuit layer 202 L with an NFET 204 N. In this manner, the vertical stacking reduces the horizontal footprint of the CFET cell circuit 200 in the Y-axis direction.
- the NFET 204 N and the PFET 204 P may be interconnected in a complementary configuration, as in a CMOS circuit.
- an X-axis dimension of a footprint of the CFET cell circuit 200 may be reduced by reducing length dimensions of the NFET 204 N and the PFET 204 P.
- the NFET 204 N in the lower circuit layer 202 L is formed in a lower channel structure 206 L in which a gate region 208 L has a length dimension LG L in the X-axis direction
- the PFET 204 P in the upper circuit layer 202 U is formed in an upper channel structure 206 U in which a gate region 208 U has a length dimension LG U in the X-axis direction.
- MX 2 -type compounds e.g., transition metal dichalcogenide crystals
- 2D materials transition metal dichalcogenide crystals
- the lower circuit layer 202 L includes the NFET 204 N
- the upper circuit layer 202 U includes the PFET 204 P.
- the NFET 204 N is disposed on an isolation layer 207 L above a substrate 209 .
- the lower channel structure 2061 _ includes a first 2D semiconductor slab (“2D slab”) 210 N( 1 ) of the 2D material vertically integrated with a second 2D slab 210 N( 2 ).
- a “slab” is a structure formed of one or more layers of a 2D material, with first and second dimensions in orthogonal directions (e.g., X-axis and Y-axis directions) and having a thickness dimension which is orthogonal to the first and second dimensions (e.g., Z-axis direction) and is smaller than the first and second dimensions.
- first and second dimensions in orthogonal directions (e.g., X-axis and Y-axis directions) and having a thickness dimension which is orthogonal to the first and second dimensions (e.g., Z-axis direction) and is smaller than the first and second dimensions.
- the 2D slabs 210 N( 1 ) and 210 N( 1 ) may each extend in a range from 20 nm to 500 nm in a longitudinal direction (e.g., X-axis direction), and extend in a range from 3 nm to 50 nm in a direction orthogonal to the longitudinal direction (e.g., Y-axis direction).
- the 2D slabs 210 N( 1 ) and 210 N( 2 ) have a thickness dimension, which may be in the range from 0.6 nm to 10.0 nm.
- 2A may also include additional 2D slabs, such as 2D slab 210 N( 3 ), vertically integrated with the first and second 2D slabs 210 N( 1 ) and 210 N( 2 ) to increase a drive strength of the NFET 204 N.
- additional 2D slabs such as 2D slab 210 N( 3 )
- the slab structures in FIG. 2A may appear to be planar, stackable slabs having other (e.g., non-planar) shapes are within the scope of the present disclosure.
- Each of the 2D slabs 210 N( 1 )- 210 N( 3 ) includes at least one monolayer (not individually shown) of a first type of 2D semiconductor material 218 ( 1 ), such as an N-type material 218 N, extending in the X-axis direction and the Y-axis direction.
- 2D materials are atomically thin semiconductor monolayers of an MX 2 compound, where M is a transition metal atom (Mo, W, etc.) and X is a chalcogen atom (S, Se, or Te).
- the N-type material 218 N may be tungsten disulfide (WS 2 ).
- Crystal monolayers of MX 2 compounds have a high carrier mobility, lower dielectric constant, and thinner channel thickness than silicon, providing strong on/off control of the channel. Therefore, a channel structure formed of MX 2 compounds may have higher drive strength and lower leakage current than a similarly-sized silicon channel structure.
- channel control in the lower gate region 208 L is improved over a channel region of the same length in a channel structure formed of silicon.
- the length LG L of the lower gate region 208 L may be made smaller to reduce a dimension of the CFET cell circuit 200 in the X-axis direction without a causing an increase in leakage current in the NFET 204 N.
- the 2D slabs 210 N( 1 )- 210 N( 3 ) extend along respective longitudinal axes A 2 L ( 1 )-A 2 L ( 3 ) and may be integrated by stacking in a vertical (e.g., Z-axis) direction one above another.
- the lower channel structure 206 L also includes a lower source/drain material 221 L integrated with first end portions 216 LS( 1 )- 216 LS( 3 ) of the 2D slabs 210 N( 1 )- 210 N( 3 ) for forming a lower source/drain region 214 LS and the lower source/drain material 221 L integrated with second end portions 216 LD( 1 )- 216 LD( 3 ) of the 2D slabs 210 N( 1 )- 210 N( 3 ) to form a lower drain/source region 214 LD.
- the lower source/drain material 221 L of the lower source/drain region 214 LS and the lower drain/source region 214 LD may be formed on faces of the 2D slabs 210 N( 1 )- 210 N( 3 ), except where the 2D slab 210 N( 1 ) is in contact with the isolation layer 2071 .
- the lower source/drain material 221 L may be formed on top face 220 LT, bottom face 220 LB, side face 220 LS, and end faces 220 LE of 2D slab 210 N( 2 ) in the first and second end portions 216 LS( 2 ) and 216 LD( 2 ).
- the lower source/drain material 221 L may be similarly formed on faces of 2D slabs 210 N( 1 ) and 210 N( 3 ), as shown in FIG. 2A .
- the lower channel structure 206 L includes a lower gate 222 L disposed on faces of the 2D slabs 210 N( 1 )- 210 N( 3 ), such as the faces 220 LT, 220 LB, and 220 LS of 2D slab 210 N( 2 ).
- the lower gate 222 L is disposed on the 2D slabs 210 N( 1 )- 210 N( 3 ) between the lower source/drain region 214 LS and the lower drain/source region 214 LD in the X-axis direction.
- the lower gate 222 L is separated from the lower source/drain region 214 LS by side spacer 224 LS and separated from the lower drain/source region 214 LD by side spacer 224 LD.
- the lower gate 222 L includes gate portions 225 L electrically insulated from the respective 2D slabs 210 N( 1 )- 210 N( 3 ) by gate dielectric layers 226 L.
- the lower gate 222 L also includes a lower field gate 227 L (shown in FIG.
- the lower circuit layer 202 L also includes trench contacts 230 LS and 230 LD formed above the lower source/drain region 214 LS and the lower drain/source region 214 LD, respectively.
- An inter-layer dielectric (ILD) 228 L surrounds the MET 204 N, the lower field gate 227 L and the trench contacts 230 LS and 230 LD.
- the lower field gate 227 L and the trench contacts 230 LS and 230 LD are discussed further with respect to FIG. 2B , below.
- the CFET cell circuit 200 in FIG. 2A also includes the upper circuit layer 202 U disposed above the lower circuit layer 202 L that includes the PFET 204 P to provide a CMOS architecture for the CFET cell circuit 200 .
- the upper circuit layer 202 U of the CFET cell circuit 200 will now be discussed.
- the upper circuit layer 202 U includes the PFET 204 P disposed on an isolation layer 207 U.
- the PFET 204 P is formed in an upper channel structure 206 U including a third 2D slab 210 P( 1 ) vertically integrated with a fourth 2D slab 210 P( 2 ).
- each of the 2D slabs 2101 )( 1 )- 210 P( 3 ) includes at least one monolayer (not individually shown) of a second 2D semiconductor material 218 ( 2 ) (e.g., MX 2 material), such as a P-type material 218 P, extending in the X-axis direction and the Y-axis direction.
- the P-type material 218 P may be molybdenum disulfide (MoS 2 ).
- channel control in an upper gate region 208 U is improved over a channel region in a channel structure formed of silicon. Therefore, the length LG U of the upper gate region 208 U may be made smaller to reduce a dimension of the OTT cell circuit 200 in the X-axis direction without causing an increase in leakage current in the PFET 204 P.
- the 2D slabs 210 P( 1 )- 210 P( 3 ) extend along respective longitudinal axes A 2 U ( 1 )-A 2 U ( 3 ) in the X-axis direction and may be integrated in the vertical direction one above another.
- the upper channel structure 206 U also includes an upper source/drain material 221 U integrated with first end portions 216 US( 1 )- 216 US( 3 ) of the 2D slabs 210 P( 1 )- 210 P( 3 ) to form an upper source/drain region 214 US and the upper source/drain material 221 U integrated with second end portions 216 UD( 1 )- 216 UD( 3 ) of the 2D slabs 2101 )( 1 )- 210 P( 3 ) to form an upper drain/source region 214 UD.
- either the upper source/drain region 214 US or the upper drain/source region 214 UD may function as a source while the other functions as a drain.
- Integration of the upper source/drain region 214 US and the upper drain/source region 214 UD with the respective end portions 216 US( 1 )- 216 US( 3 ) and 216 UD( 1 )- 216 UD( 3 ) may include one or more of doping the 2D slabs 210 P( 1 )- 210 P( 3 ) with the upper source/drain material 221 U, growing the upper source/drain material 221 U epitaxially on the 2D slabs 210 P( 1 )- 210 P( 3 ), and forming the upper source/drain material 221 U on or in contact with the 2D slabs 210 P( 1 )- 210 P( 3 ). As shown in FIG.
- the upper source/drain material 221 U of the upper source/drain region 214 US and the upper drain/source region 214 UD may be formed on faces of the 2D slabs 210 P( 1 )- 210 P( 3 ), except where the 2D slab 210 P( 1 ) is in contact with the isolation layer 207 U.
- the upper source/drain material 221 U may be formed on faces of the 2D slab 210 P( 2 ) in the end portions 216 US( 2 ) and 216 UD( 2 ).
- the upper source/drain material 221 U may be similarly formed on faces of 2D slabs 210 P( 1 ) and 210 P( 3 ), as shown in FIG. 2A .
- the upper channel structure 206 U also includes an upper gate 222 U disposed on faces of the 2D slabs 210 P( 1 )- 210 P( 3 ).
- the upper gate 222 U is disposed on the 2D slabs 210 P( 1 )- 210 P( 3 ) between the upper source/drain region 214 US and the upper drain/source region 214 UD.
- the upper gate 222 U is separated from the upper source/drain region 214 US by side spacer 224 US and separated from the lower drain/source region 214 UD by side spacer 224 UD.
- the upper gate 222 U includes gate portions 225 U electrically insulated from the respective 2D slabs 210 P( 1 )- 210 P( 3 ) by gate dielectric layers 226 U.
- the upper gate 222 U also includes an upper field gate 227 U (shown in FIG. 2B ) which provides a horizontal interconnect disposed on the upper gate 222 U.
- the upper circuit layer 202 U includes trench contacts 230 US and 230 UD disposed above the upper source/drain region 214 US and the upper drain/source region 214 UD, respectively.
- the upper circuit layer 202 U also includes a trench contact 230 UG disposed on the upper gate 222 U.
- Metal layer interconnects M SD , M G , and M DS are disposed on the trench contracts 230 US, 230 UG, and 230 UD, respectively, for coupling external circuits to the PFET 204 P.
- An ILD 228 U surrounds the PFET 204 P, the metal layer interconnects M SD , M G , and M DS , and the trench contacts 230 US, 230 UG, and 230 UD.
- an upper channel column 236 U extends vertically (up and down) from a horizontal area of the upper channel structure 206 U, and a lower channel column 236 L extends vertically from a horizontal area of the lower channel structure 206 L.
- the upper channel column 236 U overlaps at least a portion of the lower channel column 236 L.
- the upper channel structure 206 U in the upper circuit layer 202 U overlaps the lower channel structure 206 L in the lower circuit layer 202 L such that the upper channel column 236 U fully overlaps (i.e., occupies substantially the same horizontal area extending in a vertical direction) as the lower channel column 236 L.
- the 2D slab 210 N( 2 ) may partially overlap or fully overlap the 2D slab 210 N( 1 ) when vertically stacked on the 2D slab 210 N( 1 ) to minimize a horizontal area occupied by the lower channel structure 206 L
- the 2D slab 210 P( 2 ) may partially overlap or fully overlap the 2D slab 210 P( 1 ) when vertically stacked on the 2D slab 210 P( 1 ) to minimize a horizontal area occupied by the upper channel structure 206 U.
- a horizontal area (X-axis and Y-axis directions) occupied by the CFET cell circuit 200 may be reduced in comparison to the standard cell 102 of FIG. 1 in exchange for an increased dimension in the Z-direction.
- FIG. 2B illustrates a side view of a cross-section in the Y-axis and Z-axis directions of the CFET cell circuit 200 .
- the cross-sectional view shown in FIG. 2B is taken along the line Y-Y′ shown in the top view of the CFET cell circuit 200 illustrated in FIG. 2D .
- the cross-sectional view in FIG. 2B shows the 2D slabs 210 N( 1 )- 210 N( 3 ) one above another in the lower channel structure 206 L and the 2D slabs 210 P( 1 )- 210 P( 3 ) one above another in the upper channel structure 206 U. As shown in FIG.
- the gate dielectric layers 226 L are formed around each of the 2D slabs 210 N( 1 )- 210 N( 3 ) to separate the 2D slabs 210 N( 1 )- 210 N( 3 ) from the gate portions 225 L of the lower gate 222 L.
- the gate dielectric layers 226 U are formed around each of the 2D slabs 210 P( 1 )- 210 P( 3 ) to separate the 2D slabs 210 P( 1 )- 210 P( 3 ) from the gate portions 225 U of the upper gate 222 U.
- FIG. 2B shows an example of vertical integration of the upper channel structure 206 U in the upper circuit layer 202 U above the lower channel structure 206 L in the lower circuit layer 202 L to reduce a dimension of the CFET cell circuit 200 in the Y-axis direction.
- the upper channel structure 206 U may be positioned directly above the lower channel structure 206 L.
- the lower gate 222 L in the lower channel structure 206 L located directly below the upper channel structure 206 U, a vertical inter-layer access (via) from the lower gate 222 L to the metal interconnect M G may be obstructed.
- the lower field gate 227 L extends in the Y-axis direction, orthogonal to the longitudinal axis A 2 L ( 1 ) of the first 2D slab 210 N( 1 ), from the lower gate 222 L to a location in the lower circuit layer 202 L that is not vertically obstructed.
- the lower field gate 227 L provides a horizontal interconnect orthogonal to the longitudinal axes A 2 L ( 1 )-A 2 L ( 3 ) (see FIG. 2A ) from the lower gate 222 L to a location in the lower circuit layer 202 U in which a via 232 LG to the metal interconnect M G is not obstructed by the upper channel structure 206 U.
- the upper field gate 227 U may be formed on the upper gate 222 U as a horizontal interconnect in the upper circuit layer 202 U.
- the upper field gate 227 U may provide an alternative location for the trench contact 230 UG, if needed.
- a trench contact 230 LG is formed on the lower field gate 227 L, and the via 232 LG extends through the upper circuit layer 202 U from the trench contact 230 LG in the lower circuit layer 202 L to the metal interconnect M G above the upper circuit layer 202 U. As will be disclosed with regard to FIGS.
- horizontal interconnects similar to the lower field gate 227 L are provided in the lower circuit layer 202 L from the lower source/drain region 214 LS and the lower drain/source region 214 LD to locations at which a via to metal interconnects above the upper circuit layer 202 U may be unobstructed.
- FIG. 2C-1 illustrates a top view of a horizontal cross-section, taken at line Z-Z′ in FIG. 2B , showing features of the lower circuit layer 202 L including the NFET 204 N.
- FIG. 2C-1 shows horizontal interconnects 234 LS and 234 LD extending in the X-axis direction, orthogonal to the lower channel structure 206 L, from the lower source/drain region 214 LS and the lower drain/source region 214 LD, respectively.
- the lower field gate 227 L is also shown extending in the Y-axis direction from the lower gate 222 L.
- FIG. 2C-1 illustrates a top view of a horizontal cross-section, taken at line Z-Z′ in FIG. 2B , showing features of the lower circuit layer 202 L including the NFET 204 N.
- FIG. 2C-1 shows horizontal interconnects 234 LS and 234 LD extending in the X-axis direction, orthogonal to the lower channel structure 206 L, from the lower source
- FIG. 2C-1 shows that the trench contacts 230 LS, 230 LG, and 230 LD are in locations of the lower circuit layer 202 L that are not vertically obstructed by the upper channel structure 206 U in the upper circuit layer 202 U.
- FIG. 2C-1 shows that the trench contacts 230 LS, 230 LG, and 230 LD are positioned according to a line pitch P Y in the Y-axis direction relative to the lower channel structure 206 L, and according to a line pitch P X in the X-axis direction relative to the lower field gate 227 L.
- Line pitches P X and P Y may be a center-to-center distance between features, as shown in FIG. 2C-1 .
- FIG. 2C-2 illustrates a top view of features of the upper circuit layer 202 U including the PFET 204 P.
- FIG. 2C-2 shows the upper field gate 227 U extending in the Y-axis direction orthogonal to the longitudinal axes A 2 U ( 1 )-A 2 U ( 3 ) (see FIG. 2A ) and the trench contact 230 UG in an alternative location to the location shown in FIG. 2B .
- FIG. 2C-2 shows top views of the via 232 LG and vias 232 LS and 232 LD which are positioned to extend vertically from the trench contacts 230 LG, 230 LS, and 230 LD, respectively, in the lower circuit layer 202 L.
- 2C-2 also shows top views of the trench contracts 230 US, 230 UG, and 230 UD in the upper circuit layer 202 U.
- the vias 232 LS, 232 LG and 232 LD and the trench contacts 230 UG, 230 US, and 230 UD are spaced apart in the upper circuit layer 202 U according to the line pitch P X in the X-axis direction and according to the line pitch P Y in the Y-axis direction in an arrangement to minimize a footprint of the CFET cell circuit 200 .
- FIG. 2C-2 shows electrical connections for configuring the NFET 204 N in FIG. 2C-1 and the PFET 204 P in a CMOS inverter configuration.
- the metal interconnect M G connects between the trench contacts 230 LG and 230 UG to electrically couple the lower gate 222 L and the upper gate 222 U.
- the metal interconnection M DS connects between the trench contacts 230 LD and 230 UD to electrically couple the lower drain/source region 214 LD and the upper drain/source region 214 UD.
- the metal interconnect M SD is connected between the trench contact 230 LS and a via 238 to electrically couple the upper source/drain region 214 US of the PFET 204 P to a supply voltage (e.g., V DD ).
- the via 232 LS electrically couples the lower source/drain region 214 LS of the NFET 204 N to ground (e.g., V SS ).
- FIGS. 2C-1 and 2C-2 also show dummy gates 240 located according to a gate pitch P G in the X-axis direction relative to the lower field gate 227 L and the upper field gate 227 U.
- the supply voltage V DD and ground V SS may each be provided by one of the power rails 240 .
- the length dimensions LG L and LG U of the CFET cell circuit 200 in the X-axis direction may be smaller than a length of a channel region in a silicon channel structure (e.g., fin) without a corresponding increase in leakage current.
- the gate pitch P G of the CFET cell circuit 200 which determines a dimension of the CFET cell circuit 200 in the X-axis direction, may also be smaller.
- FIG. 2D shows a top view of the CFET cell circuit 200 with the upper circuit layer 202 U of FIG. 2C-2 disposed above and in horizontal alignment with the lower circuit layer 202 L of FIG. 2C-1 .
- FIG. 2D shows the upper channel structure 206 U disposed directly above the lower channel structure 206 L to reduce a dimension of the CFET cell circuit 200 in the Y-axis direction.
- the horizontal interconnects 234 LS, 234 LD and the lower field gate 227 L provide unobstructed vertical access locations for the vias 232 LS, 232 LG, and 232 LD to electrically couple the NFET 204 N to the PFET 204 P and/or an external circuit.
- FIG. 3 is a flowchart illustrating an exemplary process 300 for fabricating a CFET cell circuit 400 , which corresponds to the CFET cell circuit 200 illustrated in FIGS. 2A-2D .
- the process 300 is explained with reference to the fabrication stages illustrated in FIGS. 4A-4O .
- FIG. 4A is a cross-sectional view of a first circuit layer 402 L in a first fabrication stage 401 (A) in which the CFET cell circuit 400 is formed.
- the first circuit layer 402 L corresponds to the lower circuit layer 202 L in FIGS. 2A-2D .
- An isolation layer 407 L such as a shallow trench isolation (STI) layer, is formed on a substrate 409 , which may be formed of silicon.
- the lower circuit layer 402 L including the isolation layer 407 L is formed above the substrate 409 (block 302 in FIG. 3 ).
- Forming the lower circuit layer 402 L includes vertically stacking a first 2D slab 410 N( 1 ) and a second 2D slab 410 N( 2 ) to form a lower channel structure 406 L.
- the first and second 2D slabs 410 N( 1 ) and 410 N( 2 ) have longitudinal axes A 4 L ( 1 ) and A 4 L ( 2 ), respectively, in a first direction and include a semiconductor material 418 ( 1 ) of a first type (e.g., one of N-type or P-type) (block 304 in FIG. 3 ).
- a semiconductor material 418 ( 1 ) of a first type e.g., one of N-type or P-type
- Vertically stacking the first and second 2D slabs 410 N( 1 ) and 410 N( 2 ) includes forming one or more layers of the semiconductor material 418 ( 1 ) (e.g., monolayers of MX 2 material) for the first 2D slab 410 N( 1 ) on the isolation layer 407 L, forming an oxide layer 411 ( 1 ) on the first 2D slab 410 N( 1 ), forming one or more layers of the semiconductor material 418 ( 1 ) for the second 2D slab 410 N( 2 ), and forming another oxide layer 411 ( 2 ) above the second 2D slab 210 N( 2 ).
- the semiconductor material 418 ( 1 ) e.g., monolayers of MX 2 material
- Each 2D slab 410 N( 1 ), 410 N( 2 ) may include, for example, from one (1) to four (4) monolayers of the semiconductor material 418 ( 1 ).
- the lower channel structure 406 L includes three (3) 2D slabs 410 N( 1 )- 410 N( 3 ) and three (3) oxide layers 411 ( 1 )- 411 ( 3 ), but additional alternating 2D slabs and oxide layers may be vertically stacked for increased drive strength capability in the lower channel structure 406 L.
- the vertically-stacked 2D slabs 410 N( 1 )- 410 N( 3 ) and oxide layers 411 ( 1 )- 411 ( 3 ) are etched to form the lower channel structure 406 L.
- FIG. 4B illustrates an exemplary fabrication stage 401 (B) of fabricating the CFET cell circuit 400 that further includes depositing a dummy gate polysilicon layer 413 L on the lower channel structure 406 L to fabrication stage 401 (A) in FIG. 4A , and using photolithographic patterning and etching to remove the dummy gate polysilicon layer 413 L from the lower channel structure 406 L except in a lower gate region 408 L. Portions of the polysilicon also remain to form dummy gate 417 L at each end of the lower channel structure 406 L.
- FIG. 4C illustrates an exemplary fabrication stage 401 (C) of fabricating the CFET cell circuit 400 that further includes employing the dummy gate polysilicon layer 413 L as a mask to fabrication stage 401 (B) in FIG. 4B .
- the oxide layers 411 ( 1 )- 411 ( 3 ) on and between first and second end portions 416 LS and 416 LD of the 2D slabs 410 N( 1 )- 410 N( 3 ) as shown in FIG. 4B are removed, but portions 411 A( 1 )- 411 A( 3 ) of the oxide layers 411 ( 1 )- 411 ( 3 ) beneath the dummy gate polysilicon layer 413 L are not removed.
- a spacer layer which may be silicon nitride (SiN or SiON), for example, is deposited on respective vertical sides of the remaining portions of the oxide layers 411 ( 1 )- 411 ( 3 ), and is etched to form side spacers 424 LS and 424 LD that will electrically isolate the lower gate 422 L (see FIG. 4F ) from the lower source/drain region 414 LS and the lower drain/source region 414 LD.
- Side spacers 415 L may also be formed on vertical sides of the dummy gate 417 L.
- Fabrication stage 401 (C) also includes doping the first and second end portions 416 LS and 416 LD of the 2D slabs 410 N( 1 )- 410 N( 3 ) with a first type of dopant (not shown) to form an N-type or P-type semiconductor.
- FIG. 4D illustrates an exemplary fabrication stage 401 (D) in which an ILD 428 L is disposed to surround the doped 2D slabs 410 N( 1 )- 410 N( 3 ) in fabrication stage 401 (C) in FIG. 4C .
- the ILD 428 L provides a structural support for the 2D slabs 410 N( 1 )- 410 N( 3 ) and also provides electrical isolation for the lower channel structure 406 L.
- a top surface 428 LT of the ILD 428 L is planarized (e.g., by chemical mechanical planarization (CMP)), and a SiN layer 429 L is formed on the top surface 428 LT.
- CMP chemical mechanical planarization
- FIG. 4E illustrates an exemplary fabrication stage 401 (E) in which the photolithography and etching are employed to fabrication stage 401 (D) in FIG. 4D to remove the SiN layer 429 L, the dummy gate polysilicon layer 413 L, and the dummy gate 417 L shown in FIG. 4D .
- the remaining portions 411 A( 1 )- 411 A( 3 ) of the oxide layers 411 ( 1 )- 411 ( 3 ) that are on and between the 2D slabs 410 N( 1 )- 410 N( 3 ) in the vertical direction and between the side spacers 424 LS and 424 LD in the horizontal direction are removed.
- Forming the lower circuit layer 402 L further includes disposing a lower gate 422 L on faces of the 2D slabs 410 N( 1 )- 410 N( 3 ) between the first and second end portions 416 LS and 416 LD of the 2D slabs 410 N( 1 )- 410 N( 3 ) (block 306 in FIG. 3 ).
- lower gate dielectric layers 426 L formed of a high-k dielectric material are deposited on exposed faces of the 2D slabs 410 N( 1 )- 410 N( 3 ) between the side spacers 424 LS and 424 LD, and gate portions 425 L formed of a conductive gate material (e.g., metal) are disposed over the gate dielectric layers 426 L to form the lower gate 422 L.
- Forming the lower gate 422 L may further include forming a lower field gate 427 L (not shown) corresponding to the lower field gate 227 L shown in FIG. 2B extending orthogonally from the lower channel structure 406 L.
- the polysilicon material of the dummy gate 417 L is replaced with conductive metal gate material.
- FIG. 4F illustrates an exemplary fabrication stage 401 (F) which includes integrating a lower source/drain material 421 L with the first end portions 416 LS of the 2D slabs 410 N( 1 )- 410 N( 3 ) to fabrication stage 401 (E) in FIG. 4E to form a lower source/drain region 414 LS on a first side of the lower gate 422 L, and integrating the lower source/drain material 421 L with the second end portions 416 LD of the 2D slabs 410 N( 1 )- 410 N( 3 ) to form a lower drain/source region 414 LD on a second side of the lower gate 422 L (block 308 in FIG. 3 ).
- photolithography and etching are used to remove portions of the ILD 428 L in the first and second end portions 416 LS and 416 LD.
- the ILD 428 L between the 2D slabs 410 N( 1 )- 410 N( 3 ) in the first end portions 416 LS is replaced by forming the lower source/drain material 421 L
- the ILD 428 L between the 2D slabs 410 N( 1 )- 410 N( 3 ) in the second end portions 416 LD is replaced by forming the lower source/drain material 421 L.
- the lower source/drain material 421 L may be an N-type material for an NFET 404 N.
- the lower source/drain material 421 L may be a P-type material to form a PFET 404 P in the lower circuit layer 402 L.
- FIG. 4G illustrates an exemplary fabrication stage 401 (G) of fabricating the CFET cell circuit 400 that further includes disposing more ILD to the fabrication stage 401 (F) in FIG. 4F to electrically isolate the lower source/drain material 421 L, which increases a thickness of the ILD 428 L to form a new top surface 428 LT′ of the first circuit layer 402 L.
- Photolithography and etching are employed to remove portions of the ILD 428 L to open a contact area above the first end portions 416 LS and the second end portions 416 LD, allowing trench contacts 430 LS and 430 LD to be formed in contact with the lower source/drain region 414 LS and the lower drain/source region 414 LD by depositing metal or another conductive material.
- Forming the trench contacts 430 LS and 430 LD may include forming horizontal interconnects 434 LS and 434 LD (not shown), which correspond to horizontal interconnects 234 LS and 234 LD shown in FIG. 2C-1
- FIG. 4H illustrates an exemplary fabrication stage 401 (H) of fabricating the CFET cell circuit 400 that further includes forming an upper circuit layer 402 U (which corresponds to the upper circuit layer 202 U in FIGS. 2A-2D ) above the lower circuit layer 402 L (block 310 in FIG. 3 ) in the fabrication stage 401 (G) in FIG. 4G .
- Forming the upper circuit layer 402 U includes forming an isolation layer 407 U on the top surface 428 LT′ of the lower circuit layer 402 L.
- Forming the upper circuit layer 402 U further includes forming an upper channel structure 406 U, which further includes vertically stacking a third 2D slab 410 P( 1 ) and a fourth second 2D slab 410 P( 2 ) above the isolation layer 407 U.
- the third and fourth 2D slabs 410 P( 1 ) and 410 P( 2 ) have longitudinal axes A 4 u ( 1 ) and A 4 u ( 2 ), respectively, in the first direction, and include a semiconductor material 418 ( 2 ) of a second type (e.g., one of P-type or N-type) (block 312 in FIG. 3 ).
- Vertically stacking the third and fourth 2D slabs 410 P( 1 ) and 410 P( 2 ) includes depositing one or more layers of the semiconductor material 418 ( 2 ) (e.g., monolayers of MX 2 material) to form the third 2D slab 410 P( 1 ) on the isolation layer 407 U, depositing an oxide layer 411 ( 4 ) on the third 2D slab 410 P( 1 ), depositing one or more layers of the semiconductor material 418 ( 2 ) to form the fourth 2D slab 410 P( 2 ), and depositing another oxide layer 411 ( 5 ) above the fourth 2D slab 410 P( 2 ).
- the semiconductor material 418 ( 2 ) e.g., monolayers of MX 2 material
- Each 2D slab 410 P( 1 ), 410 P( 2 ) may include, for example, from one (1) to four (4) monolayers of the semiconductor material 418 ( 2 ).
- the upper channel structure includes three (3) 2D slabs 410 P( 1 )- 410 P( 3 ) and three (3) oxide layers 411 ( 4 )- 411 ( 6 ), but additional alternating 2D slabs and oxide layers may be vertically stacked for increased drive strength capability in the upper channel structure 406 U.
- the vertically stacked 2D slabs 410 P( 1 )- 410 P( 3 ) and oxide layers 411 ( 3 )- 411 ( 4 ) are etched to form the upper channel structure 406 U.
- FIG. 4I illustrates an exemplary fabrication stage 401 (I) of fabricating the CFET cell circuit 400 that further includes depositing a dummy gate polysilicon layer 413 U on the upper channel structure 406 U in the fabrication stage 401 (H) in FIG. 4H , and using photolithographic patterning and etching to remove the dummy gate polysilicon layer 413 U from the upper channel structure 406 U except in an upper gate region 408 U. Portions of the polysilicon also remain to form dummy gate 417 U at each end of the upper channel structure 406 U.
- FIG. 4J illustrates an exemplary fabrication stage 401 (J) of fabricating the CFET cell circuit 400 that further includes employing the dummy gate polysilicon layer 413 U in the fabrication stage 401 (I) in FIG. 4I as a mask.
- the oxide layers 411 ( 4 )- 411 ( 6 ) on and between first and second end portions 416 US and 416 UD of the 2D slabs 410 P( 1 )- 410 P( 3 ) are removed, but portions 411 A( 4 )- 411 A( 6 ) of the oxide layers 411 ( 4 )- 411 ( 6 ) beneath the dummy gate polysilicon layer 413 U are not removed.
- a spacer layer which may be silicon nitride (SiN), for example, is deposited on respective vertical sides of the remaining portions of the oxide layers 411 ( 4 )- 411 ( 6 ), and is etched to form side spacers 424 US and 424 UD that will electrically isolate the upper gate 422 U (see FIG. 4M ) from the upper source/drain region 414 US and the upper drain/source region 414 UD.
- Side spacers 415 U may also be formed on vertical sides of the dummy gate 417 U.
- Fabrication stage 401 (J) also includes doping the first and second end portions 416 US and 416 UD of the 2D slabs 410 P( 1 )- 410 P( 3 ) with a second type of dopant to form a P-type or N-type semiconductor.
- FIG. 4K illustrates an exemplary fabrication stage 401 (K) in which an ILD 428 U is disposed to surround the doped 2D slabs 410 P( 1 )- 410 P( 3 ) in the fabrication stage 401 (J) in FIG. 4J .
- a top surface 428 UT of the ILD 428 U is planarized (e.g., by chemical mechanical planarization (CMP)), and a SiN layer 429 U is formed on the top surface 428 UT.
- CMP chemical mechanical planarization
- FIG. 4L illustrates an exemplary fabrication stage 401 (L) in which photolithography and etching are employed to remove the dummy gate polysilicon layer 413 U and the dummy gate 417 U of the CFET cell circuit 400 in the fabrication stage 401 (K) in FIG. 4K .
- the remaining portions 411 A( 4 )- 411 A( 6 ) of the oxide layers 411 ( 4 )- 411 ( 6 ) that are on and between the 2D slabs 410 P( 1 )- 410 P( 3 ) in the vertical direction and between the side spacers 424 US and 424 UD in the horizontal direction are removed.
- Forming the upper circuit layer 402 U above the lower circuit layer 402 L further includes disposing an upper gate 422 U on faces of the 2D slabs 410 P( 1 )- 410 P( 3 ) between the first and second end portions 416 US and 416 UD of the 2D slabs 410 P( 1 )- 410 P( 3 ) (block 314 in FIG. 3 ).
- upper gate dielectric layers 426 U of a high-k material are deposited on exposed faces of the 2D slabs 410 P( 1 )- 410 P( 3 ) between the side spacers 424 US and 424 UD, and gate portions 425 U formed of a conductive gate material (e.g., metal) are disposed over the upper gate dielectric layers 426 U to form an upper gate 422 U.
- An upper field gate 427 U (not shown) corresponding to the upper field gate 227 U in FIG. 2B may also be formed with the upper gate 422 U in the upper circuit layer 402 U.
- the polysilicon material of the dummy gate 417 U is also replaced with conductive metal gate material in this stage.
- FIG. 4M illustrates an exemplary fabrication stage 401 (M) which includes integrating an upper source/drain material 421 U with the first end portions 416 US of the 2D slabs 410 P( 1 )- 410 P( 3 ) to form an upper source/drain region 414 US on a first side of the upper gate 422 U in the fabrication stage 401 (L) in FIG. 4L , and integrating the upper source/drain material 421 U with the second end portions 416 UD of the 2D slabs 410 P( 1 )- 410 P( 3 ) to form an upper drain/source region 414 UD on a second side of the upper gate 422 U (block 316 in FIG. 3 ).
- photolithography and etching are used to remove portions of the ILD 428 U in the first and second end portions 416 US and 416 UD.
- the ILD 428 U between the 2D slabs 410 P( 1 )- 410 P( 3 ) in the first end portions 416 US is replaced with the upper source/drain material 421 U
- the ILD 428 U between the 2D slabs 410 P( 1 )- 410 P( 3 ) in the second end portions 416 UD is replaced with the upper source/drain material 421 U.
- the upper source/drain material 421 U may be a P-type material for a PFET 404 P.
- the upper source/drain material 421 U may each be an N-type material to form an NFET 404 N in the upper circuit layer 402 U.
- FIG. 4N illustrates an exemplary fabrication stage 401 (N) of fabricating the CFET cell circuit 400 that further includes disposing more ILD to increase a thickness of the ILD 428 U in the fabrication stage 401 (M) in FIG. 4M to form a new top surface 428 UT′ of the upper circuit layer 402 U.
- Photolithography and etching are employed to remove portions of the ILD 428 U to open a contact area above the first end portions 416 US and the second end portions 416 UD, allowing trench contacts 430 US and 430 UD to be formed in contact with the upper source/drain region 414 US and the upper drain/source region 414 UD by deposition of metal or another conductive material.
- a trench contact 430 UG is formed on the upper gate 422 U.
- Forming the trench contacts 430 US and 430 UD may include forming horizontal interconnects 434 US and 434 UD (not shown), which correspond to horizontal interconnects 234 US and 234 UD in FIG. 2C-2 .
- the top surface 428 UT′ is planarized by CMP.
- FIG. 4O illustrates an exemplary fabrication stage 401 ( 0 ) of fabricating the CFET cell circuit 400 that further includes disposing more ILD to further increase a thickness of the ILD 428 U in the fabrication stage 401 (N) in FIG. 4N to form another new top surface 428 UT′′ of the upper circuit layer 402 U.
- Photolithography and etching are employed to remove portions of the ILD 428 U over the trench contacts 430 US, 430 UG, and 430 UD where the metal layer interconnects M SD , M G , and M DS , respectively, are formed to provide connections to the CFET cell circuit 400 .
- the top surface 428 UT′′ is planarized by CMP.
- FIG. 5A is a cross-sectional view of a CFET cell circuit 500 in the X-axis and Z-axis directions shown therein.
- the cross-sectional view shown in FIG. 5A is taken along the line X-X′ shown in a top view of the CFET cell circuit 500 illustrated in FIG. 5D .
- the CFET cell circuit 500 corresponds to the CFET cell circuit 200 in FIGS. 2A-2D , except with respect to the semiconductor types of the FETs in the lower and upper layers.
- the CFET cell circuit 500 includes a PFET 504 P in a lower circuit layer 502 L and an NFET 504 N in an upper circuit layer 502 U.
- the CFET cell circuit 500 includes an upper circuit layer 502 U with an NFET 504 N disposed vertically above (i.e., stacked above) a lower circuit layer 502 L with a PFET 504 P. In this manner, the vertical stacking reduces the horizontal footprint of the CFET cell circuit 500 in the Y-axis direction.
- the PFET 504 P and the NFET 504 N may be interconnected in a complementary configuration, as in a CMOS circuit.
- an X-axis dimension of a footprint of the CFET cell circuit 500 may be reduced by reducing length dimensions of the PFET 504 P and the NFET 504 N.
- the PFET 504 P in the lower circuit layer 502 L is formed in a lower channel structure 506 L in which a gate region 508 L has a length dimension LG L in the X-axis direction
- the NFET 504 N in the upper circuit layer 502 U is formed in an upper channel structure 506 U in which a gate region 508 U has a length dimension LG U in the X-axis direction.
- MX 2 -type compounds e.g., transition metal dichalcogenide crystals
- 2D materials transition metal dichalcogenide crystals
- the lower circuit layer 502 L includes the PFET 504 P
- the upper circuit layer 502 U includes the NFET 504 N.
- the PFET 504 P is disposed on an isolation layer 507 L above a substrate 509 .
- the lower channel structure 506 L includes a first 2D slab 510 P( 1 ) of the 2D material vertically integrated with a second 2D slab 510 P( 2 ) of the 2D material.
- a “slab” is a structure formed of one or more layers of a 2D material with first and second dimensions in orthogonal directions (e.g., X-axis and Y-axis directions) and having a thickness dimension which is orthogonal to the first and second dimensions (e.g., Z-axis direction) and is smaller than the first and second dimensions.
- first and second dimensions in orthogonal directions
- Z-axis direction e.g., Z-axis direction
- the first and second 2D slabs 510 P( 1 ) and 510 P( 2 ) may each extend in a range from 20 nm to 500 nm in a longitudinal direction (e.g., X-axis direction), and extend in a range from 3 nm to 50 nm in a direction orthogonal to the longitudinal direction (e.g., Y-axis direction).
- the first and second 2D slabs 510 P( 1 ) and 510 P( 2 ) have a thickness dimension, which may be in the range from 0.6 nm to 10.0 nm.
- 5A may also include additional 2D slabs, such as third 2D slab 510 P( 3 ) vertically integrated with the first and second 2D slabs 510 P( 1 ) and 510 P( 2 ) to increase a drive strength of the PFET 504 P.
- additional 2D slabs such as third 2D slab 510 P( 3 ) vertically integrated with the first and second 2D slabs 510 P( 1 ) and 510 P( 2 ) to increase a drive strength of the PFET 504 P.
- the slab structures in FIG. 5A may appear to be planar, stackable slabs having other (e.g., non-planar) shapes are within the scope of the present disclosure.
- Each of the 2D slabs 510 P( 1 )- 510 P( 3 ) includes at least one monolayer (not individually shown) of a first type of 2D semiconductor material 518 ( 1 ), such as a P-type material 518 P, extending in the X-axis direction and the Y-axis direction.
- 2D materials are atomically thin semiconductor monolayers of the type MX 2 , where M is a transition metal atom (Mo, W, etc.) and X is a chalcogen atom (S, Se, or Te).
- the P-type material 518 P may be molybdenum disulfide (MoS 2 ).
- Crystal monolayers of MX 2 compounds have a higher carrier mobility, lower dielectric constant, and thinner channel thickness than silicon, providing a strong on/off control of the channel. Therefore, a channel structure formed of MX 2 compounds may have higher drive strength and lower leakage current than a similarly-sized silicon channel structure.
- channel control in a lower gate region 508 L is improved over a channel region of the same length in a channel structure formed of silicon.
- the length LG L of the lower gate region 508 L may be made smaller to reduce a dimension of the CFET cell circuit 500 in the X-axis direction without a causing an increase in leakage current in the PFET 504 P.
- the 2D slabs 510 P( 1 )- 510 P( 3 ) extend along respective longitudinal axes A 5 L ( 1 )-A 5 L ( 3 ) and may be integrated by stacking in a vertical (e.g., Z-axis) direction one above another.
- the lower channel structure 506 L also includes a lower source/drain material 521 L integrated with first end portions 516 LS( 1 )- 516 LS( 3 ) of the 2D slabs 510 P( 1 )- 510 P( 3 ) for forming a lower source/drain region 514 LS and the lower source/drain material integrated with second end portions 516 LD( 1 )- 516 LD( 3 ) of the 2D slabs 510 P( 1 )- 510 P( 3 ) to form a lower drain/source region 514 LD.
- a lower source/drain material 521 L integrated with first end portions 516 LS( 1 )- 516 LS( 3 ) of the 2D slabs 510 P( 1 )- 510 P( 3 ) for forming a lower source/drain region 514 LS and the lower source/drain material integrated with second end portions 516 LD( 1 )- 516 LD( 3 ) of the 2D slabs 510 P(
- the lower source/drain material 521 L of the lower source/drain region 514 LS and the lower drain/source region 514 LD may be formed on faces of the 2D slabs 510 P( 1 )- 510 P( 3 ), except where the first 2D slab 510 P( 1 ) is in contact with the isolation layer 507 L.
- the lower source/drain material 521 L may be formed on top face 520 LT, bottom face 520 LB, side face 520 LS, and end faces 520 LE of 2D slab 510 P( 2 ) in the first and second end portions 516 LS( 2 ) and 516 LD( 2 ).
- the lower source/drain material 521 L may be similarly formed on faces of 2D slabs 510 P( 1 ) and 510 P( 3 ), as shown in FIG. 5A .
- the lower channel structure 506 L includes a lower gate 522 L disposed on faces of the 2D slabs 510 P( 1 )- 510 P( 3 ), such as the faces 520 LT, 520 LB and 520 LS of the second 2D slab 510 P( 2 ).
- the lower gate 522 L is disposed on the 2D slabs 510 P( 1 )- 510 P( 3 ) between the lower source/drain region 514 LS and the lower drain/source region 514 LD in the X-axis direction.
- the lower gate 522 L is separated from the lower source/drain region 514 LS by side spacer 524 LS and separated from the lower drain/source region 514 LD by side spacer 524 LD.
- the lower gate 522 L includes gate portions 525 L electrically insulated from the respective 2D slabs 510 P( 1 )- 510 P( 3 ) by gate dielectric layers 526 L.
- the lower gate 522 L also includes a lower field gate 527 L not shown in FIG. 5A .
- the lower circuit layer 502 L also includes trench contacts 530 LS and 530 LD formed above the lower source/drain region 514 LS and the lower drain/source region 514 LD, respectively.
- An inter-layer dielectric (ILD) 528 L surrounds the PFET 504 P, the lower field gate 527 L, and the trench contacts 530 LS and 530 LD.
- the lower field gate 527 L and the trench contacts 530 LS and 530 LD are discussed further with respect to FIG. 5B below.
- the CFET cell circuit 500 in FIG. 5A also includes the upper circuit layer 502 U disposed above the lower circuit layer 502 L that includes the PFET 504 P to provide a CMOS architecture for the CFET cell circuit 500 .
- the upper circuit layer 502 U of the CFET cell circuit 500 will now be discussed.
- the upper circuit layer 502 U includes the NFET 504 N disposed on the isolation layer 507 L.
- the NFET 504 N is formed in an upper channel structure 506 U including a third 2D slab 510 N( 1 ) vertically integrated with a fourth 2D slab 510 N( 2 ).
- each of the 2D slabs 510 N( 1 )- 510 N( 3 ) includes at least one monolayer (not individually shown) of a second 2D semiconductor material 518 ( 2 ) (e.g., MX 2 material), such as an N-type material 518 N, extending in the X-axis direction and the Y-axis direction.
- the N-type material 518 N may be molybdenum disulfide (MoS 2 ).
- channel control in an upper gate region 508 U is improved over a channel region in a channel structure formed of silicon. Therefore, the length LG U of the upper gate region 508 U may be made smaller to reduce a dimension of the CFET cell circuit 500 in the X-axis direction without causing an increase in leakage current in the NFET 504 N.
- the 2D slabs 510 N( 1 )- 510 N( 3 ) extend along respective longitudinal axes A 5 U ( 1 )-A 5 U ( 3 ) in the X-axis direction and may be integrated in the vertical direction one above another.
- the upper channel structure 506 U also includes an upper source/drain material 521 U integrated with first end portions 516 US( 1 )- 516 US( 3 ) of the 2D slabs 510 N( 1 )- 510 N( 3 ) to form an upper source/drain region 514 US and the upper source/drain material 521 U integrated with second end portions 516 UD( 1 )- 516 UD( 3 ) of the 2D slabs 510 N( 1 )- 510 N( 3 ) to form an upper drain/source region 514 UD.
- either the upper source/drain region 514 US or the upper drain/source region 514 UD may function as a source while the other functions as a drain.
- Integration of the upper source/drain region 514 US and the upper drain/source region 514 UD with the respective end portions 516 US( 1 )- 516 US( 3 ) and 516 UD( 1 )- 516 UD( 3 ) may include one or more of doping the 2D slabs 510 N( 1 )- 510 N( 3 ) with the upper source/drain material 521 U, growing the upper source/drain material 521 U epitaxially on the 2D slabs 510 N( 1 )- 510 N( 3 ), and depositing the upper source/drain material 521 U on or in contact with the 2D slabs 510 N( 1 )- 510 N( 3 ). As shown in FIG.
- the upper source/drain material 521 U of the upper source/drain region 514 US and the upper drain/source region 514 UD may be formed on faces of the 2D slabs 510 N( 1 )- 510 N( 3 ), except where the 2D slab 510 N( 1 ) is in contact with the isolation layer 507 U.
- the upper source/drain material 521 U may be formed on faces of the 2D slab 510 N( 2 ) in the end portions 516 US( 2 ) and 516 UD( 2 ).
- the upper source/drain material 521 U may be similarly formed on faces of 2D slabs 510 N( 1 ) and 510 N( 3 ), as shown in FIG. 5A .
- the upper channel structure 506 U also includes an upper gate 522 U disposed on faces of the 2D slabs 510 N( 1 )- 510 N( 3 ).
- the upper gate 522 U is disposed on the 2D slabs 510 N( 1 )- 510 N( 3 ) between the upper source/drain region 514 US and the upper drain/source region 514 UD.
- the upper gate 522 U is separated from the upper source/drain region 514 US by side spacers 524 US and separated from the upper drain/source region 514 UD by side spacer 524 UD.
- the upper gate 522 U includes gate portions 525 U electrically insulated from the respective 2D slabs 510 N( 1 )- 510 N( 3 ) by gate dielectric layers 526 U.
- the upper gate 522 U also includes an upper field gate 527 U not shown in FIG. 5A which is a horizontal interconnect disposed on the upper gate 522 U.
- the upper circuit layer 502 U includes trench contacts 530 US and 530 UD disposed above the upper source/drain region 514 US and the upper drain/source region 514 UD, respectively.
- the upper circuit layer 502 U also includes a trench contact 530 UG disposed on the upper gate 522 U.
- Metal layer interconnects M SD , M G , and M DS are disposed on the trench contracts 530 US, 530 UG, and 530 UD, respectively, for coupling external circuits to the NFET 504 N.
- An ILD 528 U surrounds the NFET 504 N, the metal layer interconnects M SD , M G , and M DS , the upper gate 522 U, and the trench contacts 530 US and 530 UD.
- an upper channel column 536 U extends vertically (up and down) from a horizontal area of the upper channel structure 506 U, and a lower channel column 536 L extends vertically from a horizontal area of the lower channel structure 506 L.
- the upper channel column 536 U overlaps at least a portion of the lower channel column 536 L.
- the upper channel structure 506 U in the upper circuit layer 502 U overlaps the lower channel structure 506 L in the lower circuit layer 502 L such that the upper channel column 536 U fully overlaps (i.e., occupies substantially the same horizontal area extending in a vertical direction) as the lower channel column 536 L.
- the second 2D slab 510 P( 2 ) may partially overlap or fully overlap the first 2D slab 510 P( 1 ) when vertically stacked on the first 2D slab 510 P( 1 ) to minimize a horizontal area occupied by the lower channel structure 506 L
- the second 2D slab 510 N( 2 ) may partially overlap or fully overlap the first 2D slab 510 N( 1 ) when vertically stacked on the first 2D slab 510 N( 1 ) to minimize a horizontal area occupied by the upper channel structure 506 U.
- a horizontal area (X-axis and Y-axis directions) occupied by the CFET cell circuit 500 may be reduced in comparison to the standard cell 102 of FIG. 1 in exchange for an increased dimension in the Z-direction.
- Figure SB illustrates a side view of a cross-section in the Y-axis and Z-axis directions of the CFET cell circuit 500 .
- the cross-sectional view shown in FIG. 5B is taken along the line Y-Y′ shown in the top view of the CFET cell circuit 500 illustrated in FIG. 5D .
- the cross-sectional view in FIG. 5B shows the 2D slabs 510 P( 1 )- 510 P( 3 ) one above another in the lower channel structure 506 L and the 2D slabs 510 N( 1 )- 510 N( 3 ) one above another in the upper channel structure 506 U.
- FIG. 5B shows the 2D slabs 510 P( 1 )- 510 P( 3 ) one above another in the lower channel structure 506 L and the 2D slabs 510 N( 1 )- 510 N( 3 ) one above another in the upper channel structure 506 U.
- the gate dielectric layers 526 L are formed around each of the 2D slabs 510 P( 1 )- 510 P( 3 ) to separate the 2D slabs 510 P( 1 )- 510 P( 3 ) from the gate portions 525 L of the lower gate 522 L.
- the gate dielectric layers 526 U are formed around each of the 2D slabs 510 N( 1 )- 510 N( 3 ) to separate the 2D slabs 510 N( 1 )- 510 N( 3 ) from the gate portions 525 U of the upper gate 522 U.
- FIG. 5B shows an example of vertical integration of the upper channel structure 506 U in the upper circuit layer 502 U above the lower channel structure 506 L in the lower circuit layer 502 L to reduce a dimension of the CFET cell circuit 500 in the Y-axis direction.
- the upper channel structure 506 U may be positioned directly above the lower channel structure 506 L.
- a vertical inter-layer access (via) from the lower gate 522 L to the metal interconnect M G may be obstructed.
- the lower field gate 527 L extends in the Y-axis direction, orthogonal to the longitudinal axes A 5 L ( 1 )-A 5 L ( 3 ) of the lower channel structure 506 L, from the lower gate 522 L to a location in the lower circuit layer 502 L that is not vertically obstructed.
- the lower field gate 527 L provides a horizontal interconnect from the lower gate 522 L to a location in the upper circuit layer 502 U in which a via to the metal interconnect M G is not obstructed by the upper channel structure 506 U.
- An upper field gate 527 U may be formed on the upper gate 522 U as a horizontal interconnect in the upper circuit layer 502 U to an alternative location for the trench contact 530 UG, if needed.
- a trench contact 530 LG is formed on the lower field gate 527 L and a via 532 LG extends through the upper circuit layer 502 U from the trench contact 530 LG in the lower circuit layer 502 L to the metal interconnect M G above the upper circuit layer 502 U.
- FIG. 5C-1 illustrates a top view of a horizontal cross-section, taken at line Z-Z′ in FIG. 5B , showing features of the lower circuit layer 502 L including the PFET 504 P.
- FIG. 5C-1 shows horizontal interconnects 534 LS and 534 LD extending in the X-axis direction, orthogonal to the lower channel structure 506 L, from the lower source/drain region 514 LS and the lower drain/source region 514 LD, respectively.
- the lower field gate 527 L is also shown extending in the Y-axis direction from the lower gate 522 L.
- FIG. 5C-1 illustrates a top view of a horizontal cross-section, taken at line Z-Z′ in FIG. 5B , showing features of the lower circuit layer 502 L including the PFET 504 P.
- FIG. 5C-1 shows horizontal interconnects 534 LS and 534 LD extending in the X-axis direction, orthogonal to the lower channel structure 506 L, from the lower source
- FIG. 5C-1 shows that the trench contacts 530 LS, 530 LG, and 530 LD are in locations of the lower circuit layer 502 L that are not vertically obstructed by the upper channel structure 506 U in the upper circuit layer 502 U.
- FIG. 5C-1 shows that the trench contacts 530 LS, 530 LG, and 530 LD are positioned according to a line pitch P Y in the Y-axis direction relative to the lower channel structure 506 L and according to a line pitch P X in the X-axis direction relative to the lower field gate 527 L.
- Line pitches P X and P Y may be a center-to-center distance between features, as shown in FIG. 5C-1 .
- FIG. 5C-2 illustrates a top view of features of the upper circuit layer 502 U including the NFET 504 N.
- FIG. 5C-2 shows the upper field gate 527 U extending in the Y-axis direction orthogonal to the upper channel structure 506 U, and the trench contact 530 UG in an alternative location to the location shown in FIG. 5B .
- FIG. 5C-2 shows top views of the via 532 LG and vias 532 LS and 532 LD which are positioned to extend vertically from the trench contacts 530 LG, 530 LS, and 530 LD, respectively, in the lower circuit layer 502 L.
- FIG. 5C-2 also shows top views of the trench contracts 530 US, 530 UG, and 530 UD in the upper circuit layer 502 U.
- the vias 532 LS, 532 LG, and 532 LD and the trench contacts 530 UG, 530 US, and 530 UD are spaced apart in the upper circuit layer 502 U according to the line pitch P X in the X-axis direction and according to the line pitch P Y in the Y-axis direction in an arrangement to minimize a footprint of the CFET cell circuit 500 .
- FIG. 5C-2 shows electrical connections for configuring the PFET 504 P and the NFET 504 N in a configuration of a CMOS inverter.
- the metal interconnect M G connects between the trench contacts 530 LG and 530 UG to electrically couple the lower gate 522 L and the upper gate 522 U.
- the metal interconnect M DS connects between the trench contacts 530 LD and 530 UD to electrically couple the lower drain/source region 514 LD and the upper drain/source region 514 UD.
- the metal interconnect M SD is connected between the trench contact 530 LS and a via 538 to electrically couple the upper source/drain region 514 US of the NFET 504 N to ground (e.g., V SS ).
- the via 532 LS electrically couples the lower source/drain region 514 LS of the PFET 504 P to a supply voltage (V DD ).
- FIGS. 5C-1 and 5C-2 also show dummy gates 540 located according to a gate pitch P G in the X-axis direction relative to the lower field gate 527 L and the upper field gate 527 U.
- the length dimension LG L of the upper gate region 508 U of the CFET cell circuit 500 in the X-axis direction may be smaller than a length of a channel region in a silicon channel structure (e.g., fin).
- the gate pitch P G of the CFET standard cell which determines a dimension of the CFET cell circuit 500 in the X-axis direction, may also be smaller.
- FIG. 5D shows a top view of the CFET cell circuit 500 with the upper circuit layer 502 U of FIG. 5C-2 disposed above and in horizontal alignment with the lower circuit layer 502 L of FIG. 5C-1 .
- FIG. 5D shows the upper channel structure 506 U disposed directly above the lower channel structure 506 L to reduce a dimension of the CFET cell circuit 500 in the Y-axis direction.
- the horizontal interconnects 534 LS and 534 LD and the lower field gate 527 L provide unobstructed vertical access locations for the vias 532 LS, 532 LG, and 532 LD to electrically couple the PFET 504 P to the NFET 504 N and/or an external circuit.
- CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit, as illustrated in any of FIGS. 2A-2D and 5A-5D , and according to any aspects disclosed herein, may be provided in or integrated into any processor-based device.
- GPS
- FIG. 6 illustrates an example of a processor-based system 600 with circuits 602 that can include CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit, including, but not limited to, the cell circuits 200 and 500 of FIGS. 2A-2D and 5A-5D , respectively, and according to any aspects disclosed herein.
- the processor-based system 600 may be formed as an IC 604 in a system-on-a-chip (SoC) 606 .
- SoC system-on-a-chip
- the processor-based system 600 includes a processor 608 that includes one or more central processor units (CPUs) 610 , which may also be referred to as CPU or processor cores.
- the processor 608 may have cache memory 612 coupled to the CPUs 610 for rapid access to temporarily stored data.
- the CPUs 610 could include CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit, including, but not limited to, the cell circuits 200 and 500 of FIGS.
- the processor 608 is coupled to a system bus 614 and can intercouple master and slave devices included in the processor-based system 600 . As is well known, the processor 608 communicates with these other devices by exchanging address, control, and data information over the system bus 614 . For example, the processor 608 can communicate bus transaction requests to a memory controller 616 as an example of a slave device. Although not illustrated in FIG. 6 , multiple system buses 614 could be provided, wherein each system bus 614 constitutes a different fabric.
- Other master and slave devices can be connected to the system bus 614 . As illustrated in FIG. 6 , these devices can include a memory system 620 that includes the memory controller 616 and a memory array(s) 618 , one or more input devices 622 , one or more output devices 624 , one or more network interface devices 626 , and one or more display controllers 628 , as examples.
- Each of the memory system 620 , the one or more input devices 622 , the one or more output devices 624 , the one or more network interface devices 626 , and the one or more display controllers 628 can include CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit including, but not limited to, the cell circuits 200 and 500 of FIGS. 2A-2D and 5A-5D , respectively, and according to any aspects disclosed herein.
- the input device(s) 622 can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc.
- the output device(s) 624 can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc.
- the network interface device(s) 626 can be any device configured to allow exchange of data to and from a network 630 .
- the network 630 can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTHTM network, and the Internet.
- the network interface device(s) 626 can be configured to support any type of communications protocol desired.
- the processor 608 may also be configured to access the display controller(s) 628 over the system bus 614 to control information sent to one or more displays 632 .
- the display controller(s) 628 sends information to the display(s) 632 to be displayed via one or more video processors 634 , which process the information to be displayed into a format suitable for the display(s) 632 .
- the display(s) 632 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.
- the display controller(s) 628 , display(s) 632 , and/or the video processor(s) 634 can include CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit, including, but not limited to, the cell circuits 200 and 500 of FIGS. 2A-2D and 5A-5D , respectively, and according to any aspects disclosed herein.
- FIG. 7 illustrates an exemplary wireless communications device 700 that includes radio frequency (RF) components formed from an IC 702 , wherein any of the components therein can include CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit, including, but not limited to, the cell circuits 200 and 500 of FIGS. 2A-2D and 5A-5D , respectively, and according to any aspects disclosed herein.
- the wireless communications device 700 may include or be provided in any of the above-referenced devices, as examples. As shown in FIG.
- the wireless communications device 700 includes a transceiver 704 and a data processor 706 .
- the data processor 706 may include a memory to store data and program codes.
- the transceiver 704 includes a transmitter 708 and a receiver 710 that support bi-directional communications.
- the wireless communications device 700 may include any number of transmitters 708 and/or receivers 710 for any number of communication systems and frequency bands. All or a portion of the transceiver 704 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.
- the transmitter 708 or the receiver 710 may be implemented with a super-heterodyne architecture or a direct-conversion architecture.
- a signal is frequency-converted between RF and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for the receiver 710 .
- IF intermediate frequency
- the direct-conversion architecture a signal is frequency-converted between RF and baseband in one stage.
- the super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements.
- the transmitter 708 and the receiver 710 are implemented with the direct-conversion architecture.
- the data processor 706 processes data to be transmitted and provides I and Q analog output signals to the transmitter 708 .
- the data processor 706 includes digital-to-analog converters (DACs) 712 ( 1 ), 712 ( 2 ) for converting digital signals generated by the data processor 706 into the I and Q analog output signals, e.g., I and Q output currents, for further processing.
- DACs digital-to-analog converters
- lowpass filters 714 ( 1 ), 714 ( 2 ) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the prior digital-to-analog conversion.
- Amplifiers (AMPs) 716 ( 1 ), 716 ( 2 ) amplify the signals from the lowpass filters 714 ( 1 ), 714 ( 2 ), respectively, and provide I and Q baseband signals.
- An upconverter 718 upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals through mixers 720 ( 1 ), 720 ( 2 ) from a TX LO signal generator 722 to provide an upconverted signal 724 .
- TX transmit
- LO local oscillator
- a filter 726 filters the upconverted signal 724 to remove undesired signals caused by the frequency upconversion as well as noise in a receive frequency band.
- a power amplifier (PA) 728 amplifies the upconverted signal 724 from the filter 726 to obtain the desired output power level and provides a transmitted RF signal.
- the transmitted RF signal is routed through a duplexer or switch 730 and transmitted via an antenna 732 .
- the antenna 732 receives signals transmitted by base stations and provides a received RF signal, which is routed through the duplexer or switch 730 and provided to a low noise amplifier (LNA) 734 .
- the duplexer or switch 730 is designed to operate with a specific receive (RX)-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals.
- the received RF signal is amplified by the LNA 734 and filtered by a filter 736 to obtain a desired RF input signal.
- Downconversion mixers 738 ( 1 ), 738 ( 2 ) mix the output of the filter 736 with I and Q RX LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator 740 to generate I and Q baseband signals.
- the I and Q baseband signals are amplified by amplifiers (AMPs) 742 ( 1 ), 742 ( 2 ) and further filtered by lowpass filters 744 ( 1 ), 744 ( 2 ) to obtain I and Q analog input signals, which are provided to the data processor 706 .
- the data processor 706 includes Analog to Digital Converters (ADCs) 746 ( 1 ), 746 ( 2 ) for converting the analog input signals into digital signals to be further processed by the data processor 706 .
- ADCs Analog to Digital Converters
- the TX LO signal generator 722 generates the I and Q TX LO signals used for frequency upconversion, while the RX LO signal generator 740 generates the I and Q RX LO signals used for frequency downconversion.
- Each LO signal is a periodic signal with a particular fundamental frequency.
- a TX phase-locked loop (PLL) circuit 748 receives timing information from the data processor 706 and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from the TX LO signal generator 722 .
- an RX PLL circuit 750 receives timing information from the data processor 706 and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from the RX LO signal generator 740 .
- DSP Digital Signal Processor
- ASIC Application Specific Integrated Circuit
- FPGA Field Programmable Gate Array
- a processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
- a processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
- RAM Random Access Memory
- ROM Read Only Memory
- EPROM Electrically Programmable ROM
- EEPROM Electrically Erasable Programmable ROM
- registers a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art.
- An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
- the storage medium may be integral to the processor.
- the processor and the storage medium may reside in an ASIC.
- the ASIC may reside in a remote station.
- the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Nanotechnology (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- The technology of the disclosure relates generally to complementary metal-oxide semiconductor (MOS) (CMOS) circuits and, more specifically, to cell circuits having cell circuit architectures employing vertical integration to reduce horizontal scale of CMOS cell circuits.
- Transistors are essential and employed in large numbers in integrated circuit (IC) components. For example, components such as central processing units (CPUs) and memory systems each employ a large quantity of transistors for logic circuits and memory devices. Transistors are formed of semiconductor materials and may be identified as one of an N-type or a P-type depending on whether the semiconductor material in a channel region of the transistor is an n-type or a p-type channel, which determines whether the majority carriers for current flow are electrons or holes. A Field-Effect Transistor (FET) is a transistor technology widely used in logic circuits and memory devices. In particular, a metal-oxide semiconductor (MOS) FET (MOS FEY) may be one of a P-type or an N-type, and is referred to as a PMOS FET (PFET) and an NMOS FET (NFET). Forming logic circuits and memory devices of PFETs and NFETs coupled together in a complementary configuration provides improved performance, power reduction, and resistance to noise in comparison to designs of either NFET or PFET circuits alone. Such complementary configurations are known as complementary MOS (CMOS) circuits. To automate the process of designing IC components which may contain millions of transistors, standardized CMOS logic cell circuits (e.g., inverters, NAND, NOR, etc.) have been developed for use with design automation software tools. Design automation tools are able to generate physical layouts of circuits in which the standardized CMOS circuits are optimally positioned to minimize a total circuit area. Such standardized CMOS circuits are known as standard cells and may also be referred to herein as cell circuits.
- There is ongoing market pressure to increase functionality of electronic devices while reducing their power consumption and size, which directly relates to cost. The ICs that provide such functionality contain millions of cell circuits, so there are efforts to reduce the area occupied by each cell circuit. A physical layout of a CMOS cell circuit, which may also be referred to as a “standard cell,” includes at least one PMOS transistor and at least one NMOS transistor for forming logic gates as well as internal interconnects of the PMOS and NMOS transistors, and contacts for external interconnection to power, ground, and other circuits. The physical layout of the elements of the CMOS cell circuit determines a total area or footprint occupied by a CMOS cell circuit. To reduce a size of a cell circuit, dimensions of the elements therein, such as a gate length in the direction of current flow in the channel structure, may be reduced. However, with decreasing gate length there is an increase in problems such as leakage currents and on/off control. In addition, gate length scaling is reaching a physical limitation due to a quantum tunneling effect. To improve current flow control in the channel region, FinFET devices and Gate-All-Around (GAA) devices have been developed with gates that at least partially surround a semiconductor channel forming a channel region to apply an electric field to a larger surface area of the channel region than in planar FETs.
- In one example,
FIG. 1 illustrates a top view of alayout 100 as an example of a conventional CMOS standard cell 102 (also referred to as “standard cell 102”) employing FinFETs. FinFETs are a transistor technology in which a semiconductor channel is provided in a fin structure extending vertically above the substrate, making it possible to increase a cross-sectional area of current flow without increasing a horizontal area. Thestandard cell 102 includes gates 104(1)-104(4) disposed along respective, parallel longitudinal axes A1 Y(1)-A1 Y(4) in afirst direction 106 of the Y-axis with a defined gate pitch G. Thestandard cell 102 includes afirst voltage rail 108 configured to be coupled to a supply voltage. Thefirst voltage rail 108 is disposed along a longitudinal axis A1 X(1) in asecond direction 110 of the X-axis substantially orthogonal to thefirst direction 106 in a first metal layer 112 (e.g., a metal zero (M0) metal layer). Additionally, thestandard cell 102 includes asecond voltage rail 114 having a longitudinal axis A1 X(2) in thesecond direction 110 in thefirst metal layer 112. Thestandard cell 102 also includesdiffusion regions standard cell 102 also includes fins 118(1)-118(4) for forming semiconductor channels of FinFETs disposed in thesecond direction 110 between the first andsecond voltage rails type diffusion region 116P will include two fins 118(1), 118(2) to form its semiconductor channel, and a second FinFET 120P formed in the N-type diffusion region 116N will include two fins 118(3), 118(4) to form its semiconductor channel. The gate 104(3), for example, is disposed on a top surface and both side surfaces of each of the fins 118(1)-118(4) for improved current flow control. Trench contacts 122(1)-122(3) are also formed in thefirst direction 106 to provide contacts to source/drain regions S(1)-S(4), D(1)-D(4) of the fins 118(1)-118(4) formed in thestandard cell 102. Trench contact 122(1) has been cut. A metal line 124(1) can be formed in thefirst metal layer 112 to provide an interconnection to the trench contact 122(1) to provide interconnections to the source or drain region S(1), D(1). Vias (V1) 126(1), 126(2) can be formed over portions of the gates 104(1)-104(4) to form metal contacts to the gates 104(1)-104(4). - A dimension of the
standard cell 102 in the Y-axis direction includes dimensions of the P-type diffusion region 116P, the N-type diffusion region 116N, and a non-diffusion region between the N-type and P-type diffusion regions standard cell 102 inFIG. 1 each have two (2) respective fins 118(1)-118(2) and 118(3)-118(4) to serve as channel structures. A Y-axis dimension of a conventional CMOS standard cell may be minimized by employing a FinFET with only one fin in each of the P-type diffusion region 116P and the N-type diffusion region 116N, and further advancements in technology have made it possible to fabricate standard cells that support FinFETs employing a single fin for a channel structure. Thus, a CMOS standard cell layout for single-fin FinFETs can occupy less area than thestandard cell 102 inFIG. 1 for example, which can reduce total chip size and the number of internal interconnections required. However, there is a desire to reduce even further the footprint size of a cell circuit, but no further reduction of the number of fins in a FinFET is possible. In general, a dimension of a standard cell layout in the Y-axis direction remains constant but dimensions of cells vary in the X-axis direction. Reducing the Y-axis dimension of standard cells can significantly reduce layout size. The Y-axis dimension is dominated by a metal line pitch in the first and second metal layers (M0, M1), which are used for transistor contacts for routing power and signals, M0/M1 pitch scaling is an important factor in determining a minimum layout size but benefits of scaling M0/M1 pitch are limited by fin pitch, contact location/pitch and minimum routing requirements. Thus, other methods are sought for reducing a layout area of a standard cell. - In the X-axis direction, a dimension of the
standard cell 102 includes a length of a gate region along the longitudinal axes A1 Y(1)-A1 Y(4) of the fins 118(1)-118(4). To reduce a dimension in the X-axis direction, a length of a gate region may be reduced. However, as a length of a gate region in a conventional CMOS standard cell with a silicon (Si) channel structure is reduced, leakage currents become difficult to control, despite the increased current flow control made possible by multi-faceted gates employed in FinFETs and GAA FETs. Further gate length scaling will be limited as physical limitations are reached. - Aspects disclosed herein include vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits. An exemplary CFET cell circuit includes an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of vertically-stacked elongated slabs of 2D semiconductor material to provide a footprint reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit. In one aspect, the CFET cell circuit may include a complementary metal-oxide semiconductor (CMOS) circuit in an integrated circuit structure with an N-type semiconductor channel structure of an N-type FET (NFET) in a first layer and a P-type semiconductor channel structure of a P-type FET (PFET) in a second layer stacked vertically above the first layer to reduce a Y-axis dimension of the horizontal footprint of the CFET cell circuit. The horizontal footprint of the (TEE cell circuit may also be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type semiconductor channel structures. In this regard, the N-type and P-type semiconductor channel structures may be formed of vertically-stacked layers of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. For example, the 2D semiconductor materials may be MX2-type compounds (e.g., transition metal dichalcogenides) formed in elongated 2D atomic monolayers, each capable of conducting an amount of current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking the slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.
- In an aspect, a CFET cell circuit is disclosed herein. The CFET cell circuit includes a substrate, a lower circuit layer, and an upper circuit layer. The lower circuit layer includes an NFET that is disposed above the substrate and includes a lower channel structure and a lower gate. The lower channel structure includes a first two-dimensional (2D) semiconductor slab of a first type vertically integrated with a second 2D semiconductor slab of the first type. Each of the first and second 2D slabs has a longitudinal axis in a first direction. The lower channel structure also includes a lower source/drain region integrated with first end portions of the first and second 2D slabs, and a lower drain/source region integrated with second end portions of the first and second 2D slabs. The lower gate is disposed on faces of the first and second 2D slabs between the lower source/drain region and the lower drain/source region. The upper circuit layer includes a PFET that is disposed above the lower circuit layer and includes an upper channel structure and an upper gate. The upper channel structure includes a third 2D semiconductor slab of a second type vertically integrated with a fourth 2D semiconductor slab of the second type. Each of the third and fourth 2D slabs has a longitudinal axis in a second direction. The upper channel structure also includes an upper source/drain region integrated with first end portions of the third and fourth 2D slabs, and an upper drain/source region integrated with second end portions of the third and fourth 2D slabs. The upper gate is disposed on faces of the third and fourth 2D slabs between the lower source/drain region and the lower drain/source region.
- In another aspect, a method of fabricating a CFET cell circuit is disclosed herein. The method includes forming a lower circuit layer including an NFET above a substrate, and forming an upper circuit layer including a PE ET above the lower circuit layer. Forming the lower circuit layer includes vertically stacking a first 2D slab and a second 2D slab to form a lower semiconductor channel structure for the NFET, with the first and second 2D slabs each having a longitudinal axis and including a semiconductor material of a first type. Forming the lower circuit layer further includes disposing a lower gate of the NFET on faces of the first and second 2D slabs. Forming the lower circuit layer further includes integrating a lower source/drain material with first end portions of the first and second 2D slabs to form a lower source/drain region of the NFET on a first side of the lower gate, and integrating a lower drain/source material with second end portions of the first and second 2D slabs to form a lower drain/source region of the NFET on a second side of the lower gate. Forming the upper circuit layer includes vertically stacking a third 2D slab and a fourth 2D slab to form an upper semiconductor channel structure of the PFET, with the third and fourth 2D slabs each having a longitudinal axis and including a semiconductor material of a second type. Forming the upper circuit layer further includes disposing an upper gate of the PET on faces of the third and fourth 2D slabs. Forming the upper circuit layer further includes integrating an upper source/drain material with first end portions of the third and fourth 2D slabs to form an upper source/drain region of the PFET on a first side of the upper gate, and integrating an upper drain/source material with second end portions of the third and fourth 2D slabs to form an upper drain/source region of the PFET on a second side of the upper gate.
-
FIG. 1 is a top view of a conventional complementary metal-oxide semiconductor (CMOS) cell circuit layout including a P-type metal oxide semiconductor (MOS) (PMOS) Fin Field-Effect Transistor (FET) (FinFET) and an N-type MOS (NMOS) FinFET laterally disposed on a semiconductor layer; -
FIG. 2A is a cross-sectional side view in a first direction of an exemplary Complementary FET (CFET) cell circuit with a lower circuit layer including an N-type FET (NFET) disposed above a substrate, the NFET including a lower channel structure formed of vertically-integrated 2D semiconductor slabs of a first type, and an upper circuit layer including a P-type FET (PFET) disposed above the lower circuit layer, the PFET including an upper channel structure formed of vertically-integrated 2D semiconductor slabs of a second type to reduce the footprint size of the CFET cell circuit; -
FIG. 2B is a cross-sectional side view of the CFET cell circuit shown inFIG. 2A in a second direction orthogonal to the first direction inFIG. 2A ; -
FIGS. 2C-1 and 2C-2 are top views of the lower circuit layer of the CFET cell circuit shown inFIGS. 2A and 2B , which includes an NFET disposed on a substrate, and the upper circuit layer including a PFET disposed on the lower circuit layer during fabrication; -
FIG. 2D is a top view of the lower and upper circuit layers of the CFET cell circuit inFIGS. 2C-1 and 2C-2 , respectively, forming the CFET cell circuit inFIGS. 2A and 2B ; -
FIG. 3 is a flowchart illustrating an exemplary process for fabricating the lower and upper circuit layers that include the respective NFET and PFET in the CFET cell circuit inFIGS. 2A-2D ; -
FIG. 4A is a cross-sectional side view of a first exemplary fabrication stage for fabricating the CFET cell circuit inFIGS. 2A-2D , in which a first plurality of vertically-stacked 2D slabs, each having a first semiconductor type, is disposed above a substrate, according to the exemplary fabrication process inFIG. 3 ; -
FIG. 4B is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D of an exemplary dummy gate disposed on a lower gate region of a first plurality of vertically-integrated 2D slabs; -
FIG. 4C is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which oxide layers between first end portions and second end portions of the first plurality of vertically-integrated 2D slabs are removed, and side spacers are formed on sides of the dummy gate and sides of the lower gate region; -
FIG. 4D is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit shown inFIGS. 2A-2D in which an inter-layer dielectric (ILD) is formed between the first end portions and the second end portions of the first plurality of vertically-integrated 2D slabs, and the first plurality of vertically-integrated 2D slabs is covered with a mask layer; -
FIG. 4E is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which an opening is formed in the mask layer to allow deposition of high-k dielectric material and gate metal on faces of the first plurality of vertically-integrated 2D slabs to form a lower gate in the lower gate region, according to the fabrication process inFIG. 3 ; -
FIG. 4F is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which the ILD between the first end portions and second end portions of the first plurality of vertically-integrated 2D slabs is removed and replaced by NMOS source/drain material to form a lower source/drain region and a lower drain/source region, according to the fabrication process inFIG. 3 ; -
FIG. 4G is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which ILD is deposited above the first plurality of vertically-integrated 2D slabs, and contacts to the lower source/drain region and lower drain/source region are formed in the ILD, according to the fabrication process inFIG. 3 ; -
FIG. 4H is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which ILD is disposed on the first plurality of vertically-integrated 2D slabs to form a lower circuit layer, and a second plurality of vertically-stacked 2D slabs, each having a second semiconductor type, is disposed above the lower circuit layer, according to the fabrication process inFIG. 3 ; -
FIG. 4I is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which an exemplary dummy gate is disposed on an upper gate region of the second plurality of vertically-integrated 2D slabs; -
FIG. 4K is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which oxide layers between first end portions and second end portions of the second plurality of vertically-integrated 2D slabs are removed, and side spacers are formed on sides of the dummy gate and sides of the upper gate region; -
FIG. 4K is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which ILD is formed between the first end portions and the second end portions of the second plurality of vertically-integrated 2D slabs, and the second plurality of vertically-integrated 2D slabs is covered with a mask layer; -
FIG. 4L is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which an opening is formed in the mask layer inFIG. 4K to allow deposition of high-k dielectric material and gate metal on faces of the second plurality of vertically-integrated 2D slabs to form an upper gate in the upper gate region, according to the fabrication process inFIG. 3 ; -
FIG. 4M is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which the ILD between the first end portions and second end portions of the second plurality of vertically-integrated 2D slabs is removed and replaced by PMOS source/drain material to form an upper source/drain region and an upper drain/source region, according to the fabrication process inFIG. 3 ; -
FIG. 4N is a cross-sectional side view in another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which ILD is deposited above the second plurality of vertically-integrated 2D slabs, and contacts to the upper source/drain region and upper drain/source region are formed in the ILD; -
FIG. 4O is a cross-sectional side view in an another exemplary fabrication stage of the CFET cell circuit inFIGS. 2A-2D in which additional ILD is deposited above the contacts to the upper source/drain region and the upper drain/source region, and metal interconnects coupled to the contacts are formed in the additional ILD; -
FIG. 5A is a cross-sectional side view in a first direction of another exemplary CFET cell circuit with a lower circuit layer including a PFET disposed above a substrate, the NTT including a lower channel structure formed of vertically-integrated 2D semiconductor slabs of a first type, and an upper circuit layer including an NFET disposed above the lower circuit layer, the NFET including an upper channel structure formed of vertically-integrated 2D semiconductor slabs of a second type to reduce the footprint size of the CFET cell circuit; -
FIG. 5B is a cross-sectional side view of the CFET cell circuit shown inFIG. 5A in a second direction orthogonal to the first direction inFIG. 5A ; -
FIGS. 5C-1 and 5C-2 are top views of the lower circuit layer of the CFET′ cell circuit shown inFIGS. 5A and 5B , which includes a PFET disposed on a substrate, and the upper circuit layer including an NFET disposed on the lower circuit layer during fabrication; -
FIG. 5D is a top view of the lower and upper circuit layers of the CFET cell circuit inFIGS. 5C-1 and 5C-2 , respectively, forming the CFET cell circuit inFIGS. 5A and 5B ; -
FIG. 6 is a block diagram of an exemplary processor-based system that can include a CFET cell circuit in which a PFET and an NFET are vertically integrated by stacking a second semiconductor layer that includes a second FET above a first semiconductor layer that includes a first FET, such that the channel structure of the second FET is formed above the channel structure of the first FET to reduce a footprint of a CFET cell circuit including, but not limited to, the CFET cell circuits inFIGS. 2A-2D and 5A-5D ; and -
FIG. 7 is a block diagram of an exemplary wireless communications device that includes radio frequency (RF) components formed from an integrated circuit (IC), wherein any of the components therein can include a CFET cell circuit including, but not limited to, the CFET cell circuits inFIGS. 2A-2D and 5A-5D . - With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
- Aspects disclosed herein include vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (YET) (CFET) cell circuits. An exemplary CFET cell circuit includes an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of vertically-stacked elongated slabs of 2D semiconductor material to provide a footprint reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit. In one aspect, the CFET cell circuit may include a complementary metal-oxide semiconductor (CMOS) circuit in an integrated circuit structure with an N-type semiconductor channel structure of an N-type FET (NFET) in a first layer and a P-type semiconductor channel structure of a P-type FET (PFET) in a second layer stacked vertically above the first layer to reduce a Y-axis dimension of the horizontal footprint of the CFET cell circuit. The horizontal footprint of the CFET cell circuit may also be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type semiconductor channel structures. In this regard, the N-type and P-type semiconductor channel structures may be formed of vertically-stacked layers of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. For example, the 2D semiconductor materials may be MX2-type compounds (e.g., transition metal dichalcogenides) formed in elongated 2D atomic monolayers, each capable of conducting an amount of current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking the slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.
- To further reduce a dimension of a CFET cell circuit in the Y-axis direction, a CFET cell circuit may include an NFET vertically-integrated with a PFET in a complementary configuration (e.g., as a CMOS circuit). The disclosed CFET cell circuit is provided in an integrated circuit structure including an N-type channel structure and a P-type channel structure stacked vertically to reduce a horizontal footprint. In this regard,
FIG. 2A illustrates a cross-sectional side view of a of aCFET cell circuit 200 in the Z-axis and Z-axis shown therein. The cross-sectional view shown inFIG. 2A is taken along the line X-X′ shown in a top view of theCFET cell circuit 200 illustrated inFIG. 2D . As will be discussed in more detail below, theCFET cell circuit 200 includes anupper circuit layer 202U with aPFET 204P disposed vertically above (i.e., stacked above) alower circuit layer 202L with anNFET 204N. In this manner, the vertical stacking reduces the horizontal footprint of theCFET cell circuit 200 in the Y-axis direction. TheNFET 204N and thePFET 204P may be interconnected in a complementary configuration, as in a CMOS circuit. - In addition, an X-axis dimension of a footprint of the
CFET cell circuit 200 may be reduced by reducing length dimensions of theNFET 204N and thePFET 204P. In particular, theNFET 204N in thelower circuit layer 202L is formed in alower channel structure 206L in which agate region 208L has a length dimension LGL in the X-axis direction, and thePFET 204P in theupper circuit layer 202U is formed in anupper channel structure 206U in which agate region 208U has a length dimension LGU in the X-axis direction. By reducing the length dimensions LGL and LGU, a dimension in the X-axis direction of a footprint of theCFET cell circuit 200 may be reduced. - In an exemplary aspect, MX2-type compounds (e.g., transition metal dichalcogenide crystals), known as “2D materials,” may be employed in the semiconductor channel structures of the
NFET 204N andNTT 204P to reduce the lengths LGL and LGU in the X-axis direction without a corresponding increase in leakage current associated with reducing a length of a gate region of a silicon channel structure. In theCFET cell circuit 200 inFIG. 2A , thelower circuit layer 202L includes theNFET 204N, and theupper circuit layer 202U includes thePFET 204P. TheNFET 204N is disposed on anisolation layer 207L above asubstrate 209. The lower channel structure 2061_, includes a first 2D semiconductor slab (“2D slab”) 210N(1) of the 2D material vertically integrated with asecond 2D slab 210N(2). In theCFET cell circuit 200 inFIG. 2A , a “slab” is a structure formed of one or more layers of a 2D material, with first and second dimensions in orthogonal directions (e.g., X-axis and Y-axis directions) and having a thickness dimension which is orthogonal to the first and second dimensions (e.g., Z-axis direction) and is smaller than the first and second dimensions. As shown in a top view of theCFET cell circuit 200 inFIG. 2C-1 , the2D slabs 210N(1) and 210N(1) may each extend in a range from 20 nm to 500 nm in a longitudinal direction (e.g., X-axis direction), and extend in a range from 3 nm to 50 nm in a direction orthogonal to the longitudinal direction (e.g., Y-axis direction). As shown inFIG. 2A , the2D slabs 210N(1) and 210N(2) have a thickness dimension, which may be in the range from 0.6 nm to 10.0 nm. Thelower channel structure 206L inFIG. 2A may also include additional 2D slabs, such as2D slab 210N(3), vertically integrated with the first andsecond 2D slabs 210N(1) and 210N(2) to increase a drive strength of theNFET 204N. Although the slab structures inFIG. 2A may appear to be planar, stackable slabs having other (e.g., non-planar) shapes are within the scope of the present disclosure. - Each of the
2D slabs 210N(1)-210N(3) includes at least one monolayer (not individually shown) of a first type of 2D semiconductor material 218(1), such as an N-type material 218N, extending in the X-axis direction and the Y-axis direction. 2D materials are atomically thin semiconductor monolayers of an MX2 compound, where M is a transition metal atom (Mo, W, etc.) and X is a chalcogen atom (S, Se, or Te). For example, the N-type material 218N may be tungsten disulfide (WS2). Crystal monolayers of MX2 compounds have a high carrier mobility, lower dielectric constant, and thinner channel thickness than silicon, providing strong on/off control of the channel. Therefore, a channel structure formed of MX2 compounds may have higher drive strength and lower leakage current than a similarly-sized silicon channel structure. By employing the N-type material 218N in the2D slabs 210N(1)-210N(3), channel control in thelower gate region 208L is improved over a channel region of the same length in a channel structure formed of silicon. Therefore, by employing the 2D material in thelower channel structure 206L, rather than silicon, the length LGL of thelower gate region 208L may be made smaller to reduce a dimension of theCFET cell circuit 200 in the X-axis direction without a causing an increase in leakage current in theNFET 204N. The2D slabs 210N(1)-210N(3) extend along respective longitudinal axes A2 L(1)-A2 L(3) and may be integrated by stacking in a vertical (e.g., Z-axis) direction one above another. By vertically stacking the2D slabs 210N(1)-210N(3) such that their longitudinal axes A2 L(1)-A2 L(3) overlap (e.g., in the Z-axis direction) an area occupied by thelower channel structure 206L is minimized. - With continuing reference to
FIG. 2A , thelower channel structure 206L also includes a lower source/drain material 221L integrated with first end portions 216LS(1)-216LS(3) of the2D slabs 210N(1)-210N(3) for forming a lower source/drain region 214LS and the lower source/drain material 221L integrated with second end portions 216LD(1)-216LD(3) of the2D slabs 210N(1)-210N(3) to form a lower drain/source region 214LD. In operation of theNFET 204N, either the lower source/drain region 214LS or the lower drain/source region 214LD may function as a source while the other functions as a drain. Integration of the lower source/drain region 214LS and the lower drain/source region 214LD with the respective end portions 216LS(1)-216LS(3) and 216LD(1)-216LD(3) may include one or more of doping the2D slabs 210N(1)-210N(3) with the lower source/drain material 221L, growing the lower source/drain material 221L epitaxially on the2D slabs 210N(1)-210N(3), and forming the lower source/drain material 221L on or in contact with the2D slabs 210N(1)-210N(3) As shown inFIG. 2A , the lower source/drain material 221L of the lower source/drain region 214LS and the lower drain/source region 214LD may be formed on faces of the2D slabs 210N(1)-210N(3), except where the2D slab 210N(1) is in contact with the isolation layer 2071. For example, the lower source/drain material 221L may be formed on top face 220LT, bottom face 220LB, side face 220LS, and end faces 220LE of2D slab 210N(2) in the first and second end portions 216LS(2) and 216LD(2). The lower source/drain material 221L may be similarly formed on faces of2D slabs 210N(1) and 210N(3), as shown inFIG. 2A . - By vertically stacking the
2D slabs 210N(1)-210N(3) such that their longitudinal axes A2 L(1)-A2 L(3) overlap, as discussed above, a current flow in each of the2D slabs 210N(1)-210N(3) may be controlled by a single gate structure. In this regard, thelower channel structure 206L includes alower gate 222L disposed on faces of the2D slabs 210N(1)-210N(3), such as the faces 220LT, 220LB, and 220LS of2D slab 210N(2). Thelower gate 222L is disposed on the2D slabs 210N(1)-210N(3) between the lower source/drain region 214LS and the lower drain/source region 214LD in the X-axis direction. Thelower gate 222L is separated from the lower source/drain region 214LS by side spacer 224LS and separated from the lower drain/source region 214LD by side spacer 224LD. Thelower gate 222L includesgate portions 225L electrically insulated from therespective 2D slabs 210N(1)-210N(3) by gate dielectric layers 226L. Thelower gate 222L also includes alower field gate 227L (shown inFIG. 2B ) which provides a horizontal interconnect disposed on thelower gate 222L. Thelower circuit layer 202L also includes trench contacts 230LS and 230LD formed above the lower source/drain region 214LS and the lower drain/source region 214LD, respectively. An inter-layer dielectric (ILD) 228L surrounds theMET 204N, thelower field gate 227L and the trench contacts 230LS and 230LD. Thelower field gate 227L and the trench contacts 230LS and 230LD are discussed further with respect toFIG. 2B , below. - As noted above, the
CFET cell circuit 200 inFIG. 2A also includes theupper circuit layer 202U disposed above thelower circuit layer 202L that includes thePFET 204P to provide a CMOS architecture for theCFET cell circuit 200. Theupper circuit layer 202U of theCFET cell circuit 200 will now be discussed. In this regard, as shown inFIG. 2A , theupper circuit layer 202U includes thePFET 204P disposed on anisolation layer 207U. ThePFET 204P is formed in anupper channel structure 206U including athird 2D slab 210P(1) vertically integrated with afourth 2D slab 210P(2). Theupper channel structure 206U inFIG. 2A also includes another2D slab 210P(3) vertically integrated with the third andfourth 2D slabs 210P(1) and 210P(2) to increase a drive strength of thePFET 204P. Each of the 2D slabs 2101)(1)-210P(3) includes at least one monolayer (not individually shown) of a second 2D semiconductor material 218(2) (e.g., MX2 material), such as a P-type material 218P, extending in the X-axis direction and the Y-axis direction. For example, the P-type material 218P may be molybdenum disulfide (MoS2). By employing 2D materials for the P-type material 218P in the2D slabs 210P(1)-210P(3), channel control in anupper gate region 208U is improved over a channel region in a channel structure formed of silicon. Therefore, the length LGU of theupper gate region 208U may be made smaller to reduce a dimension of theOTT cell circuit 200 in the X-axis direction without causing an increase in leakage current in thePFET 204P. The2D slabs 210P(1)-210P(3) extend along respective longitudinal axes A2 U(1)-A2 U(3) in the X-axis direction and may be integrated in the vertical direction one above another. - The
upper channel structure 206U also includes an upper source/drain material 221U integrated with first end portions 216US(1)-216US(3) of the2D slabs 210P(1)-210P(3) to form an upper source/drain region 214US and the upper source/drain material 221U integrated with second end portions 216UD(1)-216UD(3) of the 2D slabs 2101)(1)-210P(3) to form an upper drain/source region 214UD. In operation of thePFET 204P, either the upper source/drain region 214US or the upper drain/source region 214UD may function as a source while the other functions as a drain. Integration of the upper source/drain region 214US and the upper drain/source region 214UD with the respective end portions 216US(1)-216US(3) and 216UD(1)-216UD(3) may include one or more of doping the2D slabs 210P(1)-210P(3) with the upper source/drain material 221U, growing the upper source/drain material 221U epitaxially on the2D slabs 210P(1)-210P(3), and forming the upper source/drain material 221U on or in contact with the2D slabs 210P(1)-210P(3). As shown inFIG. 2A , the upper source/drain material 221U of the upper source/drain region 214US and the upper drain/source region 214UD may be formed on faces of the2D slabs 210P(1)-210P(3), except where the2D slab 210P(1) is in contact with theisolation layer 207U. For example, the upper source/drain material 221U may be formed on faces of the2D slab 210P(2) in the end portions 216US(2) and 216UD(2). The upper source/drain material 221U may be similarly formed on faces of2D slabs 210P(1) and 210P(3), as shown inFIG. 2A . - The
upper channel structure 206U also includes anupper gate 222U disposed on faces of the2D slabs 210P(1)-210P(3). Theupper gate 222U is disposed on the2D slabs 210P(1)-210P(3) between the upper source/drain region 214US and the upper drain/source region 214UD. Theupper gate 222U is separated from the upper source/drain region 214US by side spacer 224US and separated from the lower drain/source region 214UD by side spacer 224UD. Theupper gate 222U includesgate portions 225U electrically insulated from therespective 2D slabs 210P(1)-210P(3) by gate dielectric layers 226U. Theupper gate 222U also includes anupper field gate 227U (shown inFIG. 2B ) which provides a horizontal interconnect disposed on theupper gate 222U. Theupper circuit layer 202U includes trench contacts 230US and 230UD disposed above the upper source/drain region 214US and the upper drain/source region 214UD, respectively. Theupper circuit layer 202U also includes a trench contact 230UG disposed on theupper gate 222U. Metal layer interconnects MSD, MG, and MDS are disposed on the trench contracts 230US, 230UG, and 230UD, respectively, for coupling external circuits to thePFET 204P. AnILD 228U surrounds thePFET 204P, the metal layer interconnects MSD, MG, and MDS, and the trench contacts 230US, 230UG, and 230UD. - As shown in
FIG. 2A , anupper channel column 236U extends vertically (up and down) from a horizontal area of theupper channel structure 206U, and alower channel column 236L extends vertically from a horizontal area of thelower channel structure 206L. In this regard, theupper channel column 236U overlaps at least a portion of thelower channel column 236L. In the example inFIG. 2A , theupper channel structure 206U in theupper circuit layer 202U overlaps thelower channel structure 206L in thelower circuit layer 202L such that theupper channel column 236U fully overlaps (i.e., occupies substantially the same horizontal area extending in a vertical direction) as thelower channel column 236L. In another aspect the2D slab 210N(2) may partially overlap or fully overlap the2D slab 210N(1) when vertically stacked on the2D slab 210N(1) to minimize a horizontal area occupied by thelower channel structure 206L, and the2D slab 210P(2) may partially overlap or fully overlap the2D slab 210P(1) when vertically stacked on the2D slab 210P(1) to minimize a horizontal area occupied by theupper channel structure 206U. In this regard, a horizontal area (X-axis and Y-axis directions) occupied by theCFET cell circuit 200 may be reduced in comparison to thestandard cell 102 ofFIG. 1 in exchange for an increased dimension in the Z-direction. -
FIG. 2B illustrates a side view of a cross-section in the Y-axis and Z-axis directions of theCFET cell circuit 200. The cross-sectional view shown inFIG. 2B is taken along the line Y-Y′ shown in the top view of theCFET cell circuit 200 illustrated inFIG. 2D . The cross-sectional view inFIG. 2B shows the2D slabs 210N(1)-210N(3) one above another in thelower channel structure 206L and the2D slabs 210P(1)-210P(3) one above another in theupper channel structure 206U. As shown inFIG. 2B , the gate dielectric layers 226L are formed around each of the2D slabs 210N(1)-210N(3) to separate the2D slabs 210N(1)-210N(3) from thegate portions 225L of thelower gate 222L. Similarly, the gate dielectric layers 226U are formed around each of the2D slabs 210P(1)-210P(3) to separate the2D slabs 210P(1)-210P(3) from thegate portions 225U of theupper gate 222U. - In addition,
FIG. 2B shows an example of vertical integration of theupper channel structure 206U in theupper circuit layer 202U above thelower channel structure 206L in thelower circuit layer 202L to reduce a dimension of theCFET cell circuit 200 in the Y-axis direction. For example, theupper channel structure 206U may be positioned directly above thelower channel structure 206L. However, with thelower gate 222L in thelower channel structure 206L located directly below theupper channel structure 206U, a vertical inter-layer access (via) from thelower gate 222L to the metal interconnect MG may be obstructed. To avoid such obstruction, thelower field gate 227L extends in the Y-axis direction, orthogonal to the longitudinal axis A2 L(1) of thefirst 2D slab 210N(1), from thelower gate 222L to a location in thelower circuit layer 202L that is not vertically obstructed. In this regard, thelower field gate 227L provides a horizontal interconnect orthogonal to the longitudinal axes A2 L(1)-A2 L(3) (seeFIG. 2A ) from thelower gate 222L to a location in thelower circuit layer 202U in which a via 232LG to the metal interconnect MG is not obstructed by theupper channel structure 206U. Theupper field gate 227U may be formed on theupper gate 222U as a horizontal interconnect in theupper circuit layer 202U. In this regard, theupper field gate 227U may provide an alternative location for the trench contact 230UG, if needed. Referring back to thelower circuit layer 202L inFIG. 2B , a trench contact 230LG is formed on thelower field gate 227L, and the via 232LG extends through theupper circuit layer 202U from the trench contact 230LG in thelower circuit layer 202L to the metal interconnect MG above theupper circuit layer 202U. As will be disclosed with regard toFIGS. 2C-1 and 2C-2 , horizontal interconnects similar to thelower field gate 227L are provided in thelower circuit layer 202L from the lower source/drain region 214LS and the lower drain/source region 214LD to locations at which a via to metal interconnects above theupper circuit layer 202U may be unobstructed. -
FIG. 2C-1 illustrates a top view of a horizontal cross-section, taken at line Z-Z′ inFIG. 2B , showing features of thelower circuit layer 202L including theNFET 204N.FIG. 2C-1 shows horizontal interconnects 234LS and 234LD extending in the X-axis direction, orthogonal to thelower channel structure 206L, from the lower source/drain region 214LS and the lower drain/source region 214LD, respectively. Thelower field gate 227L is also shown extending in the Y-axis direction from thelower gate 222L. In addition,FIG. 2C-1 shows that the trench contacts 230LS, 230LG, and 230LD are in locations of thelower circuit layer 202L that are not vertically obstructed by theupper channel structure 206U in theupper circuit layer 202U. In this regard,FIG. 2C-1 shows that the trench contacts 230LS, 230LG, and 230LD are positioned according to a line pitch PY in the Y-axis direction relative to thelower channel structure 206L, and according to a line pitch PX in the X-axis direction relative to thelower field gate 227L. Line pitches PX and PY may be a center-to-center distance between features, as shown inFIG. 2C-1 . -
FIG. 2C-2 illustrates a top view of features of theupper circuit layer 202U including thePFET 204P.FIG. 2C-2 shows theupper field gate 227U extending in the Y-axis direction orthogonal to the longitudinal axes A2 U(1)-A2 U(3) (seeFIG. 2A ) and the trench contact 230UG in an alternative location to the location shown inFIG. 2B .FIG. 2C-2 shows top views of the via 232LG and vias 232LS and 232LD which are positioned to extend vertically from the trench contacts 230LG, 230LS, and 230LD, respectively, in thelower circuit layer 202L.FIG. 2C-2 also shows top views of the trench contracts 230US, 230UG, and 230UD in theupper circuit layer 202U. As shown, the vias 232LS, 232LG and 232LD and the trench contacts 230UG, 230US, and 230UD are spaced apart in theupper circuit layer 202U according to the line pitch PX in the X-axis direction and according to the line pitch PY in the Y-axis direction in an arrangement to minimize a footprint of theCFET cell circuit 200. -
FIG. 2C-2 shows electrical connections for configuring theNFET 204N inFIG. 2C-1 and thePFET 204P in a CMOS inverter configuration. For example, the metal interconnect MG connects between the trench contacts 230LG and 230UG to electrically couple thelower gate 222L and theupper gate 222U. The metal interconnection MDS connects between the trench contacts 230LD and 230UD to electrically couple the lower drain/source region 214LD and the upper drain/source region 214UD. The metal interconnect MSD is connected between the trench contact 230LS and a via 238 to electrically couple the upper source/drain region 214US of thePFET 204P to a supply voltage (e.g., VDD). The via 232LS electrically couples the lower source/drain region 214LS of theNFET 204N to ground (e.g., VSS). -
FIGS. 2C-1 and 2C-2 also showdummy gates 240 located according to a gate pitch PG in the X-axis direction relative to thelower field gate 227L and theupper field gate 227U. The supply voltage VDD and ground VSS may each be provided by one of the power rails 240. By employing MX2-type 2D materials to form thelower channel structure 206L and theupper channel structure 206U, the length dimensions LGL and LGU of theCFET cell circuit 200 in the X-axis direction may be smaller than a length of a channel region in a silicon channel structure (e.g., fin) without a corresponding increase in leakage current. By reducing the length dimension LGL, the gate pitch PG of theCFET cell circuit 200, which determines a dimension of theCFET cell circuit 200 in the X-axis direction, may also be smaller. -
FIG. 2D shows a top view of theCFET cell circuit 200 with theupper circuit layer 202U ofFIG. 2C-2 disposed above and in horizontal alignment with thelower circuit layer 202L ofFIG. 2C-1 .FIG. 2D shows theupper channel structure 206U disposed directly above thelower channel structure 206L to reduce a dimension of theCFET cell circuit 200 in the Y-axis direction. To avoid vertical obstruction created by locating theupper channel structure 206U directly above thelower channel structure 206L, the horizontal interconnects 234LS, 234LD and thelower field gate 227L provide unobstructed vertical access locations for the vias 232LS, 232LG, and 232LD to electrically couple theNFET 204N to thePFET 204P and/or an external circuit. -
FIG. 3 is a flowchart illustrating anexemplary process 300 for fabricating aCFET cell circuit 400, which corresponds to theCFET cell circuit 200 illustrated inFIGS. 2A-2D . Theprocess 300 is explained with reference to the fabrication stages illustrated inFIGS. 4A-4O . -
FIG. 4A is a cross-sectional view of afirst circuit layer 402L in a first fabrication stage 401(A) in which theCFET cell circuit 400 is formed. Thefirst circuit layer 402L corresponds to thelower circuit layer 202L inFIGS. 2A-2D . Anisolation layer 407L, such as a shallow trench isolation (STI) layer, is formed on asubstrate 409, which may be formed of silicon. Thelower circuit layer 402L including theisolation layer 407L is formed above the substrate 409 (block 302 inFIG. 3 ). Forming thelower circuit layer 402L includes vertically stacking afirst 2D slab 410N(1) and asecond 2D slab 410N(2) to form alower channel structure 406L. The first andsecond 2D slabs 410N(1) and 410N(2) have longitudinal axes A4 L(1) and A4 L(2), respectively, in a first direction and include a semiconductor material 418(1) of a first type (e.g., one of N-type or P-type) (block 304 inFIG. 3 ). Vertically stacking the first andsecond 2D slabs 410N(1) and 410N(2) includes forming one or more layers of the semiconductor material 418(1) (e.g., monolayers of MX2 material) for thefirst 2D slab 410N(1) on theisolation layer 407L, forming an oxide layer 411(1) on thefirst 2D slab 410N(1), forming one or more layers of the semiconductor material 418(1) for thesecond 2D slab 410N(2), and forming another oxide layer 411(2) above thesecond 2D slab 210N(2). Each2D slab 410N(1), 410N(2) may include, for example, from one (1) to four (4) monolayers of the semiconductor material 418(1). In the example shown inFIGS. 4A-4O , thelower channel structure 406L includes three (3)2D slabs 410N(1)-410N(3) and three (3) oxide layers 411(1)-411(3), but additional alternating 2D slabs and oxide layers may be vertically stacked for increased drive strength capability in thelower channel structure 406L. Using photolithographic patterning, the vertically-stacked2D slabs 410N(1)-410N(3) and oxide layers 411(1)-411(3) are etched to form thelower channel structure 406L. -
FIG. 4B illustrates an exemplary fabrication stage 401(B) of fabricating theCFET cell circuit 400 that further includes depositing a dummy gate polysilicon layer 413L on thelower channel structure 406L to fabrication stage 401(A) inFIG. 4A , and using photolithographic patterning and etching to remove the dummy gate polysilicon layer 413L from thelower channel structure 406L except in alower gate region 408L. Portions of the polysilicon also remain to formdummy gate 417L at each end of thelower channel structure 406L. -
FIG. 4C illustrates an exemplary fabrication stage 401(C) of fabricating theCFET cell circuit 400 that further includes employing the dummy gate polysilicon layer 413L as a mask to fabrication stage 401(B) inFIG. 4B . In this regard, the oxide layers 411(1)-411(3) on and between first and second end portions 416LS and 416LD of the2D slabs 410N(1)-410N(3) as shown inFIG. 4B are removed, butportions 411A(1)-411A(3) of the oxide layers 411(1)-411(3) beneath the dummy gate polysilicon layer 413L are not removed. A spacer layer, which may be silicon nitride (SiN or SiON), for example, is deposited on respective vertical sides of the remaining portions of the oxide layers 411(1)-411(3), and is etched to form side spacers 424LS and 424LD that will electrically isolate thelower gate 422L (seeFIG. 4F ) from the lower source/drain region 414LS and the lower drain/source region 414LD.Side spacers 415L may also be formed on vertical sides of thedummy gate 417L. Fabrication stage 401(C) also includes doping the first and second end portions 416LS and 416LD of the2D slabs 410N(1)-410N(3) with a first type of dopant (not shown) to form an N-type or P-type semiconductor. -
FIG. 4D illustrates an exemplary fabrication stage 401(D) in which anILD 428L is disposed to surround the doped2D slabs 410N(1)-410N(3) in fabrication stage 401(C) inFIG. 4C . TheILD 428L provides a structural support for the2D slabs 410N(1)-410N(3) and also provides electrical isolation for thelower channel structure 406L. A top surface 428LT of theILD 428L is planarized (e.g., by chemical mechanical planarization (CMP)), and aSiN layer 429L is formed on the top surface 428LT. -
FIG. 4E illustrates an exemplary fabrication stage 401(E) in which the photolithography and etching are employed to fabrication stage 401(D) inFIG. 4D to remove theSiN layer 429L, the dummy gate polysilicon layer 413L, and thedummy gate 417L shown inFIG. 4D . In addition, the remainingportions 411A(1)-411A(3) of the oxide layers 411(1)-411(3) that are on and between the2D slabs 410N(1)-410N(3) in the vertical direction and between the side spacers 424LS and 424LD in the horizontal direction are removed. Forming thelower circuit layer 402L further includes disposing alower gate 422L on faces of the2D slabs 410N(1)-410N(3) between the first and second end portions 416LS and 416LD of the2D slabs 410N(1)-410N(3) (block 306 inFIG. 3 ). In this regard, lower gate dielectric layers 426L formed of a high-k dielectric material are deposited on exposed faces of the2D slabs 410N(1)-410N(3) between the side spacers 424LS and 424LD, andgate portions 425L formed of a conductive gate material (e.g., metal) are disposed over the gate dielectric layers 426L to form thelower gate 422L. Forming thelower gate 422L may further include forming a lower field gate 427L (not shown) corresponding to thelower field gate 227L shown inFIG. 2B extending orthogonally from thelower channel structure 406L. In the fabrication stage 401(E), the polysilicon material of thedummy gate 417L is replaced with conductive metal gate material. -
FIG. 4F illustrates an exemplary fabrication stage 401(F) which includes integrating a lower source/drain material 421L with the first end portions 416LS of the2D slabs 410N(1)-410N(3) to fabrication stage 401(E) inFIG. 4E to form a lower source/drain region 414LS on a first side of thelower gate 422L, and integrating the lower source/drain material 421L with the second end portions 416LD of the2D slabs 410N(1)-410N(3) to form a lower drain/source region 414LD on a second side of thelower gate 422L (block 308 inFIG. 3 ). In this regard, photolithography and etching are used to remove portions of theILD 428L in the first and second end portions 416LS and 416LD. TheILD 428L between the2D slabs 410N(1)-410N(3) in the first end portions 416LS is replaced by forming the lower source/drain material 421L, and theILD 428L between the2D slabs 410N(1)-410N(3) in the second end portions 416LD is replaced by forming the lower source/drain material 421L. The lower source/drain material 421L may be an N-type material for anNFET 404N. Alternatively, the lower source/drain material 421L may be a P-type material to form aPFET 404P in thelower circuit layer 402L. -
FIG. 4G illustrates an exemplary fabrication stage 401(G) of fabricating theCFET cell circuit 400 that further includes disposing more ILD to the fabrication stage 401(F) inFIG. 4F to electrically isolate the lower source/drain material 421L, which increases a thickness of theILD 428L to form a new top surface 428LT′ of thefirst circuit layer 402L. Photolithography and etching are employed to remove portions of theILD 428L to open a contact area above the first end portions 416LS and the second end portions 416LD, allowing trench contacts 430LS and 430LD to be formed in contact with the lower source/drain region 414LS and the lower drain/source region 414LD by depositing metal or another conductive material. Forming the trench contacts 430LS and 430LD may include forming horizontal interconnects 434LS and 434LD (not shown), which correspond to horizontal interconnects 234LS and 234LD shown inFIG. 2C-1 . -
FIG. 4H illustrates an exemplary fabrication stage 401(H) of fabricating theCFET cell circuit 400 that further includes forming anupper circuit layer 402U (which corresponds to theupper circuit layer 202U inFIGS. 2A-2D ) above thelower circuit layer 402L (block 310 inFIG. 3 ) in the fabrication stage 401(G) inFIG. 4G . Forming theupper circuit layer 402U includes forming anisolation layer 407U on the top surface 428LT′ of thelower circuit layer 402L. Forming theupper circuit layer 402U further includes forming anupper channel structure 406U, which further includes vertically stacking athird 2D slab 410P(1) and a fourthsecond 2D slab 410P(2) above theisolation layer 407U. The third andfourth 2D slabs 410P(1) and 410P(2) have longitudinal axes A4 u(1) and A4 u(2), respectively, in the first direction, and include a semiconductor material 418(2) of a second type (e.g., one of P-type or N-type) (block 312 inFIG. 3 ). Vertically stacking the third andfourth 2D slabs 410P(1) and 410P(2) includes depositing one or more layers of the semiconductor material 418(2) (e.g., monolayers of MX2 material) to form thethird 2D slab 410P(1) on theisolation layer 407U, depositing an oxide layer 411(4) on thethird 2D slab 410P(1), depositing one or more layers of the semiconductor material 418(2) to form thefourth 2D slab 410P(2), and depositing another oxide layer 411(5) above thefourth 2D slab 410P(2). Each2D slab 410P(1), 410P(2) may include, for example, from one (1) to four (4) monolayers of the semiconductor material 418(2). In the example shown inFIGS. 4A-4O , the upper channel structure includes three (3)2D slabs 410P(1)-410P(3) and three (3) oxide layers 411(4)-411(6), but additional alternating 2D slabs and oxide layers may be vertically stacked for increased drive strength capability in theupper channel structure 406U. Using photolithographic patterning, the vertically stacked2D slabs 410P(1)-410P(3) and oxide layers 411(3)-411(4) are etched to form theupper channel structure 406U. -
FIG. 4I illustrates an exemplary fabrication stage 401(I) of fabricating theCFET cell circuit 400 that further includes depositing a dummygate polysilicon layer 413U on theupper channel structure 406U in the fabrication stage 401(H) inFIG. 4H , and using photolithographic patterning and etching to remove the dummygate polysilicon layer 413U from theupper channel structure 406U except in anupper gate region 408U. Portions of the polysilicon also remain to formdummy gate 417U at each end of theupper channel structure 406U. -
FIG. 4J illustrates an exemplary fabrication stage 401(J) of fabricating theCFET cell circuit 400 that further includes employing the dummygate polysilicon layer 413U in the fabrication stage 401(I) inFIG. 4I as a mask. In this regard, the oxide layers 411(4)-411(6) on and between first and second end portions 416US and 416UD of the2D slabs 410P(1)-410P(3) are removed, butportions 411A(4)-411A(6) of the oxide layers 411(4)-411(6) beneath the dummygate polysilicon layer 413U are not removed. A spacer layer, which may be silicon nitride (SiN), for example, is deposited on respective vertical sides of the remaining portions of the oxide layers 411(4)-411(6), and is etched to form side spacers 424US and 424UD that will electrically isolate theupper gate 422U (seeFIG. 4M ) from the upper source/drain region 414US and the upper drain/source region 414UD.Side spacers 415U may also be formed on vertical sides of thedummy gate 417U. Fabrication stage 401(J) also includes doping the first and second end portions 416US and 416UD of the2D slabs 410P(1)-410P(3) with a second type of dopant to form a P-type or N-type semiconductor. -
FIG. 4K illustrates an exemplary fabrication stage 401(K) in which anILD 428U is disposed to surround the doped2D slabs 410P(1)-410P(3) in the fabrication stage 401(J) inFIG. 4J . A top surface 428UT of theILD 428U is planarized (e.g., by chemical mechanical planarization (CMP)), and aSiN layer 429U is formed on the top surface 428UT. -
FIG. 4L illustrates an exemplary fabrication stage 401(L) in which photolithography and etching are employed to remove the dummygate polysilicon layer 413U and thedummy gate 417U of theCFET cell circuit 400 in the fabrication stage 401(K) inFIG. 4K . In addition, the remainingportions 411A(4)-411A(6) of the oxide layers 411(4)-411(6) that are on and between the2D slabs 410P(1)-410P(3) in the vertical direction and between the side spacers 424US and 424UD in the horizontal direction are removed. Forming theupper circuit layer 402U above thelower circuit layer 402L further includes disposing anupper gate 422U on faces of the2D slabs 410P(1)-410P(3) between the first and second end portions 416US and 416UD of the2D slabs 410P(1)-410P(3) (block 314 inFIG. 3 ). In this regard, upper gate dielectric layers 426U of a high-k material are deposited on exposed faces of the2D slabs 410P(1)-410P(3) between the side spacers 424US and 424UD, andgate portions 425U formed of a conductive gate material (e.g., metal) are disposed over the upper gate dielectric layers 426U to form anupper gate 422U. An upper field gate 427U (not shown) corresponding to theupper field gate 227U inFIG. 2B may also be formed with theupper gate 422U in theupper circuit layer 402U. The polysilicon material of thedummy gate 417U is also replaced with conductive metal gate material in this stage. -
FIG. 4M illustrates an exemplary fabrication stage 401(M) which includes integrating an upper source/drain material 421U with the first end portions 416US of the2D slabs 410P(1)-410P(3) to form an upper source/drain region 414US on a first side of theupper gate 422U in the fabrication stage 401(L) inFIG. 4L , and integrating the upper source/drain material 421U with the second end portions 416UD of the2D slabs 410P(1)-410P(3) to form an upper drain/source region 414UD on a second side of theupper gate 422U (block 316 inFIG. 3 ). In this regard, photolithography and etching are used to remove portions of theILD 428U in the first and second end portions 416US and 416UD. TheILD 428U between the2D slabs 410P(1)-410P(3) in the first end portions 416US is replaced with the upper source/drain material 421U, and theILD 428U between the2D slabs 410P(1)-410P(3) in the second end portions 416UD is replaced with the upper source/drain material 421U. The upper source/drain material 421U may be a P-type material for aPFET 404P. Alternatively, the upper source/drain material 421U may each be an N-type material to form anNFET 404N in theupper circuit layer 402U. -
FIG. 4N illustrates an exemplary fabrication stage 401(N) of fabricating theCFET cell circuit 400 that further includes disposing more ILD to increase a thickness of theILD 428U in the fabrication stage 401(M) inFIG. 4M to form a new top surface 428UT′ of theupper circuit layer 402U. Photolithography and etching are employed to remove portions of theILD 428U to open a contact area above the first end portions 416US and the second end portions 416UD, allowing trench contacts 430US and 430UD to be formed in contact with the upper source/drain region 414US and the upper drain/source region 414UD by deposition of metal or another conductive material. In the same manner, a trench contact 430UG is formed on theupper gate 422U. Forming the trench contacts 430US and 430UD may include forming horizontal interconnects 434US and 434UD (not shown), which correspond to horizontal interconnects 234US and 234UD inFIG. 2C-2 . The top surface 428UT′ is planarized by CMP. -
FIG. 4O illustrates an exemplary fabrication stage 401(0) of fabricating theCFET cell circuit 400 that further includes disposing more ILD to further increase a thickness of theILD 428U in the fabrication stage 401(N) inFIG. 4N to form another new top surface 428UT″ of theupper circuit layer 402U. Photolithography and etching are employed to remove portions of theILD 428U over the trench contacts 430US, 430UG, and 430UD where the metal layer interconnects MSD, MG, and MDS, respectively, are formed to provide connections to theCFET cell circuit 400. In the fabrication stage 401(O), the top surface 428UT″ is planarized by CMP. -
FIG. 5A is a cross-sectional view of aCFET cell circuit 500 in the X-axis and Z-axis directions shown therein. The cross-sectional view shown inFIG. 5A is taken along the line X-X′ shown in a top view of theCFET cell circuit 500 illustrated inFIG. 5D . TheCFET cell circuit 500 corresponds to theCFET cell circuit 200 inFIGS. 2A-2D , except with respect to the semiconductor types of the FETs in the lower and upper layers. Specifically, in contrast to theCFET cell circuit 200, in which theNFET 204N is in thelower circuit layer 202L and thePFET 204P is in theupper circuit layer 202U, theCFET cell circuit 500 includes aPFET 504P in alower circuit layer 502L and anNFET 504N in anupper circuit layer 502U. As will be discussed in more detail below, theCFET cell circuit 500 includes anupper circuit layer 502U with anNFET 504N disposed vertically above (i.e., stacked above) alower circuit layer 502L with aPFET 504P. In this manner, the vertical stacking reduces the horizontal footprint of theCFET cell circuit 500 in the Y-axis direction. As in theCFET cell circuit 200, thePFET 504P and theNFET 504N may be interconnected in a complementary configuration, as in a CMOS circuit. - In addition, an X-axis dimension of a footprint of the
CFET cell circuit 500 may be reduced by reducing length dimensions of thePFET 504P and theNFET 504N. In particular, thePFET 504P in thelower circuit layer 502L is formed in alower channel structure 506L in which agate region 508L has a length dimension LGL in the X-axis direction, and theNFET 504N in theupper circuit layer 502U is formed in anupper channel structure 506U in which agate region 508U has a length dimension LGU in the X-axis direction. By reducing the length dimensions LGL and LGU, a dimension in the X-axis direction of the footprint of theCFET cell circuit 500 may be reduced. - In an exemplary aspect, MX2-type compounds (e.g., transition metal dichalcogenide crystals), known as “2D materials,” may be employed in the semiconductor channel structures of the
PFET 504P andNFET 504N to reduce the lengths LGL and LGU in the X-axis direction without a corresponding increase in leakage current associated with reducing a length of a gate region of a silicon channel structure. In theCFET cell circuit 500 inFIG. 5A , thelower circuit layer 502L includes thePFET 504P, and theupper circuit layer 502U includes theNFET 504N. ThePFET 504P is disposed on anisolation layer 507L above asubstrate 509. Thelower channel structure 506L includes afirst 2D slab 510P(1) of the 2D material vertically integrated with asecond 2D slab 510P(2) of the 2D material. In theCFET cell circuit 500 inFIG. 5A , a “slab” is a structure formed of one or more layers of a 2D material with first and second dimensions in orthogonal directions (e.g., X-axis and Y-axis directions) and having a thickness dimension which is orthogonal to the first and second dimensions (e.g., Z-axis direction) and is smaller than the first and second dimensions. As shown in a top view of theCFET cell circuit 500 inFIG. 5C-1 below, the first andsecond 2D slabs 510P(1) and 510P(2) may each extend in a range from 20 nm to 500 nm in a longitudinal direction (e.g., X-axis direction), and extend in a range from 3 nm to 50 nm in a direction orthogonal to the longitudinal direction (e.g., Y-axis direction). As shown inFIG. 5A , the first andsecond 2D slabs 510P(1) and 510P(2) have a thickness dimension, which may be in the range from 0.6 nm to 10.0 nm. Thelower channel structure 506L inFIG. 5A may also include additional 2D slabs, such asthird 2D slab 510P(3) vertically integrated with the first andsecond 2D slabs 510P(1) and 510P(2) to increase a drive strength of thePFET 504P. Although the slab structures inFIG. 5A may appear to be planar, stackable slabs having other (e.g., non-planar) shapes are within the scope of the present disclosure. - Each of the
2D slabs 510P(1)-510P(3) includes at least one monolayer (not individually shown) of a first type of 2D semiconductor material 518(1), such as a P-type material 518P, extending in the X-axis direction and the Y-axis direction. 2D materials are atomically thin semiconductor monolayers of the type MX2, where M is a transition metal atom (Mo, W, etc.) and X is a chalcogen atom (S, Se, or Te). For example, the P-type material 518P may be molybdenum disulfide (MoS2). Crystal monolayers of MX2 compounds have a higher carrier mobility, lower dielectric constant, and thinner channel thickness than silicon, providing a strong on/off control of the channel. Therefore, a channel structure formed of MX2 compounds may have higher drive strength and lower leakage current than a similarly-sized silicon channel structure. By employing the P-type material 518P in the2D slabs 510P(1)-510P(3), channel control in alower gate region 508L is improved over a channel region of the same length in a channel structure formed of silicon. Therefore, by employing the P-type material 518P in thelower channel structure 506L, rather than silicon, the length LGL of thelower gate region 508L may be made smaller to reduce a dimension of theCFET cell circuit 500 in the X-axis direction without a causing an increase in leakage current in thePFET 504P. The2D slabs 510P(1)-510P(3) extend along respective longitudinal axes A5 L(1)-A5 L(3) and may be integrated by stacking in a vertical (e.g., Z-axis) direction one above another. By vertically stacking the2D slabs 510N(1)-510N(3) such that their longitudinal axes A5 L(1)-A5 L(3) overlap (e.g., in the Z-axis direction), an area occupied by thelower channel structure 506L is minimized. - With continuing reference to
FIG. 5A , thelower channel structure 506L also includes a lower source/drain material 521L integrated with first end portions 516LS(1)-516LS(3) of the2D slabs 510P(1)-510P(3) for forming a lower source/drain region 514LS and the lower source/drain material integrated with second end portions 516LD(1)-516LD(3) of the2D slabs 510P(1)-510P(3) to form a lower drain/source region 514LD. In operation of thePFET 504P, either the lower source/drain region 514LS or the lower drain/source region 514LD may function as a source while the other functions as a drain. Integration of the lower source/drain region 514LS and the lower drain/source region 514LD with the respective end portions 516LS(1)-516LS(3) and 516LD(1)-516LD(3) may include one or more of doping the2D slabs 510P(1)-510P(3) with the lower source/drain material 521L, growing the lower source/drain material 521L epitaxially on the2D slabs 510P(1)-510P(3), and depositing the lower source/drain material 521L on or in contact with the2D slabs 510P(1)-510P(3). As shown inFIG. 5A , the lower source/drain material 521L of the lower source/drain region 514LS and the lower drain/source region 514LD may be formed on faces of the2D slabs 510P(1)-510P(3), except where thefirst 2D slab 510P(1) is in contact with theisolation layer 507L. For example, the lower source/drain material 521L may be formed on top face 520LT, bottom face 520LB, side face 520LS, and end faces 520LE of2D slab 510P(2) in the first and second end portions 516LS(2) and 516LD(2). The lower source/drain material 521L may be similarly formed on faces of2D slabs 510P(1) and 510P(3), as shown inFIG. 5A . - By vertically stacking the
2D slabs 510N(1)-510N(3) such that their longitudinal axes A5 L(1)-A5 L(3) overlap, as discussed above, a current flow in the each of the2D slabs 510N(1)-510N(3) may be controlled by a single gate structure. In this regard, thelower channel structure 506L includes alower gate 522L disposed on faces of the2D slabs 510P(1)-510P(3), such as the faces 520LT, 520LB and 520LS of thesecond 2D slab 510P(2). Thelower gate 522L is disposed on the2D slabs 510P(1)-510P(3) between the lower source/drain region 514LS and the lower drain/source region 514LD in the X-axis direction. Thelower gate 522L is separated from the lower source/drain region 514LS by side spacer 524LS and separated from the lower drain/source region 514LD by side spacer 524LD. Thelower gate 522L includesgate portions 525L electrically insulated from therespective 2D slabs 510P(1)-510P(3) by gate dielectric layers 526L. Thelower gate 522L also includes alower field gate 527L not shown inFIG. 5A . Thelower circuit layer 502L also includes trench contacts 530LS and 530LD formed above the lower source/drain region 514LS and the lower drain/source region 514LD, respectively. An inter-layer dielectric (ILD) 528L surrounds thePFET 504P, thelower field gate 527L, and the trench contacts 530LS and 530LD. Thelower field gate 527L and the trench contacts 530LS and 530LD are discussed further with respect toFIG. 5B below. - As noted above, the
CFET cell circuit 500 inFIG. 5A also includes theupper circuit layer 502U disposed above thelower circuit layer 502L that includes thePFET 504P to provide a CMOS architecture for theCFET cell circuit 500. Theupper circuit layer 502U of theCFET cell circuit 500 will now be discussed. In this regard, theupper circuit layer 502U includes theNFET 504N disposed on theisolation layer 507L. TheNFET 504N is formed in anupper channel structure 506U including athird 2D slab 510N(1) vertically integrated with afourth 2D slab 510N(2). Theupper channel structure 506U inFIG. 5A also includes another2D slab 510N(3) vertically integrated with the third andfourth 2D slabs 510N(1), 510N(2) to increase a drive strength of theNFET 504N. Each of the2D slabs 510N(1)-510N(3) includes at least one monolayer (not individually shown) of a second 2D semiconductor material 518(2) (e.g., MX2 material), such as an N-type material 518N, extending in the X-axis direction and the Y-axis direction. For example, the N-type material 518N may be molybdenum disulfide (MoS2). By employing 2D materials for the N-type material 518N in theslabs 510N(1)-510N(3), channel control in anupper gate region 508U is improved over a channel region in a channel structure formed of silicon. Therefore, the length LGU of theupper gate region 508U may be made smaller to reduce a dimension of theCFET cell circuit 500 in the X-axis direction without causing an increase in leakage current in theNFET 504N. The2D slabs 510N(1)-510N(3) extend along respective longitudinal axes A5 U(1)-A5 U(3) in the X-axis direction and may be integrated in the vertical direction one above another. - The
upper channel structure 506U also includes an upper source/drain material 521U integrated with first end portions 516US(1)-516US(3) of the2D slabs 510N(1)-510N(3) to form an upper source/drain region 514US and the upper source/drain material 521U integrated with second end portions 516UD(1)-516UD(3) of the2D slabs 510N(1)-510N(3) to form an upper drain/source region 514UD. In operation of theNFET 504N, either the upper source/drain region 514US or the upper drain/source region 514UD may function as a source while the other functions as a drain. Integration of the upper source/drain region 514US and the upper drain/source region 514UD with the respective end portions 516US(1)-516US(3) and 516UD(1)-516UD(3) may include one or more of doping the2D slabs 510N(1)-510N(3) with the upper source/drain material 521U, growing the upper source/drain material 521U epitaxially on the2D slabs 510N(1)-510N(3), and depositing the upper source/drain material 521U on or in contact with the2D slabs 510N(1)-510N(3). As shown inFIG. 5A , the upper source/drain material 521U of the upper source/drain region 514US and the upper drain/source region 514UD may be formed on faces of the2D slabs 510N(1)-510N(3), except where the2D slab 510N(1) is in contact with theisolation layer 507U. For example, the upper source/drain material 521U may be formed on faces of the2D slab 510N(2) in the end portions 516US(2) and 516UD(2). The upper source/drain material 521U may be similarly formed on faces of2D slabs 510N(1) and 510N(3), as shown inFIG. 5A . - The
upper channel structure 506U also includes anupper gate 522U disposed on faces of the2D slabs 510N(1)-510N(3). Theupper gate 522U is disposed on the2D slabs 510N(1)-510N(3) between the upper source/drain region 514US and the upper drain/source region 514UD. Theupper gate 522U is separated from the upper source/drain region 514US by side spacers 524US and separated from the upper drain/source region 514UD by side spacer 524UD. Theupper gate 522U includesgate portions 525U electrically insulated from therespective 2D slabs 510N(1)-510N(3) by gate dielectric layers 526U. Theupper gate 522U also includes anupper field gate 527U not shown inFIG. 5A which is a horizontal interconnect disposed on theupper gate 522U. Theupper circuit layer 502U includes trench contacts 530US and 530UD disposed above the upper source/drain region 514US and the upper drain/source region 514UD, respectively. Theupper circuit layer 502U also includes a trench contact 530UG disposed on theupper gate 522U. Metal layer interconnects MSD, MG, and MDS are disposed on the trench contracts 530US, 530UG, and 530UD, respectively, for coupling external circuits to theNFET 504N. AnILD 528U surrounds theNFET 504N, the metal layer interconnects MSD, MG, and MDS, theupper gate 522U, and the trench contacts 530US and 530UD. - As shown in
FIG. 5A , anupper channel column 536U extends vertically (up and down) from a horizontal area of theupper channel structure 506U, and alower channel column 536L extends vertically from a horizontal area of thelower channel structure 506L. In this regard, theupper channel column 536U overlaps at least a portion of thelower channel column 536L. In the example inFIG. 5A , theupper channel structure 506U in theupper circuit layer 502U overlaps thelower channel structure 506L in thelower circuit layer 502L such that theupper channel column 536U fully overlaps (i.e., occupies substantially the same horizontal area extending in a vertical direction) as thelower channel column 536L. In another aspect, thesecond 2D slab 510P(2) may partially overlap or fully overlap thefirst 2D slab 510P(1) when vertically stacked on thefirst 2D slab 510P(1) to minimize a horizontal area occupied by thelower channel structure 506L, and thesecond 2D slab 510N(2) may partially overlap or fully overlap thefirst 2D slab 510N(1) when vertically stacked on thefirst 2D slab 510N(1) to minimize a horizontal area occupied by theupper channel structure 506U. In this regard, a horizontal area (X-axis and Y-axis directions) occupied by theCFET cell circuit 500 may be reduced in comparison to thestandard cell 102 ofFIG. 1 in exchange for an increased dimension in the Z-direction. - Figure SB illustrates a side view of a cross-section in the Y-axis and Z-axis directions of the
CFET cell circuit 500. The cross-sectional view shown inFIG. 5B is taken along the line Y-Y′ shown in the top view of theCFET cell circuit 500 illustrated inFIG. 5D . The cross-sectional view inFIG. 5B shows the2D slabs 510P(1)-510P(3) one above another in thelower channel structure 506L and the2D slabs 510N(1)-510N(3) one above another in theupper channel structure 506U. As shown inFIG. 5B , the gate dielectric layers 526L are formed around each of the2D slabs 510P(1)-510P(3) to separate the2D slabs 510P(1)-510P(3) from thegate portions 525L of thelower gate 522L. Similarly, the gate dielectric layers 526U are formed around each of the2D slabs 510N(1)-510N(3) to separate the2D slabs 510N(1)-510N(3) from thegate portions 525U of theupper gate 522U. - In addition,
FIG. 5B shows an example of vertical integration of theupper channel structure 506U in theupper circuit layer 502U above thelower channel structure 506L in thelower circuit layer 502L to reduce a dimension of theCFET cell circuit 500 in the Y-axis direction. For example, theupper channel structure 506U may be positioned directly above thelower channel structure 506L. However, with thelower gate 522L in thelower channel structure 506L located directly below theupper channel structure 506U, a vertical inter-layer access (via) from thelower gate 522L to the metal interconnect MG may be obstructed. To avoid such obstruction, thelower field gate 527L extends in the Y-axis direction, orthogonal to the longitudinal axes A5 L(1)-A5 L(3) of thelower channel structure 506L, from thelower gate 522L to a location in thelower circuit layer 502L that is not vertically obstructed. In this regard, thelower field gate 527L provides a horizontal interconnect from thelower gate 522L to a location in theupper circuit layer 502U in which a via to the metal interconnect MG is not obstructed by theupper channel structure 506U. Anupper field gate 527U may be formed on theupper gate 522U as a horizontal interconnect in theupper circuit layer 502U to an alternative location for the trench contact 530UG, if needed. Referring back to thelower circuit layer 502L inFIG. 5B , a trench contact 530LG is formed on thelower field gate 527L and a via 532LG extends through theupper circuit layer 502U from the trench contact 530LG in thelower circuit layer 502L to the metal interconnect MG above theupper circuit layer 502U. As will be disclosed with regard toFIGS. 5C-1 and 5C-2 , horizontal interconnects extending in the Y-axis direction, similar to thelower field gate 527L, are provided in thelower circuit layer 502L from the lower source/drain region 514LS and the lower drain/source region 514LD to locations at which a via to metal interconnects above theupper circuit layer 502U may not be obstructed by theupper channel structure 506U. -
FIG. 5C-1 illustrates a top view of a horizontal cross-section, taken at line Z-Z′ inFIG. 5B , showing features of thelower circuit layer 502L including thePFET 504P.FIG. 5C-1 shows horizontal interconnects 534LS and 534LD extending in the X-axis direction, orthogonal to thelower channel structure 506L, from the lower source/drain region 514LS and the lower drain/source region 514LD, respectively. Thelower field gate 527L is also shown extending in the Y-axis direction from thelower gate 522L. In addition,FIG. 5C-1 shows that the trench contacts 530LS, 530LG, and 530LD are in locations of thelower circuit layer 502L that are not vertically obstructed by theupper channel structure 506U in theupper circuit layer 502U. In this regard,FIG. 5C-1 shows that the trench contacts 530LS, 530LG, and 530LD are positioned according to a line pitch PY in the Y-axis direction relative to thelower channel structure 506L and according to a line pitch PX in the X-axis direction relative to thelower field gate 527L. Line pitches PX and PY may be a center-to-center distance between features, as shown inFIG. 5C-1 . -
FIG. 5C-2 illustrates a top view of features of theupper circuit layer 502U including theNFET 504N.FIG. 5C-2 shows theupper field gate 527U extending in the Y-axis direction orthogonal to theupper channel structure 506U, and the trench contact 530UG in an alternative location to the location shown inFIG. 5B .FIG. 5C-2 shows top views of the via 532LG and vias 532LS and 532LD which are positioned to extend vertically from the trench contacts 530LG, 530LS, and 530LD, respectively, in thelower circuit layer 502L.FIG. 5C-2 also shows top views of the trench contracts 530US, 530UG, and 530UD in theupper circuit layer 502U. As shown, the vias 532LS, 532LG, and 532LD and the trench contacts 530UG, 530US, and 530UD are spaced apart in theupper circuit layer 502U according to the line pitch PX in the X-axis direction and according to the line pitch PY in the Y-axis direction in an arrangement to minimize a footprint of theCFET cell circuit 500. -
FIG. 5C-2 shows electrical connections for configuring thePFET 504P and theNFET 504N in a configuration of a CMOS inverter. For example, the metal interconnect MG connects between the trench contacts 530LG and 530UG to electrically couple thelower gate 522L and theupper gate 522U. The metal interconnect MDS connects between the trench contacts 530LD and 530UD to electrically couple the lower drain/source region 514LD and the upper drain/source region 514UD. The metal interconnect MSD is connected between the trench contact 530LS and a via 538 to electrically couple the upper source/drain region 514US of theNFET 504N to ground (e.g., VSS). The via 532LS electrically couples the lower source/drain region 514LS of thePFET 504P to a supply voltage (VDD). -
FIGS. 5C-1 and 5C-2 also showdummy gates 540 located according to a gate pitch PG in the X-axis direction relative to thelower field gate 527L and theupper field gate 527U. By employing 2D materials to form theupper channel structure 506U, the length dimension LGL of theupper gate region 508U of theCFET cell circuit 500 in the X-axis direction may be smaller than a length of a channel region in a silicon channel structure (e.g., fin). By reducing the length dimension LGL, the gate pitch PG of the CFET standard cell, which determines a dimension of theCFET cell circuit 500 in the X-axis direction, may also be smaller. -
FIG. 5D shows a top view of theCFET cell circuit 500 with theupper circuit layer 502U ofFIG. 5C-2 disposed above and in horizontal alignment with thelower circuit layer 502L ofFIG. 5C-1 .FIG. 5D shows theupper channel structure 506U disposed directly above thelower channel structure 506L to reduce a dimension of theCFET cell circuit 500 in the Y-axis direction. To avoid vertical obstruction created by locating theupper channel structure 506U directly above thelower channel structure 506L, the horizontal interconnects 534LS and 534LD and thelower field gate 527L provide unobstructed vertical access locations for the vias 532LS, 532LG, and 532LD to electrically couple thePFET 504P to theNFET 504N and/or an external circuit. - CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit, as illustrated in any of
FIGS. 2A-2D and 5A-5D , and according to any aspects disclosed herein, may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter. - In this regard,
FIG. 6 illustrates an example of a processor-basedsystem 600 withcircuits 602 that can include CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit, including, but not limited to, thecell circuits FIGS. 2A-2D and 5A-5D , respectively, and according to any aspects disclosed herein. In this example, the processor-basedsystem 600 may be formed as anIC 604 in a system-on-a-chip (SoC) 606. The processor-basedsystem 600 includes aprocessor 608 that includes one or more central processor units (CPUs) 610, which may also be referred to as CPU or processor cores. Theprocessor 608 may havecache memory 612 coupled to theCPUs 610 for rapid access to temporarily stored data. As an example, theCPUs 610 could include CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit, including, but not limited to, thecell circuits FIGS. 2A-2D and 5A-5D , respectively, and according to any aspects disclosed herein. Theprocessor 608 is coupled to asystem bus 614 and can intercouple master and slave devices included in the processor-basedsystem 600. As is well known, theprocessor 608 communicates with these other devices by exchanging address, control, and data information over thesystem bus 614. For example, theprocessor 608 can communicate bus transaction requests to a memory controller 616 as an example of a slave device. Although not illustrated inFIG. 6 ,multiple system buses 614 could be provided, wherein eachsystem bus 614 constitutes a different fabric. - Other master and slave devices can be connected to the
system bus 614. As illustrated inFIG. 6 , these devices can include amemory system 620 that includes the memory controller 616 and a memory array(s) 618, one ormore input devices 622, one ormore output devices 624, one or more network interface devices 626, and one ormore display controllers 628, as examples. Each of thememory system 620, the one ormore input devices 622, the one ormore output devices 624, the one or more network interface devices 626, and the one ormore display controllers 628 can include CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit including, but not limited to, thecell circuits FIGS. 2A-2D and 5A-5D , respectively, and according to any aspects disclosed herein. The input device(s) 622 can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s) 624 can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) 626 can be any device configured to allow exchange of data to and from anetwork 630. Thenetwork 630 can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) 626 can be configured to support any type of communications protocol desired. - The
processor 608 may also be configured to access the display controller(s) 628 over thesystem bus 614 to control information sent to one ormore displays 632. The display controller(s) 628 sends information to the display(s) 632 to be displayed via one ormore video processors 634, which process the information to be displayed into a format suitable for the display(s) 632. The display(s) 632 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc. The display controller(s) 628, display(s) 632, and/or the video processor(s) 634 can include CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit, including, but not limited to, thecell circuits FIGS. 2A-2D and 5A-5D , respectively, and according to any aspects disclosed herein. -
FIG. 7 illustrates an exemplarywireless communications device 700 that includes radio frequency (RF) components formed from anIC 702, wherein any of the components therein can include CFET cell circuits including an N-type channel structure in a first circuit layer and P-type channel structure in a second circuit layer, each channel structure formed of stacked elongated slabs of 2D semiconductor material to provide a reduction in the X-axis direction and the Y-axis direction of a horizontal footprint of the CFET cell circuit, including, but not limited to, thecell circuits FIGS. 2A-2D and 5A-5D , respectively, and according to any aspects disclosed herein. Thewireless communications device 700 may include or be provided in any of the above-referenced devices, as examples. As shown inFIG. 7 , thewireless communications device 700 includes atransceiver 704 and adata processor 706. Thedata processor 706 may include a memory to store data and program codes. Thetransceiver 704 includes atransmitter 708 and areceiver 710 that support bi-directional communications. In general, thewireless communications device 700 may include any number oftransmitters 708 and/orreceivers 710 for any number of communication systems and frequency bands. All or a portion of thetransceiver 704 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc. - The
transmitter 708 or thereceiver 710 may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between RF and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for thereceiver 710. In the direct-conversion architecture, a signal is frequency-converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In thewireless communications device 700 inFIG. 7 , thetransmitter 708 and thereceiver 710 are implemented with the direct-conversion architecture. - In the transmit path, the
data processor 706 processes data to be transmitted and provides I and Q analog output signals to thetransmitter 708. In the exemplarywireless communications device 700, thedata processor 706 includes digital-to-analog converters (DACs) 712(1), 712(2) for converting digital signals generated by thedata processor 706 into the I and Q analog output signals, e.g., I and Q output currents, for further processing. - Within the
transmitter 708, lowpass filters 714(1), 714(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the prior digital-to-analog conversion. Amplifiers (AMPs) 716(1), 716(2) amplify the signals from the lowpass filters 714(1), 714(2), respectively, and provide I and Q baseband signals. Anupconverter 718 upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals through mixers 720(1), 720(2) from a TXLO signal generator 722 to provide anupconverted signal 724. Afilter 726 filters theupconverted signal 724 to remove undesired signals caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA) 728 amplifies theupconverted signal 724 from thefilter 726 to obtain the desired output power level and provides a transmitted RF signal. The transmitted RF signal is routed through a duplexer or switch 730 and transmitted via anantenna 732. - In the receive path, the
antenna 732 receives signals transmitted by base stations and provides a received RF signal, which is routed through the duplexer or switch 730 and provided to a low noise amplifier (LNA) 734. The duplexer or switch 730 is designed to operate with a specific receive (RX)-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by theLNA 734 and filtered by afilter 736 to obtain a desired RF input signal. Downconversion mixers 738(1), 738(2) mix the output of thefilter 736 with I and Q RX LO signals (i.e., LO_I and LO_Q) from an RXLO signal generator 740 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers (AMPs) 742(1), 742(2) and further filtered by lowpass filters 744(1), 744(2) to obtain I and Q analog input signals, which are provided to thedata processor 706. In this example, thedata processor 706 includes Analog to Digital Converters (ADCs) 746(1), 746(2) for converting the analog input signals into digital signals to be further processed by thedata processor 706. - In the
wireless communications device 700 ofFIG. 7 , the TXLO signal generator 722 generates the I and Q TX LO signals used for frequency upconversion, while the RXLO signal generator 740 generates the I and Q RX LO signals used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A TX phase-locked loop (PLL)circuit 748 receives timing information from thedata processor 706 and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from the TXLO signal generator 722. Similarly, anRX PLL circuit 750 receives timing information from thedata processor 706 and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from the RXLO signal generator 740. - Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The master and slave devices described herein may be employed in any circuit, hardware component, IC, or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
- The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
- The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
- It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
- The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but, is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (28)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/255,008 US10734384B1 (en) | 2019-01-23 | 2019-01-23 | Vertically-integrated two-dimensional (2D) semiconductor slabs in complementary field effect transistor (CFET) cell circuits, and method of fabricating |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/255,008 US10734384B1 (en) | 2019-01-23 | 2019-01-23 | Vertically-integrated two-dimensional (2D) semiconductor slabs in complementary field effect transistor (CFET) cell circuits, and method of fabricating |
Publications (2)
Publication Number | Publication Date |
---|---|
US20200235098A1 true US20200235098A1 (en) | 2020-07-23 |
US10734384B1 US10734384B1 (en) | 2020-08-04 |
Family
ID=71609151
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/255,008 Active US10734384B1 (en) | 2019-01-23 | 2019-01-23 | Vertically-integrated two-dimensional (2D) semiconductor slabs in complementary field effect transistor (CFET) cell circuits, and method of fabricating |
Country Status (1)
Country | Link |
---|---|
US (1) | US10734384B1 (en) |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200295127A1 (en) * | 2019-03-13 | 2020-09-17 | Intel Corporation | Stacked transistors with different crystal orientations in different device strata |
US20210118879A1 (en) * | 2019-10-18 | 2021-04-22 | Tokyo Electron Limited | Method of making a charge trap tfet semiconductor device for advanced logic operations |
US20210249430A1 (en) * | 2020-02-12 | 2021-08-12 | Tokyo Electron Limited | Architecture design and process for 3d logic and 3d memory |
US20210273093A1 (en) * | 2020-02-27 | 2021-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device |
US11251159B2 (en) * | 2019-12-06 | 2022-02-15 | Tokyo Electron Limited | High performance CMOS using 3D device layout |
CN114078952A (en) * | 2020-10-29 | 2022-02-22 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
EP4020586A1 (en) * | 2020-12-23 | 2022-06-29 | INTEL Corporation | Transition metal dichalcogenide nanosheet transistors and methods of fabrication |
US11488947B2 (en) * | 2019-07-29 | 2022-11-01 | Tokyo Electron Limited | Highly regular logic design for efficient 3D integration |
WO2023011177A1 (en) * | 2021-08-03 | 2023-02-09 | International Business Machines Corporation | Stacked complementary field effect transistors |
US11581430B2 (en) * | 2019-08-22 | 2023-02-14 | Globalfoundries U.S. Inc. | Planar transistor device comprising at least one layer of a two-dimensional (2D) material and methods for making such transistor devices |
EP4156303A1 (en) * | 2021-09-24 | 2023-03-29 | INTEL Corporation | Thin film transistors having multi-layer gate dielectric structures integrated with 2d channel materials |
EP4156246A1 (en) * | 2021-09-24 | 2023-03-29 | INTEL Corporation | Thin film transistors having cmos functionality integrated with 2d channel materials |
US11670677B2 (en) * | 2020-10-02 | 2023-06-06 | Samsung Electronics Co., Ltd. | Crossing multi-stack nanosheet structure and method of manufacturing the same |
WO2023098600A1 (en) * | 2021-12-02 | 2023-06-08 | International Business Machines Corporation | Stacked nanosheet transistor with defect free channel |
WO2023146696A1 (en) * | 2022-01-26 | 2023-08-03 | Qualcomm Incorporated | Trench power rail in cell circuits to reduce resistance and related power distribution networks and fabrication methods |
US11799035B2 (en) * | 2019-04-12 | 2023-10-24 | The Research Foundation For The State University Of New York | Gate all-around field effect transistors including quantum-based features |
WO2023216679A1 (en) * | 2022-05-09 | 2023-11-16 | 成都海光微电子技术有限公司 | Layout design method, system and device, and circuit layout and storage medium |
EP4228002A3 (en) * | 2022-02-15 | 2023-11-29 | Samsung Electronics Co., Ltd. | Semiconductor device having a two-dimensional channel and method for fabricating the same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11349025B2 (en) * | 2018-10-31 | 2022-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-channel device to improve transistor speed |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1895579B1 (en) * | 2005-06-20 | 2016-06-15 | Nippon Telegraph And Telephone Corporation | Diamond semiconductor element and process for producing the same |
KR102144999B1 (en) * | 2013-11-05 | 2020-08-14 | 삼성전자주식회사 | Two-dimensional material, method of forming the same and device including two-dimensional material |
KR102156320B1 (en) * | 2013-11-21 | 2020-09-15 | 삼성전자주식회사 | Inverter including two-dimensional material, method of manufacturing the same and logic device including inverter |
US10269981B2 (en) * | 2014-11-17 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-channel field effect transistors using 2D-material |
US10020300B2 (en) * | 2014-12-18 | 2018-07-10 | Agilome, Inc. | Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids |
US10217819B2 (en) * | 2015-05-20 | 2019-02-26 | Samsung Electronics Co., Ltd. | Semiconductor device including metal-2 dimensional material-semiconductor contact |
US9735227B2 (en) * | 2015-08-03 | 2017-08-15 | Synopsys, Inc. | 2D material super capacitors |
GB2568110B (en) * | 2017-11-07 | 2019-12-04 | Emberion Oy | Photosensitive field-effect transistor |
US10622476B2 (en) * | 2017-12-27 | 2020-04-14 | Samsung Electronics Co., Ltd. | Vertical field effect transistor having two-dimensional channel structure |
US10541132B2 (en) * | 2018-06-11 | 2020-01-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Forming semiconductor structures with two-dimensional materials |
US10872973B2 (en) * | 2018-06-28 | 2020-12-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structures with two-dimensional materials |
-
2019
- 2019-01-23 US US16/255,008 patent/US10734384B1/en active Active
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200295127A1 (en) * | 2019-03-13 | 2020-09-17 | Intel Corporation | Stacked transistors with different crystal orientations in different device strata |
US11799035B2 (en) * | 2019-04-12 | 2023-10-24 | The Research Foundation For The State University Of New York | Gate all-around field effect transistors including quantum-based features |
US11488947B2 (en) * | 2019-07-29 | 2022-11-01 | Tokyo Electron Limited | Highly regular logic design for efficient 3D integration |
US11581430B2 (en) * | 2019-08-22 | 2023-02-14 | Globalfoundries U.S. Inc. | Planar transistor device comprising at least one layer of a two-dimensional (2D) material and methods for making such transistor devices |
US20210118879A1 (en) * | 2019-10-18 | 2021-04-22 | Tokyo Electron Limited | Method of making a charge trap tfet semiconductor device for advanced logic operations |
US11251159B2 (en) * | 2019-12-06 | 2022-02-15 | Tokyo Electron Limited | High performance CMOS using 3D device layout |
US20210249430A1 (en) * | 2020-02-12 | 2021-08-12 | Tokyo Electron Limited | Architecture design and process for 3d logic and 3d memory |
US11527545B2 (en) * | 2020-02-12 | 2022-12-13 | Tokyo Electron Limited | Architecture design and process for 3D logic and 3D memory |
US20210273093A1 (en) * | 2020-02-27 | 2021-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device |
US11469321B2 (en) * | 2020-02-27 | 2022-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device |
US11670677B2 (en) * | 2020-10-02 | 2023-06-06 | Samsung Electronics Co., Ltd. | Crossing multi-stack nanosheet structure and method of manufacturing the same |
US20220140098A1 (en) * | 2020-10-29 | 2022-05-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nano Transistors with Source/Drain Having Side Contacts to 2-D Material |
CN114078952A (en) * | 2020-10-29 | 2022-02-22 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
US11955527B2 (en) * | 2020-10-29 | 2024-04-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nano transistors with source/drain having side contacts to 2-D material |
EP4020586A1 (en) * | 2020-12-23 | 2022-06-29 | INTEL Corporation | Transition metal dichalcogenide nanosheet transistors and methods of fabrication |
WO2023011177A1 (en) * | 2021-08-03 | 2023-02-09 | International Business Machines Corporation | Stacked complementary field effect transistors |
US11916073B2 (en) | 2021-08-03 | 2024-02-27 | International Business Machines Corporation | Stacked complementary field effect transistors |
EP4156303A1 (en) * | 2021-09-24 | 2023-03-29 | INTEL Corporation | Thin film transistors having multi-layer gate dielectric structures integrated with 2d channel materials |
EP4156246A1 (en) * | 2021-09-24 | 2023-03-29 | INTEL Corporation | Thin film transistors having cmos functionality integrated with 2d channel materials |
WO2023098600A1 (en) * | 2021-12-02 | 2023-06-08 | International Business Machines Corporation | Stacked nanosheet transistor with defect free channel |
US11705504B2 (en) | 2021-12-02 | 2023-07-18 | International Business Machines Corporation | Stacked nanosheet transistor with defect free channel |
WO2023146696A1 (en) * | 2022-01-26 | 2023-08-03 | Qualcomm Incorporated | Trench power rail in cell circuits to reduce resistance and related power distribution networks and fabrication methods |
EP4228002A3 (en) * | 2022-02-15 | 2023-11-29 | Samsung Electronics Co., Ltd. | Semiconductor device having a two-dimensional channel and method for fabricating the same |
WO2023216679A1 (en) * | 2022-05-09 | 2023-11-16 | 成都海光微电子技术有限公司 | Layout design method, system and device, and circuit layout and storage medium |
Also Published As
Publication number | Publication date |
---|---|
US10734384B1 (en) | 2020-08-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10734384B1 (en) | Vertically-integrated two-dimensional (2D) semiconductor slabs in complementary field effect transistor (CFET) cell circuits, and method of fabricating | |
US10861852B2 (en) | Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) for complementary metal-oxide semiconductor (CMOS) cell circuits | |
US10332881B1 (en) | Integrating a gate-all-around (GAA) field-effect transistor(s) (FET(S)) and a finFET(s) on a common substrate of a semiconductor die | |
US11011602B2 (en) | Circuits employing adjacent low-k dummy gate to a field-effect transistor (FET) to reduce FET source/drain parasitic capacitance, and related fabrication methods | |
US10679994B1 (en) | Circuits employing asymmetric diffusion breaks in different type semiconductor diffusion regions, and related fabrication methods | |
US20170207313A1 (en) | NANOWIRE METAL-OXIDE SEMICONDUCTOR (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETs) EMPLOYING A NANOWIRE CHANNEL STRUCTURE EMPLOYING RECESSED CONDUCTIVE STRUCTURES FOR CONDUCTIVELY COUPLING NANOWIRE STRUCTURES | |
US20200105670A1 (en) | MIDDLE-OF-LINE (MOL) COMPLEMENTARY POWER RAIL(S) IN INTEGRATED CIRCUITS (ICs) FOR REDUCED SEMICONDUCTOR DEVICE RESISTANCE | |
US10622479B1 (en) | Circuits employing a double diffusion break (DDB) and single diffusion break (SDB) in different type diffusion region(s), and related fabrication methods | |
US10892322B2 (en) | Circuits employing a double diffusion break (DDB) and single diffusion break (SDB) in different type diffusion region(s), and related fabrication methods | |
US20210384227A1 (en) | Gate-all-around (gaa) transistor with insulator on substrate and methods of fabricating | |
US10483200B1 (en) | Integrated circuits (ICs) employing additional output vertical interconnect access(es) (VIA(s)) coupled to a circuit output VIA to decrease circuit output resistance | |
US20200020688A1 (en) | Integrated circuits employing varied gate topography between an active gate region(s) and a field gate region(s) in a gate(s) for reduced gate layout parasitic capacitance, and related methods | |
US11404374B2 (en) | Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods | |
US11437379B2 (en) | Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits | |
US10763364B1 (en) | Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods | |
US20210118985A1 (en) | Circuits employing on-diffusion (od) edge (ode) dummy gate structures in cell circuit with increased gate dielectric thickness to reduce leakage current | |
US10431686B1 (en) | Integrated circuit (IC) employing a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformity | |
US10411091B1 (en) | Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods | |
US11295991B2 (en) | Complementary cell circuits employing isolation structures for defect reduction and related methods of fabrication | |
US20240021586A1 (en) | Stacked complementary field effect transistor (cfet) and method of manufacture | |
US20240096964A1 (en) | Vertical channel field effect transistor (vcfet) with reduced contact resistance and/or parasitic capacitance, and related fabrication methods | |
US20240047455A1 (en) | Monolithic three-dimensional (3d) complementary field effect transistor (cfet) circuits and method of manufacture | |
US20210143153A1 (en) | Fin field-effect transistor (fet) (finfet) circuits employing replacement n-type fet (nfet) source/drain (s/d) to avoid or prevent short defects and related methods of fabrication |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: QUALCOMM INCORPORATED, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LI, XIA;YANG, BIN;TAO, GENGMING;SIGNING DATES FROM 20190312 TO 20190313;REEL/FRAME:048657/0574 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |