US20200194341A1 - Semiconductor Package and Fabricating Method thereof - Google Patents

Semiconductor Package and Fabricating Method thereof Download PDF

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Publication number
US20200194341A1
US20200194341A1 US16/695,190 US201916695190A US2020194341A1 US 20200194341 A1 US20200194341 A1 US 20200194341A1 US 201916695190 A US201916695190 A US 201916695190A US 2020194341 A1 US2020194341 A1 US 2020194341A1
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Prior art keywords
substrate layer
chip
internal space
liquid
semiconductor package
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US16/695,190
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Tien-Chien Cheng
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Cheng Tien Chien
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Tien-Chien Cheng
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Priority to US16/695,190 priority Critical patent/US20200194341A1/en
Publication of US20200194341A1 publication Critical patent/US20200194341A1/en
Priority to US17/469,698 priority patent/US20210407886A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/22—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device liquid at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Definitions

  • the present invention relates to a semiconductor package and a method of fabricating such semiconductor package, and more particularly, to a semiconductor package and a method of fabricating a semiconductor package having better heat dissipation and a method of fabricating such semiconductor package.
  • a conventional semiconductor package typically has weak heat dissipation. Therefore, such conventional semiconductor package is vulnerable to concentrated heat and malfunctions consequently. Such heat concentration easily occurs during the fabrication process of the conventional semiconductor package. For preventing damages to the conventional semiconductor package caused by heat, such heat concentration is required to be removed or neutralized.
  • the present disclosure aims at disclosing a semiconductor package for efficiently facilitating heat dissipation.
  • the semiconductor package includes a substrate layer, a chip and a housing lid.
  • the chip is disposed on the substrate layer.
  • the chip is electrically coupled to the substrate layer.
  • the chip is smaller than the substrate layer in area.
  • the housing lid is disposed above the chip.
  • the housing lid covers the chip and the substrate layer.
  • the housing lid, the chip and the substrate layer form an internal space.
  • the internal space fills with a thermal interface material (TIM).
  • TIM thermal interface material
  • the thermal interface material includes a heat conductive liquid.
  • the thermal interface material includes a silicon oil, a thermal grease, a thermal gel, a phase change liquid material, and/or a thermal conductive adhesive.
  • the housing lid includes an inlet hole.
  • the inlet hole allows the liquid-form TIM to flow into the internal space.
  • the semiconductor package further includes an inlet plug.
  • the inlet plug blocks the inlet hole for stopping other liquid-form TIM from flowing into the internal space. Such that the liquid-form TIM is sealed inside the internal space.
  • the inlet plug includes a screw.
  • the inlet hole includes a lateral thread. Also, the screw detachably engages with the lateral thread for blocking the inlet hole.
  • the housing lid further includes an outlet hole.
  • the outlet hole allows the liquid-form TIM to flow out of the internal space.
  • the semiconductor package further includes an inlet plug. And the inlet plug blocks the inlet hole for stopping other liquid-form TIM from flowing into the internal space via the inlet hole.
  • the outlet plug blocks the outlet hole for stopping the liquid-form TIM from flowing out of the internal space via the outlet hole.
  • the inlet plug and the outlet plug additionally seal the liquid-form TIM inside the internal space.
  • the inlet plug includes an inlet screw.
  • the outlet plug includes an outlet screw.
  • the inlet hole includes a first lateral thread.
  • the outlet hole includes a second lateral thread.
  • the inlet screw detachably engages with the first lateral thread for blocking the inlet hole.
  • the outlet screw detachably engages with the second lateral thread for blocking the outlet hole.
  • the semiconductor package further includes an adhesive layer.
  • the adhesive layer is disposed between the housing lid and the substrate layer. Also, the adhesive layer substantially contacts both the housing lid and the substrate layer. Such that the housing lid is adhered with the substrate layer.
  • the substrate layer further includes a plurality of solder bumps.
  • the solder bumps are configured disposed between the substrate layer and an external printed circuit board (PCB). Such that the substrate layer is electrically coupled to the external PCB via the plurality of solder bumps.
  • PCB printed circuit board
  • the substrate layer further includes a plurality of solder bumps.
  • the solder bumps are sandwiched between the substrate layer and the chip. Such that the chip is electrically coupled to the substrate layer via the plurality of solder bumps.
  • the present disclosure also discloses a method of fabricating a semiconductor package.
  • a chip is disposed above a substrate layer. Such that the chip is electrically coupled to the substrate layer. Additionally, the chip is smaller than the substrate layer in area.
  • a housing lid is disposed to cover the chip and the substrate layer.
  • an internal space is formed between the housing lid, the chip and the substrate layer.
  • the internal space is filled with a liquid-form TIM.
  • an inlet hole is drilled on the housing lid. And the conductive liquid flows into the internal space via the inlet hole.
  • the inlet hole is additionally blocked to stop other liquid-form TIM from flowing into the internal space via the inlet hole and to seal the liquid-form TIM inside the internal space.
  • an outlet hole is additionally drilled on the housing lid. Also, at least part of the liquid-form TIM is driven to flow out of the internal space via the outlet hole.
  • the inlet hole is blocked to stop other liquid-form TIM from flowing into the internal space via the inlet hole.
  • the outlet hole is blocked to stop the liquid-form TIM from flowing out of the internal space via the outlet hole.
  • the housing lid is additionally adhered to the substrate layer.
  • a plurality of solder bumps is sandwiched between the substrate layer and an external PCB in a way that the substrate layer is electrically coupled to the external PCB via the plurality of solder bumps.
  • a plurality of solder bumps is additionally sandwiched between the substrate layer and the chip in a way that the chip is electrically coupled to the substrate layer via the plurality of solder bumps.
  • FIG. 1 illustrates a semiconductor package according to one embodiment of the present disclosure.
  • FIG. 2 illustrates at least one inlet hole disposed on a housing lid shown in FIG. 1 .
  • FIG. 3 illustrates at least one inlet plug used for blocking the at least one inlet hole shown in FIG. 2 .
  • FIG. 4 illustrates at least one inlet hole and/or at least one outlet hole disposed on the housing lid shown in FIG. 1 .
  • FIG. 5 illustrates at least one inlet plug and/or at least one outlet plug for blocking the at least one inlet hole and/or the at least one outlet hole shown in FIG. 4 .
  • FIG. 6 illustrate at least one adhesive layer and/or at least one solder bump applied on the semiconductor package shown in FIG. 1 .
  • the present disclosure discloses a semiconductor package that can improve heat dissipation. In this way, the semiconductor package can be substantially prevented from being damaged by over-concentrated heat during its fabrication process.
  • FIG. 1 illustrates a semiconductor package 100 according to one embodiment of the present disclosure.
  • the semiconductor package 100 includes a substrate layer 110 , a chip 120 , and a housing lid 130 .
  • the chip 120 is disposed on the substrate layer 110 . Also, the chip 120 is electrically coupled to the substrate layer 110 . Additionally, the chip 120 's area is smaller than that of the substrate layer 110 .
  • the housing lid 130 is disposed above the chip 120 . Also, the housing lid 130 covers the chip 120 and the substrate layer 110 from their top side.
  • the housing lid 130 , the chip 120 and the substrate layer 110 form an internal space 140 .
  • the internal space 140 fills with a liquid-form thermal interface material (TIM).
  • TIM liquid-form thermal interface material
  • Such liquid-form TIM flows inside the semiconductor package 100 while fabricating the semiconductor package 100 . In this way, heat inside the semiconductor package 100 can be dissipated externally, and the semiconductor package 100 can be prevented from being damaged by concentrated heat.
  • the TIM include a heat conductive liquid.
  • the heat conductive liquid may include a silicon oil, a thermal grease, a thermal gel, a phase change liquid material, and/or a thermal conductive adhesive.
  • the abovementioned exemplary materials for implementing the TIM are qualified for efficiently dissipating heat from a highly concentrated heat source within the semiconductor package 100 .
  • the liquid-form TIM's thermal conductivity exceeds 10 W/(cm*K) or even 150 W/(cm*K), depending on the semiconductor packages 110 's different heat-dissipating requirements.
  • the housing lid 130 includes an inlet hole 150 for receiving the liquid-form TIM, as illustrated in FIG. 2 . In this way, the liquid-form TIM is allowed to flow into the internal space 140 .
  • the semiconductor package 100 further includes an inlet plug 160 for sealing the liquid-form TIM inside the internal space 140 , as illustrated in FIG. 3 . Also, external liquid-form TIM is stopped by the inlet plug 160 from being flowing into the inlet hole 150 .
  • the inlet plug 160 is implemented using a screw.
  • the inlet hole 150 further includes a lateral thread for receiving the screw. Such that the screw is detachably engaged with the lateral thread for blocking the inlet hole 150 .
  • the screw blocks the liquid-form TIM within the internal space 140 and stops external liquid-form TIM from flowing into the inlet hole 150 .
  • the housing lid 130 further includes an outlet hole 170 , as illustrated in FIG. 4 .
  • an outlet hole 170 After the liquid-form TIM flows into the inlet hole 150 and enters the internal space 140 , overflow liquid-form TIM inside the internal space 140 can flow out of the internal space 140 via the outlet hole 160 . That is, the inlet hole 150 , the internal space 140 and the outlet hole 160 forma heat cycle for removing over concentrated heat inside the semiconductor package 100 . In this way, the semiconductor package 100 can have a better heat protection.
  • the semiconductor package 100 further includes an outlet plug 180 for blocking the outlet hole 170 , as illustrated in FIG. 5 . Therefore, the abovementioned heat cycle stops. So, both the inlet plug 160 and the outlet plug 180 seal the liquid-form TIM inside the internal space 140 . Such that the liquid-form TIM within the internal space 140 keeps on cooling and solidifying. Also, both the inlet plug 160 and the outlet plug 180 block external liquid-form TIM from flowing into the inlet hole 150 and from flowing out of the outlet hole 170 .
  • both the inlet plug 160 and the outlet plug 180 are implemented using screws.
  • both the inlet hole 150 and the outlet hole 170 have lateral threads. Such that the inlet plug 160 screws into the inlet hole 150 for blocking the inlet hole 150 , and the outlet plug 180 screws into the outlet hole 160 for blocking the outlet hole 160 .
  • the semiconductor package 100 applies various numbers of inlet holes 160 and/or outlet holes 180 , according to various requirements of cooling/solidifying the liquid-form TIM sealed within the internal space 140 .
  • the semiconductor package 100 also applies at least one adhesive layer 210 , as illustrated in FIG. 6 .
  • the at least one adhesive layer 210 is disposed between the housing lid 130 and the substrate layer 110 . In this way, the at least one adhesive layer 210 substantially and partially contacts and adheres the housing lid 130 to the substrate layer 110 . Such that the housing lid 130 and the substrate layer 110 can form an integral structure and a more compact structure.
  • the semiconductor package 100 applies solder bumps for improving its electronic operations.
  • the semiconductor package 100 applies solder bumps 220 between the substrate layer 110 and an external printed circuit board (PCB).
  • PCB printed circuit board
  • the semiconductor package 100 optionally applies solder bumps 230 between the chip 120 and the substrate layer 110 , as illustrated in FIG. 6 . Such that the chip 120 is electrically coupled to the substrate layer 110 via the solder bumps 230 for required operations.
  • the present disclosure also introduces a method of fabricating the semiconductor package 100 .
  • the chip 120 is disposed above the substrate layer 110 to render the chip 120 to be electrically coupled to the substrate layer 110 .
  • the housing lid 130 is disposed to cover the chip 120 and the substrate layer 110 .
  • the internal space 140 is formed between the housing lid 130 , the chip 120 and the substrate layer 110 .
  • the liquid-form TIM is filled into the internal space 140 . Additionally, after performing an appropriate baking procedure, the liquid-form TIM is solidified within the internal space 140 , such that the semiconductor package 110 's electronic properties become stable.
  • the inlet hole 150 is additionally drilled on the housing lid 130 for allowing the liquid-form
  • the inlet plug 160 is used for blocking the inlet hole 150 to seal the liquid-form TIM within the internal space 140 .
  • the outlet hole 170 is further drilled on the housing lid 130 for allowing the liquid-form TIM to flow out of the internal space 140 .
  • the outlet plug 180 is used for blocking the outlet hole 170 for sealing the liquid-form TIM within the internal space 140 .
  • the housing lid 130 is at least partially adhered to the substrate layer, e.g., with the aid of the at least one adhesive layer 210 .
  • solder bumps 220 are sandwiched between the substrate layer 110 and the external PCB for enabling mutual electronic operations.
  • solder bumps 230 are disposed between the substrate layer 110 and the chip 120 for enabling mutual electronic operations.

Abstract

A semiconductor package is disclosed for efficiently facilitating heat dissipation. The semiconductor package includes a substrate layer, a chip and a housing lid. The chip is disposed on the substrate layer. Also, the chip is electrically coupled to the substrate layer. Additionally, the chip is smaller than the substrate layer in area. The housing lid is disposed above the chip. Moreover, the housing lid covers the chip and the substrate layer. The housing lid, the chip and the substrate layer form an internal space. The internal space fills with a thermal interface material.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This application claims the benefit of U.S. Provisional Application No. 62/780,932, filed on Dec. 18, 2018 and entitled “ SEMICONDUCTOR TESTING DEVICE AND PACKAGE”, the contents of which are incorporated herein by reference.
    • BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present invention relates to a semiconductor package and a method of fabricating such semiconductor package, and more particularly, to a semiconductor package and a method of fabricating a semiconductor package having better heat dissipation and a method of fabricating such semiconductor package.
    • 2. Description of the Prior Art
  • A conventional semiconductor package typically has weak heat dissipation. Therefore, such conventional semiconductor package is vulnerable to concentrated heat and malfunctions consequently. Such heat concentration easily occurs during the fabrication process of the conventional semiconductor package. For preventing damages to the conventional semiconductor package caused by heat, such heat concentration is required to be removed or neutralized.
    • SUMMARY OF THE INVENTION
  • The present disclosure aims at disclosing a semiconductor package for efficiently facilitating heat dissipation. The semiconductor package includes a substrate layer, a chip and a housing lid. The chip is disposed on the substrate layer. Also, the chip is electrically coupled to the substrate layer. Additionally, the chip is smaller than the substrate layer in area. The housing lid is disposed above the chip. Moreover, the housing lid covers the chip and the substrate layer. The housing lid, the chip and the substrate layer form an internal space. The internal space fills with a thermal interface material (TIM).
  • In one example, the thermal interface material includes a heat conductive liquid. In one example, the thermal interface material includes a silicon oil, a thermal grease, a thermal gel, a phase change liquid material, and/or a thermal conductive adhesive.
  • In one example, the housing lid includes an inlet hole. The inlet hole allows the liquid-form TIM to flow into the internal space.
  • In one example, the semiconductor package further includes an inlet plug. The inlet plug blocks the inlet hole for stopping other liquid-form TIM from flowing into the internal space. Such that the liquid-form TIM is sealed inside the internal space. The inlet plug includes a screw. The inlet hole includes a lateral thread. Also, the screw detachably engages with the lateral thread for blocking the inlet hole.
  • In one example, the housing lid further includes an outlet hole. The outlet hole allows the liquid-form TIM to flow out of the internal space. Also, in another example, the semiconductor package further includes an inlet plug. And the inlet plug blocks the inlet hole for stopping other liquid-form TIM from flowing into the internal space via the inlet hole. The outlet plug blocks the outlet hole for stopping the liquid-form TIM from flowing out of the internal space via the outlet hole. The inlet plug and the outlet plug additionally seal the liquid-form TIM inside the internal space.
  • In one example, the inlet plug includes an inlet screw. The outlet plug includes an outlet screw. The inlet hole includes a first lateral thread. And the outlet hole includes a second lateral thread. Also, the inlet screw detachably engages with the first lateral thread for blocking the inlet hole. Additionally, the outlet screw detachably engages with the second lateral thread for blocking the outlet hole.
  • In one example, the semiconductor package further includes an adhesive layer. The adhesive layer is disposed between the housing lid and the substrate layer. Also, the adhesive layer substantially contacts both the housing lid and the substrate layer. Such that the housing lid is adhered with the substrate layer.
  • In one example, the substrate layer further includes a plurality of solder bumps. The solder bumps are configured disposed between the substrate layer and an external printed circuit board (PCB). Such that the substrate layer is electrically coupled to the external PCB via the plurality of solder bumps.
  • In one example, the substrate layer further includes a plurality of solder bumps. The solder bumps are sandwiched between the substrate layer and the chip. Such that the chip is electrically coupled to the substrate layer via the plurality of solder bumps.
  • The present disclosure also discloses a method of fabricating a semiconductor package. In the disclosed method, first, a chip is disposed above a substrate layer. Such that the chip is electrically coupled to the substrate layer. Additionally, the chip is smaller than the substrate layer in area. Second, a housing lid is disposed to cover the chip and the substrate layer. Third, an internal space is formed between the housing lid, the chip and the substrate layer.
  • Last, the internal space is filled with a liquid-form TIM.
  • In one example, an inlet hole is drilled on the housing lid. And the conductive liquid flows into the internal space via the inlet hole.
  • In one example, the inlet hole is additionally blocked to stop other liquid-form TIM from flowing into the internal space via the inlet hole and to seal the liquid-form TIM inside the internal space.
  • In one example, an outlet hole is additionally drilled on the housing lid. Also, at least part of the liquid-form TIM is driven to flow out of the internal space via the outlet hole.
  • In one example, the inlet hole is blocked to stop other liquid-form TIM from flowing into the internal space via the inlet hole. Moreover, the outlet hole is blocked to stop the liquid-form TIM from flowing out of the internal space via the outlet hole.
  • In one example, the housing lid is additionally adhered to the substrate layer.
  • In one example, a plurality of solder bumps is sandwiched between the substrate layer and an external PCB in a way that the substrate layer is electrically coupled to the external PCB via the plurality of solder bumps.
  • In one example, a plurality of solder bumps is additionally sandwiched between the substrate layer and the chip in a way that the chip is electrically coupled to the substrate layer via the plurality of solder bumps.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates a semiconductor package according to one embodiment of the present disclosure.
  • FIG. 2 illustrates at least one inlet hole disposed on a housing lid shown in FIG. 1.
  • FIG. 3 illustrates at least one inlet plug used for blocking the at least one inlet hole shown in FIG. 2.
  • FIG. 4 illustrates at least one inlet hole and/or at least one outlet hole disposed on the housing lid shown in FIG. 1.
  • FIG. 5 illustrates at least one inlet plug and/or at least one outlet plug for blocking the at least one inlet hole and/or the at least one outlet hole shown in FIG. 4.
  • FIG. 6 illustrate at least one adhesive layer and/or at least one solder bump applied on the semiconductor package shown in FIG. 1.
    •  DETAILED DESCRIPTION
  • As mentioned above, the present disclosure discloses a semiconductor package that can improve heat dissipation. In this way, the semiconductor package can be substantially prevented from being damaged by over-concentrated heat during its fabrication process.
  • FIG. 1 illustrates a semiconductor package 100 according to one embodiment of the present disclosure. The semiconductor package 100 includes a substrate layer 110, a chip 120, and a housing lid 130.
  • The chip 120 is disposed on the substrate layer 110. Also, the chip 120 is electrically coupled to the substrate layer 110. Additionally, the chip 120's area is smaller than that of the substrate layer 110.
  • The housing lid 130 is disposed above the chip 120. Also, the housing lid 130 covers the chip 120 and the substrate layer 110 from their top side.
  • The housing lid 130, the chip 120 and the substrate layer 110 form an internal space 140. In some examples, the internal space 140 fills with a liquid-form thermal interface material (TIM). Such liquid-form TIM flows inside the semiconductor package 100 while fabricating the semiconductor package 100. In this way, heat inside the semiconductor package 100 can be dissipated externally, and the semiconductor package 100 can be prevented from being damaged by concentrated heat.
  • In some examples, the TIM include a heat conductive liquid. In some other examples, the heat conductive liquid may include a silicon oil, a thermal grease, a thermal gel, a phase change liquid material, and/or a thermal conductive adhesive. The abovementioned exemplary materials for implementing the TIM are qualified for efficiently dissipating heat from a highly concentrated heat source within the semiconductor package 100. In some examples, the liquid-form TIM's thermal conductivity exceeds 10 W/(cm*K) or even 150 W/(cm*K), depending on the semiconductor packages 110's different heat-dissipating requirements.
  • In some examples, the housing lid 130 includes an inlet hole 150 for receiving the liquid-form TIM, as illustrated in FIG. 2. In this way, the liquid-form TIM is allowed to flow into the internal space 140. Also, in some examples, the semiconductor package 100 further includes an inlet plug 160 for sealing the liquid-form TIM inside the internal space 140, as illustrated in FIG. 3. Also, external liquid-form TIM is stopped by the inlet plug 160 from being flowing into the inlet hole 150.
  • In some other examples, the inlet plug 160 is implemented using a screw. In addition, the inlet hole 150 further includes a lateral thread for receiving the screw. Such that the screw is detachably engaged with the lateral thread for blocking the inlet hole 150. Similarly, the screw blocks the liquid-form TIM within the internal space 140 and stops external liquid-form TIM from flowing into the inlet hole 150.
  • In some examples, the housing lid 130 further includes an outlet hole 170, as illustrated in FIG. 4. After the liquid-form TIM flows into the inlet hole 150 and enters the internal space 140, overflow liquid-form TIM inside the internal space 140 can flow out of the internal space 140 via the outlet hole 160. That is, the inlet hole 150, the internal space 140 and the outlet hole 160 forma heat cycle for removing over concentrated heat inside the semiconductor package 100. In this way, the semiconductor package 100 can have a better heat protection.
  • Similarly, in some examples, besides the inlet plug 160, the semiconductor package 100 further includes an outlet plug 180 for blocking the outlet hole 170, as illustrated in FIG. 5. Therefore, the abovementioned heat cycle stops. So, both the inlet plug 160 and the outlet plug 180 seal the liquid-form TIM inside the internal space 140. Such that the liquid-form TIM within the internal space 140 keeps on cooling and solidifying. Also, both the inlet plug 160 and the outlet plug 180 block external liquid-form TIM from flowing into the inlet hole 150 and from flowing out of the outlet hole 170.
  • Similarly, in some examples, both the inlet plug 160 and the outlet plug 180 are implemented using screws. In addition, both the inlet hole 150 and the outlet hole 170 have lateral threads. Such that the inlet plug 160 screws into the inlet hole 150 for blocking the inlet hole 150, and the outlet plug 180 screws into the outlet hole 160 for blocking the outlet hole 160.
  • In some examples, the semiconductor package 100 applies various numbers of inlet holes 160 and/or outlet holes 180, according to various requirements of cooling/solidifying the liquid-form TIM sealed within the internal space 140.
  • In some examples, the semiconductor package 100 also applies at least one adhesive layer 210, as illustrated in FIG. 6. The at least one adhesive layer 210 is disposed between the housing lid 130 and the substrate layer 110. In this way, the at least one adhesive layer 210 substantially and partially contacts and adheres the housing lid 130 to the substrate layer 110. Such that the housing lid 130 and the substrate layer 110 can form an integral structure and a more compact structure.
  • In some examples, the semiconductor package 100 applies solder bumps for improving its electronic operations. Optionally, as illustrated in FIG. 6, the semiconductor package 100 applies solder bumps 220 between the substrate layer 110 and an external printed circuit board (PCB). In this way, the substrate layer 110 and the external PCB is electrically coupled via the solder bumps 220. Therefore, the semiconductor package 100 is capable of cooperating with the external PCB. In some examples, the semiconductor package 100 optionally applies solder bumps 230 between the chip 120 and the substrate layer 110, as illustrated in FIG. 6. Such that the chip 120 is electrically coupled to the substrate layer 110 via the solder bumps 230 for required operations.
  • The present disclosure also introduces a method of fabricating the semiconductor package 100. First, the chip 120 is disposed above the substrate layer 110 to render the chip 120 to be electrically coupled to the substrate layer 110. Second, the housing lid 130 is disposed to cover the chip 120 and the substrate layer 110. Third, the internal space 140 is formed between the housing lid 130, the chip 120 and the substrate layer 110. Last, the liquid-form TIM is filled into the internal space 140. Additionally, after performing an appropriate baking procedure, the liquid-form TIM is solidified within the internal space 140, such that the semiconductor package 110's electronic properties become stable.
  • In some examples, the inlet hole 150 is additionally drilled on the housing lid 130 for allowing the liquid-form
  • TIM to flow into the internal space 140. Also, the inlet plug 160 is used for blocking the inlet hole 150 to seal the liquid-form TIM within the internal space 140.
  • Similarly, in some examples, the outlet hole 170 is further drilled on the housing lid 130 for allowing the liquid-form TIM to flow out of the internal space 140. Moreover, the outlet plug 180 is used for blocking the outlet hole 170 for sealing the liquid-form TIM within the internal space 140. In some examples, the housing lid 130 is at least partially adhered to the substrate layer, e.g., with the aid of the at least one adhesive layer 210.
  • In some examples, the solder bumps 220 are sandwiched between the substrate layer 110 and the external PCB for enabling mutual electronic operations. Similarly, in some examples, the solder bumps 230 are disposed between the substrate layer 110 and the chip 120 for enabling mutual electronic operations.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (20)

What is claimed is:
1. A semiconductor package, comprising:
a substrate layer;
a chip, disposed on the substrate layer and electrically coupled to the substrate layer, wherein the chip is smaller than the substrate layer in area; and
a housing lid, disposed above the chip, and configured to cover the chip and the substrate layer;
wherein the housing lid, the chip and the substrate layer are configured to form an internal space, which is configured to fill with a thermal interface material (TIM).
2. The semiconductor package of claim 1, wherein the thermal interface material comprises a heat conductive liquid.
3. The semiconductor package of claim 1, wherein the thermal interface material comprises a silicon oil, a thermal grease, a thermal gel, a phase change liquid material, and/or a thermal conductive adhesive.
4. The semiconductor package of claim 1, wherein the housing lid comprises an inlet hole, which is configured to allow the liquid-form TIM to flow into the internal space.
5. The semiconductor package of claim 4, further comprising an inlet plug, which is configured to block the inlet hole for stopping other liquid-form TIM from flowing into the internal space, such that the liquid-form TIM is sealed inside the internal space.
6. The semiconductor package of claim 5, wherein the inlet plug comprises a screw, and the inlet hole comprises a lateral thread, and the screw is configured to detachably engage with the lateral thread for blocking the inlet hole.
7. The semiconductor package of claim 4, wherein the housing lid further comprises an outlet hole, which is configured to allow the liquid-form TIM to flow out of the internal space.
8. The semiconductor package of claim 7, further comprising:
an inlet plug, configured to block the inlet hole for stopping other liquid-form TIM from flowing into the internal space via the inlet hole; and
an outlet plug, configured to block the outlet hole for stopping the liquid-form TIM from flowing out of the internal space via the outlet hole;
wherein the inlet plug and the outlet plug are further configured to seal the liquid-form TIM inside the internal space.
9. The semiconductor package of claim 8, wherein the inlet plug comprises an inlet screw, the outlet plug comprises an outlet screw, the inlet hole comprises a first lateral thread, and the outlet hole comprises a second lateral thread; and
wherein the inlet screw is configured to detachably engage with the first lateral thread for blocking the inlet hole, and the outlet screw is configured to detachably engage with the second lateral thread for blocking the outlet hole.
10. The semiconductor package of claim 1, further comprising:
an adhesive layer, disposed between the housing lid and the substrate layer, and configured to substantially contact both the housing lid and the substrate layer for adhering the housing lid with the substrate layer.
11. The semiconductor package of claim 1, wherein the substrate layer further comprises a plurality of solder bumps, which are configured to be disposed between the substrate layer and an external printed circuit board (PCB), such that the substrate layer is electrically coupled to the external PCB via the plurality of solder bumps.
12. The semiconductor package of claim 1, wherein the substrate layer further comprises a plurality of solder bumps, which are configured to be sandwiched between the substrate layer and the chip, such that the chip is electrically coupled to the substrate layer via the plurality of solder bumps.
13. A method of fabricating a semiconductor package, comprising:
disposing a chip above a substrate layer, such that the chip electrically coupled to the substrate layer, wherein the chip is smaller than the substrate layer in area;
disposing a housing lid to cover the chip and the substrate layer;
forming an internal space between the housing lid, the chip and the substrate layer; and
filling the internal space with a liquid-form TIM.
14. The method of claim 13, further comprising:
drilling an inlet hole on the housing lid; and
flowing the conductive liquid into the internal space via the inlet hole.
15. The method of claim 14, further comprising:
blocking the inlet hole to stop other liquid-form TIM from flowing into the internal space via the inlet hole and to seal the liquid-form TIM inside the internal space.
16. The method of claim 14, further comprising:
drilling an outlet hole on the housing lid; and
driving at least part of the liquid-form TIM to flow out of the internal space via the outlet hole.
17. The method of claim 16, further comprising:
blocking the inlet hole to stop other liquid-form TIM from flowing into the internal space via the inlet hole; and
blocking the outlet hole to stop the liquid-form TIM from flowing out of the internal space via the outlet hole.
18. The method of claim 13, further comprising:
adhering the housing lid to the substrate layer.
19. The method of claim 13, further comprising:
sandwiching a plurality of solder bumps between the substrate layer and an external PCB in a way that the substrate layer is electrically coupled to the external PCB via the plurality of solder bumps.
20. The method of claim 13, further comprising:
sandwiching a plurality of solder bumps between the substrate layer and the chip in a way that the chip is electrically coupled to the substrate layer via the plurality of solder bumps.
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