US20200159048A1 - Lateral moscap phase adjuster - Google Patents
Lateral moscap phase adjuster Download PDFInfo
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- US20200159048A1 US20200159048A1 US16/196,947 US201816196947A US2020159048A1 US 20200159048 A1 US20200159048 A1 US 20200159048A1 US 201816196947 A US201816196947 A US 201816196947A US 2020159048 A1 US2020159048 A1 US 2020159048A1
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- 239000000758 substrate Substances 0.000 claims abstract description 28
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Images
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/015—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction
- G02F1/025—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction in an optical waveguide structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
- H01L29/66189—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors with PN junction, e.g. hybrid capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/10—Materials and properties semiconductor
- G02F2202/104—Materials and properties semiconductor poly-Si
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/10—Materials and properties semiconductor
- G02F2202/105—Materials and properties semiconductor single crystal Si
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2203/00—Function characteristic
- G02F2203/50—Phase-only modulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
Definitions
- the present invention relates to a phase adjuster, and in particular to a lateral metal-oxide-semiconductor capacitor (MOSCAP) structure for use as a phase adjuster in optical devices, such as modulators.
- MOSCAP metal-oxide-semiconductor capacitor
- MOSCAP e.g. silicon-insulator-silicon capacitor (SISCAP)
- phase adjuster charge is accumulated or depleted at the interface of a thin insulating region between two conductive regions.
- the metal conductive region is typically a p+ or n+ doped poly-silicon region, that behaves like a metal.
- the change in effective index of the waveguide material is driven by a modulation of the carrier density in an electrically active waveguide.
- SISCAP Mach-Zehnder modulators comprising a pair of waveguide arms
- a MOSCAP phase adjuster causes changes to the effective index of the waveguide material resulting in a differential change in phase of the light propagating in the arms, which can be used to modulate an optical signal.
- An object of the present invention is to overcome the shortcomings of the prior art by providing a laterally disposed MOSCAP phase adjuster, and a method of fabricating a MOSCAP phase adjuster.
- phase adjuster device comprising:
- a first conductive region on the substrate including a first n or p dopant material at a first doping level
- a first contact region on the substrate adjacent to the first conductive region, including the first dopant material at a second, higher, doping level;
- a second conductive region including a second n or p dopant material, opposite the first dopant material, at a second doping level
- the second conductive region includes a raised spacer portion extending upwardly beyond the first conductive region and at least partially across the top of the first conductive region.
- Another aspect of the present invention relates to a method of fabricating a phase adjuster device comprising;
- etching the device layer to form a first conductive region, a first contact region, and an opening on the substrate;
- step of depositing the second material in the opening also comprises depositing the second material over the first conductive region forming a rounded transition section on top of the second conductive region;
- etching the second material comprises etching the rounded transition section to form a raised spacer portion extending from the first conductive region adjacent the insulator layer.
- FIG. 1 is a cross-sectional view of a phase adjuster in accordance with an embodiment of the present invention
- FIGS. 2A to 2F are side views representing fabrication steps for a method of fabricating the device of FIG. 1 ;
- FIGS. 3A to 3E are side views representing a preferred embodiment for the final deposition, masking and etching steps of the method of FIGS. 2A to 2F ;
- FIGS. 4A to 4E are side views representing an alternative embodiment for the final deposition, masking and etching steps of the method of FIGS. 2A to 2F .
- a MOSCAP phase adjuster 1 in accordance with the present invention includes a first conductive region 2 , e.g. body, a second conductive region 3 , e.g. gate, and a insulator region 4 therebetween, all mounted on a substrate 5 .
- the first and second conductive regions 2 and 3 may form a ridge waveguide structure.
- the substrate 5 may be comprised of a dielectric material, such as an oxide of a semiconductor, and may be comprised of a silicon dioxide layer of a silicon on insulator (SOI) structure, as is well known in the industry.
- SOI silicon on insulator
- the first conductive region may be comprised of a semiconductor material, e.g. silicon, doped with n+ material, e.g. phosphorous, arsenic, antimony, bismuth and lithium. Typically, the first conductive region 2 is about 200 nm to 250 nm high, but any suitable height is possible. Adjacent to the first conductive region 2 is a first contact region 6 , which is thinner than the first conductive region 2 , e.g. about half as thick or 100 nm to 125 nm thick. The first contact region 6 may form a second slab waveguide region. The first contact region 6 may comprise the same semiconductor material as the first conductive region 2 , and may include a higher concentration of n++ doping material providing greater electrical conductivity.
- n+ material e.g. phosphorous, arsenic, antimony, bismuth and lithium.
- n+ material e.g. phosphorous, arsenic, antimony, bismuth and lithium.
- the first contact region 6 may include a gradually increasing doping concentration from the first conductive region 2 to the outer end of the first contact region 3 .
- the first contact region 6 may be capable of receiving metal contacts (not shown) for transmitting electrical control, e.g. modulation, signals.
- the second conductive region 3 may be comprised of a semiconductor, a metal, or metal like material, e.g. poly-silicon, doped with p+ material, e.g. boron, aluminum, gallium and indium. Typically, the second conductive region 3 is about 200 nm to 250 nm high, but any suitable height is possible.
- the second conductive region 3 may include a raised spacer portion 7 .
- the raised spacer portion 7 may extend upwardly from the second conductive region 3 beyond the first conductive region 2 , and may include an arm, which extends at least partially across the first conductive region 2 with the insulator region 4 therebetween, as hereinbelow discussed with reference to FIGS. 4A to 4E .
- Adjacent to the second conductive region 6 is a second contact region 8 , which is thinner than the second conductive region 3 , e.g. about half as thick or 100 nm to 125 nm thick.
- the second contact region 8 may form a second slab waveguide region.
- the second contact region 8 may comprise the same material as the second conductive region 3 , and may include a higher concentration of p++ doping material providing greater electrical conductivity.
- the second contact region 8 may include a gradually increasing doping concentration from the second conductive region 3 to the outer end of the second contact region 8 .
- the second contact region 8 may be capable of receiving metal contacts (not shown) for transmitting electrical control, e.g. modulation, signals.
- the insulator region or gate dielectric layer 4 extends perpendicular to the substrate 5 in between the first and second conductive regions 2 and 3 .
- the insulator region 4 may be comprised of a dielectric material, which may be the same as the substrate 5 or a different dielectric material.
- the insulator region 4 may be from 5 nm to 20 nm wide, and preferably about 10 nm wide.
- Example dielectric materials include one or a combination of silicon dioxide, silicon nitride, and hafnium oxide, ideally having high dielectric constants providing a fast charging and discharging of the free carriers.
- the raised spacer portion 7 may be extended over top of the first conductive region 2 forming an arm 47 of the second conductive region 3 .
- the arm 47 may extend across the top of the second conductive region 3 forming an L-shaped second conductive region 3 .
- the insulator region 4 may also extend across the top of the first conductive region 2 between the first and second conductive regions 2 and 3 .
- the extended L-shaped second conductive region 3 / 47 increases optical mode overlap compared to either horizontal or lateral MOSCAP phase adjusters.
- the initial step includes providing a substrate 5 , which may be comprised of a dielectric material, e.g. silicon dioxide, with a waveguide device layer 21 , e.g. a semiconductor material, such as silicon, thereon.
- the device layer 21 may be the thickness of the first conductive region 2 or larger. If the device layer 21 is larger than the first conductive region 2 , then an initial etch or polishing step is required.
- the substrate 5 and device layer 21 comprise a SOI wafer, as is well known in the art.
- a hard mask 22 e.g.
- FIG. 2B illustrates a multi-step etching process, in which one section of the layer 21 is partially etched, e.g. about half the height or about 100 nm to 125 nm, to form the first contact region 6 , and another section of the device layer 21 , on the opposite side of the first conductive region 2 is fully etched down to the substrate 5 to form the first conductive region 2 , and to provide an opening on the substrate 5 to make room for the second conductive region 3 .
- a hard mask removal step may be conducted before the remaining structure, i.e. the first conductive region 2 and the first contact region 6 , is then subject to an oxidation step, FIG. 2C , to form the insulator region 4 on the side of the first conductive region 2 .
- a pad oxide layer may be applied to those areas of the first conductive region 2 , e.g. top, and o2Dpposite side, and the first contact region 6 , e.g. top and opposite side, to prevent oxide from developing thereon.
- the superfluous oxide may be removed, e.g. polished, after the oxidation step.
- FIG. 2D illustrates a deposition step for a second semiconductor, metal or metal-like material 23 , e.g. poly-silicon, on the substrate 5 and adjacent to the insulator region 4 .
- the material 23 may then be subject to a masking step to define the second conductive region 3 and the second contact region 8 , and then an etching step to form the second conductive region 3 and the second contact region 8 .
- FIG. 2E illustrates a deposition step for a second semiconductor, metal or metal-like material 23 , e.g. poly-silicon
- FIGS. 3A to 3E illustrate a preferred embodiment for the deposition, masking and etching steps for the second conductive region 3 and the second contact region 8 , as hereinbefore illustrated with reference to FIGS. 2D and 2E .
- the material 23 is deposited over the entire remaining structure, i.e. the opening on the substrate 5 , the first conductive region 2 , and the first contact region 6 .
- the deposition step forms a rounded transition section in the material 23 , which will become the raised spacer portion 7 , overtop of the second conductive region 2 as the material 23 transitions between the covering the opening on the substrate 5 to the top of the first conductive region 2 .
- a hard mask 31 is placed over a portion of the material 23 , including over the second contact region 8 and the second conductive region 3 , including the raised spacer portion 7 .
- a first etching step is conducted to remove all of the material 23 over the first conductive region 2 and the first contact region 6 .
- a mask 32 is deposited over the first conductive region 2 , the first contact region 6 , and the second conductive region 3 , including the raised spacer portion 7 to define the second contact region 8 .
- a second etching step ( FIG. 3E ) is provided to form the second contact region 8 . Any remnants of the mask 32 may then be removed by any suitable means to form the finished phase adjuster device 1 .
- FIGS. 4A to 4E illustrate an alternative embodiment for the deposition, masking and etching steps for the second conductive region 3 and the second contact region 8 , as hereinbefore illustrated with reference to FIGS. 2D and 2E for a phase adjuster 41 .
- the material 23 is deposited over the entire remaining structure, i.e. the opening on the substrate 5 , the first conductive region 2 , and the first contact region 6 .
- the deposition step forms a rounded transition section in the material 23 , which will become the raised spacer portion 7 , and an arm 47 extending overtop of, e.g.
- a first hard mask 42 is placed over a portion of the material 23 , including over the first contact region 2 , the second contact region 8 and the second conductive region 3 , including the raised spacer portion 7 , only leaving the material 23 over the first contact region 6 exposed.
- a first etching step is conducted to remove all of the material 23 over the first contact region 6 , and form an L-shaped second conductive region 3 , including the raised spacer portion 7 and the arm 47 over the first conductive region 2 with the insulating layer 4 therebetween.
- a second mask 43 is deposited over the first conductive region 2 , the first contact region 6 , and the second conductive region 3 , including the raised spacer portion 7 and arm 47 to define the second contact region 8 .
- a second etching step ( FIG. 4E ) is provided to form the second contact region 8 . Any remnants of the mask 42 may then be removed by any suitable means to form the finished phase adjuster device 41 .
- the L-shaped second conductive region 3 / 47 increases optical mode overlap for either a horizontal or a lateral MOSCAP phase adjuster.
- the doping steps for the first conductive region 2 and the first contact region 6 may be executed prior to the material 23 being deposited.
Abstract
Description
- The present invention relates to a phase adjuster, and in particular to a lateral metal-oxide-semiconductor capacitor (MOSCAP) structure for use as a phase adjuster in optical devices, such as modulators.
- In a MOSCAP, e.g. silicon-insulator-silicon capacitor (SISCAP), phase adjuster, charge is accumulated or depleted at the interface of a thin insulating region between two conductive regions. The metal conductive region is typically a p+ or n+ doped poly-silicon region, that behaves like a metal. The change in effective index of the waveguide material is driven by a modulation of the carrier density in an electrically active waveguide. In SISCAP Mach-Zehnder modulators, comprising a pair of waveguide arms, a MOSCAP phase adjuster causes changes to the effective index of the waveguide material resulting in a differential change in phase of the light propagating in the arms, which can be used to modulate an optical signal.
- In conventional SISCAP modulators, such as the one disclosed in U.S. Pat. No. 7,657,130, issued Feb. 2, 2010, to Shastri et al, the conductive and insulating regions are superposed layers, extending horizontally parallel to the substrate. Unfortunately, horizontally layered SISCAP phase adjusters do not provide the same flexibility in waveguide design as lateral SICAP devices, and therefore not provide as good a mode confinement and resulting phase shift performance
- An object of the present invention is to overcome the shortcomings of the prior art by providing a laterally disposed MOSCAP phase adjuster, and a method of fabricating a MOSCAP phase adjuster.
- Accordingly, the present invention relates to a phase adjuster device comprising:
- a substrate;
- a first conductive region on the substrate including a first n or p dopant material at a first doping level;
- a first contact region on the substrate, adjacent to the first conductive region, including the first dopant material at a second, higher, doping level;
- a second conductive region including a second n or p dopant material, opposite the first dopant material, at a second doping level;
- a second contact region on the substrate, adjacent to the first conductive region, including the second dopant material at a second, higher, doping level; and
- an insulator layer extending perpendicularly from the substrate between the first conductive region and the second conductive region;
- wherein the second conductive region includes a raised spacer portion extending upwardly beyond the first conductive region and at least partially across the top of the first conductive region.
- Another aspect of the present invention relates to a method of fabricating a phase adjuster device comprising;
- providing a substrate with a device layer, comprising a first material thereon;
- etching the device layer to form a first conductive region, a first contact region, and an opening on the substrate;
- forming an insulator layer on a vertical side of the first conductive region;
- depositing a second material, different than the first material, in the opening;
- etching the second material to form a second conductive region and a second contact region;
- doping the first conductive region with a first doping material at a first doping concentration;
- doping the first contact region with the first doping material at a second doping concentration, higher than the first doping concentration;
- doping the second conductive region with a second doping material at a third doping concentration; and
- doping the second contact region with the second doping material at a fourth doping concentration, higher than the third doping concentration;
- wherein the step of depositing the second material in the opening also comprises depositing the second material over the first conductive region forming a rounded transition section on top of the second conductive region; and
- wherein etching the second material comprises etching the rounded transition section to form a raised spacer portion extending from the first conductive region adjacent the insulator layer.
- The invention will be described in greater detail with reference to the accompanying drawings which represent preferred embodiments thereof, wherein:
-
FIG. 1 is a cross-sectional view of a phase adjuster in accordance with an embodiment of the present invention; -
FIGS. 2A to 2F are side views representing fabrication steps for a method of fabricating the device ofFIG. 1 ; -
FIGS. 3A to 3E are side views representing a preferred embodiment for the final deposition, masking and etching steps of the method ofFIGS. 2A to 2F ; and -
FIGS. 4A to 4E are side views representing an alternative embodiment for the final deposition, masking and etching steps of the method ofFIGS. 2A to 2F . - While the present teachings are described in conjunction with various embodiments and examples, it is not intended that the present teachings be limited to such embodiments. On the contrary, the present teachings encompass various alternatives and equivalents, as will be appreciated by those of skill in the art.
- A MOSCAP phase adjuster 1 in accordance with the present invention includes a first
conductive region 2, e.g. body, a secondconductive region 3, e.g. gate, and ainsulator region 4 therebetween, all mounted on asubstrate 5. The first and secondconductive regions substrate 5 may be comprised of a dielectric material, such as an oxide of a semiconductor, and may be comprised of a silicon dioxide layer of a silicon on insulator (SOI) structure, as is well known in the industry. - The first conductive region may be comprised of a semiconductor material, e.g. silicon, doped with n+ material, e.g. phosphorous, arsenic, antimony, bismuth and lithium. Typically, the first
conductive region 2 is about 200 nm to 250 nm high, but any suitable height is possible. Adjacent to the firstconductive region 2 is afirst contact region 6, which is thinner than the firstconductive region 2, e.g. about half as thick or 100 nm to 125 nm thick. Thefirst contact region 6 may form a second slab waveguide region. Thefirst contact region 6 may comprise the same semiconductor material as the firstconductive region 2, and may include a higher concentration of n++ doping material providing greater electrical conductivity. Thefirst contact region 6 may include a gradually increasing doping concentration from the firstconductive region 2 to the outer end of thefirst contact region 3. Thefirst contact region 6 may be capable of receiving metal contacts (not shown) for transmitting electrical control, e.g. modulation, signals. - The second
conductive region 3, may be comprised of a semiconductor, a metal, or metal like material, e.g. poly-silicon, doped with p+ material, e.g. boron, aluminum, gallium and indium. Typically, the secondconductive region 3 is about 200 nm to 250 nm high, but any suitable height is possible. The secondconductive region 3 may include a raisedspacer portion 7. The raisedspacer portion 7 may extend upwardly from the secondconductive region 3 beyond the firstconductive region 2, and may include an arm, which extends at least partially across the firstconductive region 2 with theinsulator region 4 therebetween, as hereinbelow discussed with reference toFIGS. 4A to 4E . Adjacent to the secondconductive region 6 is asecond contact region 8, which is thinner than the secondconductive region 3, e.g. about half as thick or 100 nm to 125 nm thick. Thesecond contact region 8 may form a second slab waveguide region. Thesecond contact region 8 may comprise the same material as the secondconductive region 3, and may include a higher concentration of p++ doping material providing greater electrical conductivity. Thesecond contact region 8 may include a gradually increasing doping concentration from the secondconductive region 3 to the outer end of thesecond contact region 8. Thesecond contact region 8 may be capable of receiving metal contacts (not shown) for transmitting electrical control, e.g. modulation, signals. - The insulator region or
gate dielectric layer 4 extends perpendicular to thesubstrate 5 in between the first and secondconductive regions insulator region 4 may be comprised of a dielectric material, which may be the same as thesubstrate 5 or a different dielectric material. Theinsulator region 4 may be from 5 nm to 20 nm wide, and preferably about 10 nm wide. Example dielectric materials include one or a combination of silicon dioxide, silicon nitride, and hafnium oxide, ideally having high dielectric constants providing a fast charging and discharging of the free carriers. - In an alternate embodiment illustrated in
FIG. 4E , the raisedspacer portion 7 may be extended over top of the firstconductive region 2 forming anarm 47 of the secondconductive region 3. Ideally, thearm 47, may extend across the top of the secondconductive region 3 forming an L-shaped secondconductive region 3. Furthermore, theinsulator region 4 may also extend across the top of the firstconductive region 2 between the first and secondconductive regions conductive region 3/47 increases optical mode overlap compared to either horizontal or lateral MOSCAP phase adjusters. - In an example fabrication method, illustrated in
FIGS. 2A to 2F , the initial step, illustrated inFIG. 2A , includes providing asubstrate 5, which may be comprised of a dielectric material, e.g. silicon dioxide, with awaveguide device layer 21, e.g. a semiconductor material, such as silicon, thereon. Thedevice layer 21 may be the thickness of the firstconductive region 2 or larger. If thedevice layer 21 is larger than the firstconductive region 2, then an initial etch or polishing step is required. Ideally, thesubstrate 5 anddevice layer 21 comprise a SOI wafer, as is well known in the art. Ahard mask 22, e.g. silicon nitride, may be positioned over a portion of thesemiconductor layer 21 to define the firstconductive region 2.FIG. 2B illustrates a multi-step etching process, in which one section of thelayer 21 is partially etched, e.g. about half the height or about 100 nm to 125 nm, to form thefirst contact region 6, and another section of thedevice layer 21, on the opposite side of the firstconductive region 2 is fully etched down to thesubstrate 5 to form the firstconductive region 2, and to provide an opening on thesubstrate 5 to make room for the secondconductive region 3. - If some or all of the
hard mask 22 remains, a hard mask removal step may be conducted before the remaining structure, i.e. the firstconductive region 2 and thefirst contact region 6, is then subject to an oxidation step,FIG. 2C , to form theinsulator region 4 on the side of the firstconductive region 2. A pad oxide layer may be applied to those areas of the firstconductive region 2, e.g. top, and o2Dpposite side, and thefirst contact region 6, e.g. top and opposite side, to prevent oxide from developing thereon. Alternatively, the superfluous oxide may be removed, e.g. polished, after the oxidation step. -
FIG. 2D illustrates a deposition step for a second semiconductor, metal or metal-like material 23, e.g. poly-silicon, on thesubstrate 5 and adjacent to theinsulator region 4. Thematerial 23 may then be subject to a masking step to define the secondconductive region 3 and thesecond contact region 8, and then an etching step to form the secondconductive region 3 and thesecond contact region 8. (FIG. 2E ). Finally, as illustrated inFIG. 2F , the various elements, i.e. the firstconductive region 2, the secondconductive region 3, thefirst contact region 6 and thesecond contact region 8 are subject to doping to diffuse the desired amounts of dopants, as hereinbefore discussed. -
FIGS. 3A to 3E illustrate a preferred embodiment for the deposition, masking and etching steps for the secondconductive region 3 and thesecond contact region 8, as hereinbefore illustrated with reference toFIGS. 2D and 2E . In the deposition step,FIG. 3A , thematerial 23 is deposited over the entire remaining structure, i.e. the opening on thesubstrate 5, the firstconductive region 2, and thefirst contact region 6. The deposition step forms a rounded transition section in thematerial 23, which will become the raisedspacer portion 7, overtop of the secondconductive region 2 as the material 23 transitions between the covering the opening on thesubstrate 5 to the top of the firstconductive region 2. With reference toFIG. 3B , ahard mask 31 is placed over a portion of thematerial 23, including over thesecond contact region 8 and the secondconductive region 3, including the raisedspacer portion 7. - With reference to
FIG. 3C , a first etching step is conducted to remove all of the material 23 over the firstconductive region 2 and thefirst contact region 6. Then amask 32 is deposited over the firstconductive region 2, thefirst contact region 6, and the secondconductive region 3, including the raisedspacer portion 7 to define thesecond contact region 8. A second etching step (FIG. 3E ) is provided to form thesecond contact region 8. Any remnants of themask 32 may then be removed by any suitable means to form the finishedphase adjuster device 1. -
FIGS. 4A to 4E illustrate an alternative embodiment for the deposition, masking and etching steps for the secondconductive region 3 and thesecond contact region 8, as hereinbefore illustrated with reference toFIGS. 2D and 2E for aphase adjuster 41. In the deposition step,FIG. 4A , thematerial 23 is deposited over the entire remaining structure, i.e. the opening on thesubstrate 5, the firstconductive region 2, and thefirst contact region 6. The deposition step forms a rounded transition section in thematerial 23, which will become the raisedspacer portion 7, and anarm 47 extending overtop of, e.g. at least ½ way across, preferably at least ¾ the way across, and ideally completely across the secondconductive region 2 as the material 23 transitions between covering the opening on thesubstrate 5 to the top of the firstconductive region 2. With reference toFIG. 4B , a firsthard mask 42 is placed over a portion of thematerial 23, including over thefirst contact region 2, thesecond contact region 8 and the secondconductive region 3, including the raisedspacer portion 7, only leaving thematerial 23 over thefirst contact region 6 exposed. - With reference to
FIG. 4C , a first etching step is conducted to remove all of the material 23 over thefirst contact region 6, and form an L-shaped secondconductive region 3, including the raisedspacer portion 7 and thearm 47 over the firstconductive region 2 with the insulatinglayer 4 therebetween. Then asecond mask 43 is deposited over the firstconductive region 2, thefirst contact region 6, and the secondconductive region 3, including the raisedspacer portion 7 andarm 47 to define thesecond contact region 8. A second etching step (FIG. 4E ) is provided to form thesecond contact region 8. Any remnants of themask 42 may then be removed by any suitable means to form the finishedphase adjuster device 41. The L-shaped secondconductive region 3/47 increases optical mode overlap for either a horizontal or a lateral MOSCAP phase adjuster. - For the
phase adjuster device 41, the doping steps for the firstconductive region 2 and thefirst contact region 6 may be executed prior to thematerial 23 being deposited. - The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
Claims (11)
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US16/196,947 US10642077B1 (en) | 2018-11-20 | 2018-11-20 | Lateral MOSCAP phase adjuster |
US16/838,112 US20200233242A1 (en) | 2018-11-20 | 2020-04-02 | Lateral moscap phase adjuster |
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US16/196,947 US10642077B1 (en) | 2018-11-20 | 2018-11-20 | Lateral MOSCAP phase adjuster |
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US16/838,112 Continuation US20200233242A1 (en) | 2018-11-20 | 2020-04-02 | Lateral moscap phase adjuster |
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US16/838,112 Abandoned US20200233242A1 (en) | 2018-11-20 | 2020-04-02 | Lateral moscap phase adjuster |
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US10852570B1 (en) * | 2019-10-16 | 2020-12-01 | Inphi Corporation | Dual-slab-layer low-loss silicon optical modulator |
US20220276512A1 (en) * | 2019-08-26 | 2022-09-01 | Rockley Photonics Limited | Optical modulator and method of fabricating an optical modulator |
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TW232751B (en) * | 1992-10-09 | 1994-10-21 | Semiconductor Energy Res Co Ltd | Semiconductor device and method for forming the same |
TW405155B (en) * | 1997-07-15 | 2000-09-11 | Toshiba Corp | Semiconductor device and its manufacture |
CN101842736A (en) * | 2007-08-08 | 2010-09-22 | 新加坡科技研究局 | An electro-optic device and a method for manufacturing the same |
US7657130B2 (en) | 2007-10-19 | 2010-02-02 | Lightwire, Inc. | Silicon-based optical modulator for analog applications |
US8149493B2 (en) * | 2008-09-06 | 2012-04-03 | Sifotonics Technologies (Usa) Inc. | Electro-optic silicon modulator |
US7747122B2 (en) * | 2008-09-30 | 2010-06-29 | Intel Corporation | Method and apparatus for high speed silicon optical modulation using PN diode |
US8737772B2 (en) * | 2010-02-19 | 2014-05-27 | Kotura, Inc. | Reducing optical loss in an optical modulator using depletion region |
US9684194B2 (en) * | 2012-08-14 | 2017-06-20 | University Of Southampton | Method for making electro-optical device |
US9329415B2 (en) * | 2012-11-05 | 2016-05-03 | Agency For Science, Technology And Research | Method for forming an optical modulator |
US9766484B2 (en) | 2014-01-24 | 2017-09-19 | Cisco Technology, Inc. | Electro-optical modulator using waveguides with overlapping ridges |
CN107533248A (en) * | 2015-03-05 | 2018-01-02 | 洛克利光子有限公司 | waveguide modulator structure |
US9891450B2 (en) * | 2015-09-16 | 2018-02-13 | Stmicroelectronics (Crolles 2) Sas | Integrated electro-optic modulator |
-
2018
- 2018-11-20 US US16/196,947 patent/US10642077B1/en active Active
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US20220276512A1 (en) * | 2019-08-26 | 2022-09-01 | Rockley Photonics Limited | Optical modulator and method of fabricating an optical modulator |
US10852570B1 (en) * | 2019-10-16 | 2020-12-01 | Inphi Corporation | Dual-slab-layer low-loss silicon optical modulator |
US11500229B2 (en) * | 2019-10-16 | 2022-11-15 | Marvell Asia Pte Ltd. | Dual-slab-layer low-loss silicon optical modulator |
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