US20200119165A1 - Fin field-effect transistors and methods of forming the same - Google Patents
Fin field-effect transistors and methods of forming the same Download PDFInfo
- Publication number
- US20200119165A1 US20200119165A1 US16/713,355 US201916713355A US2020119165A1 US 20200119165 A1 US20200119165 A1 US 20200119165A1 US 201916713355 A US201916713355 A US 201916713355A US 2020119165 A1 US2020119165 A1 US 2020119165A1
- Authority
- US
- United States
- Prior art keywords
- spacers
- fin
- source
- substrate
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 144
- 230000005669 field effect Effects 0.000 title claims description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 160
- 230000008569 process Effects 0.000 claims abstract description 103
- 239000000463 material Substances 0.000 claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000002955 isolation Methods 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 14
- 239000000203 mixture Substances 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 6
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- 239000010410 layer Substances 0.000 description 108
- 238000005530 etching Methods 0.000 description 17
- 230000004888 barrier function Effects 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000007493 shaping process Methods 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 239000010936 titanium Substances 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 239000012774 insulation material Substances 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- -1 InAlAs Inorganic materials 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 239000011295 pitch Substances 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000003638 chemical reducing agent Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- 229910017115 AlSb Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910012990 NiSi2 Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910020751 SixGe1-x Inorganic materials 0.000 description 1
- 229910004490 TaAl Inorganic materials 0.000 description 1
- 229910004217 TaSi2 Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- DUMHRFXBHXIRTD-UHFFFAOYSA-N Tantalum carbide Chemical compound [Ta+]#[C-] DUMHRFXBHXIRTD-UHFFFAOYSA-N 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical group [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011417 postcuring Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 239000010948 rhodium Substances 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910021354 zirconium(IV) silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Definitions
- Fin Field-Effect Transistor (FinFET) devices are becoming commonly used in integrated circuits.
- FinFET devices have a three-dimensional structure that comprises a semiconductor fin protruding from a substrate.
- a gate structure configured to control the flow of charge carriers within a conductive channel of the FinFET device, wraps around the semiconductor fin.
- the gate structure wraps around three sides of the semiconductor fin, thereby forming conductive channels on three sides of the semiconductor fin.
- FIG. 1 illustrates a perspective view of a Fin Field-Effect Transistor (FinFET), in accordance with some embodiments.
- FinFET Fin Field-Effect Transistor
- FIGS. 2-5, 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9-14, 15A, and 15B illustrate various views of a FinFET device at various stages of fabrication, in accordance with some embodiments.
- FIG. 16 illustrates a flow chart of a method for forming a semiconductor device, in some embodiments.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Embodiments of the present disclosure are discussed in the context of forming a FinFET device, and in particular, in the context of forming the epitaxial source/drain regions of a multiple-fin FinFET device.
- a pre-bake process is performed prior to epitaxially growing the source/drain material to reshape the spacers on opposing sides of each of the fins.
- the pre-bake process curves the inner sidewalls of the spacers to facilitate horizontal growth of the epitaxial source/drain material, and therefore, results in merged source/drain regions with increased volume over the multiple fins.
- the increased volume of the merge source/drain regions allows for reliable connection with source/drain contact plugs formed subsequently, lower contact resistance, and reduces the possibility of etch through of the source/drain region during formation of the source/drain contact plugs, in some embodiments.
- FIG. 1 illustrates an example of a FinFET 30 in a perspective view.
- the FinFET 30 includes a substrate 50 having a fin 64 .
- the fin 64 protrudes above neighboring isolation regions 62 disposed on opposing sides of the fin 64 .
- a gate dielectric 66 is along sidewalls and over a top surface of the fin 64
- a gate 68 is over the gate dielectric 66 .
- Source/drain regions 80 are in the fin 64 on opposite sides of the gate dielectric 66 and gate 68 .
- FIG. 1 further illustrates reference cross-sections that are used in later figures.
- Cross-section B-B extends along a longitudinal axis of the gate 68 of the FinFET 30 .
- Cross-section A-A is perpendicular to cross-section B-B and is along a longitudinal axis of the fin 64 and in a direction of, for example, a current flow between the source/drain regions 80 .
- Cross-section C-C is parallel to cross-section B-B and is across the source/drain region 80 . Subsequent figures refer to these reference cross-sections for clarity.
- FIGS. 2-5, 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9-14, 15A, and 15B illustrate various views of a FinFET device 100 at various stages of fabrication, in accordance with some embodiments.
- the FinFET device 100 is similar to the FinFET 30 in FIG. 1 , except for multiple fins.
- FIGS. 2-5 illustrate cross-section views of the FinFET device 100 along cross-section B-B.
- FIGS. 6A and 6B illustrate cross-sectional views of the FinFET device 100 along cross-sections A-A and C-C, respectively.
- FIG. 7A illustrates cross-sectional view of the FinFET device 100 along cross-sections C-C, and FIGS.
- FIGS. 7B and 7C illustrate zoomed-in views of the spacers of the FinFET device 100 in FIG. 7A in various embodiments.
- FIGS. 8A and 8B illustrate cross-sectional views of the FinFET device 100 along cross-sections C-C and A-A, respectively.
- FIGS. 9-14 and 15A illustrate cross-sectional views of the FinFET device 100 along cross-section A-A
- FIG. 15B illustrates cross-sectional view of the FinFET device 100 along cross-section C-C.
- FIG. 2 illustrates a cross-sectional view of the substrate 50 .
- the substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped.
- the substrate 50 may be a wafer, such as a silicon wafer.
- an SOI substrate includes a layer of a semiconductor material formed on an insulator layer.
- the insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like.
- the insulator layer is provided on a substrate, typically a silicon or glass substrate.
- the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.
- the substrate 50 shown in FIG. 2 is patterned using, for example, photolithography and etching techniques.
- a mask layer such as a pad oxide layer 52 and an overlying pad nitride layer 56 , is formed over the substrate 50 .
- the pad oxide layer 52 may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process.
- the pad oxide layer 52 may act as an adhesion layer between the substrate 50 and the overlying pad nitride layer 56 .
- the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof, and may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), as examples.
- LPCVD low-pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- the mask layer may be patterned using photolithography techniques.
- photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching.
- the photoresist material is used to pattern the pad oxide layer 52 and pad nitride layer 56 to form a patterned mask 58 , as illustrated in FIG. 3 .
- the patterned mask 58 is subsequently used to pattern exposed portions of the substrate 50 to form trenches 61 , thereby defining semiconductor fins 64 (e.g., fin 64 A and fin 64 B) between adjacent trenches 61 as illustrated in FIG. 3 .
- the semiconductor fins 64 are formed by etching trenches in the substrate 50 using, for example, reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic.
- the trenches 61 may be strips (viewed from the top) parallel to each other, and closely spaced with respect to each other.
- the trenches 61 may be continuous and surround the semiconductor fins 64 . Although two fins 64 are illustrated in FIG. 3 and subsequent drawings, more or less than two fins may be formed for the FinFET device 100 .
- the fins 64 may be patterned by any suitable method.
- the fins may 64 be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes.
- double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
- a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins.
- FIG. 4 illustrates the formation of an insulation material between neighboring semiconductor fins 64 to form isolation regions 62 .
- the insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof.
- HDP-CVD high density plasma chemical vapor deposition
- FCVD flowable CVD
- the insulation material is silicon oxide formed by a FCVD process.
- An anneal process may be performed once the insulation material is formed.
- a planarization process such as a chemical mechanical polish (CMP) may remove any excess insulation material and form top surfaces of the isolation regions 62 and top surfaces of the semiconductor fins 64 that are coplanar (not shown).
- CMP chemical mechanical polish
- the patterned mask 58 may also be removed by the planarization process.
- the isolation regions 62 include a liner, e.g., a liner oxide (not shown), at the interface between the isolation region 62 and the substrate 50 /semiconductor fins 64 .
- the liner oxide is formed to reduce crystalline defects at the interface between the substrate 50 and the isolation region 62 .
- the liner oxide may also be used to reduce crystalline defects at the interface between the semiconductor fins 64 and the isolation region 62 .
- the liner oxide (e.g., silicon oxide) may be a thermal oxide formed through a thermal oxidation of a surface layer of substrate 50 , although other suitable method may also be used to form the liner oxide.
- the isolation regions 62 are recessed to form shallow trench isolation (STI) regions 62 .
- the isolation regions 62 are recessed such that the upper portions of the semiconductor fins 64 protrude from between neighboring STI regions 62 .
- the top surfaces of the STI regions 62 may have a flat surface (as illustrated), a convex surface, a concave surface (such as dishing), or a combination thereof.
- the top surfaces of the STI regions 62 may be formed flat, convex, and/or concave by an appropriate etch.
- the isolation regions 62 may be recessed using an acceptable etching process, such as one that is selective to the material of the isolation regions 62 . For example, a chemical oxide removal using a CERTAS® etch or an Applied Materials SICONI tool or dilute hydrofluoric (dHF) acid may be used.
- FIGS. 2 through 4 illustrate an embodiment of forming fins 64 , but fins may be formed in various different processes.
- a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins.
- heteroepitaxial structures can be used for the fins.
- the semiconductor fins can be recessed, and a material different from the semiconductor fins may be epitaxially grown in their place.
- a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the substrate; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form fins.
- the grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material in an NMOS region different from the material in a PMOS region.
- the fins may comprise silicon germanium (Si x Ge 1-x , where x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like.
- the available materials for forming III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.
- FIG. 5 illustrates the formation of dummy gate structure 75 over the semiconductor fins 64 .
- Dummy gate structure 75 includes gate dielectric 66 and gate 68 , in some embodiments.
- a mask 70 may be formed over the dummy gate structure 75 .
- a dielectric layer is formed on the semiconductor fins 64 .
- the dielectric layer may be, for example, silicon oxide, silicon nitride, multilayers thereof, or the like, and may be deposited or thermally grown according to acceptable techniques.
- a gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer.
- the gate layer may be deposited over the dielectric layer and then planarized, such as by a CMP.
- the mask layer may be deposited over the gate layer.
- the gate layer may be formed of, for example, polysilicon, although other materials may also be used.
- the mask layer may be formed of, for example, silicon nitride or the like.
- the mask layer may be patterned using acceptable photolithography and etching techniques to form mask 70 .
- the pattern of the mask 70 then may be transferred to the gate layer and the dielectric layer by an acceptable etching technique to form gate 68 and gate dielectric 66 , respectively.
- the gate 68 and the gate dielectric 66 cover respective channel regions of the semiconductor fins 64 .
- the gate 68 may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective semiconductor fins 64 .
- FIG. 6A illustrates the cross-section view of further processing of the FinFET device 100 along cross-section A-A (e.g., along a longitudinal axis of the fin 64 )
- FIG. 6B illustrates the cross-section view of the FinFET device 100 shown in FIG. 6A , but along cross-section C-C.
- lightly doped drain (LDD) regions 65 are formed in the fins 64 .
- the LDD regions 65 may be formed by a plasma doping process.
- the plasma doping process may implant N-type or P-type impurities in the fins 64 to form the LDD regions 65 .
- P-type impurities such as boron
- N-type impurities such as phosphorus
- the LDD regions 65 abut the channel region of the FinFET device 100 .
- Portions of the LDD regions 65 may extend under gate 68 and into the channel region of the FinFET device 100 .
- FIG. 6A illustrates a non-limiting example of the LDD regions 65 .
- Other configurations, shapes, and formation methods of the LDD regions 65 are also possible and are fully intended to be included within the scope of the present disclosure.
- LDD regions 65 may be formed after gate spacers 87 are formed.
- gate spacers 87 are formed on the dummy gate structure 75 .
- the gate spacers 87 may be formed of a suitable material such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof, and may be formed using, e.g., a thermal oxidation, CVD, or other suitable deposition process.
- the gate spacers 87 are formed by blanket depositing a nitride layer over the FinFET device 100 , then performing a suitable etching process, such as an anisotropic etch, to remove the nitride layer from the upper surface of the dummy gate structure 75 and from the upper surface of the fins 64 . Portions of the nitride layer along sidewalls of the dummy gate structure 75 remain to form the gate spacers 87 , in some embodiments. Portions of the nitride layer along sidewalls of the fins 64 may also remain to form fin spacer 86 (see FIG. 6B ). In the discussion below, the fin spacers 86 may also be referred to as spacers.
- FIG. 6B illustrates the FinFET device 100 along cross-section C-C.
- spacers 86 are formed over the STI regions 62 and on opposing sidewalls of the fins 64 A and 64 B. Note that since the LDD regions 65 are doped regions of the fins 64 in the illustrated embodiments, the description herein may consider the LDD regions 65 as part of the fins 64 .
- a height H 1 of the spacers 86 is in a range from about 5 nm to about 30 nm
- a width W 1 of the spacer 86 measured at an upper surface 86 U of the spacers 86 is in a range from about 2 nm to about 5 nm
- a width W 2 of the spacers 86 measured at an upper surface 62 U of the STI regions 62 is in a range from about 2 nm to about 8 nm, although other dimensions are also possible.
- the fins 64 are recessed by a suitable process, such as an etching process.
- a suitable process such as an etching process.
- an etchant with an etching selectivity to the material of the fins 64 may be used to selectively remove top portions of the fin 64 (e.g., top portions of the LDD regions 65 ).
- a patterned mask layer (e.g., photoresist, not shown) may be formed over the FinFET device 100 to expose portions of the fins 64 on opposing sides of the gate structure, then an etching processing (e.g., an anisotropic etch) may be performed to remove top portions of the fins 64 .
- the patterned mask layer may then be removed by, e.g., an ashing process or an etching process.
- an upper surface 65 U of the fins 64 (e.g., a top surface of the LDD regions 65 ) is below an upper surface 86 U of the spacers 86 .
- the upper surface 65 U of the remaining portions of the LDD regions 65 is substantially level with an upper surface 62 U of the STI regions 62 .
- the upper surface of the remaining portions of the LDD regions 65 is above (see 65 U′) or below (see 65 U′′) the upper surface 62 U of the STI regions 62 , as illustrated in phantom in FIG. 7A .
- a depth H R of the recess is in a range from about 30 nm to about 65 nm.
- a cleaning process is performed after the recessing process to remove oxide from the fins 64 before a subsequent epitaxial growth process to form source/drain regions, in some embodiments.
- the cleaning process may be performed using a suitable etchant, such as hydrofluoric (HF) acid.
- the spacers 86 are treated with a baking process.
- the baking process removes byproducts or residues, such as chloride (Cl), fluoride (F), and/or carbon (C), that are left by the preceding processes (e.g., etching and/or cleaning processes), in some embodiments.
- the baking process also removes oxide (e.g., silicon oxide) that is over, e.g., the fins 64 in preparation for a subsequent epitaxial source/drain material growth process, in some embodiments.
- the baking process is performed using a gas comprising molecular hydrogen (e.g., H 2 ).
- the gas used in the baking process (may also be referred to as a baking gas) comprises a mixture of H 2 and one or more reactant gas(es).
- a mixture of H 2 and HCl, or a mixture of H 2 , HCl and GeH 4 may be used as the baking gas in the baking process.
- the HCl and/or GeH4 in the baking gas may help to clean the surface of, e.g., the fins 64 by etching a small amount of, e.g., silicon.
- the baking process is performed in a processing chamber with the baking gas being supplied into the processing chamber.
- Carrier gases such as nitrogen, argon, helium, or the like, may be used to carry the baking gas into the processing chamber.
- the baking process may be performed at a temperature in a range from about 650° C. to about 750° C., such as 680° C.
- a pressure in the processing chamber may be in a range from about 10 torr to about 80 torr.
- the baking process may be performed for a pre-determined duration, such as between about 10 seconds and about 90 seconds. In an exemplary embodiment, the baking process is performed for a duration between about 30 seconds and about 90 seconds.
- a flow rate of H 2 is in a range between about 3000 standard cubic centimeters per minute (sccm) and about 10000 sccm
- a flow rate of HCl is in a range between about 50 sccm and about 500 sccm.
- a flow rate of H 2 is in a range between about 3000 sccm and about 10000 sccm
- a flow rate of HCl is in a range between about 50 sccm and about 500 sccm
- a flow rate of GeH 4 is in a range between about 50 sccm and 200 sccm.
- native oxide such as silicon oxide over the fins 64 may be reduced to, e.g., silicon, by the reducing agent (e.g., H 2 ), and the byproduct(s) of the reduction process, such as water, is evaporated by the baking process and evacuated from the processing chamber.
- the reducing agent e.g., H 2
- Byproducts from previous process steps, such as carbon, may also be removed by the baking process.
- a chemical equation describing the chemical reaction to remove the carbon is given below.
- the baking process changes the profile of the spacers 86 , in some embodiments.
- the baking process re-shapes the spacers 86 .
- the inner sidewalls 86 S of the spacers 86 are curved after the baking process.
- the inner sidewalls 86 S, or at least the middle portions of the inner sidewalls 86 S bend outwards and away from a center axis 64 C of the fins 64 , where the center axis 64 C is perpendicular to an upper surface 50 U of the substrate 50 .
- a distance between middle portions of opposing inner sidewalls 86 S increases after the re-shaping due to the baking process.
- a first distance between the inner sidewalls 86 S of respective spacers 86 measured after the baking process at a midpoint between the upper surface 86 U and a lower surface 86 L of the spacers 86 , is larger than a second distance between the inner sidewalls 86 S measured at the midpoint before the baking process.
- FIG. 7B illustrates a zoomed-in view of the spacer 86 shown in FIG. 7A .
- the spacer 86 has a width W 3 at the upper surface 86 U and a width W 5 at the lower surface 86 L. Due to the curved inner sidewall 86 S, the spacer 86 has a minimum width W 4 at point C, which corresponds to a point where the inner sidewall 86 S extends furthest away from line M-N, where the line M-N is a line connecting the uppermost point M of the inner sidewall 86 S and the lowermost point N of the inner sidewall 86 S in FIG. 7B .
- the width W 3 is between about 2 nm and about 5 nm
- the width W 5 is between about 2 nm and 9 nm
- the width W 4 may be between about 2 nm and about 5 nm.
- the height H 2 of the spacer 86 may be between about 5 nm and about 30 nm.
- an angle at between a ray R 1 and a ray R 2 is in a range between about 5 degrees and about 15 degrees, where R 1 is a ray from the uppermost point M of the inner sidewall 86 S to the point C, and R 2 is a ray from the point M toward the lower surface 86 L of the spacer 86 , and where R 2 is perpendicular to the upper surface 50 U (see FIG. 7A ) of the substrate 50 .
- the ray R 2 may or may not overlap with the line M-N.
- the dimensions described above are merely non-limiting examples, other dimensions for the spacer 86 are also possible and are fully intended to be included within the scope of the present disclosure.
- FIG. 7C illustrates another embodiment of the spacer 86 after the baking process.
- the outer sidewall 86 O of the spacer 86 may also be curved due to the baking process.
- the conditions of the baking process such as the temperature, the flow rate of the baking gas, the pressure, and/or the duration of the baking process, are adjusted to achieve a specific profile (e.g., straight or curved) for the outer sidewall 86 O and/or the inner sidewall 86 S of the spacer 86 .
- the amount of re-shaping of the spacer 86 may determine whether the outer sidewall 86 O of the spacer 86 is curved (as illustrated in FIG. 7C ) or substantially straight (as illustrated FIG. 7B ). For example, it is observed that at a high temperature (e.g., >680° C.), the baking process is likely to reshape the spacer 86 such that the outer sidewall 86 O is curved. In addition, the baking process may reduce the width of the spacer 86 at the upper surface 86 U to a width W 6 .
- a high temperature e.g., >680° C.
- the width W 6 of the spacer 86 measured at the upper surface 86 U after the baking process, is smaller than the width W 1 (see FIG. 6B ) of the spacer 86 , measured at the upper surface 86 U before the baking process.
- the curved inner sidewall 86 S extends furthest from line M-N at point C, where line M-N is a line connecting the uppermost point M of the inner sidewall 86 S and the lowermost point N of the inner sidewall 86 S.
- a width of the spacer 86 measured at the point C is W 7
- a width of the spacer measured at the lower surface is W 8 .
- W 6 is smaller than W 7
- W 7 is smaller than W 8 .
- an angle ⁇ between a ray R 1 and a ray R 2 is in a range between about 5 degrees and about 15 degrees, where R 1 is a ray from the uppermost point M of the inner sidewall 86 S to the point C, and R 2 is a ray from the point M toward the lower surface 86 L of the spacer 86 , and where R 2 is perpendicular to the upper surface 50 U (see FIG. 7A ) of the substrate 50 .
- the ray R 2 may or may not overlap with the line M-N.
- the width W 6 is between about 2 nm and about 5 nm
- the width W 8 is between about 2 nm and 10 nm
- the width W 7 may be between about 2 nm and about 7 nm
- the height H 3 of the spacer 86 may be between about 5 nm and about 30 nm.
- the curved inner sidewalls 86 S, and/or the narrower width W 6 (if formed) at the upper surface of the spacer 86 facilitate horizontal growth of the epitaxial source/drain regions 80 (see FIG. 8A ) in subsequent processing, and therefore, results in merged source/drain regions 80 with increased volumes over the multiple fins 64 . More details are discussed hereinafter with reference to FIG. 8A .
- the increased volume of the merged source/drain regions 80 allows for reliable connection with source/drain contact plugs 102 (see FIG. 15B ) formed subsequently, lowers contact resistance, and reduces the possibility of etch through of the source/drain regions 80 during formation of the source/drain contact plugs 102 , in some embodiments.
- source/drain regions 80 are formed by epitaxially growing a material in the recesses between spacers 86 , using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof.
- MOCVD metal-organic CVD
- MBE molecular beam epitaxy
- LPE liquid phase epitaxy
- VPE vapor phase epitaxy
- SEG selective epitaxial growth
- the epitaxial source/drain regions 80 fill the recesses between spacers 86 , and extend over the upper surface 86 U of the spacers 86 .
- the source/drain regions 80 of adjacent fins 64 merge to form a continuous epitaxial source/drain region 80 that connects the multiple fins 64 of the FinFET device 100 .
- the source/drain regions 80 comprise curved lower surfaces 80 L.
- the curved lower surfaces 80 L increase the volume of the source/drain regions 80 .
- the curved lower surfaces 80 L also result in merged source/drain regions 80 with increased thickness (e.g., D 1 and D 2 ).
- a thickness D 2 of the source/drain region 80 measured midway between two adjacent fins 64 , is in a range from about 15 nm to about 35 nm.
- a thickness D 1 of the source/drain region 80 measured along the center axis 64 C (see FIG. 7A ) of the fin 64 and over the spacer 86 , is in a range from about 25 nm to about 45 nm, in some embodiments.
- a fin pitch P may be in a range from about 25 nm to about 85 nm.
- a ratio of D 1 to D 2 is larger than 0.8, e.g., between about 0.8 and 3, and a ratio of D 2 to the fin pitch P, is in a range between about 0.2 and 0.6, in various embodiments.
- the merged source/drain regions 80 comprise slanted upper surfaces (e.g., 80 S) that are substantially planar.
- the slanted planar upper surfaces 80 S may also be referred to as facets of the source/drain regions 80 . Therefore, the merged source/drain regions 80 have curved lower surfaces 80 L and slated planar upper surfaces 80 S, in some embodiments.
- FIG. 8A also illustrates a substantially flat upper surface (e.g., 80 U) between slanted planar upper surfaces 80 S, where the upper surface 80 U is substantially parallel to the upper surface 50 U of the substrate 50 .
- the upper surface 80 U has a curved shape (e.g., a concave curved upper surface, not shown).
- the source/drain regions 80 fill the recesses between respective spacers 86 , the source/drain regions 80 have a width D 5 at the lower surface of the spacers 86 , a width D 4 at the upper surface of the spacers 86 , and a width D 3 between (e.g., midway between) the upper surface and the lower surface of the spacers 86 .
- D 3 is large than D 4 and D 5 .
- D 3 is in a range from about 5 nm to about 30 nm
- D 4 is in a range from about 5 nm to about 25 nm
- D 5 is in a range from about 5 nm to about 25 nm, although other dimension are also possible.
- ray R 1 and ray R 2 form an angle ⁇ between about 90 degrees and about 150 degrees (e.g., 90° ⁇ 150°), where ray R 1 and ray R 2 start at a point where the lower surface 80 L of the source/drain region 80 intersects (e.g., contacts) the spacers 86 , and where ray R 2 is perpendicular to the upper surface 50 U of the substrate 50 , and ray R 1 is tangent to the lower surface 80 L.
- the resulting FinFET device 100 is an n-type FinFET, and source/drain regions 80 of the fins 64 comprise silicon carbide (SiC), silicon phosphorous (SiP), phosphorous-doped silicon carbon (SiCP), or the like.
- the resulting FinFET device 100 is a p-type FinFET, and source/drain regions 80 of the fins 64 comprise SiGe, and a p-type impurity such as boron or indium.
- the epitaxial source/drain regions 80 may be implanted with dopants to form source/drain regions 80 followed by an anneal process.
- the source/drain regions 80 may have an impurity (e.g., dopant) concentration in a range from about 1E19 cm-3 to about 1E21 cm-3.
- P-type impurities such as boron or indium, may be implanted in the source/drain region 80 of a P-type transistor.
- N-type impurities, such as phosphorous or arsenide, may be implanted in the source/drain regions 80 of an N-type transistor.
- the epitaxial source/drain regions may be in situ doped during growth.
- a composition of a lower portion (e.g., a portion of 80 between the upper surface of the STI regions 62 and the upper surface 86 U of the spacers 86 ) of the source/drain region 80 is different from a composition of an upper portion (e.g., a portion of 80 above the upper surface 86 U of the spacers 86 ) of the source/drain region 80 .
- the upper portion of the source/drain region 80 has a higher dopant concentration than that of the lower portion of the source/drain region 80 .
- the concentration of P for the lower portion of the source/drain region 80 may be between about 1E20/cm 3 and about 1E21/cm 3
- the concentration of P for the higher portion of the source/drain region 80 may be between about 1E21/cm 3 and about 5E21/cm 3 .
- the concentration of B for the lower portion of the source/drain region 80 may be between about 1E20/cm 3 and about 5E20/cm 3
- the concentration of B for the upper portion of the source/drain region 80 may be between about 2E20/cm 3 and about 1E21/cm 3
- an atomic percentage of Ge of the source/drain region 80 (e.g., SiGe doped by B) in the lower portion may be between about 15% and about 30%
- an atomic percentage of Ge of the source/drain region 80 in the upper portion may be between about 30% and about 60%.
- a first interlayer dielectric (ILD) 90 is formed over the source/drain regions 80 , the fins 64 , and the dummy gate structures 75 .
- the first ILD 90 is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD.
- a planarization process such as a CMP process, may be performed to remove the mask 70 , and to planarize the top surface of the first ILD 90 such that the top surface of the first ILD 90 is level with the top surface of the gate 68 .
- an embodiment gate-last process (sometimes referred to as replacement gate process) is performed subsequently to replace the gate 68 and the gate dielectric 66 with active gates and active gate dielectric materials. Therefore, the gate 68 and the gate dielectric 66 are considered dummy gate structures in a gate-last process. Details of the embodiment gate-last process are described hereinafter with reference to FIGS. 10-14, 15A and 15B .
- the gate 68 and the gate dielectric 66 directly under the gate 68 are removed in an etching step(s), so that recesses (not shown) are formed between respective gate spacers 87 .
- Each recess exposes a channel region of a respective fin 64 .
- Each channel region is disposed between neighboring pairs of epitaxial source/drain regions 80 .
- the dummy gate dielectric layer 66 may be used as an etch stop layer when the dummy gate 68 is etched. The dummy gate dielectric layer 66 may then be removed after the removal of the dummy gate 68 .
- a gate dielectric layer 96 is formed for replacement gate 97 (see FIG. 11 ).
- the gate dielectric layer 96 is deposited conformally in the recesses, such as on the top surfaces and the sidewalls of the fins 64 and on sidewalls of the gate spacers 87 , and on a top surface of the first ILD 90 .
- the gate dielectric layer 96 comprises silicon oxide, silicon nitride, or multilayers thereof.
- the gate dielectric layer 96 includes a high-k dielectric material, and in these embodiments, the gate dielectric layers 96 may have a k value greater than about 7.0, and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof.
- the formation methods of gate dielectric layer 96 may include MBD, ALD, PECVD, and the like.
- the barrier layer 94 is formed conformally over the gate dielectric layer 96 .
- the barrier layer 94 may comprise an electrically conductive material such as titanium nitride, although other materials, such as tantalum nitride, titanium, tantalum, or the like, may alternatively be utilized.
- the barrier layer 94 may be formed using a CVD process, such as plasma-enhanced CVD (PECVD). However, other alternative processes, such as sputtering or metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), may alternatively be used.
- PECVD plasma-enhanced CVD
- MOCVD metal organic chemical vapor deposition
- ALD atomic layer deposition
- work function layers may be formed in the replacement gate 97 , e.g., over the barrier layer 94 .
- P-type work function layer(s) may be formed for P-type devices
- N-type work function layer(s) may be formed for N-type devices.
- Exemplary P-type work function metals that may be included in the gate structure (e.g., 97 ) include TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , WN, other suitable P-type work function materials, or combinations thereof.
- Exemplary N-type work function metals that may be included in the gate structure include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof.
- a work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage Vt is achieved in the device to be formed.
- the work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), and/or other suitable process.
- the seed layer 92 is formed over the barrier layer 94 (or the work function layers if formed).
- the seed layer 92 may include copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof, and may be deposited by atomic layer deposition (ALD), sputtering, physical vapor deposition (PVD), or the like.
- the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials.
- the seed layer comprises a titanium layer and a copper layer over the titanium layer.
- the gate electrode 98 is deposited over the seed layer 92 , and fills the remaining portions of the recesses.
- the gate electrode 98 may be made of a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multilayers thereof, and may be formed by, e.g., electroplating, electroless plating, or other suitable method.
- a planarization process such as a CMP, may be performed to remove the excess portions of the gate dielectric layer 96 , the barrier layer 94 , the work function layer(s) (if formed), the seed layer 92 , and the material of the gate electrode 98 , which excess portions are over the top surface of first ILD 90 .
- the resulting remaining portions of material of the gate electrode 98 , the seed layer 92 , the work function layer(s) (if formed), the barrier layer 94 , and the gate dielectric layer 96 thus form a replacement gate 97 of the resulting FinFET device 100 .
- a second ILD 95 is deposited over the first ILD 90 .
- the second ILD 95 is a flowable film formed by a flowable CVD method.
- the second ILD 95 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD.
- Contact openings 91 and 93 for contact plugs 102 are formed through the first ILD 90 and/or the second ILD 95 .
- the contact opening 91 is formed through the second ILD 95 and exposes the replacement gate 97
- the contact openings 93 are formed through the first ILD 90 and the second ILD 95 , and exposes source/drain regions 80 .
- contact openings 91 / 93 may be formed to extend into the source/drain regions 80 , as illustrated in FIG. 12 , to ensure good contact between the subsequently formed contact plugs and the source/drain regions 80 .
- a depth of the openings H 4 may be in a range between about 15 nm to about 25 nm, as examples.
- silicide regions 82 are formed over the source/drain regions 80 , and a barrier layer 104 is formed over the silicide regions 82 and the second ILD 95 .
- the silicide regions 82 are formed by depositing, over the source/drain regions 80 , a metal capable of reacting with semiconductor materials (e.g., silicon, germanium) to form silicide or germanide regions.
- the metal may be nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys.
- a thermal anneal process is then performed so that the deposited metal reacts with the source/drain regions 80 to form silicide regions 82 . After the thermal anneal process, the unreacted metal is removed.
- the barrier layer 104 is conformally formed over the silicide regions 82 and the second ILD 95 , and lines sidewalls and bottoms of the contact openings 91 / 93 .
- the barrier layer 104 may comprise an electrically conductive material such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or the like, and may be formed using a CVD process, such as plasma-enhanced CVD (PECVD).
- PECVD plasma-enhanced CVD
- other alternative processes such as sputtering or metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), may also be used.
- a seed layer 109 is formed over the barrier layer 104 , and an electrically conductive material 110 is formed over the seed layer 109 .
- the seed layer 109 may be deposited by PVD, ALD or CVD, and may be formed of tungsten, copper, or copper alloys, although other suitable methods and materials may alternatively be used.
- the conductive material 110 may be formed onto the seed layer 109 to fill the contact openings 91 / 93 .
- the conductive material 110 may comprise tungsten, although other suitable materials such as aluminum, copper, tungsten nitride, rhuthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys of these, combinations thereof, and the like, may alternatively be utilized. Any suitable deposition method, such as PVD, CVD, ALD, plating (e.g., electroplating), and reflow, may be used to form the conductive material 110 .
- FIG. 15B illustrates the FinFET device 100 in FIG. 15A , but along cross-section C-C.
- the contact openings, and hence the contact plugs 102 may extend into the source/drain regions 80 .
- the current disclosed embodiments produces merged source/drain regions 80 with increased thickness, e.g., D 2 (see FIG. 8A ).
- the increased thickness of the merged source/drain regions 80 reduces or eliminates the possibility of over etching (e.g., contact holes 91 / 93 becoming through-holes in the source/drain regions 80 ) in forming the contact openings 91 / 93 .
- FIG. 16 illustrates a flow chart of a method of forming a semiconductor device, in accordance with some embodiments. It should be understood that the embodiment method shown in FIG. 16 is merely an example of many possible embodiment methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as illustrated in FIG. 16 may be added, removed, replaced, rearranged and repeated.
- first spacers are formed on opposing sidewalls of a first fin, where the first fin protrudes above a substrate.
- the first fin is recessed to form a first recess between the first spacers.
- the first spacers are treated using a baking process, where treating the first spacers changes a profile of the first spacers.
- a first semiconductor material is epitaxially grown over a top surface of the first fin.
- Embodiments may achieve advantages.
- the baking process not only removes oxide from the recesses between spacers to facilitate growth of the epitaxial source/drain material, but also re-shapes the spacers to facilitate horizontal growth of the epitaxial source/drain material.
- the merged epitaxial source/drain regions have increased volume and increased thickness, which results in lower contact resistance and more reliable contact with contact plugs formed subsequently.
- the thicker source/drain regions prevents or reduces the possibility of over etching in forming the contact openings, which in turn prevents or reduces the possibility of the contact plugs being formed incorrectly or being formed through the source/drain regions, thereby improving device performance and increasing production yields.
- a method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate; recessing the first fin to form a first recess between the first spacers; treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers; and epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
- the baking process is performed using a gas comprising hydrogen.
- the baking process is performed at a temperature in a range between about 650° C. and about 750° C.
- the baking process is performed in a pressure in a range between about 10 torr and about 80 torr. In an embodiment, the baking process is performed for a duration between about 10 seconds and about 90 seconds.
- treating the first spacers curves inner sidewalls of the first spacers such that a first distance between the inner sidewalls of the first spacers, measured after the treating at a midpoint of the inner sidewalls of the first spacers between an upper surface of the first spacers and a bottom surface of the first spacers, is larger than a second distance between the inner sidewalls of the first spacers measured at the midpoint before the treating.
- treating the first spacers further reduces a width of the first spacers measured at the top surface of the first spacers.
- the baking process reduces an oxide in the first recess using a reducing agent, where the method further comprises performing an oxide removal process after recessing the first fin and before treating the first spacers.
- performing the oxide removal process uses hydrofluoric acid.
- the method further includes forming second spacers on opposing sidewalls of a second fin; recessing the second fin to form a second recess between the second spacers; treating the second spacers using the baking process, where treating the second spacers changes a profile of the second spacers; and epitaxially growing a second semiconductor material over a top surface of the second fin, where the first semiconductor material and the second semiconductor material merge to form a continuous semiconductor region between the first fin and the second fin.
- a lower surface of the continuous semiconductor region is curved, and an upper surface of the continuous semiconductor region is planar.
- a method includes forming first spacers on opposing sidewalls of a first fin; forming second spacers on opposing sidewalls of a second fin; recessing the first fin and the second fin, where the recessing forms a first recess between the first spacers and a second recess between the second spacers; re-shaping the first spacers and the second spacers; and growing an epitaxial material in the first recess and the second recess.
- the re-shaping bends first inner sidewalls of the first spacers and second inner sidewalls of the second spacers, where a distance between middle portions of the first inner sidewalls increases during the re-shaping, and a distance between middle portions of the second inner sidewalls increases during the re-shaping.
- the re-shaping reduces a first width of the first spacers measured at a top surface of the first spacers, where the re-shaping reduces a second width of the second spacers measured at a top surface of the second spacers.
- the re-shaping comprises a baking process.
- the baking process is performed in an environment comprising hydrogen at a temperature between about 650° C. and about 750° C.
- the epitaxial material extends over the first spacers and the second spacers, where the epitaxial material over the first fin and the second fin merge to form a semiconductor region extending continuously from the first fin to the second fin, and where a lower surface of the semiconductor region is curved.
- a Fin Field-Effect Transistor (FinFET) device includes a first fin and a second fin; first spacers on opposing sides of the first fin, where inner sidewalls of the first spacers bend away from a longitudinal axis of the first fin; second spacers on opposing sides of the second fin, where inner sidewalls of the second spacers bend away from a center axis of the second fin; and a semiconductor material between the first spacers and between the second spacers, the semiconductor material extending continuously from the first fin to the second fin.
- the semiconductor material has a curved lower surface.
- the semiconductor material has a slanted planar upper surface.
- a semiconductor device includes a first fin and a second fin protruding above a substrate; and a semiconductor material over the first fin and the second fin, the semiconductor material extending continuously from the first fin to the second fin, the semiconductor material having a curved lower surface and a slanted planar upper surface.
- the semiconductor material further has a substantially flat upper surface between the first fin and the second fin.
- the semiconductor material has a first portion over and contacting the first fin, a second portion over and contacting the first portion, and a third portion over and contacting the second portion, where the second portion has a second width larger than a first width of the first portion, and the third portion has a third width smaller than the second width.
- the semiconductor device further includes first spacers on opposing sides of the first fin, where the first spacers have inner sidewalls that are curved, and where a distance between middle portions of the inner sidewalls of the first spacers is larger than a distance between end portions of the inner sidewalls of the first spacers.
- a method of forming a semiconductor device includes recessing a first fin; recessing a second fin; and growing an epitaxial material over the first fin and over the second fin, where growing the epitaxial material forms a first portion of the epitaxial material over the first fin and over the second fin, forms a second portion of the epitaxial material over the first portion, forms a third portion of the epitaxial material over the second portion, and forms a fourth portion of the epitaxial material over the third portion, where the first portion has a first width smaller than a second width of the second portion, and the third portion has a third width smaller than the second width, and where the third portion comprises two separate regions, and the fourth portion extends continuously from the first fin to the second fin.
- the fourth portion has a curved lower surface.
- the method further includes forming first spacers on opposing sides of the first fin; forming second spacers on opposing sides of the second fin; and curving first inner sidewalls of the first spacers and second inner sidewalls of the second spacers before growing the epitaxial material.
- the curving comprises performing a baking process using a gas comprising molecular hydrogen.
- a method of forming a Fin Field-Effect Transistor (FinFET) device includes forming a plurality of fins; forming spacers along sidewalls of each of the plurality of fins; recessing the plurality of fins; re-shaping the spacers of each of the plurality of fins; and epitaxially growing a semiconductor material over each of the plurality of fins, where the semiconductor material continuously connects the plurality of fins, and where a lower surface of the semiconductor material is curved.
- an upper surface of the semiconductor material is planar.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- This application is a continuation of U.S. patent application Ser. No. 16/511,580, filed on Jul. 15, 2019, which is a continuation of U.S. patent application Ser. No. 15/799,344, filed on Oct. 31, 2017, and entitled “Fin Field-Effect Transistors and Methods of Forming the Same,” now U.S. Pat. No. 10,355,105 issued on Jul. 16, 2019, which applications are incorporated herein by reference.
- The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
- Fin Field-Effect Transistor (FinFET) devices are becoming commonly used in integrated circuits. FinFET devices have a three-dimensional structure that comprises a semiconductor fin protruding from a substrate. A gate structure, configured to control the flow of charge carriers within a conductive channel of the FinFET device, wraps around the semiconductor fin. For example, in a tri-gate FinFET device, the gate structure wraps around three sides of the semiconductor fin, thereby forming conductive channels on three sides of the semiconductor fin.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 illustrates a perspective view of a Fin Field-Effect Transistor (FinFET), in accordance with some embodiments. -
FIGS. 2-5, 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9-14, 15A, and 15B illustrate various views of a FinFET device at various stages of fabrication, in accordance with some embodiments. -
FIG. 16 illustrates a flow chart of a method for forming a semiconductor device, in some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Embodiments of the present disclosure are discussed in the context of forming a FinFET device, and in particular, in the context of forming the epitaxial source/drain regions of a multiple-fin FinFET device. In accordance with some embodiments, prior to epitaxially growing the source/drain material, a pre-bake process is performed to reshape the spacers on opposing sides of each of the fins. In some embodiments, the pre-bake process curves the inner sidewalls of the spacers to facilitate horizontal growth of the epitaxial source/drain material, and therefore, results in merged source/drain regions with increased volume over the multiple fins. The increased volume of the merge source/drain regions allows for reliable connection with source/drain contact plugs formed subsequently, lower contact resistance, and reduces the possibility of etch through of the source/drain region during formation of the source/drain contact plugs, in some embodiments.
-
FIG. 1 illustrates an example of aFinFET 30 in a perspective view. The FinFET 30 includes asubstrate 50 having afin 64. The fin 64 protrudes above neighboringisolation regions 62 disposed on opposing sides of thefin 64. A gate dielectric 66 is along sidewalls and over a top surface of thefin 64, and agate 68 is over the gate dielectric 66. Source/drain regions 80 are in thefin 64 on opposite sides of the gate dielectric 66 andgate 68.FIG. 1 further illustrates reference cross-sections that are used in later figures. Cross-section B-B extends along a longitudinal axis of thegate 68 of the FinFET 30. Cross-section A-A is perpendicular to cross-section B-B and is along a longitudinal axis of thefin 64 and in a direction of, for example, a current flow between the source/drain regions 80. Cross-section C-C is parallel to cross-section B-B and is across the source/drain region 80. Subsequent figures refer to these reference cross-sections for clarity. -
FIGS. 2-5, 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9-14, 15A, and 15B illustrate various views of aFinFET device 100 at various stages of fabrication, in accordance with some embodiments. TheFinFET device 100 is similar to the FinFET 30 inFIG. 1 , except for multiple fins.FIGS. 2-5 illustrate cross-section views of theFinFET device 100 along cross-section B-B.FIGS. 6A and 6B illustrate cross-sectional views of theFinFET device 100 along cross-sections A-A and C-C, respectively.FIG. 7A illustrates cross-sectional view of theFinFET device 100 along cross-sections C-C, andFIGS. 7B and 7C illustrate zoomed-in views of the spacers of theFinFET device 100 inFIG. 7A in various embodiments.FIGS. 8A and 8B illustrate cross-sectional views of theFinFET device 100 along cross-sections C-C and A-A, respectively.FIGS. 9-14 and 15A illustrate cross-sectional views of theFinFET device 100 along cross-section A-A, andFIG. 15B illustrates cross-sectional view of theFinFET device 100 along cross-section C-C. -
FIG. 2 illustrates a cross-sectional view of thesubstrate 50. Thesubstrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Thesubstrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of thesubstrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. - Referring to
FIG. 3 , thesubstrate 50 shown inFIG. 2 is patterned using, for example, photolithography and etching techniques. For example, a mask layer, such as apad oxide layer 52 and an overlyingpad nitride layer 56, is formed over thesubstrate 50. Thepad oxide layer 52 may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. Thepad oxide layer 52 may act as an adhesion layer between thesubstrate 50 and the overlyingpad nitride layer 56. In some embodiments, thepad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof, and may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), as examples. - The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. In this example, the photoresist material is used to pattern the
pad oxide layer 52 andpad nitride layer 56 to form a patternedmask 58, as illustrated inFIG. 3 . - The patterned
mask 58 is subsequently used to pattern exposed portions of thesubstrate 50 to formtrenches 61, thereby defining semiconductor fins 64 (e.g.,fin 64A andfin 64B) betweenadjacent trenches 61 as illustrated inFIG. 3 . In some embodiments, thesemiconductor fins 64 are formed by etching trenches in thesubstrate 50 using, for example, reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic. In some embodiments, thetrenches 61 may be strips (viewed from the top) parallel to each other, and closely spaced with respect to each other. In some embodiments, thetrenches 61 may be continuous and surround thesemiconductor fins 64. Although twofins 64 are illustrated inFIG. 3 and subsequent drawings, more or less than two fins may be formed for theFinFET device 100. - The
fins 64 may be patterned by any suitable method. For example, the fins may 64 be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins. -
FIG. 4 illustrates the formation of an insulation material between neighboringsemiconductor fins 64 to formisolation regions 62. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulation materials and/or other formation processes may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. A planarization process, such as a chemical mechanical polish (CMP), may remove any excess insulation material and form top surfaces of theisolation regions 62 and top surfaces of thesemiconductor fins 64 that are coplanar (not shown). The patterned mask 58 (seeFIG. 3 ) may also be removed by the planarization process. - In some embodiments, the
isolation regions 62 include a liner, e.g., a liner oxide (not shown), at the interface between theisolation region 62 and thesubstrate 50/semiconductor fins 64. In some embodiments, the liner oxide is formed to reduce crystalline defects at the interface between thesubstrate 50 and theisolation region 62. Similarly, the liner oxide may also be used to reduce crystalline defects at the interface between thesemiconductor fins 64 and theisolation region 62. The liner oxide (e.g., silicon oxide) may be a thermal oxide formed through a thermal oxidation of a surface layer ofsubstrate 50, although other suitable method may also be used to form the liner oxide. - Next, the
isolation regions 62 are recessed to form shallow trench isolation (STI)regions 62. Theisolation regions 62 are recessed such that the upper portions of thesemiconductor fins 64 protrude from between neighboringSTI regions 62. The top surfaces of theSTI regions 62 may have a flat surface (as illustrated), a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of theSTI regions 62 may be formed flat, convex, and/or concave by an appropriate etch. Theisolation regions 62 may be recessed using an acceptable etching process, such as one that is selective to the material of theisolation regions 62. For example, a chemical oxide removal using a CERTAS® etch or an Applied Materials SICONI tool or dilute hydrofluoric (dHF) acid may be used. -
FIGS. 2 through 4 illustrate an embodiment of formingfins 64, but fins may be formed in various different processes. In one example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. In another example, heteroepitaxial structures can be used for the fins. For example, the semiconductor fins can be recessed, and a material different from the semiconductor fins may be epitaxially grown in their place. - In an even further example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the substrate; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form fins.
- In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material in an NMOS region different from the material in a PMOS region. In various embodiments, the fins may comprise silicon germanium (SixGe1-x, where x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.
-
FIG. 5 illustrates the formation ofdummy gate structure 75 over thesemiconductor fins 64.Dummy gate structure 75 includesgate dielectric 66 andgate 68, in some embodiments. Amask 70 may be formed over thedummy gate structure 75. To form thedummy gate structure 75, a dielectric layer is formed on thesemiconductor fins 64. The dielectric layer may be, for example, silicon oxide, silicon nitride, multilayers thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. - A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, such as by a CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed of, for example, polysilicon, although other materials may also be used. The mask layer may be formed of, for example, silicon nitride or the like.
- After the layers (e.g., the dielectric layer, the gate layer, and the mask layer) are formed, the mask layer may be patterned using acceptable photolithography and etching techniques to form
mask 70. The pattern of themask 70 then may be transferred to the gate layer and the dielectric layer by an acceptable etching technique to formgate 68 andgate dielectric 66, respectively. Thegate 68 and thegate dielectric 66 cover respective channel regions of thesemiconductor fins 64. Thegate 68 may also have a lengthwise direction substantially perpendicular to the lengthwise direction ofrespective semiconductor fins 64. -
FIG. 6A illustrates the cross-section view of further processing of theFinFET device 100 along cross-section A-A (e.g., along a longitudinal axis of the fin 64),FIG. 6B illustrates the cross-section view of theFinFET device 100 shown inFIG. 6A , but along cross-section C-C. - As illustrated in
FIG. 6A , lightly doped drain (LDD)regions 65 are formed in thefins 64. TheLDD regions 65 may be formed by a plasma doping process. The plasma doping process may implant N-type or P-type impurities in thefins 64 to form theLDD regions 65. For example, P-type impurities, such as boron, may be implanted in thefins 64 to form theLDD regions 65 for a P-type device, and N-type impurities, such as phosphorus, may be implanted in thefins 64 to form theLDD regions 65 for an N-type device. In some embodiments, theLDD regions 65 abut the channel region of theFinFET device 100. Portions of theLDD regions 65 may extend undergate 68 and into the channel region of theFinFET device 100.FIG. 6A illustrates a non-limiting example of theLDD regions 65. Other configurations, shapes, and formation methods of theLDD regions 65 are also possible and are fully intended to be included within the scope of the present disclosure. For example,LDD regions 65 may be formed aftergate spacers 87 are formed. - Still referring to
FIG. 6A , after theLDD regions 65 are formed,gate spacers 87 are formed on thedummy gate structure 75. The gate spacers 87 may be formed of a suitable material such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof, and may be formed using, e.g., a thermal oxidation, CVD, or other suitable deposition process. In some embodiments, thegate spacers 87 are formed by blanket depositing a nitride layer over theFinFET device 100, then performing a suitable etching process, such as an anisotropic etch, to remove the nitride layer from the upper surface of thedummy gate structure 75 and from the upper surface of thefins 64. Portions of the nitride layer along sidewalls of thedummy gate structure 75 remain to form thegate spacers 87, in some embodiments. Portions of the nitride layer along sidewalls of thefins 64 may also remain to form fin spacer 86 (seeFIG. 6B ). In the discussion below, thefin spacers 86 may also be referred to as spacers. -
FIG. 6B illustrates theFinFET device 100 along cross-section C-C. As illustrated inFIG. 6B , spacers 86 are formed over theSTI regions 62 and on opposing sidewalls of thefins LDD regions 65 are doped regions of thefins 64 in the illustrated embodiments, the description herein may consider theLDD regions 65 as part of thefins 64. In some embodiments, a height H1 of thespacers 86 is in a range from about 5 nm to about 30 nm, a width W1 of thespacer 86 measured at anupper surface 86U of thespacers 86 is in a range from about 2 nm to about 5 nm, and a width W2 of thespacers 86 measured at anupper surface 62U of theSTI regions 62 is in a range from about 2 nm to about 8 nm, although other dimensions are also possible. - Referring now to
FIG. 7A , which illustrates theFinFET device 100 along cross-section C-C, the fins 64 (e.g., theLDD regions 65 of the fins 64) are recessed by a suitable process, such as an etching process. For example, an etchant with an etching selectivity to the material of the fins 64 (e.g., the LDD regions 65) may be used to selectively remove top portions of the fin 64 (e.g., top portions of the LDD regions 65). As another example, a patterned mask layer (e.g., photoresist, not shown) may be formed over theFinFET device 100 to expose portions of thefins 64 on opposing sides of the gate structure, then an etching processing (e.g., an anisotropic etch) may be performed to remove top portions of thefins 64. The patterned mask layer may then be removed by, e.g., an ashing process or an etching process. - After the recessing process, an
upper surface 65U of the fins 64 (e.g., a top surface of the LDD regions 65) is below anupper surface 86U of thespacers 86. In the example ofFIG. 7A , theupper surface 65U of the remaining portions of theLDD regions 65 is substantially level with anupper surface 62U of theSTI regions 62. In other embodiments, the upper surface of the remaining portions of theLDD regions 65 is above (see 65U′) or below (see 65U″) theupper surface 62U of theSTI regions 62, as illustrated in phantom inFIG. 7A . As a result of the recessing process, recesses (or openings) are formed between respective spacers 86 (e.g., spacers on opposing sidewalls of a fin 64). A depth HR of the recess, measured between theupper surface 86U of thespacers 86 and theupper surface 65U of the remaining portions of theLDD regions 65, is in a range from about 30 nm to about 65 nm. - A cleaning process is performed after the recessing process to remove oxide from the
fins 64 before a subsequent epitaxial growth process to form source/drain regions, in some embodiments. The cleaning process may be performed using a suitable etchant, such as hydrofluoric (HF) acid. - Next, the
spacers 86 are treated with a baking process. The baking process removes byproducts or residues, such as chloride (Cl), fluoride (F), and/or carbon (C), that are left by the preceding processes (e.g., etching and/or cleaning processes), in some embodiments. The baking process also removes oxide (e.g., silicon oxide) that is over, e.g., thefins 64 in preparation for a subsequent epitaxial source/drain material growth process, in some embodiments. - For example, in accordance with some embodiments, the baking process is performed using a gas comprising molecular hydrogen (e.g., H2). In some embodiments, the gas used in the baking process (may also be referred to as a baking gas) comprises a mixture of H2 and one or more reactant gas(es). For example, a mixture of H2 and HCl, or a mixture of H2, HCl and GeH4, may be used as the baking gas in the baking process. The HCl and/or GeH4 in the baking gas may help to clean the surface of, e.g., the
fins 64 by etching a small amount of, e.g., silicon. In some embodiments, the baking process is performed in a processing chamber with the baking gas being supplied into the processing chamber. Carrier gases, such as nitrogen, argon, helium, or the like, may be used to carry the baking gas into the processing chamber. The baking process may be performed at a temperature in a range from about 650° C. to about 750° C., such as 680° C. A pressure in the processing chamber may be in a range from about 10 torr to about 80 torr. The baking process may be performed for a pre-determined duration, such as between about 10 seconds and about 90 seconds. In an exemplary embodiment, the baking process is performed for a duration between about 30 seconds and about 90 seconds. In embodiments where the baking gas comprises a mixture of H2 and HCl, a flow rate of H2 is in a range between about 3000 standard cubic centimeters per minute (sccm) and about 10000 sccm, and a flow rate of HCl is in a range between about 50 sccm and about 500 sccm. In embodiments where the baking gas comprises a mixture of H2, HCl and GeH4, a flow rate of H2 is in a range between about 3000 sccm and about 10000 sccm, a flow rate of HCl is in a range between about 50 sccm and about 500 sccm, and a flow rate of GeH4 is in a range between about 50 sccm and 200 sccm. - In accordance with some embodiments, native oxide such as silicon oxide over the
fins 64 may be reduced to, e.g., silicon, by the reducing agent (e.g., H2), and the byproduct(s) of the reduction process, such as water, is evaporated by the baking process and evacuated from the processing chamber. Byproducts from previous process steps, such as carbon, may also be removed by the baking process. A chemical equation describing the chemical reaction to remove the carbon is given below. -
SiC+2H2→Si+CH4 - The baking process changes the profile of the
spacers 86, in some embodiments. In accordance with some embodiments, the baking process re-shapes thespacers 86. As illustrated inFIG. 7A , theinner sidewalls 86S of thespacers 86 are curved after the baking process. For example, theinner sidewalls 86S, or at least the middle portions of theinner sidewalls 86S, bend outwards and away from acenter axis 64C of thefins 64, where thecenter axis 64C is perpendicular to anupper surface 50U of thesubstrate 50. In particular, a distance between middle portions of opposinginner sidewalls 86S increases after the re-shaping due to the baking process. For example, a first distance between theinner sidewalls 86S ofrespective spacers 86, measured after the baking process at a midpoint between theupper surface 86U and alower surface 86L of thespacers 86, is larger than a second distance between theinner sidewalls 86S measured at the midpoint before the baking process. -
FIG. 7B illustrates a zoomed-in view of thespacer 86 shown inFIG. 7A . As illustrated inFIG. 7B , thespacer 86 has a width W3 at theupper surface 86U and a width W5 at thelower surface 86L. Due to the curvedinner sidewall 86S, thespacer 86 has a minimum width W4 at point C, which corresponds to a point where theinner sidewall 86S extends furthest away from line M-N, where the line M-N is a line connecting the uppermost point M of theinner sidewall 86S and the lowermost point N of theinner sidewall 86S inFIG. 7B . In some embodiments, the width W3 is between about 2 nm and about 5 nm, the width W5 is between about 2 nm and 9 nm. The width W4 may be between about 2 nm and about 5 nm. The height H2 of thespacer 86 may be between about 5 nm and about 30 nm. - In some embodiments, an angle at between a ray R1 and a ray R2 is in a range between about 5 degrees and about 15 degrees, where R1 is a ray from the uppermost point M of the
inner sidewall 86S to the point C, and R2 is a ray from the point M toward thelower surface 86L of thespacer 86, and where R2 is perpendicular to theupper surface 50U (seeFIG. 7A ) of thesubstrate 50. Depending on the shape of thespacer 86, the ray R2 may or may not overlap with the line M-N. The dimensions described above are merely non-limiting examples, other dimensions for thespacer 86 are also possible and are fully intended to be included within the scope of the present disclosure. -
FIG. 7C illustrates another embodiment of thespacer 86 after the baking process. As illustrated inFIG. 7C , in addition to theinner sidewall 86S, the outer sidewall 86O of thespacer 86 may also be curved due to the baking process. In some embodiments, the conditions of the baking process, such as the temperature, the flow rate of the baking gas, the pressure, and/or the duration of the baking process, are adjusted to achieve a specific profile (e.g., straight or curved) for the outer sidewall 86O and/or theinner sidewall 86S of thespacer 86. Without being limited to a particular theory, it is believed that the amount of re-shaping of thespacer 86 may determine whether the outer sidewall 86O of thespacer 86 is curved (as illustrated inFIG. 7C ) or substantially straight (as illustratedFIG. 7B ). For example, it is observed that at a high temperature (e.g., >680° C.), the baking process is likely to reshape thespacer 86 such that the outer sidewall 86O is curved. In addition, the baking process may reduce the width of thespacer 86 at theupper surface 86U to a width W6. In other words, the width W6 of thespacer 86, measured at theupper surface 86U after the baking process, is smaller than the width W1 (seeFIG. 6B ) of thespacer 86, measured at theupper surface 86U before the baking process. - Still referring to
FIG. 7C , the curvedinner sidewall 86S extends furthest from line M-N at point C, where line M-N is a line connecting the uppermost point M of theinner sidewall 86S and the lowermost point N of theinner sidewall 86S. A width of thespacer 86 measured at the point C is W7, and a width of the spacer measured at the lower surface is W8. In some embodiments, W6 is smaller than W7, and W7 is smaller than W8. In some embodiments, an angle α between a ray R1 and a ray R2 is in a range between about 5 degrees and about 15 degrees, where R1 is a ray from the uppermost point M of theinner sidewall 86S to the point C, and R2 is a ray from the point M toward thelower surface 86L of thespacer 86, and where R2 is perpendicular to theupper surface 50U (seeFIG. 7A ) of thesubstrate 50. Depending on the shape of thespacer 86, the ray R2 may or may not overlap with the line M-N. - In some embodiments, the width W6 is between about 2 nm and about 5 nm, the width W8 is between about 2 nm and 10 nm. The width W7 may be between about 2 nm and about 7 nm. The height H3 of the
spacer 86 may be between about 5 nm and about 30 nm. The dimensions described above are merely non-limiting examples, other dimensions for thespacer 86 are also possible and are fully intended to be included within the scope of the present disclosure. - The curved
inner sidewalls 86S, and/or the narrower width W6 (if formed) at the upper surface of thespacer 86, facilitate horizontal growth of the epitaxial source/drain regions 80 (seeFIG. 8A ) in subsequent processing, and therefore, results in merged source/drain regions 80 with increased volumes over themultiple fins 64. More details are discussed hereinafter with reference toFIG. 8A . The increased volume of the merged source/drain regions 80 allows for reliable connection with source/drain contact plugs 102 (seeFIG. 15B ) formed subsequently, lowers contact resistance, and reduces the possibility of etch through of the source/drain regions 80 during formation of the source/drain contact plugs 102, in some embodiments. - Next, as illustrated in
FIG. 8A , source/drain regions 80 are formed by epitaxially growing a material in the recesses betweenspacers 86, using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof.FIG. 8B illustrates theFinFET device 100 ofFIG. 8A , but along cross-section A-A. - As illustrated in
FIG. 8A , the epitaxial source/drain regions 80 fill the recesses betweenspacers 86, and extend over theupper surface 86U of thespacers 86. In the illustrated embodiment, the source/drain regions 80 ofadjacent fins 64 merge to form a continuous epitaxial source/drain region 80 that connects themultiple fins 64 of theFinFET device 100. - As illustrated in
FIG. 8A , the source/drain regions 80 comprise curvedlower surfaces 80L. The curvedlower surfaces 80L increase the volume of the source/drain regions 80. The curvedlower surfaces 80L also result in merged source/drain regions 80 with increased thickness (e.g., D1 and D2). For example, a thickness D2 of the source/drain region 80, measured midway between twoadjacent fins 64, is in a range from about 15 nm to about 35 nm. A thickness D1 of the source/drain region 80, measured along thecenter axis 64C (seeFIG. 7A ) of thefin 64 and over thespacer 86, is in a range from about 25 nm to about 45 nm, in some embodiments. A fin pitch P may be in a range from about 25 nm to about 85 nm. A ratio of D1 to D2 is larger than 0.8, e.g., between about 0.8 and 3, and a ratio of D2 to the fin pitch P, is in a range between about 0.2 and 0.6, in various embodiments. - Still referring to
FIG. 8A , the merged source/drain regions 80 comprise slanted upper surfaces (e.g., 80S) that are substantially planar. The slanted planarupper surfaces 80S may also be referred to as facets of the source/drain regions 80. Therefore, the merged source/drain regions 80 have curvedlower surfaces 80L and slated planarupper surfaces 80S, in some embodiments. In addition,FIG. 8A also illustrates a substantially flat upper surface (e.g., 80U) between slanted planarupper surfaces 80S, where theupper surface 80U is substantially parallel to theupper surface 50U of thesubstrate 50. In some embodiments, theupper surface 80U has a curved shape (e.g., a concave curved upper surface, not shown). - Since the source/
drain regions 80 fill the recesses betweenrespective spacers 86, the source/drain regions 80 have a width D5 at the lower surface of thespacers 86, a width D4 at the upper surface of thespacers 86, and a width D3 between (e.g., midway between) the upper surface and the lower surface of thespacers 86. In the illustrated example, D3 is large than D4 and D5. In some embodiments, D3 is in a range from about 5 nm to about 30 nm, D4 is in a range from about 5 nm to about 25 nm, and D5 is in a range from about 5 nm to about 25 nm, although other dimension are also possible. As illustrated inFIG. 8A , ray R1 and ray R2 form an angle α between about 90 degrees and about 150 degrees (e.g., 90°≤α≤150°), where ray R1 and ray R2 start at a point where thelower surface 80L of the source/drain region 80 intersects (e.g., contacts) thespacers 86, and where ray R2 is perpendicular to theupper surface 50U of thesubstrate 50, and ray R1 is tangent to thelower surface 80L. - In some embodiments, the resulting
FinFET device 100 is an n-type FinFET, and source/drain regions 80 of thefins 64 comprise silicon carbide (SiC), silicon phosphorous (SiP), phosphorous-doped silicon carbon (SiCP), or the like. In some embodiments, the resultingFinFET device 100 is a p-type FinFET, and source/drain regions 80 of thefins 64 comprise SiGe, and a p-type impurity such as boron or indium. - The epitaxial source/
drain regions 80 may be implanted with dopants to form source/drain regions 80 followed by an anneal process. The source/drain regions 80 may have an impurity (e.g., dopant) concentration in a range from about 1E19 cm-3 to about 1E21 cm-3. P-type impurities, such as boron or indium, may be implanted in the source/drain region 80 of a P-type transistor. N-type impurities, such as phosphorous or arsenide, may be implanted in the source/drain regions 80 of an N-type transistor. In some embodiments, the epitaxial source/drain regions may be in situ doped during growth. - In some embodiments, a composition of a lower portion (e.g., a portion of 80 between the upper surface of the
STI regions 62 and theupper surface 86U of the spacers 86) of the source/drain region 80 is different from a composition of an upper portion (e.g., a portion of 80 above theupper surface 86U of the spacers 86) of the source/drain region 80. In an exemplary embodiment, the upper portion of the source/drain region 80 has a higher dopant concentration than that of the lower portion of the source/drain region 80. As an example, consider the case where the FinFET device is a n-type FinFET and the source/drain region 80 comprises SiP, the concentration of P for the lower portion of the source/drain region 80 may be between about 1E20/cm3 and about 1E21/cm3, and the concentration of P for the higher portion of the source/drain region 80 may be between about 1E21/cm3 and about 5E21/cm3. As another example, consider the case where the FinFET device is an P-type FinFET and the source/drain region 80 comprises SiGe doped by boron (B), the concentration of B for the lower portion of the source/drain region 80 may be between about 1E20/cm3 and about 5E20/cm3, and the concentration of B for the upper portion of the source/drain region 80 may be between about 2E20/cm3 and about 1E21/cm3. In addition, an atomic percentage of Ge of the source/drain region 80 (e.g., SiGe doped by B) in the lower portion may be between about 15% and about 30%, and an atomic percentage of Ge of the source/drain region 80 in the upper portion may be between about 30% and about 60%. - Next, as illustrated in
FIG. 9 , a first interlayer dielectric (ILD) 90 is formed over the source/drain regions 80, thefins 64, and thedummy gate structures 75. In some embodiments, thefirst ILD 90 is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. A planarization process, such as a CMP process, may be performed to remove themask 70, and to planarize the top surface of thefirst ILD 90 such that the top surface of thefirst ILD 90 is level with the top surface of thegate 68. - Next, an embodiment gate-last process (sometimes referred to as replacement gate process) is performed subsequently to replace the
gate 68 and thegate dielectric 66 with active gates and active gate dielectric materials. Therefore, thegate 68 and thegate dielectric 66 are considered dummy gate structures in a gate-last process. Details of the embodiment gate-last process are described hereinafter with reference toFIGS. 10-14, 15A and 15B . - Referring now to
FIG. 10 , thegate 68 and thegate dielectric 66 directly under thegate 68 are removed in an etching step(s), so that recesses (not shown) are formed betweenrespective gate spacers 87. Each recess exposes a channel region of arespective fin 64. Each channel region is disposed between neighboring pairs of epitaxial source/drain regions 80. During the dummy gate removal, the dummygate dielectric layer 66 may be used as an etch stop layer when thedummy gate 68 is etched. The dummygate dielectric layer 66 may then be removed after the removal of thedummy gate 68. - Next, a
gate dielectric layer 96, abarrier layer 94, aseed layer 92, and agate electrode 98 are formed for replacement gate 97 (seeFIG. 11 ). Thegate dielectric layer 96 is deposited conformally in the recesses, such as on the top surfaces and the sidewalls of thefins 64 and on sidewalls of thegate spacers 87, and on a top surface of thefirst ILD 90. In accordance with some embodiments, thegate dielectric layer 96 comprises silicon oxide, silicon nitride, or multilayers thereof. In other embodiments, thegate dielectric layer 96 includes a high-k dielectric material, and in these embodiments, the gate dielectric layers 96 may have a k value greater than about 7.0, and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation methods ofgate dielectric layer 96 may include MBD, ALD, PECVD, and the like. - Next, the
barrier layer 94 is formed conformally over thegate dielectric layer 96. Thebarrier layer 94 may comprise an electrically conductive material such as titanium nitride, although other materials, such as tantalum nitride, titanium, tantalum, or the like, may alternatively be utilized. Thebarrier layer 94 may be formed using a CVD process, such as plasma-enhanced CVD (PECVD). However, other alternative processes, such as sputtering or metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), may alternatively be used. - Although not illustrated in
FIG. 10 , work function layers may be formed in thereplacement gate 97, e.g., over thebarrier layer 94. For example, P-type work function layer(s) may be formed for P-type devices, and N-type work function layer(s) may be formed for N-type devices. Exemplary P-type work function metals that may be included in the gate structure (e.g., 97) include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. Exemplary N-type work function metals that may be included in the gate structure include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof. A work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage Vt is achieved in the device to be formed. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), and/or other suitable process. - Next, the
seed layer 92 is formed over the barrier layer 94 (or the work function layers if formed). Theseed layer 92 may include copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof, and may be deposited by atomic layer deposition (ALD), sputtering, physical vapor deposition (PVD), or the like. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. - Next, the
gate electrode 98 is deposited over theseed layer 92, and fills the remaining portions of the recesses. Thegate electrode 98 may be made of a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multilayers thereof, and may be formed by, e.g., electroplating, electroless plating, or other suitable method. - Next, as illustrated in
FIG. 11 , after the formation of thegate electrode 98, a planarization process, such as a CMP, may be performed to remove the excess portions of thegate dielectric layer 96, thebarrier layer 94, the work function layer(s) (if formed), theseed layer 92, and the material of thegate electrode 98, which excess portions are over the top surface offirst ILD 90. The resulting remaining portions of material of thegate electrode 98, theseed layer 92, the work function layer(s) (if formed), thebarrier layer 94, and thegate dielectric layer 96 thus form areplacement gate 97 of the resultingFinFET device 100. - Next, in
FIG. 12 , asecond ILD 95 is deposited over thefirst ILD 90. In an embodiment, thesecond ILD 95 is a flowable film formed by a flowable CVD method. In some embodiments, thesecond ILD 95 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD. Contactopenings FIG. 15A ) are formed through thefirst ILD 90 and/or thesecond ILD 95. For example, thecontact opening 91 is formed through thesecond ILD 95 and exposes thereplacement gate 97, while thecontact openings 93 are formed through thefirst ILD 90 and thesecond ILD 95, and exposes source/drain regions 80. - In advanced processing nodes, due to the high ratio of fin height to fin pitch,
contact openings 91/93 may be formed to extend into the source/drain regions 80, as illustrated inFIG. 12 , to ensure good contact between the subsequently formed contact plugs and the source/drain regions 80. A depth of the openings H4 may be in a range between about 15 nm to about 25 nm, as examples. - Next, in
FIG. 13 ,silicide regions 82 are formed over the source/drain regions 80, and abarrier layer 104 is formed over thesilicide regions 82 and thesecond ILD 95. In some embodiments, thesilicide regions 82 are formed by depositing, over the source/drain regions 80, a metal capable of reacting with semiconductor materials (e.g., silicon, germanium) to form silicide or germanide regions. The metal may be nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys. A thermal anneal process is then performed so that the deposited metal reacts with the source/drain regions 80 to formsilicide regions 82. After the thermal anneal process, the unreacted metal is removed. - The
barrier layer 104 is conformally formed over thesilicide regions 82 and thesecond ILD 95, and lines sidewalls and bottoms of thecontact openings 91/93. Thebarrier layer 104 may comprise an electrically conductive material such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or the like, and may be formed using a CVD process, such as plasma-enhanced CVD (PECVD). However, other alternative processes, such as sputtering or metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), may also be used. - Next, in
FIG. 14 , aseed layer 109 is formed over thebarrier layer 104, and an electricallyconductive material 110 is formed over theseed layer 109. Theseed layer 109 may be deposited by PVD, ALD or CVD, and may be formed of tungsten, copper, or copper alloys, although other suitable methods and materials may alternatively be used. - Once the
seed layer 109 has been formed, theconductive material 110 may be formed onto theseed layer 109 to fill thecontact openings 91/93. Theconductive material 110 may comprise tungsten, although other suitable materials such as aluminum, copper, tungsten nitride, rhuthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys of these, combinations thereof, and the like, may alternatively be utilized. Any suitable deposition method, such as PVD, CVD, ALD, plating (e.g., electroplating), and reflow, may be used to form theconductive material 110. - Referring next to
FIG. 15A , once thecontact openings 91/93 have been filled, excess portions of thebarrier layer 104, theseed layer 109, and theconductive material 110 outside of thecontact openings 91/93 may be removed through a planarization process such as CMP, although any suitable removal process may be used. Contact plugs 102 are thus formed in thecontact openings 91/93. Although contact plugs 102 over the source/drain regions 80 and over thereplacement gate 97 are illustrated in a same cross-section inFIG. 15A , the contact plugs 102 may be in different cross-sections in theFinFET device 100. -
FIG. 15B illustrates theFinFET device 100 inFIG. 15A , but along cross-section C-C. As discussed earlier, in advanced processing nodes, the contact openings, and hence the contact plugs 102, may extend into the source/drain regions 80. The current disclosed embodiments produces merged source/drain regions 80 with increased thickness, e.g., D2 (seeFIG. 8A ). The increased thickness of the merged source/drain regions 80 reduces or eliminates the possibility of over etching (e.g., contact holes 91/93 becoming through-holes in the source/drain regions 80) in forming thecontact openings 91/93. Over etching of thecontact openings 91/93 may result in the contact plugs 102 not being formed properly, or the contact plugs 102 extending through the source/drain regions 80, which may result in higher contact resistance and/or device failure. The disclosed embodiments, therefore, avoid these issues and provide improved production yield and better device performance. -
FIG. 16 illustrates a flow chart of a method of forming a semiconductor device, in accordance with some embodiments. It should be understood that the embodiment method shown inFIG. 16 is merely an example of many possible embodiment methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as illustrated inFIG. 16 may be added, removed, replaced, rearranged and repeated. - Referring to
FIG. 16 , atstep 1010, first spacers are formed on opposing sidewalls of a first fin, where the first fin protrudes above a substrate. Atstep 1020, the first fin is recessed to form a first recess between the first spacers. Atstep 1030, the first spacers are treated using a baking process, where treating the first spacers changes a profile of the first spacers. Atstep 1040, a first semiconductor material is epitaxially grown over a top surface of the first fin. - Embodiments may achieve advantages. For example, the baking process not only removes oxide from the recesses between spacers to facilitate growth of the epitaxial source/drain material, but also re-shapes the spacers to facilitate horizontal growth of the epitaxial source/drain material. As a result, the merged epitaxial source/drain regions have increased volume and increased thickness, which results in lower contact resistance and more reliable contact with contact plugs formed subsequently. The thicker source/drain regions prevents or reduces the possibility of over etching in forming the contact openings, which in turn prevents or reduces the possibility of the contact plugs being formed incorrectly or being formed through the source/drain regions, thereby improving device performance and increasing production yields.
- In an embodiment, a method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate; recessing the first fin to form a first recess between the first spacers; treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers; and epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers. In an embodiment, the baking process is performed using a gas comprising hydrogen. In an embodiment, the baking process is performed at a temperature in a range between about 650° C. and about 750° C. In an embodiment, the baking process is performed in a pressure in a range between about 10 torr and about 80 torr. In an embodiment, the baking process is performed for a duration between about 10 seconds and about 90 seconds. In an embodiment, treating the first spacers curves inner sidewalls of the first spacers such that a first distance between the inner sidewalls of the first spacers, measured after the treating at a midpoint of the inner sidewalls of the first spacers between an upper surface of the first spacers and a bottom surface of the first spacers, is larger than a second distance between the inner sidewalls of the first spacers measured at the midpoint before the treating. In an embodiment, treating the first spacers further reduces a width of the first spacers measured at the top surface of the first spacers. In an embodiment, the baking process reduces an oxide in the first recess using a reducing agent, where the method further comprises performing an oxide removal process after recessing the first fin and before treating the first spacers. In an embodiment, performing the oxide removal process uses hydrofluoric acid. In an embodiment, the method further includes forming second spacers on opposing sidewalls of a second fin; recessing the second fin to form a second recess between the second spacers; treating the second spacers using the baking process, where treating the second spacers changes a profile of the second spacers; and epitaxially growing a second semiconductor material over a top surface of the second fin, where the first semiconductor material and the second semiconductor material merge to form a continuous semiconductor region between the first fin and the second fin. In an embodiment, a lower surface of the continuous semiconductor region is curved, and an upper surface of the continuous semiconductor region is planar.
- In an embodiment, a method includes forming first spacers on opposing sidewalls of a first fin; forming second spacers on opposing sidewalls of a second fin; recessing the first fin and the second fin, where the recessing forms a first recess between the first spacers and a second recess between the second spacers; re-shaping the first spacers and the second spacers; and growing an epitaxial material in the first recess and the second recess. In an embodiment, the re-shaping bends first inner sidewalls of the first spacers and second inner sidewalls of the second spacers, where a distance between middle portions of the first inner sidewalls increases during the re-shaping, and a distance between middle portions of the second inner sidewalls increases during the re-shaping. In an embodiment, the re-shaping reduces a first width of the first spacers measured at a top surface of the first spacers, where the re-shaping reduces a second width of the second spacers measured at a top surface of the second spacers. In an embodiment, the re-shaping comprises a baking process. In an embodiment, the baking process is performed in an environment comprising hydrogen at a temperature between about 650° C. and about 750° C. In an embodiment, the epitaxial material extends over the first spacers and the second spacers, where the epitaxial material over the first fin and the second fin merge to form a semiconductor region extending continuously from the first fin to the second fin, and where a lower surface of the semiconductor region is curved.
- In an embodiment, a Fin Field-Effect Transistor (FinFET) device includes a first fin and a second fin; first spacers on opposing sides of the first fin, where inner sidewalls of the first spacers bend away from a longitudinal axis of the first fin; second spacers on opposing sides of the second fin, where inner sidewalls of the second spacers bend away from a center axis of the second fin; and a semiconductor material between the first spacers and between the second spacers, the semiconductor material extending continuously from the first fin to the second fin. In an embodiment, the semiconductor material has a curved lower surface. In an embodiment, the semiconductor material has a slanted planar upper surface.
- In an embodiment, a semiconductor device includes a first fin and a second fin protruding above a substrate; and a semiconductor material over the first fin and the second fin, the semiconductor material extending continuously from the first fin to the second fin, the semiconductor material having a curved lower surface and a slanted planar upper surface. In an embodiment, the semiconductor material further has a substantially flat upper surface between the first fin and the second fin. In an embodiment, the semiconductor material has a first portion over and contacting the first fin, a second portion over and contacting the first portion, and a third portion over and contacting the second portion, where the second portion has a second width larger than a first width of the first portion, and the third portion has a third width smaller than the second width. In an embodiment, the semiconductor device further includes first spacers on opposing sides of the first fin, where the first spacers have inner sidewalls that are curved, and where a distance between middle portions of the inner sidewalls of the first spacers is larger than a distance between end portions of the inner sidewalls of the first spacers.
- In an embodiment, a method of forming a semiconductor device includes recessing a first fin; recessing a second fin; and growing an epitaxial material over the first fin and over the second fin, where growing the epitaxial material forms a first portion of the epitaxial material over the first fin and over the second fin, forms a second portion of the epitaxial material over the first portion, forms a third portion of the epitaxial material over the second portion, and forms a fourth portion of the epitaxial material over the third portion, where the first portion has a first width smaller than a second width of the second portion, and the third portion has a third width smaller than the second width, and where the third portion comprises two separate regions, and the fourth portion extends continuously from the first fin to the second fin. In an embodiment, the fourth portion has a curved lower surface. In an embodiment, the method further includes forming first spacers on opposing sides of the first fin; forming second spacers on opposing sides of the second fin; and curving first inner sidewalls of the first spacers and second inner sidewalls of the second spacers before growing the epitaxial material. In an embodiment, the curving comprises performing a baking process using a gas comprising molecular hydrogen.
- In an embodiment, a method of forming a Fin Field-Effect Transistor (FinFET) device includes forming a plurality of fins; forming spacers along sidewalls of each of the plurality of fins; recessing the plurality of fins; re-shaping the spacers of each of the plurality of fins; and epitaxially growing a semiconductor material over each of the plurality of fins, where the semiconductor material continuously connects the plurality of fins, and where a lower surface of the semiconductor material is curved. In an embodiment, an upper surface of the semiconductor material is planar.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/713,355 US11049954B2 (en) | 2017-10-31 | 2019-12-13 | Fin field-effect transistors and methods of forming the same |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/799,344 US10355105B2 (en) | 2017-10-31 | 2017-10-31 | Fin field-effect transistors and methods of forming the same |
US16/511,580 US10510868B2 (en) | 2017-10-31 | 2019-07-15 | Fin Field-Effect Transistors and methods of forming the same |
US16/713,355 US11049954B2 (en) | 2017-10-31 | 2019-12-13 | Fin field-effect transistors and methods of forming the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/511,580 Continuation US10510868B2 (en) | 2017-10-31 | 2019-07-15 | Fin Field-Effect Transistors and methods of forming the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20200119165A1 true US20200119165A1 (en) | 2020-04-16 |
US11049954B2 US11049954B2 (en) | 2021-06-29 |
Family
ID=66243301
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/799,344 Active US10355105B2 (en) | 2017-10-31 | 2017-10-31 | Fin field-effect transistors and methods of forming the same |
US16/511,580 Active US10510868B2 (en) | 2017-10-31 | 2019-07-15 | Fin Field-Effect Transistors and methods of forming the same |
US16/713,355 Active US11049954B2 (en) | 2017-10-31 | 2019-12-13 | Fin field-effect transistors and methods of forming the same |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/799,344 Active US10355105B2 (en) | 2017-10-31 | 2017-10-31 | Fin field-effect transistors and methods of forming the same |
US16/511,580 Active US10510868B2 (en) | 2017-10-31 | 2019-07-15 | Fin Field-Effect Transistors and methods of forming the same |
Country Status (3)
Country | Link |
---|---|
US (3) | US10355105B2 (en) |
CN (1) | CN109727868B (en) |
TW (1) | TWI720322B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10355105B2 (en) * | 2017-10-31 | 2019-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field-effect transistors and methods of forming the same |
US11088150B2 (en) * | 2019-01-28 | 2021-08-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
TWI817126B (en) * | 2020-05-22 | 2023-10-01 | 台灣積體電路製造股份有限公司 | Semiconductor device including fin field-effect transistor |
US11854904B2 (en) * | 2020-08-13 | 2023-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Different source/drain profiles for n-type FinFETs and p-type FinFETs |
KR20220022507A (en) | 2020-08-18 | 2022-02-28 | 삼성전자주식회사 | Semiconductor device |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080265321A1 (en) * | 2007-04-27 | 2008-10-30 | Chen-Hua Yu | Fin Field-Effect Transistors |
US20100052043A1 (en) * | 2006-11-25 | 2010-03-04 | Kyungpook National University Industry- Academic Cooperation Foundation | High density flash memory device and fabricating method thereof |
US20140346607A1 (en) * | 2013-05-23 | 2014-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tuning Tensile Strain on FinFET |
US20150214366A1 (en) * | 2014-01-24 | 2015-07-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Embedded source or drain region of transistor with downward tapered region under facet region |
US20150243745A1 (en) * | 2012-08-30 | 2015-08-27 | Taiwan Semiconductor Manufacturing Company Ltd. | Finfet device with epitaxial structure |
US20150279894A1 (en) * | 2014-03-28 | 2015-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS Image Sensor with Epitaxial Passivation Layer |
US20170222006A1 (en) * | 2016-01-28 | 2017-08-03 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US20180350934A1 (en) * | 2017-06-05 | 2018-12-06 | United Microelectronics Corp. | Semiconductor structure |
US10355105B2 (en) * | 2017-10-31 | 2019-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field-effect transistors and methods of forming the same |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1763069B1 (en) * | 2005-09-07 | 2016-04-13 | Soitec | Method for forming a semiconductor heterostructure |
US20080227267A1 (en) | 2007-03-14 | 2008-09-18 | Theodorus Gerardus Maria Oosterlaken | Stop mechanism for trench reshaping process |
DE102007015504B4 (en) * | 2007-03-30 | 2014-10-23 | Advanced Micro Devices, Inc. | SOI transistor having reduced length drain and source regions and a strained dielectric material adjacent thereto and method of fabrication |
CN101796616A (en) * | 2007-09-05 | 2010-08-04 | Nxp股份有限公司 | A transistor and a method of manufacturing the same |
US9245805B2 (en) | 2009-09-24 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs with metal gates and stressors |
KR20120019917A (en) * | 2010-08-27 | 2012-03-07 | 삼성전자주식회사 | Method of fabricating semiconductor device |
US8470187B2 (en) * | 2010-11-05 | 2013-06-25 | Asm Japan K.K. | Method of depositing film with tailored comformality |
KR20120108338A (en) * | 2011-03-23 | 2012-10-05 | 삼성전자주식회사 | Methods for fabricating semiconducor devices |
US8962400B2 (en) | 2011-07-07 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | In-situ doping of arsenic for source and drain epitaxy |
US8841701B2 (en) | 2011-08-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device having a channel defined in a diamond-like shape semiconductor structure |
US9236267B2 (en) | 2012-02-09 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut-mask patterning process for fin-like field effect transistor (FinFET) device |
US8847293B2 (en) | 2012-03-02 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure for semiconductor device |
US8836016B2 (en) | 2012-03-08 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods with high mobility and high energy bandgap materials |
US8853025B2 (en) | 2013-02-08 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET/tri-gate channel doping for multiple threshold voltage tuning |
US9093514B2 (en) | 2013-03-06 | 2015-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained and uniform doping technique for FINFETs |
CN104217948B (en) * | 2013-05-31 | 2018-04-03 | 中国科学院微电子研究所 | Semiconductor manufacturing method |
CN104377132A (en) * | 2013-08-13 | 2015-02-25 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
US9136106B2 (en) | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
US9184087B2 (en) * | 2013-12-27 | 2015-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanisms for forming FinFETs with different fin heights |
US9496398B2 (en) | 2014-01-15 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxial source/drain regions in FinFETs and methods for forming the same |
US9190272B1 (en) * | 2014-07-15 | 2015-11-17 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US9634125B2 (en) * | 2014-09-18 | 2017-04-25 | United Microelectronics Corporation | Fin field effect transistor device and fabrication method thereof |
US9559207B2 (en) * | 2015-03-23 | 2017-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having epitaxy structure |
KR102330757B1 (en) * | 2015-03-30 | 2021-11-25 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US9825036B2 (en) * | 2016-02-23 | 2017-11-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for semiconductor device |
US9882013B2 (en) * | 2016-03-31 | 2018-01-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
-
2017
- 2017-10-31 US US15/799,344 patent/US10355105B2/en active Active
-
2018
- 2018-03-15 CN CN201810213365.0A patent/CN109727868B/en active Active
- 2018-06-21 TW TW107121305A patent/TWI720322B/en active
-
2019
- 2019-07-15 US US16/511,580 patent/US10510868B2/en active Active
- 2019-12-13 US US16/713,355 patent/US11049954B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100052043A1 (en) * | 2006-11-25 | 2010-03-04 | Kyungpook National University Industry- Academic Cooperation Foundation | High density flash memory device and fabricating method thereof |
US20080265321A1 (en) * | 2007-04-27 | 2008-10-30 | Chen-Hua Yu | Fin Field-Effect Transistors |
US20150243745A1 (en) * | 2012-08-30 | 2015-08-27 | Taiwan Semiconductor Manufacturing Company Ltd. | Finfet device with epitaxial structure |
US20140346607A1 (en) * | 2013-05-23 | 2014-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tuning Tensile Strain on FinFET |
US20150214366A1 (en) * | 2014-01-24 | 2015-07-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Embedded source or drain region of transistor with downward tapered region under facet region |
US20150279894A1 (en) * | 2014-03-28 | 2015-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS Image Sensor with Epitaxial Passivation Layer |
US20170222006A1 (en) * | 2016-01-28 | 2017-08-03 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US20180350934A1 (en) * | 2017-06-05 | 2018-12-06 | United Microelectronics Corp. | Semiconductor structure |
US10355105B2 (en) * | 2017-10-31 | 2019-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field-effect transistors and methods of forming the same |
US10510868B2 (en) * | 2017-10-31 | 2019-12-17 | Taiwan Semiconductor Manufacutring Co., Ltd. | Fin Field-Effect Transistors and methods of forming the same |
Also Published As
Publication number | Publication date |
---|---|
TWI720322B (en) | 2021-03-01 |
US10510868B2 (en) | 2019-12-17 |
CN109727868A (en) | 2019-05-07 |
CN109727868B (en) | 2022-03-11 |
US11049954B2 (en) | 2021-06-29 |
TW201919114A (en) | 2019-05-16 |
US10355105B2 (en) | 2019-07-16 |
US20190131434A1 (en) | 2019-05-02 |
US20190341471A1 (en) | 2019-11-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11735430B2 (en) | Fin field-effect transistor device and method | |
US10867861B2 (en) | Fin field-effect transistor device and method of forming the same | |
US11049954B2 (en) | Fin field-effect transistors and methods of forming the same | |
US11728215B2 (en) | Fin Field-Effect Transistor device and method of forming the same | |
US11201084B2 (en) | Fin field-effect transistor device and method of forming the same | |
US12033893B2 (en) | Contact plug with impurity variation | |
US11901183B2 (en) | Fin field-effect transistor device and method of forming the same | |
US20220293742A1 (en) | Fin field-effect transistor device and method | |
US11916147B2 (en) | Fin field-effect transistor device having contact plugs with re-entrant profile | |
US11823955B2 (en) | Multi-layered insulating film stack | |
US11482421B2 (en) | Method of forming a semiconductor device by a replacement gate process | |
US20220415715A1 (en) | Fin Field-Effect Transistor Device and Method of Forming | |
US11908920B2 (en) | Fin field-effect transistor device and method of forming the same | |
US20230025645A1 (en) | Fin Field-Effect Transistor Device and Method | |
US20220359207A1 (en) | Fin Field-Effect Transistor Device and Method of Forming the Same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT RECEIVED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |