US20200075480A1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- US20200075480A1 US20200075480A1 US16/122,807 US201816122807A US2020075480A1 US 20200075480 A1 US20200075480 A1 US 20200075480A1 US 201816122807 A US201816122807 A US 201816122807A US 2020075480 A1 US2020075480 A1 US 2020075480A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
Definitions
- the present invention generally relates to semiconductor fabrication technology, and particularly to the structure and fabrication method for the semiconductor device with interconnect structure.
- the different wiring layers at different levels are connected through the via structure at the connection nodes. However, once the device size is greatly reduced, the via structure is rather close to the neighbouring lower wire. If the mechanical strength of the dielectric material to support the wiring line is insufficient, the via structure would possibly contacts to the neighbouring lower wire, causing a circuit short.
- the invention provides structure and fabrication method for the semiconductor device, in which the via structure in the interconnection layer can be well supported with less possibility of circuit short.
- the invention provides a structure of semiconductor device includes a substrate, wherein an interconnection layer is formed on the substrate.
- the interconnection layer comprises a first inter-layer dielectric layer, disposed over the substrate.
- a lower wiring structure is formed in the first inter-layer dielectric layer.
- a hard mask layer is disposed on the first inter-layer dielectric layer.
- the hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure.
- a second inter-layer dielectric layer is disposed on the hard mask layer.
- the second inter-layer dielectric layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening.
- the second inter-layer dielectric layer has a protruding portion to fill the second opening of the mask layer.
- a metal line layer fills the via opening and the trench pattern in the second inter-layer dielectric layer and the first opening of the hard mask layer.
- the first inter-layer dielectric layer is a single layer.
- the first inter-layer dielectric layer comprises multiple layers as a stacked layer.
- the first inter-layer dielectric layer comprises: a nitrogen-doped SiC (NDC) layer, disposed on the substrate; a tetraethoxysilane (TEOS) layer, disposed on the NDC layer; and a low-k dielectric layer, disposed on the TEOS layer.
- NDC nitrogen-doped SiC
- TEOS tetraethoxysilane
- the lower wiring structure in the first inter-layer dielectric layer are same height to the first inter-layer dielectric layer.
- the hard mask layer has a predetermined thickness to determine a depth of the first opening and the second opening of the hard mask layer.
- the second inter-layer dielectric layer is a single-layer structure.
- the second inter-layer dielectric layer is a multiple-layer structure.
- the second inter-layer dielectric layer comprises: an etching stop layer, disposed on the hard mask layer; a tetraethoxysilane (TEOS) layer disposed on the etching stop layer; and a low-K dielectric layer on the TEOS layer.
- the via opening penetrates through the low-K dielectric layer, the TEOS layer and the etching stop layer to expose the lower wiring structure and the trench pattern is in the low-K dielectric layer.
- the metal line layer comprises a via in the via opening to contact with the lower wiring structure, and a trench metal line to fill the trench pattern.
- the invention also provides a method for fabricating semiconductor device.
- the method comprises providing a substrate and forming an interconnection layer on the substrate.
- the interconnection layer is formed comprising forming a first inter-layer dielectric layer over the substrate.
- a lower wiring structure is formed in the first inter-layer dielectric layer.
- a hard mask layer is formed on the first inter-layer dielectric layer.
- the hard mask layer is patterned to have a first opening and a second opening being adjacent to expose the lower wiring structure.
- a second inter-layer dielectric layer is formed on the hard mask layer, wherein the second inter-layer dielectric layer has a protruding portion to fill the first opening and the second opening of the mask layer.
- the second inter-layer dielectric layer is patterned to have a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening.
- a metal line layer is formed in the second inter-layer dielectric layer, filling the via opening and the trench pattern and the first opening of the hard mask layer.
- the first inter-layer dielectric layer is a single layer.
- the first inter-layer dielectric layer comprises multiple layers as a stacked layer.
- the first inter-layer dielectric layer is formed comprising: forming a nitrogen-doped SiC (NDC) layer on the substrate; forming a tetraethoxysilane (TEOS) layer on the NDC layer; and forming a low-k dielectric layer on the TEOS layer.
- NDC nitrogen-doped SiC
- TEOS tetraethoxysilane
- a polishing process is performed on the lower wiring structure and the first inter-layer dielectric layer to have same height.
- the hard mask layer has a predetermined thickness to determine a depth of the first opening and the second opening of the hard mask layer.
- the second inter-layer dielectric layer is a single-layer structure.
- the second inter-layer dielectric layer is a multiple-layer structure.
- the step of forming the second inter-layer dielectric layer comprises: forming an etching stop layer on the hard mask layer; forming a tetraethoxysilane (TEOS) layer on the etching stop layer; and forming a low-K dielectric layer on the TEOS layer.
- the via opening penetrates through the low-K dielectric layer, the TEOS layer and the etching stop layer to expose the lower wiring structure and the trench pattern is in the low-K dielectric layer.
- the metal line layer comprises a via in the via opening to contact with the lower wiring structure, and a trench metal line to fill the trench pattern.
- FIG. 1 is a drawing, schematically illustrating a layout of interconnect structure, according to an embodiment of the invention as looked into.
- FIG. 2 is a drawing, schematically illustrating a cross-sectional structure along a cutting line I-I in FIG. 1 , according to an embodiment of the invention.
- FIG. 3 is a drawing, schematically illustrating a layout of a lower metal layer of an interconnect structure, according to an embodiment of the invention.
- FIG. 4A - FIG. 4I are drawings of cross-sectional structure cutting along the line II-II indicated in FIG. 3 crossing over the interconnection layer, schematically illustrating a fabrication process for an interconnection layer, according to an embodiment of the invention.
- FIG. 5 is a drawing, schematically illustrating a layout of an upper metal layer of the interconnect structure, according to an embodiment of the invention.
- the invention is directed to the fabrication technology of semiconductor device.
- the semiconductor device usually includes an interconnection layer with multiple metal layers in different levels, so to connect the elements, such transistors, to form the integrated circuit as intended.
- the invention has looked into the structure of interconnection layer.
- the interconnection layer has a three-dimensional structure, including a lower metal line and the upper metal line, and a via, located at a proper position to connect the lower metal line and the upper metal line, in an example.
- the adjacent via may get circuit short to other part of the lower metal line when the upper metal line is formed over the lower metal line and connected to the lower metal line through via. This situation is more obvious as the device size is greatly reduced.
- FIG. 1 is a drawing, schematically illustrating a layout of interconnect structure, according to an embodiment of the invention as looked into.
- FIG. 2 is a drawing, schematically illustrating a cross-sectional structure along a cutting line I-I in FIG. 1 , according to an embodiment of the invention.
- the structure of an interconnection layer of a semiconductor device includes a lower metal lines 50 and an upper metal lines 55 , which usually are horizontally extending in the individual layers in different directions over a substrate 70 , in an example.
- the connection between the lower metal lines 50 and the upper metal lines 55 at the connection node by a via 56 extending along a vertical direction.
- the horizontal area occupied by the interconnection layer is accordingly reduced.
- a distance 60 between the via 56 and the adjacent lower metal line 50 gets smaller.
- the via 56 may be easily connecting to the adjacent lower metal line 50 , causing a circuit short. The fabrication of the semiconductor device then gets fail.
- the vias 50 may be formed to be lower than the peripheral dielectric layer, so to have a shallow recess and further an etching stop layer on the shallow recess, so to avoid the electrical short between the lower metal line 50 and the adjacent one of the via 56 to the lower metal line 50 .
- the recess above is formed by further removing a top portion of the metal line, reducing the thickness in other words. This fabrication manner above is based on reducing the thickness of the lower metal line 50 .
- FIG. 3 is a drawing, schematically illustrating a layout of a lower metal layer of an interconnect structure, according to an embodiment of the invention.
- FIG. 4A -FIG. 4 I are drawings of cross-sectional structure cutting along the line II-II indicated in FIG. 3 crossing over the interconnection layer, schematically illustrating a fabrication process for an interconnection layer, according to an embodiment of the invention.
- a substrate 90 is provided as a base structure.
- the substrate 90 in an example is a silicon substrate. However, the substrate 90 may have already been formed with sub-structures.
- An interconnection layer 100 is to be eventually formed over the substrate 90 as to be fully shown in FIG. 4I .
- the interconnection layer 100 includes an inter-layer dielectric layer 102 serving as the lower part.
- Another inter-layer dielectric layer 128 is to be subsequently formed as to be seen from FIG. 4F .
- the inter-layer dielectric layer 102 is fabricated in an example including forming a lower metal line 94 in a dielectric layer 92 .
- An interconnection structure 85 is formed in another dielectric layer 80 over the dielectric layer 92 to contact to the lower metal line 94 .
- the interconnection structure 85 with the lower metal line 94 is a part of a lower wiring structure, which is generally referring to the necessary interconnection structure in actual need without limiting to the interconnection structure 85 with the lower metal line 94 .
- the dielectric layer 80 may include multiple dielectric layers 104 , 106 , 108 in different materials as actual need or a single-layer structure, without limiting thereto.
- the inter-layer dielectric layer 102 is a lower part of the interconnection layer 100 for any connection structure as designed. Then, another inter-layer dielectric layer 128 (seen in FIG. 4I ), serving as an upper part of the interconnection layer 100 to be subsequently formed.
- a mask layer 110 is formed over the inter-layer dielectric layer 102 .
- the mask layer 110 in an example servers as a hard mask layer, relatively hard to the inter-layer dielectric layer 102 , so the material of the mask layer 110 can be aluminium nitride as an example.
- a photoresist layer 112 with an opening 114 is formed on the mask layer 110 .
- the opening 114 exposes a portion of the mask layer 110 corresponding to the locations of the interconnection structure 85 .
- the photoresist layer 112 with an opening 114 is used as an etching mask, then an etching process is performed to etch the exposed portion of the mask layer 110 , so to form the opening 116 a , 116 b in the mask layer 110 to expose the interconnection structure 85 .
- the photoresist layer 112 is removed to further expose the mask layer 110 , which has the openings 116 a , 116 b to correspondingly expose the interconnection structure 85 .
- a top portion of the interconnection structure 85 is not necessary to be removed to have the recess.
- the openings 116 a , 116 b of the mask layer 110 provide the recess over the interconnection structure 85 .
- the inter-layer dielectric layer 128 can be a stacked layer from multiple dielectric layers in different materials.
- the inter-layer dielectric layer 128 can include an etching stop layer 120 , a TEOS layer, a dielectric layer 124 , and a mask layer 126 .
- the mask layer 126 can even include multiple layers.
- the stack of the inter-layer dielectric layer 128 is not limited to the example.
- the inter-layer dielectric layer 128 is used to subsequently form an upper wiring structure inside, so to connect to the interconnection structure 85 of the lower wiring structure.
- a trench pattern 130 is formed in the inter-layer dielectric layer 128 at the top portion by a patterning process at a first stage.
- the trench pattern 130 is corresponding to a pattern of an upper metal line structure to be formed later.
- the trench pattern 130 may stop in the dielectric layer 124 .
- a via opening 132 is then further formed in the inter-layer dielectric layer 128 by another patterning process at a second stage, so to expose the intended part of the interconnection structure 85 .
- the trench pattern 130 and the via opening 132 are connected together as a mixed opening.
- the via opening 132 is aligned to the intended portion of the interconnection structure 85 in the lower wiring structure.
- a metal line 136 including a via 134 is formed in the inter-layer dielectric layer 128 to fill the trench pattern 130 and the via opening 132 .
- the metal line 136 has a structure being extending horizontally and also including the via 134 extending vertically.
- the via 134 indeed contacts the interconnection structure 85 of the lower wiring structure.
- the mask layer 110 provides mechanical strength to support the metal line 136 with the via 134 .
- the via 134 has a significantly less probability to contact to the adjacent interconnection structure 85 of the lower wiring structure.
- inter-layer dielectric layer 128 also includes a protruding portion to fill the opening 116 b of the mask layer 110 to really insulate interconnection structure 85 at this region.
- the interconnection layer 100 including the inter-layer dielectric layer 102 , the mask layer 110 , and the inter-layer dielectric layer 128 is then formed over the substrate 90 .
- the intended wiring structure is formed in the interconnection layer 100 , wherein the bottom portion of the via 134 is additionally supported by the mask layer 110 .
- the mask layer 110 provides the additional mechanical strength to effective avoid electric short, occurring between the via and the interconnection structure.
- FIG. 5 is a drawing, schematically illustrating a layout of an upper metal layer of the interconnect structure, according to an embodiment of the invention.
- the layout of the metal line 136 over the inter-layer dielectric layer 102 in an example is extending along a direction different from the direction, similarly shown in FIG. 3 .
- the upper metal line and the lower metal line are connected at the predetermined node by the via 134 . Additionally, the bottom portion of the via 134 is protected by the mask layer 110 . The probability to contact to the adjacent lower wiring structure can be effectively reduced.
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Abstract
Description
- The present invention generally relates to semiconductor fabrication technology, and particularly to the structure and fabrication method for the semiconductor device with interconnect structure.
- As integration of integrated circuit is significantly improved, the device size is accordingly reduced. In addition, in order to keep high integration over the available area of the substrate for forming the device, some structures are formed by the manner of stacking up in the vertical direction to the wafer.
- The different wiring layers at different levels are connected through the via structure at the connection nodes. However, once the device size is greatly reduced, the via structure is rather close to the neighbouring lower wire. If the mechanical strength of the dielectric material to support the wiring line is insufficient, the via structure would possibly contacts to the neighbouring lower wire, causing a circuit short.
- How to improve the structure of inter-layer dielectric layer, so to well support the interconnection structure is still an issue to further look into and solve.
- In accordance with embodiments, the invention provides structure and fabrication method for the semiconductor device, in which the via structure in the interconnection layer can be well supported with less possibility of circuit short.
- In an embodiment, the invention provides a structure of semiconductor device includes a substrate, wherein an interconnection layer is formed on the substrate. The interconnection layer comprises a first inter-layer dielectric layer, disposed over the substrate. A lower wiring structure is formed in the first inter-layer dielectric layer. A hard mask layer is disposed on the first inter-layer dielectric layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second inter-layer dielectric layer is disposed on the hard mask layer. The second inter-layer dielectric layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second inter-layer dielectric layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second inter-layer dielectric layer and the first opening of the hard mask layer.
- In an embodiment, as to the structure of semiconductor device, the first inter-layer dielectric layer is a single layer.
- In an embodiment, as to the structure of semiconductor device, the first inter-layer dielectric layer comprises multiple layers as a stacked layer.
- In an embodiment, as to the structure of semiconductor device, the first inter-layer dielectric layer comprises: a nitrogen-doped SiC (NDC) layer, disposed on the substrate; a tetraethoxysilane (TEOS) layer, disposed on the NDC layer; and a low-k dielectric layer, disposed on the TEOS layer.
- In an embodiment, as to the structure of semiconductor device, the lower wiring structure in the first inter-layer dielectric layer are same height to the first inter-layer dielectric layer.
- In an embodiment, as to the structure of semiconductor device, the hard mask layer has a predetermined thickness to determine a depth of the first opening and the second opening of the hard mask layer.
- In an embodiment, as to the structure of semiconductor device, the second inter-layer dielectric layer is a single-layer structure.
- In an embodiment, as to the structure of semiconductor device, the second inter-layer dielectric layer is a multiple-layer structure.
- In an embodiment, as to the structure of semiconductor device, the second inter-layer dielectric layer comprises: an etching stop layer, disposed on the hard mask layer; a tetraethoxysilane (TEOS) layer disposed on the etching stop layer; and a low-K dielectric layer on the TEOS layer. The via opening penetrates through the low-K dielectric layer, the TEOS layer and the etching stop layer to expose the lower wiring structure and the trench pattern is in the low-K dielectric layer.
- In an embodiment, as to the structure of semiconductor device, the metal line layer comprises a via in the via opening to contact with the lower wiring structure, and a trench metal line to fill the trench pattern.
- In an embodiment, the invention also provides a method for fabricating semiconductor device. The method comprises providing a substrate and forming an interconnection layer on the substrate. The interconnection layer is formed comprising forming a first inter-layer dielectric layer over the substrate. A lower wiring structure is formed in the first inter-layer dielectric layer. A hard mask layer is formed on the first inter-layer dielectric layer. The hard mask layer is patterned to have a first opening and a second opening being adjacent to expose the lower wiring structure. A second inter-layer dielectric layer is formed on the hard mask layer, wherein the second inter-layer dielectric layer has a protruding portion to fill the first opening and the second opening of the mask layer. The second inter-layer dielectric layer is patterned to have a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. A metal line layer is formed in the second inter-layer dielectric layer, filling the via opening and the trench pattern and the first opening of the hard mask layer.
- In an embodiment, as to the method for fabricating semiconductor device, the first inter-layer dielectric layer is a single layer.
- In an embodiment, as to the method for fabricating semiconductor device, the first inter-layer dielectric layer comprises multiple layers as a stacked layer.
- In an embodiment, as to the method for fabricating semiconductor device, the first inter-layer dielectric layer is formed comprising: forming a nitrogen-doped SiC (NDC) layer on the substrate; forming a tetraethoxysilane (TEOS) layer on the NDC layer; and forming a low-k dielectric layer on the TEOS layer.
- In an embodiment, as to the method for fabricating semiconductor device, a polishing process is performed on the lower wiring structure and the first inter-layer dielectric layer to have same height.
- In an embodiment, as to the method for fabricating semiconductor device, the hard mask layer has a predetermined thickness to determine a depth of the first opening and the second opening of the hard mask layer.
- In an embodiment, as to the method for fabricating semiconductor device, the second inter-layer dielectric layer is a single-layer structure.
- In an embodiment, as to the method for fabricating semiconductor device, the second inter-layer dielectric layer is a multiple-layer structure.
- In an embodiment, as to the method for fabricating semiconductor device, the step of forming the second inter-layer dielectric layer comprises: forming an etching stop layer on the hard mask layer; forming a tetraethoxysilane (TEOS) layer on the etching stop layer; and forming a low-K dielectric layer on the TEOS layer. The via opening penetrates through the low-K dielectric layer, the TEOS layer and the etching stop layer to expose the lower wiring structure and the trench pattern is in the low-K dielectric layer.
- In an embodiment, as to the method for fabricating semiconductor device, the metal line layer comprises a via in the via opening to contact with the lower wiring structure, and a trench metal line to fill the trench pattern.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
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FIG. 1 is a drawing, schematically illustrating a layout of interconnect structure, according to an embodiment of the invention as looked into. -
FIG. 2 is a drawing, schematically illustrating a cross-sectional structure along a cutting line I-I inFIG. 1 , according to an embodiment of the invention. -
FIG. 3 is a drawing, schematically illustrating a layout of a lower metal layer of an interconnect structure, according to an embodiment of the invention. -
FIG. 4A -FIG. 4I are drawings of cross-sectional structure cutting along the line II-II indicated inFIG. 3 crossing over the interconnection layer, schematically illustrating a fabrication process for an interconnection layer, according to an embodiment of the invention. -
FIG. 5 is a drawing, schematically illustrating a layout of an upper metal layer of the interconnect structure, according to an embodiment of the invention. - The invention is directed to the fabrication technology of semiconductor device. The semiconductor device usually includes an interconnection layer with multiple metal layers in different levels, so to connect the elements, such transistors, to form the integrated circuit as intended. The invention has looked into the structure of interconnection layer.
- The interconnection layer has a three-dimensional structure, including a lower metal line and the upper metal line, and a via, located at a proper position to connect the lower metal line and the upper metal line, in an example. However, the adjacent via may get circuit short to other part of the lower metal line when the upper metal line is formed over the lower metal line and connected to the lower metal line through via. This situation is more obvious as the device size is greatly reduced.
-
FIG. 1 is a drawing, schematically illustrating a layout of interconnect structure, according to an embodiment of the invention as looked into.FIG. 2 is a drawing, schematically illustrating a cross-sectional structure along a cutting line I-I inFIG. 1 , according to an embodiment of the invention. - Referring to
FIG. 1 andFIG. 2 , the structure of an interconnection layer of a semiconductor device includes alower metal lines 50 and anupper metal lines 55, which usually are horizontally extending in the individual layers in different directions over asubstrate 70, in an example. The connection between thelower metal lines 50 and theupper metal lines 55 at the connection node by a via 56, extending along a vertical direction. When the device size is greatly reduced, the horizontal area occupied by the interconnection layer is accordingly reduced. In this situation, adistance 60 between the via 56 and the adjacentlower metal line 50 gets smaller. However, if the mechanical strength to support the via 56 is insufficient, the via 56 may be easily connecting to the adjacentlower metal line 50, causing a circuit short. The fabrication of the semiconductor device then gets fail. - To increase the mechanical strength as looked into above, the
vias 50 may be formed to be lower than the peripheral dielectric layer, so to have a shallow recess and further an etching stop layer on the shallow recess, so to avoid the electrical short between thelower metal line 50 and the adjacent one of the via 56 to thelower metal line 50. However, the recess above is formed by further removing a top portion of the metal line, reducing the thickness in other words. This fabrication manner above is based on reducing the thickness of thelower metal line 50. - In the invention as proposed after at least looking into the issues above, it is not necessary to form a recess by reducing the thickness of the lower metal line.
- Several embodiments are provided for describing the invention. However, the invention is not just limited to.
-
FIG. 3 is a drawing, schematically illustrating a layout of a lower metal layer of an interconnect structure, according to an embodiment of the invention.FIG. 4A -FIG. 4I are drawings of cross-sectional structure cutting along the line II-II indicated inFIG. 3 crossing over the interconnection layer, schematically illustrating a fabrication process for an interconnection layer, according to an embodiment of the invention. - Referring to
FIG. 4A withFIG. 3 , asubstrate 90 is provided as a base structure. Thesubstrate 90 in an example is a silicon substrate. However, thesubstrate 90 may have already been formed with sub-structures. Aninterconnection layer 100 is to be eventually formed over thesubstrate 90 as to be fully shown inFIG. 4I . Theinterconnection layer 100 includes aninter-layer dielectric layer 102 serving as the lower part. Anotherinter-layer dielectric layer 128 is to be subsequently formed as to be seen fromFIG. 4F . - The
inter-layer dielectric layer 102 is fabricated in an example including forming alower metal line 94 in adielectric layer 92. Aninterconnection structure 85 is formed in anotherdielectric layer 80 over thedielectric layer 92 to contact to thelower metal line 94. Theinterconnection structure 85 with thelower metal line 94 is a part of a lower wiring structure, which is generally referring to the necessary interconnection structure in actual need without limiting to theinterconnection structure 85 with thelower metal line 94. Due to the actual fabrication stages, thedielectric layer 80 may include multipledielectric layers - As see above, the
inter-layer dielectric layer 102 is a lower part of theinterconnection layer 100 for any connection structure as designed. Then, another inter-layer dielectric layer 128 (seen inFIG. 4I ), serving as an upper part of theinterconnection layer 100 to be subsequently formed. - Referring to
FIG. 4B , amask layer 110 is formed over theinter-layer dielectric layer 102. Themask layer 110 in an example servers as a hard mask layer, relatively hard to theinter-layer dielectric layer 102, so the material of themask layer 110 can be aluminium nitride as an example. - Referring to
FIG. 4C , aphotoresist layer 112 with anopening 114 is formed on themask layer 110. Theopening 114 exposes a portion of themask layer 110 corresponding to the locations of theinterconnection structure 85. - Referring to
FIG. 4D , thephotoresist layer 112 with anopening 114 is used as an etching mask, then an etching process is performed to etch the exposed portion of themask layer 110, so to form theopening mask layer 110 to expose theinterconnection structure 85. - Referring to
FIG. 4E , thephotoresist layer 112 is removed to further expose themask layer 110, which has theopenings interconnection structure 85. As remarkably noted, a top portion of theinterconnection structure 85 is not necessary to be removed to have the recess. Theopenings mask layer 110 provide the recess over theinterconnection structure 85. - Referring to
FIG. 4F , anotherinter-layer dielectric layer 128 is formed over themask layer 110. Theinter-layer dielectric layer 128 can be a stacked layer from multiple dielectric layers in different materials. In an example, theinter-layer dielectric layer 128 can include anetching stop layer 120, a TEOS layer, adielectric layer 124, and amask layer 126. Themask layer 126 can even include multiple layers. However, the stack of theinter-layer dielectric layer 128 is not limited to the example. Theinter-layer dielectric layer 128 is used to subsequently form an upper wiring structure inside, so to connect to theinterconnection structure 85 of the lower wiring structure. - Referring to
FIG. 4G , atrench pattern 130 is formed in theinter-layer dielectric layer 128 at the top portion by a patterning process at a first stage. Thetrench pattern 130 is corresponding to a pattern of an upper metal line structure to be formed later. Thetrench pattern 130 may stop in thedielectric layer 124. - Referring to
FIG. 4H , a viaopening 132 is then further formed in theinter-layer dielectric layer 128 by another patterning process at a second stage, so to expose the intended part of theinterconnection structure 85. Thetrench pattern 130 and the viaopening 132 are connected together as a mixed opening. The viaopening 132 is aligned to the intended portion of theinterconnection structure 85 in the lower wiring structure. - Referring to
FIG. 4I , ametal line 136 including a via 134 is formed in theinter-layer dielectric layer 128 to fill thetrench pattern 130 and the viaopening 132. As a result, themetal line 136 has a structure being extending horizontally and also including the via 134 extending vertically. - As noted, the via 134 indeed contacts the
interconnection structure 85 of the lower wiring structure. Themask layer 110 provides mechanical strength to support themetal line 136 with the via 134. The via 134 has a significantly less probability to contact to theadjacent interconnection structure 85 of the lower wiring structure. inter-layerdielectric layer 128 also includes a protruding portion to fill theopening 116 b of themask layer 110 to really insulateinterconnection structure 85 at this region. - In the structure of
FIG. 4I , theinterconnection layer 100 including theinter-layer dielectric layer 102, themask layer 110, and theinter-layer dielectric layer 128 is then formed over thesubstrate 90. The intended wiring structure is formed in theinterconnection layer 100, wherein the bottom portion of thevia 134 is additionally supported by themask layer 110. Themask layer 110 provides the additional mechanical strength to effective avoid electric short, occurring between the via and the interconnection structure. -
FIG. 5 is a drawing, schematically illustrating a layout of an upper metal layer of the interconnect structure, according to an embodiment of the invention. Referring toFIG. 5 , the layout of themetal line 136 over theinter-layer dielectric layer 102 in an example is extending along a direction different from the direction, similarly shown inFIG. 3 . The upper metal line and the lower metal line are connected at the predetermined node by thevia 134. Additionally, the bottom portion of thevia 134 is protected by themask layer 110. The probability to contact to the adjacent lower wiring structure can be effectively reduced. - It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (20)
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