US20200067404A1 - Cross-coupled charge-pumps - Google Patents
Cross-coupled charge-pumps Download PDFInfo
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- US20200067404A1 US20200067404A1 US16/225,605 US201816225605A US2020067404A1 US 20200067404 A1 US20200067404 A1 US 20200067404A1 US 201816225605 A US201816225605 A US 201816225605A US 2020067404 A1 US2020067404 A1 US 2020067404A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0041—Control circuits in which a clock signal is selectively enabled or disabled
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0083—Converters characterised by their input or output configuration
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- H02M2001/0041—
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
Definitions
- a charge pump is type of power converter that increases voltage such that the voltage output is higher than the voltage input.
- One type of charge pump is a cross-coupled charge pump.
- the related art cross-coupled charge pumps experience unwanted cross-conduction that lowers operating efficiency.
- cross-coupled charge pumps use field effect transistors (FET) to selectively pump charge from a charged capacitor to the voltage output, and simultaneously use another FET to refresh the voltage on a second capacitor.
- FET field effect transistors
- the roles of the pump and charge for the two capacitors alternate. However, it takes a finite amount of time for FETs to transition from a conductive state to a non-conductive state, and vice versa. In certain situations partially conductive FETs in cross-coupled charge pumps may allow current to back flow from the voltage output to the voltage input, lowering efficiency.
- FIG. 1 shows a circuit diagram of a charge pump
- FIG. 2 shows a circuit diagram in accordance with at least some embodiments
- FIG. 3 shows a simplified circuit diagram of a charge pump during a first phase in accordance with at least some embodiments
- FIG. 4 shows a simplified circuit diagram of a charge pump during a second first phase in accordance with at least some embodiments.
- FIG. 5 shows a flow diagram in accordance with at least some embodiments.
- a controller may have a gate output and one or more sense inputs.
- Various embodiments are directed to improved cross-coupled charge pumps. More particularly, various example embodiments are directed to cross-coupled charge pumps that reduce or eliminate reverse current from the voltage output to the voltage input. The reduced reverse current not only increases operational efficiency, but also enables increased clocking frequency. Increased clocking frequency, in turn, increases the ability to supply current to a load without increasing the size of the various capacitors. More particularly still, example embodiments are directed to a cross-coupled charge pump configured to pump charge through two capacitors and simultaneously refresh two capacitors, and then the roles reverse. The specification first turns to a conceptual overview of a charge pump.
- FIG. 1 shows a circuit diagram of a charge pump in two operational states or phases.
- the circuit diagram on the left shows the charge pump 100 in the first phase 102
- the circuit diagram on the right shows the charge pump 100 in the second phase 104 .
- current to the voltage output V OUT is supplied by capacitor 106 coupled to the voltage input V IN1 . That is, the voltage output V OUT is the sum of voltage input V IN1 and the voltage on the capacitor 106 , which we shall see also is initially equal to the voltage input V IN2 .
- the capacitor 106 is pumping current to the voltage output V OUT
- the example circuit is charging or refreshing capacitor 108 to equal the voltage input V IN2 .
- the roles of the capacitors reverse. That is, during the example second phase 104 current supplied to the voltage output V OUT is pumped by capacitor 108 to the voltage output V OUT .
- the voltage output V OUT is the sum of voltage input V IN1 and the voltage on the capacitor 108 , where the capacitor 108 was charged to match the voltage input V IN2 in the first phase. It follows the voltage output V OUT during the second phase is the sum of the voltage input V IN1 and the voltage on the capacitor 108 , which we shall see also is initially equal to the voltage input V IN2 .
- the example circuit is refreshing capacitor 106 to equal the voltage input V IN2 .
- the circuit then reverts to the first phase 102 , and the cycle continues supplying voltage and current to the voltage output V OUT .
- the selective coupling of the capacitors 106 and 108 to either pump current to the voltage output V OUT or be refreshed by the voltage input V IN2 is implemented in FIG. 1 as four electrically controlled switches 110 , 112 , 114 , and 116 .
- the electrically controlled switches are shown as single-pole, double-throw switches.
- the coil signal or control input to each electrically controlled switch is not shown in FIG. 1 so as not to unduly complicate the description. While it may be possible to implement a charge pump with mechanical single-pole, double-throw switches as shown, the operating frequency (e.g., how quickly the circuit could switch between phases) would be severely limited by the time it takes the mechanical switches to change physical positions.
- the electrically controlled switches are operated as cross-coupled field effect transistors (FETs).
- FETs field effect transistors
- partially conductive FETs in cross-coupled charge pumps may allow current to back flow from the voltage output V OUT to the voltage input V IN2 , lowering efficiency.
- FETs that implement the functionality of electrically controlled switch 110 are simultaneously conductive, current will tend to back flow from the voltage output V OUT to the lower voltage input V IN2 through the FETs.
- a similar situation occurs with respect to FETs that implement the functionality of electrically controlled switch 112 .
- Various embodiments are directed to reducing or eliminating reverse current from the voltage output V OUT to the voltage input V IN through the cross-coupled FETs that implement the functionality of the electrically controlled switches 110 and 112 . Additional FETs are added along with additional capacitors. The additional capacitors increase the charge pumping capability of the overall circuit.
- FIG. 2 shows a circuit diagram in accordance with at least some embodiments.
- FIG. 2 shows a cross-coupled charge pump 200 (hereafter just charge pump 200 ) comprising an upper set of FETs 202 (hereafter just upper FETs 202 ) that implement pumping charge to the voltage output V OUT and refreshing capacitors.
- the functionality of the upper FETs 202 corresponds to the electrically controlled switches 110 and 112 of FIG. 1 , but as discussed more below the functionality of the electrically controlled switches 110 and 112 is implemented across duplicated sets of FETs to reduce or eliminate back flow of current from the voltage output V OUT to the input output V IN2 .
- the upper FETs 202 work with four capacitors.
- the example charge pump 200 comprises a first capacitor 206 , a second capacitor 208 , a third capacitor 210 , and a fourth capacitor 212 . Roles of the capacitors 206 , 208 , 210 , and 212 are dependent, in part, on the state of the switch network 204 , so the discussion turns first to the switch network 204 .
- the switch network 204 implements functionality that corresponds to electrically controlled switches 114 and 116 of FIG. 1 , and is merely an example circuit to help understand operation of the upper FETs 202 . Implementation of the switch network 204 may take any suitable form.
- the switch network 204 comprises a plurality of electrically controlled (discussed more below).
- the switch network 204 defines a first through fourth clock inputs 219 , 221 , 223 , and 225 .
- the switch network 204 defines a first through fourth outputs 227 , 229 , 231 , and 233 .
- the example switch network 204 is configured to drive the voltage input V IN1 to the first output 227 and second output 229 when the first and second clock signals are asserted.
- the switch network 204 is configured to ground the first output 227 and second output 229 when the first and second clock signals are de-asserted.
- the switch network 204 is configured to drive the voltage input V IN to the third output 231 and fourth output 233 when the third and fourth clock signals are asserted.
- the switch network 204 is configured to ground the third output 231 and fourth output 233 when the third and fourth clock signals are de-asserted.
- a first lead 214 of the first capacitor 206 couples to complementary FETs 216 by way of the first output 227 .
- Complementary FETs 216 selectively couple the first lead 214 to the voltage input V IN1 or ground 217 depending on the state of the first clock signal applied to gates of the complementary FETs 216 .
- the complementary FETs 216 when the first clock signal is asserted the complementary FETs 216 couple the first lead to the voltage input V IN1 .
- the complementary FETs 216 couple the first lead 214 to ground 217 .
- the complementary FETs 216 couple the first lead to the voltage input V IN1 .
- the complementary FETs 216 couple the first lead 214 to ground 217 .
- a first lead 218 of the second capacitor 208 couples to complementary FETs 220 by way of second output 229 .
- Complementary FETs 220 selectively couple the first lead 218 to the voltage input V IN1 or ground 217 depending on the state of the second clock signal applied to gates of the complementary FETs 220 .
- the complementary FETs 220 couple the first lead 218 to the voltage input V IN1 .
- the complementary FETs 220 couple the first lead 218 to ground 217 .
- the example switch network 204 likewise contains complementary FETs 222 and 224 coupled to the first lead 226 of the third capacitor 210 and the first lead 228 of the fourth capacitor 212 , respectively.
- the complementary FETs 222 and 224 operate similarly with respect to the third clock signal and the fourth clock signal, respectively, as described with respect to complementary FETs 216 and 220 , and so as not to further lengthen the description the operational aspects are not repeated.
- the upper FETs 202 in example systems comprise first FET 230 , second FET 232 , third FET 234 , and fourth FET 236 .
- the FETs 230 , 232 , 234 , and 236 are introduced as a group because these FETs are conductive during an example first phase (though their conduction times are not necessarily the same).
- the FET 230 defines a gate 238 , a source 240 , and a drain 244 .
- the drain 244 of the first FET 230 is coupled to a second lead 246 of the first capacitor 206 .
- the source 240 of the first FET 230 is coupled to the voltage output V OUT .
- the gate 238 of the first FET 230 is coupled to a second lead 248 of the fourth capacitor 212 .
- the second FET 232 defines a gate 250 , a drain 252 , and a source 254 .
- the drain 252 of the second FET 232 is coupled to a second lead 256 of the second capacitor 208 .
- the source 254 of the second FET 232 is coupled to the voltage output V OUT .
- the gate 250 of the second FET 232 is coupled to the second lead 248 of the fourth capacitor 212 .
- the third FET 234 defines a gate 257 , a drain 258 , and a source 260 .
- the source 260 of the third FET 234 is coupled to the voltage input V IN2 .
- the drain 258 of the third FET 234 is coupled to a second lead 262 of the third capacitor 210 .
- the gate 257 of the third FET 234 is coupled to the second lead 246 of the first capacitor 206 .
- the fourth FET 236 defines a gate 264 , a drain 266 , and a source 268 .
- the source 268 of the fourth FET 236 is coupled to the voltage input V IN2
- the drain 266 of the fourth FET 236 is coupled to the second lead 248 of the fourth capacitor 212
- the gate 264 of the fourth FET 236 is coupled to the second lead 246 of the first capacitor 206 .
- the upper FETs 202 in example systems further comprise fifth FET 270 , sixth FET 272 , seventh FET 274 , and an eighth FET 276 .
- the FETs 270 , 272 , 274 , and 276 are introduced as a group because these FETs are conductive during an example second phase (though their conduction times are not necessarily the same).
- the fifth FET 270 defines a gate 278 , source 280 , and a drain 282 .
- the drain 282 of the fifth FET 270 is coupled to the second lead 262 of the third capacitor 210 .
- the source 280 of the fifth FET is coupled to the voltage output V OUT .
- the gate 278 of the fifth FET 270 is coupled to the second lead 256 of the second capacitor 208 .
- the sixth FET 272 defines a gate 284 , a source 286 , and a drain 288 .
- the drain 288 of the sixth FET 272 is coupled to the second lead 248 of the fourth capacitor 212 .
- the source 286 of the sixth FET 272 is coupled to the voltage output V OUT .
- the gate 284 of the sixth FET 272 is coupled to the second lead 256 of the second capacitor 208 .
- the seventh FET 274 defines a gate 290 , a drain 292 , and a source 294 .
- the source 294 of the seventh FET 274 is coupled to the voltage input V IN2 .
- the drain 292 of the seventh FET 274 is coupled to the second lead 246 of the first capacitor 206 .
- the gate 290 of the seventh FET 274 is coupled to the second lead 262 of the third capacitor 210 .
- the eighth FET 276 defines a gate 296 , a drain 298 , and a source 299 .
- the source 299 of the eighth FET 276 is coupled to the voltage input V IN2 .
- the drain 298 of the eighth FET 274 is coupled to the second lead 256 of the second capacitor 208 .
- the gate 296 of the eighth FET 276 is coupled to the second lead 262 of the third capacitor 210 .
- the first FET 230 , the second FET 232 , the fifth FET 270 , and the sixth FET 272 are p-channel metal-oxide semiconductor FETs as illustrated in FIG. 2 .
- each of these example FETs are conductive when the gate voltage is lower than the drain Source voltage, and are non-conductive when the gate is about the same as the drain Source voltage.
- the third FET 234 , fourth FET 236 , seventh FET 274 , and eighth FET 276 are n-channel metal-oxide semiconductor FETS as illustrated in FIG. 2 .
- each of these example FETs are conductive when the gate voltage is about the same as the drain higher than the source voltage, and are non-conductive when the gate is lower than the drain voltage is about the same as the source voltage.
- the charge pump 200 is designed and constructed to operate in two phases.
- the FETs are configured to pump charge from the first capacitor 206 and second capacitor 208 to the voltage output V OUT .
- the charge pump 200 is configured to refresh the third capacitor 210 and fourth capacitor 212 from the voltage input V IN2 .
- the FETs are configured to pump charge from the third capacitor 210 and fourth capacitor 212 to the voltage output V OUT .
- the charge pump 200 is configured to refresh the first capacitor 206 and second capacitor 208 from the voltage input V IN2 .
- the specification turns to simplified circuit diagram of the charge pump.
- FIG. 3 shows a simplified circuit diagram of a charge pump during a first phase in accordance with at least some embodiments.
- FIG. 3 shows the example charge pump 200 with only the FETs that are conductive during the first phase shown, and the remaining FETs removed to simplify the drawing.
- a clock circuit 300 configured to produce distinct first through fourth clock signals on clock outputs 302 , 304 , 306 , and 308 , respectively.
- Embedded within the clock circuit 300 block are four example clock signals during the first phase (not necessarily to scale). Any suitable system to generate the clock signals may be used.
- each phase is preceded by a transitional period.
- the times t0 to t1 represent a transitional period prior to the first phase.
- times t2 to t3 represent a transitional period after the first phase and prior to the second phase.
- the first through fourth clock outputs are coupled to a first through fourth buffers 310 , 312 , 314 , and 316 , respectively.
- the buffers represent the functionality of the switch network 204 ( FIG. 2 ) for purposes of explanation, but are not necessarily used in actual practice. When the input to a buffer is asserted, the buffer couples V IN to its output, and when the input to a buffer is de-asserted, the buffer grounds its output.
- the first lead 214 of the first capacitor 206 is driven to V IN1 ; the first lead 218 of the second capacitor 208 is driven to V IN1 ; the first lead 226 of the third capacitor 210 is grounded; and the first lead 228 of the fourth capacitor 212 is grounded. It follows that the gates of the first FET 230 and second FET 232 are low (e.g., approximately at V IN2 ) and thus FETs 230 and 232 are conductive.
- charge is pumped from the first capacitor 206 through the first FET 230 to the voltage output V OUT (as shown by arrow 318 ) and charge is pumped from the second capacitor 208 through the second FET 232 to the voltage output V OUT (as shown by arrow 320 ).
- the gates of the third FET 234 and fourth FET 236 are high (e.g., approximately at V OUT ) and thus FETs 234 and 236 are conductive, refreshing charge to the third capacitor 210 (as shown by arrow 322 ) and a fourth capacitor 212 (as shown by arrow 324 ).
- the first lead 214 of the first capacitor 206 is grounded; the first lead 218 of the second capacitor 208 remains driven to V IN1 ; the first lead 226 of the third capacitor 210 remains grounded; and the first lead 228 of the fourth capacitor 212 is driven to V IN1 .
- the gates of the first FET 230 and second FET 232 are high (e.g., approximately at V OUT ) and thus FETs 230 and 232 are non-conductive.
- the gates of the third FET 234 and fourth FET 236 are low (e.g., approximately at V IN2 ) and thus FETs 234 and 236 are non-conductive.
- the transitional period between times t2 and t3 is a period of time where the FETs are non-conductive, and for that reason the transitional period is referred to herein as a dead time.
- the state of the various clock signals during the transitional period between times t0 and t1 is the same as the transitional period between t2 and t3, and thus the transitional period between times t0 and t1 also represents a dead time.
- the example circuit then transitions to a second phase.
- FIG. 4 shows a simplified circuit diagram of a charge pump during a second phase in accordance with at least some embodiments.
- FIG. 4 shows the example charge pump 200 with only the FETs that are conductive during the second phase shown, and the remaining FETs removed to simplify the drawing.
- the clock circuit 300 in this case including four example clock signals during the second phase (not necessarily to scale).
- any suitable system to generate the clock signals may be used.
- each phase is preceded by a transitional period. Since the example second phase immediately follows the first phase (from FIG. 3 ), t2 to t3 represent the transitional period between the first phase and the second phase.
- the first through fourth clock outputs are coupled to a respect first through fourth buffers 310 , 312 , 314 , and 316 , respectively.
- the first lead 214 of the first capacitor 206 is grounded; the first lead 218 of the second capacitor 208 is grounded; the first lead 226 of the third capacitor 210 is driven to V IN1 ; and the first lead 228 of the fourth capacitor 212 is driven to V IN1 .
- the gates of the fifth FET 270 and sixth FET 272 are low (e.g., approximately at V IN2 ) and thus FETs 270 and 272 are conductive.
- charge is pumped from the third capacitor 210 through the fifth FET 270 to the voltage output V OUT (as shown by arrow 400 ) and charge is pumped from the fourth capacitor 212 through the sixth FET 272 to the voltage output V OUT (as shown by arrow 402 ).
- the gates of the seventh FET 274 and eighth FET 276 are high (e.g., approximately at V OUT ) and thus FETs 274 and 276 are conductive, refreshing charge to the first capacitor 206 (as shown by arrow 404 ) and a third capacitor 208 (as shown by arrow 406 ).
- the first lead 214 of the first capacitor 206 remains grounded; the first lead 218 of the second capacitor 208 is driven to V IN1 ; the first lead 226 of the third capacitor 210 is grounded; and the first lead 228 of the fourth capacitor 212 remains driven to V IN1 .
- the gates of the fifth FET 270 and sixth FET 272 are high (e.g., approximately at V OUT ) and thus FETs 270 and 272 are non-conductive.
- the gates of the seventh FET 274 and eighth FET 276 are low (e.g., approximately at V IN2 ) and thus FETs 234 and 236 are non-conductive.
- the transitional period between times t4 and t5 is a period of time where the FETs are non-conductive, and for that reason the transitional period is again referred to as a dead time.
- the description of operation started at time t3 it can be now seen that the state of the various clock signals during the transitional period between times t2 and t3 is the same as the transitional period between t4 and t5.
- the example circuit then transitions back to the first phase.
- the charge pump 200 pumps charge from the first capacitor 206 through the first FET 230 to the voltage output V OUT and couples the first lead 214 of the first capacitor 206 to the voltage input V IN1 (through the switch network 204 ). Also during the first phase the charge pump 200 pumps charge from the second capacitor 208 through a second FET 232 to the voltage output V OUT and couples the first lead 218 of the second capacitor 208 to the voltage input V IN1 (through the switch network 204 ). Also during the first phase, the charge pump 200 is designed and constructed to refresh charge to the third capacitor 210 and the fourth capacitor 212 .
- the example charge pump 200 couples the voltage input V IN2 to a second lead 262 of the third capacitor 210 through a third FET 234 , and grounds a first lead of the third capacitor 210 (through the switch network 204 ), and couples the voltage input V IN2 to a second lead 248 of the fourth capacitor 212 , and grounds a first lead 228 of the fourth capacitor 212 .
- the dead times in combination with the duplicated FETs thus reduce or eliminate cross conduction or reverse current from the voltage output V OUT to the voltage input V IN2 .
- the dead times ensure that the first FET 230 and seventh FET 274 cannot be conductive at the same time.
- all four capacitors 206 , 208 , 210 and 212 contribute to the output current (during their respective phases).
- the reduced reverse current not only increases operational efficiency, but also enables increased clocking frequency. Increased clocking frequency, in turn, increases the ability to supply current to a load without increasing the size of the various capacitors.
- FIG. 5 shows a flow diagram in accordance with at least some embodiments.
- the method starts (block 500 ) and comprises: pumping charge from a first capacitor through a first field effect transistor (FET) to a voltage output and from a second capacitor through a second FET to the voltage output of the charge pump (block 502 ); refreshing charge to a third capacitor and a fourth capacitor during the pumping of charge (block 504 ); electrically isolating the first through fourth capacitors during a dead time (block 506 ); and then pumping charge from the third capacitor through a third FET to the voltage output and from the fourth capacitor through a fourth FET to the voltage output of the charge pump (block 508 ); and refreshing charge to the first capacitor and the second capacitor during the pumping of charge from the third and fourth capacitors (block 510 ). Thereafter the method end (block 512 ).
- FET field effect transistor
- switch network 204 could likewise be implemented by a set of eight FETs as shown by the upper FETs 202 . It is intended that the following claims be interpreted to embrace all such variations and modifications.
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Abstract
Description
- This application is a continuation of U.S. patent application Ser. No. 16/108,949 filed Aug. 22, 2018 titled “Cross-Coupled Charge Pumps,” which application is incorporated by reference herein as if reproduced in full below.
- Power converters convert electrical energy at a first voltage to a second voltage. A charge pump is type of power converter that increases voltage such that the voltage output is higher than the voltage input. One type of charge pump is a cross-coupled charge pump. The related art cross-coupled charge pumps experience unwanted cross-conduction that lowers operating efficiency. In particular, cross-coupled charge pumps use field effect transistors (FET) to selectively pump charge from a charged capacitor to the voltage output, and simultaneously use another FET to refresh the voltage on a second capacitor. The roles of the pump and charge for the two capacitors alternate. However, it takes a finite amount of time for FETs to transition from a conductive state to a non-conductive state, and vice versa. In certain situations partially conductive FETs in cross-coupled charge pumps may allow current to back flow from the voltage output to the voltage input, lowering efficiency.
- For a detailed description of example embodiments, reference will now be made to the accompanying drawings in which:
-
FIG. 1 shows a circuit diagram of a charge pump; -
FIG. 2 shows a circuit diagram in accordance with at least some embodiments; -
FIG. 3 shows a simplified circuit diagram of a charge pump during a first phase in accordance with at least some embodiments; -
FIG. 4 shows a simplified circuit diagram of a charge pump during a second first phase in accordance with at least some embodiments; and -
FIG. 5 shows a flow diagram in accordance with at least some embodiments. - Various terms are used to refer to particular system components. Different companies may refer to a component by different names—this document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections.
- In relation to electrical devices, the terms “input” and “output” refer to electrical connections to the electrical devices, and shall not be read as verbs requiring action. For example, a controller may have a gate output and one or more sense inputs.
- The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
- Various embodiments are directed to improved cross-coupled charge pumps. More particularly, various example embodiments are directed to cross-coupled charge pumps that reduce or eliminate reverse current from the voltage output to the voltage input. The reduced reverse current not only increases operational efficiency, but also enables increased clocking frequency. Increased clocking frequency, in turn, increases the ability to supply current to a load without increasing the size of the various capacitors. More particularly still, example embodiments are directed to a cross-coupled charge pump configured to pump charge through two capacitors and simultaneously refresh two capacitors, and then the roles reverse. The specification first turns to a conceptual overview of a charge pump.
-
FIG. 1 shows a circuit diagram of a charge pump in two operational states or phases. In particular, the circuit diagram on the left shows thecharge pump 100 in thefirst phase 102, and the circuit diagram on the right shows thecharge pump 100 in thesecond phase 104. During thefirst phase 102 current to the voltage output VOUT is supplied bycapacitor 106 coupled to the voltage input VIN1. That is, the voltage output VOUT is the sum of voltage input VIN1 and the voltage on thecapacitor 106, which we shall see also is initially equal to the voltage input VIN2. At the same time thecapacitor 106 is pumping current to the voltage output VOUT, the example circuit is charging or refreshingcapacitor 108 to equal the voltage input VIN2. - In the example
second phase 104, the roles of the capacitors reverse. That is, during the examplesecond phase 104 current supplied to the voltage output VOUT is pumped bycapacitor 108 to the voltage output VOUT. Here again, in thesecond phase 104 the voltage output VOUT is the sum of voltage input VIN1 and the voltage on thecapacitor 108, where thecapacitor 108 was charged to match the voltage input VIN2 in the first phase. It follows the voltage output VOUT during the second phase is the sum of the voltage input VIN1 and the voltage on thecapacitor 108, which we shall see also is initially equal to the voltage input VIN2. At the same time thecapacitor 108 is pumping current to the voltage output VOUT, the example circuit is refreshingcapacitor 106 to equal the voltage input VIN2. The circuit then reverts to thefirst phase 102, and the cycle continues supplying voltage and current to the voltage output VOUT. - The selective coupling of the
capacitors FIG. 1 as four electrically controlledswitches FIG. 1 so as not to unduly complicate the description. While it may be possible to implement a charge pump with mechanical single-pole, double-throw switches as shown, the operating frequency (e.g., how quickly the circuit could switch between phases) would be severely limited by the time it takes the mechanical switches to change physical positions. In many cases the electrically controlled switches are operated as cross-coupled field effect transistors (FETs). As alluded to in the Background section, it takes a finite amount of time for FETs to transition from a conductive state to a non-conductive state, and vice versa. In certain situations partially conductive FETs in cross-coupled charge pumps may allow current to back flow from the voltage output VOUT to the voltage input VIN2, lowering efficiency. For example, if the FETs that implement the functionality of electrically controlledswitch 110 are simultaneously conductive, current will tend to back flow from the voltage output VOUT to the lower voltage input VIN2 through the FETs. A similar situation occurs with respect to FETs that implement the functionality of electrically controlledswitch 112. Various embodiments are directed to reducing or eliminating reverse current from the voltage output VOUT to the voltage input VIN through the cross-coupled FETs that implement the functionality of the electrically controlledswitches -
FIG. 2 shows a circuit diagram in accordance with at least some embodiments. In particular,FIG. 2 shows a cross-coupled charge pump 200 (hereafter just charge pump 200) comprising an upper set of FETs 202 (hereafter just upper FETs 202) that implement pumping charge to the voltage output VOUT and refreshing capacitors. The functionality of theupper FETs 202 corresponds to the electrically controlledswitches FIG. 1 , but as discussed more below the functionality of the electrically controlledswitches upper FETs 202 work with four capacitors. During a first phase, two capacitors pump charge to the voltage output VOUT while two capacitors are refreshed with the voltage of the voltage input VIN2. During a second phase, roles are reversed, and two capacitors pump charge to the voltage output VOUT while two capacitors are refreshed with the voltage of the voltage input VIN2. Thus, theexample charge pump 200 comprises afirst capacitor 206, asecond capacitor 208, athird capacitor 210, and afourth capacitor 212. Roles of thecapacitors switch network 204, so the discussion turns first to theswitch network 204. - The
switch network 204 implements functionality that corresponds to electrically controlledswitches FIG. 1 , and is merely an example circuit to help understand operation of theupper FETs 202. Implementation of theswitch network 204 may take any suitable form. Theswitch network 204 comprises a plurality of electrically controlled (discussed more below). Theswitch network 204 defines a first throughfourth clock inputs switch network 204 defines a first throughfourth outputs example switch network 204 is configured to drive the voltage input VIN1 to thefirst output 227 andsecond output 229 when the first and second clock signals are asserted. Theswitch network 204 is configured to ground thefirst output 227 andsecond output 229 when the first and second clock signals are de-asserted. Theswitch network 204 is configured to drive the voltage input VIN to thethird output 231 andfourth output 233 when the third and fourth clock signals are asserted. Theswitch network 204 is configured to ground thethird output 231 andfourth output 233 when the third and fourth clock signals are de-asserted. - More particularly, in the example switch network 204 a
first lead 214 of thefirst capacitor 206 couples tocomplementary FETs 216 by way of thefirst output 227.Complementary FETs 216 selectively couple thefirst lead 214 to the voltage input VIN1 orground 217 depending on the state of the first clock signal applied to gates of thecomplementary FETs 216. For purposes of this discussion, when the first clock signal is asserted thecomplementary FETs 216 couple the first lead to the voltage input VIN1. Conversely, when the first clock signal is de-asserted, thecomplementary FETs 216 couple thefirst lead 214 toground 217. Stated differently, when the first clock signal is asserted thecomplementary FETs 216 couple the first lead to the voltage input VIN1. Conversely, when the first clock signal is de-asserted, thecomplementary FETs 216 couple thefirst lead 214 toground 217. - Still referring to the
switch network 204 ofFIG. 1 , afirst lead 218 of thesecond capacitor 208 couples tocomplementary FETs 220 by way ofsecond output 229.Complementary FETs 220 selectively couple thefirst lead 218 to the voltage input VIN1 orground 217 depending on the state of the second clock signal applied to gates of thecomplementary FETs 220. For purposes of this discussion, when the second clock signal is asserted thecomplementary FETs 220 couple thefirst lead 218 to the voltage input VIN1. Conversely, when the second clock signal is de-asserted, thecomplementary FETs 220 couple thefirst lead 218 toground 217. Theexample switch network 204 likewise containscomplementary FETs 222 and 224 coupled to thefirst lead 226 of thethird capacitor 210 and thefirst lead 228 of thefourth capacitor 212, respectively. Thecomplementary FETs 222 and 224 operate similarly with respect to the third clock signal and the fourth clock signal, respectively, as described with respect tocomplementary FETs upper FETs 202. - The
upper FETs 202 in example systems comprisefirst FET 230,second FET 232,third FET 234, andfourth FET 236. TheFETs FET 230 defines agate 238, asource 240, and adrain 244. Thedrain 244 of thefirst FET 230 is coupled to asecond lead 246 of thefirst capacitor 206. Thesource 240 of thefirst FET 230 is coupled to the voltage output VOUT. Thegate 238 of thefirst FET 230 is coupled to asecond lead 248 of thefourth capacitor 212. Thesecond FET 232 defines agate 250, adrain 252, and asource 254. Thedrain 252 of thesecond FET 232 is coupled to asecond lead 256 of thesecond capacitor 208. Thesource 254 of thesecond FET 232 is coupled to the voltage output VOUT. Thegate 250 of thesecond FET 232 is coupled to thesecond lead 248 of thefourth capacitor 212. - Still referring to
FIG. 2 , thethird FET 234 defines agate 257, adrain 258, and asource 260. Thesource 260 of thethird FET 234 is coupled to the voltage input VIN2. Thedrain 258 of thethird FET 234 is coupled to asecond lead 262 of thethird capacitor 210. Thegate 257 of thethird FET 234 is coupled to thesecond lead 246 of thefirst capacitor 206. Thefourth FET 236 defines agate 264, adrain 266, and asource 268. Thesource 268 of thefourth FET 236 is coupled to the voltage input VIN2, thedrain 266 of thefourth FET 236 is coupled to thesecond lead 248 of thefourth capacitor 212. Thegate 264 of thefourth FET 236 is coupled to thesecond lead 246 of thefirst capacitor 206. - The
upper FETs 202 in example systems further comprisefifth FET 270,sixth FET 272,seventh FET 274, and aneighth FET 276. TheFETs fifth FET 270 defines agate 278,source 280, and adrain 282. Thedrain 282 of thefifth FET 270 is coupled to thesecond lead 262 of thethird capacitor 210. Thesource 280 of the fifth FET is coupled to the voltage output VOUT. Thegate 278 of thefifth FET 270 is coupled to thesecond lead 256 of thesecond capacitor 208. Thesixth FET 272 defines agate 284, asource 286, and adrain 288. Thedrain 288 of thesixth FET 272 is coupled to thesecond lead 248 of thefourth capacitor 212. Thesource 286 of thesixth FET 272 is coupled to the voltage output VOUT. Thegate 284 of thesixth FET 272 is coupled to thesecond lead 256 of thesecond capacitor 208. - Still referring to
FIG. 2 , theseventh FET 274 defines agate 290, adrain 292, and asource 294. Thesource 294 of theseventh FET 274 is coupled to the voltage input VIN2. Thedrain 292 of theseventh FET 274 is coupled to thesecond lead 246 of thefirst capacitor 206. Thegate 290 of theseventh FET 274 is coupled to thesecond lead 262 of thethird capacitor 210. Theeighth FET 276 defines agate 296, adrain 298, and asource 299. Thesource 299 of theeighth FET 276 is coupled to the voltage input VIN2. Thedrain 298 of theeighth FET 274 is coupled to thesecond lead 256 of thesecond capacitor 208. Thegate 296 of theeighth FET 276 is coupled to thesecond lead 262 of thethird capacitor 210. - In the
example charge pump 200, thefirst FET 230, thesecond FET 232, thefifth FET 270, and thesixth FET 272 are p-channel metal-oxide semiconductor FETs as illustrated inFIG. 2 . Thus, each of these example FETs are conductive when the gate voltage is lower than the drain Source voltage, and are non-conductive when the gate is about the same as the drain Source voltage. In the example circuit thethird FET 234,fourth FET 236,seventh FET 274, andeighth FET 276 are n-channel metal-oxide semiconductor FETS as illustrated inFIG. 2 . Thus, each of these example FETs are conductive when the gate voltage is about the same as the drain higher than the source voltage, and are non-conductive when the gate is lower than the drain voltage is about the same as the source voltage. - The
charge pump 200 is designed and constructed to operate in two phases. In a first phase of operation of thecharge pump 200, the FETs are configured to pump charge from thefirst capacitor 206 andsecond capacitor 208 to the voltage output VOUT. Also during the first phase thecharge pump 200 is configured to refresh thethird capacitor 210 andfourth capacitor 212 from the voltage input VIN2. In a second phase of operation of thecharge pump 200, the FETs are configured to pump charge from thethird capacitor 210 andfourth capacitor 212 to the voltage output VOUT. Also during the second phase, thecharge pump 200 is configured to refresh thefirst capacitor 206 andsecond capacitor 208 from the voltage input VIN2. In order to better describe the first phase, the specification turns to simplified circuit diagram of the charge pump. -
FIG. 3 shows a simplified circuit diagram of a charge pump during a first phase in accordance with at least some embodiments. In particular,FIG. 3 shows theexample charge pump 200 with only the FETs that are conductive during the first phase shown, and the remaining FETs removed to simplify the drawing. Also shown inFIG. 3 is aclock circuit 300 configured to produce distinct first through fourth clock signals onclock outputs clock circuit 300 block are four example clock signals during the first phase (not necessarily to scale). Any suitable system to generate the clock signals may be used. In accordance with example embodiments, each phase is preceded by a transitional period. In the example timing diagram shown, the times t0 to t1 represent a transitional period prior to the first phase. Similarly, times t2 to t3 represent a transitional period after the first phase and prior to the second phase. For purposes of explanation the first through fourth clock outputs are coupled to a first throughfourth buffers FIG. 2 ) for purposes of explanation, but are not necessarily used in actual practice. When the input to a buffer is asserted, the buffer couples VIN to its output, and when the input to a buffer is de-asserted, the buffer grounds its output. - During the first phase between times t1 and t2: the
first lead 214 of thefirst capacitor 206 is driven to VIN1; thefirst lead 218 of thesecond capacitor 208 is driven to VIN1; thefirst lead 226 of thethird capacitor 210 is grounded; and thefirst lead 228 of thefourth capacitor 212 is grounded. It follows that the gates of thefirst FET 230 andsecond FET 232 are low (e.g., approximately at VIN2) and thusFETs first capacitor 206 through thefirst FET 230 to the voltage output VOUT (as shown by arrow 318) and charge is pumped from thesecond capacitor 208 through thesecond FET 232 to the voltage output VOUT (as shown by arrow 320). Also during the first phase, the gates of thethird FET 234 andfourth FET 236 are high (e.g., approximately at VOUT) and thusFETs - Still referring to
FIG. 3 , in the transitional period between times t2 and t3: thefirst lead 214 of thefirst capacitor 206 is grounded; thefirst lead 218 of thesecond capacitor 208 remains driven to VIN1; thefirst lead 226 of thethird capacitor 210 remains grounded; and thefirst lead 228 of thefourth capacitor 212 is driven to VIN1. It follows that the gates of thefirst FET 230 andsecond FET 232 are high (e.g., approximately at VOUT) and thusFETs third FET 234 andfourth FET 236 are low (e.g., approximately at VIN2) and thusFETs -
FIG. 4 shows a simplified circuit diagram of a charge pump during a second phase in accordance with at least some embodiments. In particular,FIG. 4 shows theexample charge pump 200 with only the FETs that are conductive during the second phase shown, and the remaining FETs removed to simplify the drawing. Also shown inFIG. 4 is theclock circuit 300, in this case including four example clock signals during the second phase (not necessarily to scale). As before, any suitable system to generate the clock signals may be used. As previously mentioned, each phase is preceded by a transitional period. Since the example second phase immediately follows the first phase (fromFIG. 3 ), t2 to t3 represent the transitional period between the first phase and the second phase. As before, consider that the first through fourth clock outputs are coupled to a respect first throughfourth buffers - During the second phase between times t3 and t4: the
first lead 214 of thefirst capacitor 206 is grounded; thefirst lead 218 of thesecond capacitor 208 is grounded; thefirst lead 226 of thethird capacitor 210 is driven to VIN1; and thefirst lead 228 of thefourth capacitor 212 is driven to VIN1. It follows that the gates of thefifth FET 270 andsixth FET 272 are low (e.g., approximately at VIN2) and thusFETs third capacitor 210 through thefifth FET 270 to the voltage output VOUT (as shown by arrow 400) and charge is pumped from thefourth capacitor 212 through thesixth FET 272 to the voltage output VOUT (as shown by arrow 402). Also during the second phase, the gates of theseventh FET 274 andeighth FET 276 are high (e.g., approximately at VOUT) and thusFETs - Still referring to
FIG. 4 , in the transitional period between times t4 and t5: thefirst lead 214 of thefirst capacitor 206 remains grounded; thefirst lead 218 of thesecond capacitor 208 is driven to VIN1; thefirst lead 226 of thethird capacitor 210 is grounded; and thefirst lead 228 of thefourth capacitor 212 remains driven to VIN1. It follows that the gates of thefifth FET 270 andsixth FET 272 are high (e.g., approximately at VOUT) and thusFETs seventh FET 274 andeighth FET 276 are low (e.g., approximately at VIN2) and thusFETs - During a first phase of operation, the
charge pump 200 pumps charge from thefirst capacitor 206 through thefirst FET 230 to the voltage output VOUT and couples thefirst lead 214 of thefirst capacitor 206 to the voltage input VIN1 (through the switch network 204). Also during the first phase thecharge pump 200 pumps charge from thesecond capacitor 208 through asecond FET 232 to the voltage output VOUT and couples thefirst lead 218 of thesecond capacitor 208 to the voltage input VIN1 (through the switch network 204). Also during the first phase, thecharge pump 200 is designed and constructed to refresh charge to thethird capacitor 210 and thefourth capacitor 212. In particular, during the refresh in the first phase theexample charge pump 200 couples the voltage input VIN2 to asecond lead 262 of thethird capacitor 210 through athird FET 234, and grounds a first lead of the third capacitor 210 (through the switch network 204), and couples the voltage input VIN2 to asecond lead 248 of thefourth capacitor 212, and grounds afirst lead 228 of thefourth capacitor 212. - Referring again to
FIG. 2 , the dead times in combination with the duplicated FETs thus reduce or eliminate cross conduction or reverse current from the voltage output VOUT to the voltage input VIN2. For example, the dead times ensure that thefirst FET 230 andseventh FET 274 cannot be conductive at the same time. A similar statement is true forFETs FETs FETs capacitors -
FIG. 5 shows a flow diagram in accordance with at least some embodiments. In particular, the method starts (block 500) and comprises: pumping charge from a first capacitor through a first field effect transistor (FET) to a voltage output and from a second capacitor through a second FET to the voltage output of the charge pump (block 502); refreshing charge to a third capacitor and a fourth capacitor during the pumping of charge (block 504); electrically isolating the first through fourth capacitors during a dead time (block 506); and then pumping charge from the third capacitor through a third FET to the voltage output and from the fourth capacitor through a fourth FET to the voltage output of the charge pump (block 508); and refreshing charge to the first capacitor and the second capacitor during the pumping of charge from the third and fourth capacitors (block 510). Thereafter the method end (block 512). - Many of the electrical connections in the drawings are shown as direct couplings having no intervening devices, but not expressly stated as such in the description above. Nevertheless, this paragraph shall serve as antecedent basis in the claims for referencing any electrical connection as “directly coupled” for electrical connections shown in the drawing with no intervening device(s).
- The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, the
switch network 204 could likewise be implemented by a set of eight FETs as shown by theupper FETs 202. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Claims (20)
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WO2004040761A1 (en) * | 2002-10-29 | 2004-05-13 | Koninklijke Philips Electronics N.V. | Bi-directional double nmos switch |
US7741898B2 (en) * | 2007-01-23 | 2010-06-22 | Etron Technology, Inc. | Charge pump circuit for high voltage generation |
CN101247076B (en) * | 2008-03-01 | 2011-04-06 | 炬力集成电路设计有限公司 | Voltage doubler and method for outputting current |
CN103001487A (en) * | 2011-09-08 | 2013-03-27 | 中国科学院微电子研究所 | Charge pump capable of eliminating threshold voltage influence |
CN202513820U (en) * | 2012-02-08 | 2012-10-31 | 北京兆易创新科技有限公司 | Charge pump single-stage circuit and charge pump circuit |
KR102140269B1 (en) * | 2014-01-02 | 2020-07-31 | 에스케이하이닉스 주식회사 | Pumping circuit |
US10050522B2 (en) * | 2015-02-15 | 2018-08-14 | Skyworks Solutions, Inc. | Interleaved dual output charge pump |
CN107070205B (en) * | 2017-05-10 | 2019-09-20 | 湘潭大学 | A kind of new charge pump circuit |
CN107707117B (en) * | 2017-11-20 | 2023-11-14 | 广东工业大学 | Charge pump time sequence control circuit and charge pump circuit |
CN207442695U (en) * | 2017-11-20 | 2018-06-01 | 广东工业大学 | A kind of charge pump sequential control circuit and charge pump circuit |
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